TWI779956B - Heat dissipating sheet and chip on film package structure - Google Patents

Heat dissipating sheet and chip on film package structure Download PDF

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Publication number
TWI779956B
TWI779956B TW110145955A TW110145955A TWI779956B TW I779956 B TWI779956 B TW I779956B TW 110145955 A TW110145955 A TW 110145955A TW 110145955 A TW110145955 A TW 110145955A TW I779956 B TWI779956 B TW I779956B
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heat dissipation
metal layer
chip
adhesive layer
edges
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TW110145955A
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Chinese (zh)
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TW202324632A (en
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陳宗謙
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南茂科技股份有限公司
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Priority to CN202210207691.7A priority patent/CN116247016A/en
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Publication of TW202324632A publication Critical patent/TW202324632A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates

Abstract

A heat dissipating sheet including an insulating protective layer, a heat dissipating metal layer, a first adhesive layer and a second adhesive layer is provided. The heat dissipating metal layer has a first surface and a second surface opposite to each other. The first adhesive layer is disposed between the insulating protective layer and the heat dissipating metal layer. The first adhesive layer covers the first surface of the heat dissipating metal layer, and the heat dissipating metal layer is attached to the insulating protective layer through the first adhesive layer. The second adhesive layer is disposed on the second surface of the heat dissipating metal layer. The second adhesive layer has a chip attaching part, two opposite first parts and at least one opening. The opening exposes the heat dissipating metal layer, is located beside the chip attaching part and extends along an extending direction of the chip attaching part. The two first parts at least cover two opposite first edges of the heat dissipating metal layer.

Description

散熱貼片以及薄膜覆晶封裝結構Heat dissipation patch and thin film chip-on-chip package structure

本發明是有關於一種貼片以及封裝結構，且特別是有關於一種散熱貼片以及採用此散熱貼片的薄膜覆晶封裝結構。 The present invention relates to a patch and a package structure, and in particular to a heat dissipation patch and a film-on-chip packaging structure using the heat dissipation patch.

現行的薄膜覆晶封裝(Chip on Film,COF)結構為增進散熱效果，會貼附散熱貼片於封裝結構的表面上。目前普遍使用的散熱貼片主要包括散熱層以及設置於散熱層相對二個表面的絕緣保護層和底部黏膠層，其中底部黏膠層一般是全面性地覆蓋散熱層。為能增加散熱面積以達到較佳的散熱效果，散熱貼片的尺寸通常會盡可能加大(遠大於晶片設置區範圍)。然而，當晶片判定為不良品而需藉由衝切打拔機構將不良晶片由薄膜覆晶封裝結構上移除時，由於衝切打拔機構的衝切範圍通常只針對晶片設置區範圍進行設計，因此衝切範圍往往會小於散熱貼片的尺寸。如此一來，衝切打拔機構在進行衝孔時，其刀具會經過散熱貼片的底部黏膠層，導致刀具上殘留黏膠，而影響刀具效能及減短其使用壽命。此外，衝切後薄膜覆晶封裝結構上剩餘的底部黏膠也可能在 整卷的薄膜覆晶封裝結構捲繞加壓時經由衝孔溢出而污染其他良品。因此，為降低前述情況發生，常需先將散熱貼片移除後再進行衝切動作，導致製程複雜度及時間增加。 In order to improve the heat dissipation effect of the current Chip on Film (COF) structure, a heat dissipation patch is attached on the surface of the package structure. The commonly used heat dissipation patch mainly includes a heat dissipation layer, an insulating protection layer and a bottom adhesive layer disposed on two opposite surfaces of the heat dissipation layer, wherein the bottom adhesive layer generally covers the heat dissipation layer comprehensively. In order to increase the heat dissipation area to achieve a better heat dissipation effect, the size of the heat dissipation patch is usually as large as possible (much larger than the range of the chip installation area). However, when the chip is judged to be a defective product and the defective chip needs to be removed from the film-on-chip package structure by the punching and pulling mechanism, the punching range of the punching and pulling mechanism is usually only designed for the area where the chip is installed. , so the die cut range tends to be smaller than the thermal pad size. In this way, when the punching and punching mechanism punches holes, its tool will pass through the adhesive layer at the bottom of the heat dissipation patch, resulting in residual adhesive on the tool, which affects the performance of the tool and shortens its service life. In addition, the bottom adhesive remaining on the thin-film chip-on-chip packaging structure after die-cutting may also be in the The entire roll of film-on-chip packaging structure overflows through punching holes when it is wound and pressurized, contaminating other good products. Therefore, in order to reduce the occurrence of the above-mentioned situation, it is often necessary to remove the heat dissipation patch first and then carry out the punching operation, resulting in an increase in the complexity and time of the manufacturing process.

本發明提供一種散熱貼片，其可降低衝切打拔機構在進行衝切時，其刀具上殘留黏膠導致刀具損壞的機率，進而提高衝切打拔工具的使用壽命。 The invention provides a heat dissipation patch, which can reduce the probability of damage to the tool due to residual glue on the knife when the punching and pulling mechanism is punching, thereby improving the service life of the punching and pulling tool.

本發明還提供一種薄膜覆晶封裝結構，其包括上述的散熱貼片，可降低衝切打拔機構在進行衝切時，其刀具上殘留黏膠導致刀具損壞的機率，進而提高衝切打拔工具的使用壽命。也可減少衝切後衝孔周圍剩餘的黏膠量，避免剩餘的黏膠在整卷的薄膜覆晶封裝結構捲繞加壓時產生溢膠而污染良品的問題。 The present invention also provides a film-on-chip packaging structure, which includes the above-mentioned heat dissipation patch, which can reduce the probability of damage to the tool due to residual glue on the tool when the punching and pulling mechanism is punching, thereby improving the efficiency of punching and pulling. tool life. It can also reduce the amount of remaining adhesive around the punching hole after punching, avoiding the problem of excess adhesive overflowing and contaminating good products when the entire roll of film-on-chip packaging structure is wound and pressurized.

本發明的一種散熱貼片，其包括一絕緣保護層、一散熱金屬層、一第一膠層以及一第二膠層。散熱金屬層具有彼此相對的第一側面與第二側面。第一膠層配置於絕緣保護層與散熱金屬層之間。第一膠層覆蓋散熱金屬層的第一側面，且散熱金屬層透過第一膠層貼附於絕緣保護層上。第二膠層配置於散熱金屬層的第二側面上。第二膠層具有一晶片黏貼部、相對的二個第一部分與至少一開口。開口暴露出散熱金屬層且位於晶片黏貼部旁並沿著晶片黏貼部的一延伸方向延伸。二個第一部分至少覆蓋散熱金屬層的相對二個第一邊緣。 A heat dissipation patch of the present invention comprises an insulating protection layer, a heat dissipation metal layer, a first adhesive layer and a second adhesive layer. The heat dissipation metal layer has a first side and a second side opposite to each other. The first adhesive layer is disposed between the insulating protection layer and the heat dissipation metal layer. The first adhesive layer covers the first side of the heat dissipation metal layer, and the heat dissipation metal layer is pasted on the insulating protection layer through the first adhesive layer. The second adhesive layer is configured on the second side surface of the heat dissipation metal layer. The second glue layer has a wafer bonding part, two opposite first parts and at least one opening. The opening exposes the heat dissipating metal layer and is located beside the chip bonding part and extends along an extending direction of the chip bonding part. The two first parts cover at least two opposite first edges of the heat dissipation metal layer.

本發明的一種薄膜覆晶封裝結構，其包括如上述實施例中任一項所述的散熱貼片、一可撓性線路載板、一晶片以及一預定缺陷衝切區。可撓性線路載板具有相對的第一表面與第二表面以及定義於第一表面的晶片設置區。晶片配置於晶片設置區內並與可撓性線路載板電性連接。預定缺陷衝切區大於晶片設置區，且晶片設置區位於預定缺陷衝切區內。散熱貼片設置於可撓性線路載板的第一表面或第二表面上。散熱貼片的第二膠層的晶片黏貼部對應晶片設置區。開口對應預定缺陷衝切區的至少一邊緣。 A chip-on-film packaging structure of the present invention includes the heat dissipation patch as described in any one of the above embodiments, a flexible circuit carrier, a chip, and a predetermined defect punching area. The flexible circuit carrier has a first surface and a second surface opposite to each other and a chip setting area defined on the first surface. The chip is arranged in the chip setting area and electrically connected with the flexible circuit carrier. The predetermined defect trimming area is larger than the wafer setting area, and the wafer setting area is located in the predetermined defect trimming area. The heat dissipation patch is disposed on the first surface or the second surface of the flexible circuit carrier. The chip bonding part of the second adhesive layer of the heat dissipation patch corresponds to the chip setting area. The opening corresponds to at least one edge of the predetermined defect blanking area.

基於上述，在本發明的散熱貼片的設計中，配置於散熱金屬層上的第二膠層形成至少一開口，使得散熱貼片設置於可撓性線路載板上時，第二膠層可具有對應晶片設置區的晶片黏貼部與至少覆蓋散熱金屬層的相對二個第一邊緣的二個第一部分，且至少一開口對應預定缺陷衝切區的至少一邊緣。也就是說，本發明的第二膠層並不是全面性地覆蓋散熱金屬層，而是具有對應預定缺陷衝切區的邊緣的開口設計。藉此，當衝切打拔機構在進行衝孔時，可減少其刀具經過第二膠層的範圍，以降低刀具上殘留黏膠而導致刀具損壞的機率，進而提高衝切工具的使用壽命。此外，也可減少衝切後衝孔周圍剩餘的第二膠層的量，避免剩餘的第二膠層在整卷的薄膜覆晶封裝結構捲繞加壓時產生溢膠而污染良品的問題。 Based on the above, in the design of the heat dissipation patch of the present invention, the second adhesive layer disposed on the heat dissipation metal layer forms at least one opening, so that when the heat dissipation patch is placed on the flexible circuit carrier, the second adhesive layer can There is a chip bonding part corresponding to the chip setting area and two first parts covering at least two opposite first edges of the heat dissipation metal layer, and at least one opening corresponds to at least one edge of the predetermined defect trimming area. That is to say, the second adhesive layer of the present invention does not completely cover the heat dissipation metal layer, but has an opening design corresponding to the edge of the predetermined defect punching area. In this way, when the punching and pulling mechanism is punching, the range of the tool passing through the second adhesive layer can be reduced, so as to reduce the probability of damage to the tool due to residual glue on the tool, thereby improving the service life of the punching tool. In addition, it can also reduce the amount of the remaining second adhesive layer around the punching hole after punching, avoiding the problem of the remaining second adhesive layer overflowing and polluting good products when the entire roll of the film-on-chip packaging structure is rolled and pressed.

為了讓本發明的上述特徵及優點能夠更明顯易懂，下文特舉實施例，並配合所附圖式詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

10:薄膜覆晶封裝結構 10: Film-on-chip packaging structure

20:可撓性線路載板 20: Flexible circuit carrier board

22:引腳 22: pin

24:防銲層 24: Solder mask

26:晶片設置區 26: Wafer setting area

30:晶片 30: Wafer

32:凸塊 32: Bump

40a、40d、40e、40f、40g、40h、40i:預定缺陷衝切區 40a, 40d, 40e, 40f, 40g, 40h, 40i: predetermined defect punching area

40a1、40d1、40d2、40d3、40d4、40e1、40e2、40f1、40f2、40f3、40f4、40g1、40g2、40g3、40g4、40h1、40h2、40i1、40i2、 40i3、40i4:邊緣 40a1, 40d1, 40d2, 40d3, 40d4, 40e1, 40e2, 40f1, 40f2, 40f3, 40f4, 40g1, 40g2, 40g3, 40g4, 40h1, 40h2, 40i1, 40i2, 40i3, 40i4: Edge

50:填充膠層 50:Fill glue layer

100a、100b、100c、100d、100e、100f、100g、100h、100i:散熱貼片 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i: cooling pad

110:絕緣保護層 110: insulating protective layer

120:第一膠層 120: the first glue layer

130:散熱金屬層 130: heat dissipation metal layer

140a、140b、140c、140d、140e、140f、140g、140h、140i:第二膠層 140a, 140b, 140c, 140d, 140e, 140f, 140g, 140h, 140i: the second adhesive layer

142a、142b、142c、142d1、142d2、142e1、142e2、142f、142g、142h、142i:開口 142a, 142b, 142c, 142d1, 142d2, 142e1, 142e2, 142f, 142g, 142h, 142i: opening

144:晶片黏貼部 144: Wafer sticking part

144a、144b:端部 144a, 144b: ends

146a、146b、146c、146d、146e、146f、146g、146h、146i1、146i2:第一部分 146a, 146b, 146c, 146d, 146e, 146f, 146g, 146h, 146i1, 146i2: first part

148b、148c、148d、148e、148f、148g、148h1、148h2:第二部分 148b, 148c, 148d, 148e, 148f, 148g, 148h1, 148h2: Part II

200:刀具 200: knives

A1:第一表面 A1: first surface

A2:第二表面 A2: second surface

D:延伸方向 D: Extension direction

E1:第一邊緣 E1: first edge

E2、E21、E22:第二邊緣 E2, E21, E22: second edge

S1:第一側面 S1: first side

S2:第二側面 S2: second side

X、Y:方向 X, Y: direction

圖1A是根據本發明的一實施例的薄膜覆晶封裝結構的俯視示意圖。 FIG. 1A is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention.

圖1B是沿圖1A的線I-I的剖面示意圖。 FIG. 1B is a schematic cross-sectional view along line I-I of FIG. 1A .

圖1C是圖1A的薄膜覆晶封裝結構的散熱貼片的側視示意圖。 FIG. 1C is a schematic side view of the heat dissipation chip of the thin film chip-on-chip package structure shown in FIG. 1A .

圖1D是圖1A的薄膜覆晶封裝結構的散熱貼片的仰視示意圖。 FIG. 1D is a schematic bottom view of the heat dissipation pad of the thin film chip-on-chip package structure shown in FIG. 1A .

圖2A是根據本發明的一實施例的散熱貼片的仰視示意圖。 FIG. 2A is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention.

圖2B是根據本發明的一實施例的散熱貼片的仰視示意圖。 FIG. 2B is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention.

圖3A是根據本發明的一實施例的散熱貼片的仰視示意圖。 FIG. 3A is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention.

圖3B是根據本發明的一實施例的散熱貼片的仰視示意圖。 FIG. 3B is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention.

圖4是根據本發明的一實施例的散熱貼片的仰視示意圖。 FIG. 4 is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention.

圖5A是根據本發明的一實施例的散熱貼片的仰視示意圖。 FIG. 5A is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention.

圖5B是根據本發明的一實施例的散熱貼片的仰視示意圖。 FIG. 5B is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention.

圖6是根據本發明的一實施例的散熱貼片的仰視示意圖。 FIG. 6 is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention.

參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施 例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。 The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention may be embodied in various different forms and should not be limited to the implementations set forth herein. example. The thickness, size or magnitude of layers or regions in the drawings may be exaggerated for clarity.

應說明的是，下述圖式的薄膜覆晶封裝結構係以捲帶傳輸的方式作業，儘管下述圖式的散熱貼片僅示意地繪示應用於形成薄膜覆晶封裝結構的捲帶上的一個元件區(device area)，然而，本發明不限於此，下述圖式的散熱貼片可以同時應用於捲帶上的多個元件區。 It should be noted that the chip-on-film packaging structure in the following figures is transported by tape, although the heat dissipation stickers in the following figures are only schematically shown to be applied on the tape forming the chip-on-film package structure However, the present invention is not limited thereto, and the heat dissipation patch in the following figures can be applied to multiple device areas on the tape at the same time.

圖1A是根據本發明的一實施例的薄膜覆晶封裝結構的俯視示意圖。圖1B是沿圖1A的線I-I的剖面示意圖。圖1C是圖1A的薄膜覆晶封裝結構的散熱貼片的側視示意圖。圖1D是圖1A的薄膜覆晶封裝結構的散熱貼片的仰視示意圖。請先同時參考圖1A及圖1B，在本實施例中，薄膜覆晶封裝結構10包括散熱貼片100a、可撓性線路載板20、晶片30以及預定缺陷衝切區40a。可撓性線路載板20具有相對的第一表面A1與第二表面A2以及定義於第一表面A1的晶片設置區26。晶片30配置於晶片設置區26內並與可撓性線路載板20電性連接。預定缺陷衝切區40a大於晶片設置區26，且晶片設置區26位於預定缺陷衝切區40a內。 FIG. 1A is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view along line I-I of FIG. 1A . FIG. 1C is a schematic side view of the heat dissipation chip of the thin film chip-on-chip package structure shown in FIG. 1A . FIG. 1D is a schematic bottom view of the heat dissipation pad of the thin film chip-on-chip package structure shown in FIG. 1A . Please refer to FIG. 1A and FIG. 1B at the same time. In this embodiment, the film-on-chip packaging structure 10 includes a heat dissipation chip 100a, a flexible circuit carrier 20, a chip 30, and a predetermined defect punching area 40a. The flexible circuit carrier 20 has a first surface A1 and a second surface A2 opposite to each other, and a chip placement area 26 defined on the first surface A1. The chip 30 is disposed in the chip setting area 26 and is electrically connected to the flexible circuit carrier 20 . The predetermined defect trimming area 40a is larger than the wafer setting area 26, and the wafer setting area 26 is located in the predetermined defect trimming area 40a.

如圖1B所示，晶片30包括多個凸塊32，而可撓性線路載板20的第一表面A1上包括多個引腳22，其中凸塊32與引腳22電性連接。換句話說，晶片30是以覆晶接合的方式接合於引腳22上。再者，本實施例的薄膜覆晶封裝結構10還包括填充膠層50，其中填充膠層50設置在晶片30及可撓性線路載板20之間， 且包覆凸塊32及至少部分的引腳22，以避免濕氣及汙染物影響凸塊32及引腳22的電性接點。此外，本實施例的可撓性線路載板20還包括防銲層24，其中防銲層24形成在晶片設置區26外，且局部覆蓋引腳22。在本實施例中，散熱貼片100a是設置於可撓性線路載板20的第一表面A1上且貼合在晶片30上，以直接幫助晶片30散熱，但不以此為限。於其他實施例中，散熱貼片100a也可設置於可撓性線路載板20的第二表面A2上，且可對應於晶片設置區26投影至第二表面A2的位置，此仍屬於本發明所欲保護的範圍。 As shown in FIG. 1B , the chip 30 includes a plurality of bumps 32 , and the first surface A1 of the flexible circuit carrier 20 includes a plurality of pins 22 , wherein the bumps 32 are electrically connected to the pins 22 . In other words, the chip 30 is bonded to the pins 22 in a flip-chip bonding manner. Moreover, the thin film chip-on-chip packaging structure 10 of this embodiment further includes a filling glue layer 50, wherein the filling glue layer 50 is disposed between the chip 30 and the flexible circuit carrier 20, And cover the bump 32 and at least part of the pin 22 to prevent moisture and pollutants from affecting the electrical contact between the bump 32 and the pin 22 . In addition, the flexible circuit carrier 20 of this embodiment further includes a solder resist layer 24 , wherein the solder resist layer 24 is formed outside the chip placement area 26 and partially covers the pins 22 . In this embodiment, the heat dissipation patch 100a is disposed on the first surface A1 of the flexible circuit carrier 20 and attached to the chip 30 to directly help the chip 30 to dissipate heat, but it is not limited thereto. In other embodiments, the heat dissipation patch 100a can also be disposed on the second surface A2 of the flexible circuit carrier 20, and can correspond to the position where the chip installation area 26 is projected onto the second surface A2, which still belongs to the present invention. the scope of protection desired.

更進一步來說，請同時參考圖1C以及圖1D，本實施例的散熱貼片100a包括絕緣保護層110、散熱金屬層130、第一膠層120以及第二膠層140a。散熱金屬層130具有彼此相對的第一側面S1與第二側面S2。第一膠層120配置於絕緣保護層110與散熱金屬層130之間，其中第一膠層120覆蓋散熱金屬層130的第一側面S1，且散熱金屬層130透過第一膠層120貼附於絕緣保護層110上。換言之，絕緣保護層110以及散熱金屬層130之間是透過第一膠層120連接。在此，散熱金屬層130的材質可包括金屬箔或石墨類薄膜，其中金屬箔例如是鋁箔或銅箔，但本發明不限於此。絕緣保護層110的材質例如是聚醯亞胺(Polyimide,PI)，但本發明亦不限於此。 Furthermore, please refer to FIG. 1C and FIG. 1D at the same time. The heat dissipation patch 100a of this embodiment includes an insulating protection layer 110 , a heat dissipation metal layer 130 , a first adhesive layer 120 and a second adhesive layer 140a. The heat dissipation metal layer 130 has a first side S1 and a second side S2 opposite to each other. The first adhesive layer 120 is disposed between the insulating protection layer 110 and the heat dissipation metal layer 130, wherein the first adhesive layer 120 covers the first side S1 of the heat dissipation metal layer 130, and the heat dissipation metal layer 130 is attached to the heat dissipation metal layer 130 through the first adhesive layer 120. on the insulating protection layer 110. In other words, the insulation protection layer 110 and the heat dissipation metal layer 130 are connected through the first adhesive layer 120 . Here, the material of the heat dissipation metal layer 130 may include metal foil or graphite film, wherein the metal foil is, for example, aluminum foil or copper foil, but the invention is not limited thereto. The material of the insulating protection layer 110 is, for example, polyimide (PI), but the invention is not limited thereto.

再者，本實施例的第二膠層140a配置於散熱金屬層130的第二側面S2上，且第二膠層140a具有晶片黏貼部144、相對的 二個第一部分146a與至少一開口142a(示意地繪示二個開口142a)。請同時參考圖1A、圖1B以及圖1D，本實施例的散熱貼片100a的第二膠層140a的晶片黏貼部144對應晶片設置區26，其中散熱貼片100a可透過第二膠層140a黏貼在晶片30與可撓性線路載板20上。詳細來說，第二膠層140a的二個開口142a暴露出散熱金屬層130且位於晶片黏貼部144旁並沿著晶片黏貼部144的延伸方向D延伸。第二膠層140a的二個第一部分146a至少覆蓋散熱金屬層130的相對二個第一邊緣E1，在本實施例中，二個第一邊緣E1為散熱金屬層130的二個短邊。進一步來說，第二膠層140a的二個第一部分146a垂直晶片黏貼部144的延伸方向D並連接晶片黏貼部144的二個端部144a、144b。第二膠層140a的二個開口142a分別位於晶片黏貼部144的兩側。散熱金屬層130具有垂直連接二個第一邊緣E1的相對二個第二邊緣E2，且二個開口142a分別暴露出散熱金屬層130的二個第二邊緣E2。 Moreover, the second adhesive layer 140a of this embodiment is disposed on the second side S2 of the heat dissipation metal layer 130, and the second adhesive layer 140a has a chip bonding portion 144, opposite Two first portions 146a and at least one opening 142a (two openings 142a are schematically shown). Please refer to FIG. 1A, FIG. 1B and FIG. 1D at the same time. The chip bonding portion 144 of the second adhesive layer 140a of the heat dissipation patch 100a of this embodiment corresponds to the chip installation area 26, wherein the heat dissipation patch 100a can be pasted through the second adhesive layer 140a. On the chip 30 and the flexible circuit carrier 20 . In detail, the two openings 142a of the second adhesive layer 140a expose the heat dissipation metal layer 130 and are located beside the die bonding portion 144 and extend along the extending direction D of the die bonding portion 144 . The two first portions 146 a of the second adhesive layer 140 a cover at least two opposite first edges E1 of the heat dissipation metal layer 130 , and in this embodiment, the two first edges E1 are two short sides of the heat dissipation metal layer 130 . Further, the two first portions 146a of the second adhesive layer 140a are perpendicular to the extending direction D of the die attaching portion 144 and connect the two ends 144a, 144b of the die attaching portion 144 . The two openings 142 a of the second adhesive layer 140 a are respectively located on two sides of the wafer bonding portion 144 . The heat dissipation metal layer 130 has two opposite second edges E2 vertically connecting the two first edges E1 , and the two openings 142 a respectively expose the two second edges E2 of the heat dissipation metal layer 130 .

簡言之，本實施例的第二膠層140a沒有全面性地覆蓋散熱金屬層130，而是具有二個開口142a來暴露出部分散熱金屬層130。如圖1D所示，本實例的第二膠層140a的形狀例如是倒工字形，且二個開口142a對應預定缺陷衝切區40a的二個邊緣40a1，而預定缺陷衝切區40a的四個邊皆位於散熱貼片100a內。藉此設計，在衝切打拔機構進行衝切時，其刀具200經過散熱貼片100a的第二膠層140a的範圍可大幅減少，因此，可減少刀具200與第二膠層140a的接觸面積，可有效地降低第二膠層140a殘留於刀 具200上而導致刀具200損壞的機率，進而可提高衝切打拔工具的使用壽命。此外，也可減少衝切後衝孔周圍剩餘的第二膠層140a的量，避免剩餘的第二膠層140a在整卷的薄膜覆晶封裝結構10捲繞加壓時產生溢膠而污染良品的問題。 In short, the second adhesive layer 140 a of this embodiment does not completely cover the heat dissipation metal layer 130 , but has two openings 142 a to expose part of the heat dissipation metal layer 130 . As shown in Figure 1D, the shape of the second adhesive layer 140a in this example is, for example, an inverted I-shape, and the two openings 142a correspond to the two edges 40a1 of the predetermined defect punching area 40a, and the four edges 40a1 of the predetermined defect punching area 40a The sides are all located in the heat dissipation patch 100a. With this design, when the punching and pulling mechanism is punching, the range where the cutter 200 passes through the second adhesive layer 140a of the heat dissipation patch 100a can be greatly reduced, so the contact area between the cutter 200 and the second adhesive layer 140a can be reduced , can effectively reduce the residue of the second adhesive layer 140a on the knife The possibility of damage to the tool 200 caused by the tool 200 can be reduced, and the service life of the punching and pulling tool can be improved. In addition, the amount of the remaining second adhesive layer 140a around the punched hole after punching can also be reduced, so as to prevent the remaining second adhesive layer 140a from overflowing and polluting good products when the entire roll of the film-on-chip packaging structure 10 is rolled and pressed. The problem.

此外，如圖1A、圖1C與圖1D所示，在本實施例中，絕緣保護層110的尺寸大於散熱金屬層130的尺寸，且絕緣保護層110完全覆蓋散熱金屬層130。換句話說，散熱金屬層130於可撓性線路載板20上的正投影會完全位於絕緣保護層110於可撓性線路載板20上的正投影內，以達到對散熱金屬層130的保護效果，但本發明不限於此。 In addition, as shown in FIG. 1A , FIG. 1C and FIG. 1D , in this embodiment, the size of the insulating protection layer 110 is larger than that of the heat dissipation metal layer 130 , and the insulation protection layer 110 completely covers the heat dissipation metal layer 130 . In other words, the orthographic projection of the heat dissipation metal layer 130 on the flexible circuit carrier 20 is completely within the orthographic projection of the insulating protection layer 110 on the flexible circuit carrier 20 to protect the heat dissipation metal layer 130 effect, but the present invention is not limited thereto.

另外，在本實施例中，第一膠層120的厚度較第二膠層140a的厚度來得小頗多。舉例而言，第一膠層120的厚度約等於第二膠層140a的厚度的1/3。由於第一膠層120的厚度相較於第二膠層140a薄化許多，在進行散熱貼片100a的衝切打拔作業時，第一膠層120對刀具200(請參考圖1C)殘膠的問題上產生的影響相對微小。因此，在本實施例中，第一膠層120的尺寸可大致等於散熱金屬層130的尺寸並位於散熱金屬層130的範圍，以使散熱金屬層130與絕緣保護層110之間達到最大貼合面積，以提升兩者間的接合效果。換言之，第一膠層120於可撓性線路載板20(請參考圖1A)上的正投影會大於預定缺陷衝切區40a，但本發明不限於此。 In addition, in this embodiment, the thickness of the first adhesive layer 120 is much smaller than the thickness of the second adhesive layer 140a. For example, the thickness of the first adhesive layer 120 is approximately equal to 1/3 of the thickness of the second adhesive layer 140a. Since the thickness of the first adhesive layer 120 is much thinner than that of the second adhesive layer 140a, the first adhesive layer 120 will have residual glue on the tool 200 (please refer to FIG. The impact on the problem is relatively small. Therefore, in this embodiment, the size of the first adhesive layer 120 can be approximately equal to the size of the heat dissipation metal layer 130 and located within the range of the heat dissipation metal layer 130, so that the maximum bonding between the heat dissipation metal layer 130 and the insulating protection layer 110 can be achieved. area to enhance the bonding effect between the two. In other words, the orthographic projection of the first adhesive layer 120 on the flexible circuit carrier 20 (please refer to FIG. 1A ) is larger than the predetermined defect cutting area 40a, but the invention is not limited thereto.

應說明的是，儘管在本實施例中散熱貼片100a僅設置於 第一表面A1上，然而，本發明不限制散熱貼片100a所貼附的表面，也不限制貼附的表面數量，只要散熱貼片100a至少設置於第一表面A1與第二表面A2的其中之一上皆屬於本發明的保護範圍，因此在其他實施例中，散熱貼片100a可以是僅設置於第二表面A2或同時設置於第一表面A1與第二表面A2上。 It should be noted that, although in this embodiment the heat dissipation patch 100a is only disposed on On the first surface A1, however, the present invention does not limit the surface on which the heat dissipation patch 100a is attached, nor does it limit the number of surfaces attached, as long as the heat dissipation patch 100a is at least disposed on the first surface A1 and the second surface A2 All of them belong to the protection scope of the present invention, so in other embodiments, the heat dissipation patch 100a may be disposed only on the second surface A2 or simultaneously disposed on the first surface A1 and the second surface A2.

在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。 It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

圖2A是根據本發明的一實施例的散熱貼片的仰視示意圖。請同時參考圖1D與圖2A，本實施例的散熱貼片100b和上述的散熱貼片100a相似，兩者的差異在於：在本實施例中，第二膠層140b更具有二個第二部分148b，且二個第二部分148b完全覆蓋散熱金屬層130的二個第二邊緣E2。此處，二個第二邊緣E2為散熱金屬層130的二個長邊。進一步而言，二個開口142b位於晶片黏貼部144、二個第一部分146b與第二部分148b之間，其中每一個開口142b的形狀為矩形，且二個開口142b的尺寸大致相同。此處，二個開口142b皆被第一部分146b、第二部分148b以及晶片黏貼部144所環繞而形成封閉式開口，並使本實施例的第二膠層140b的形狀近似於曰字形。由於本實施例的散熱貼片100b在散熱金屬層130的四個邊緣(二個第一邊緣E1及二個第二邊緣E2)處皆具有第二膠層140b，亦即散熱貼片100b的四個邊皆可透 過第二膠層140b貼附於可撓性線路載板20(請參考圖1A)上，因此，可增加散熱貼片100b與可撓性線路載板20的貼合面積，提升兩者間的接合效果，進一步提高散熱效果。 FIG. 2A is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention. Please refer to FIG. 1D and FIG. 2A at the same time. The heat dissipation patch 100b of this embodiment is similar to the above-mentioned heat dissipation patch 100a. The difference between the two is that in this embodiment, the second adhesive layer 140b has two second parts. 148b , and the two second portions 148b completely cover the two second edges E2 of the heat dissipation metal layer 130 . Here, the two second edges E2 are the two long sides of the heat dissipation metal layer 130 . Furthermore, the two openings 142b are located between the wafer bonding portion 144 and the two first portions 146b and the second portion 148b, wherein each opening 142b is rectangular in shape, and the two openings 142b have approximately the same size. Here, the two openings 142b are surrounded by the first portion 146b, the second portion 148b and the die attaching portion 144 to form a closed opening, and the shape of the second adhesive layer 140b in this embodiment is approximately zigzag. Since the heat dissipation patch 100b of this embodiment has the second adhesive layer 140b at the four edges (two first edges E1 and two second edges E2) of the heat dissipation metal layer 130, that is, the four sides of the heat dissipation patch 100b All sides are transparent The second adhesive layer 140b is attached to the flexible circuit carrier 20 (please refer to FIG. 1A ), therefore, the bonding area between the heat dissipation patch 100b and the flexible circuit carrier 20 can be increased, and the distance between the two can be improved. Bonding effect, to further improve the heat dissipation effect.

圖2B是根據本發明的一實施例的散熱貼片的仰視示意圖。請同時參考圖2A與圖2B，本實施例的散熱貼片100c和上述的散熱貼片100b相似，兩者的差異在於：在本實施例中，第二膠層140c更具有二個第二部分148c，且二個第二部分148c局部覆蓋散熱金屬層130的二個第二邊緣E2。二個開口142c位於晶片黏貼部144、二個第一部分146c與第二部分148c之間。此處，第二膠層140c的每一個開口142c呈近似凸字形的半封閉式開口，且二個開口142c的尺寸大致相同。 FIG. 2B is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention. Please refer to FIG. 2A and FIG. 2B at the same time. The heat dissipation patch 100c of this embodiment is similar to the above-mentioned heat dissipation patch 100b. The difference between the two is that in this embodiment, the second adhesive layer 140c has two second parts. 148c, and the two second portions 148c partially cover the two second edges E2 of the heat dissipation metal layer 130 . The two openings 142c are located between the wafer bonding portion 144, the two first portions 146c and the second portion 148c. Here, each opening 142c of the second adhesive layer 140c is a semi-closed opening approximately in a convex shape, and the two openings 142c have approximately the same size.

值得一提的是，舉例來說，上述的散熱貼片100a、100b、100c對應設置於薄膜覆晶封裝結構10(請參考圖1A)時，在方向Y上大致為置中對應於晶片30，但不以此為限。於另一未繪示的實施例中，散熱貼片亦可在方向Y上非置中對應於晶片，此仍屬於本發明所欲保護的範圍。此外，上述的預定缺陷衝切區40a皆位於散熱貼片100a、100b、100c內，意即預定缺陷衝切區40a的兩個長邊與兩個短邊皆位於散熱貼片100a、100b、100c內，但不以此為限。於另一未繪示的實施例中，預定缺陷衝切區的一個長邊、二個短邊或一個長邊以及兩個短邊可延伸至散熱貼片外，此仍屬於本發明所欲保護的範圍。 It is worth mentioning that, for example, when the above-mentioned heat dissipation pads 100a, 100b, and 100c are correspondingly disposed on the thin film chip-on-chip package structure 10 (please refer to FIG. 1A ), they are roughly centered in the direction Y corresponding to the chip 30, But not limited to this. In another unillustrated embodiment, the heat dissipation patch can also be non-centered in the direction Y corresponding to the chip, which still belongs to the protection scope of the present invention. In addition, the above-mentioned predetermined defect punching area 40a is located in the heat dissipation patch 100a, 100b, 100c, which means that the two long sides and two short sides of the predetermined defect cutting area 40a are located in the heat dissipation patch 100a, 100b, 100c within, but not limited to. In another unillustrated embodiment, one long side, two short sides, or one long side and two short sides of the predetermined defect punching area can extend beyond the heat dissipation patch, which still belongs to the intended protection of the present invention range.

圖3A是根據本發明的一實施例的散熱貼片的仰視示意 圖。請同時參考圖1D與圖3A，本實施例的散熱貼片100d和上述的散熱貼片100a相似，兩者的差異在於：在本實施例中，第二膠層140d更具有一個第二部分148d，且第二部分148d完全覆蓋散熱金屬層130的一個第二邊緣E21。開口142d1位於晶片黏貼部144、二個第一部分146d與第二部分148d之間，而開口142d2暴露出散熱金屬層130的另一個第二邊緣E22。此處，第二邊緣E21、E22為散熱金屬層130的二個長邊。二個開口142d1、142d2的形狀皆為矩形，但開口142d1為封閉式開口，而開口142d2為半開放式開口，且開口142d2的尺寸大於開口142d1的尺寸。 Fig. 3A is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention picture. Please refer to FIG. 1D and FIG. 3A at the same time. The heat dissipation patch 100d of this embodiment is similar to the above-mentioned heat dissipation patch 100a. The difference between the two is that in this embodiment, the second adhesive layer 140d has a second portion 148d , and the second portion 148d completely covers a second edge E21 of the heat dissipation metal layer 130 . The opening 142d1 is located between the die attaching portion 144 , the two first portions 146d and the second portion 148d , and the opening 142d2 exposes another second edge E22 of the heat dissipation metal layer 130 . Here, the second edges E21 and E22 are two long sides of the heat dissipation metal layer 130 . The shapes of the two openings 142d1 and 142d2 are both rectangular, but the opening 142d1 is a closed opening, while the opening 142d2 is a semi-open opening, and the size of the opening 142d2 is larger than that of the opening 142d1.

舉例來說，如圖3A所示，本實施例的散熱貼片100d所對應設置的薄膜覆晶封裝結構10(請參考圖1A)的預定缺陷衝切區40d，在方向Y上非置中對應散熱貼片100d與晶片30，使得預定缺陷衝切區40d的一個邊緣40d2完全位於散熱貼片100d之外，其餘三個邊緣40d1、40d3、40d4則完全或大部分位於散熱貼片100d之內，但不以此為限。因此，將第二膠層140d的開口142d1對應完全位於散熱貼片100d之內的邊緣40d1配置，而開口142d2則暴露出散熱金屬層130的第二邊緣E22，使得第二膠層140d與預定缺陷衝切區40d的四個邊緣40d1、40d2、40d3、40d4產生最小範圍的接觸。簡言之，本實施例的散熱貼片100d在保留最大範圍的第二膠層140d以維持較佳之貼合力的同時，將刀具200(請參考圖1C)與第二膠層140d的接觸面積降至最低，以有效地降低第二膠層140d殘留於刀具200上導致刀具200損壞的機率，進而可 提高衝切打拔工具的使用壽命。 For example, as shown in FIG. 3A, the predetermined defect punching area 40d of the film-on-chip packaging structure 10 (please refer to FIG. 1A) corresponding to the heat dissipation patch 100d of this embodiment is not centered in the direction Y. The heat dissipation patch 100d and the wafer 30 are such that one edge 40d2 of the predetermined defect punching area 40d is completely outside the heat dissipation patch 100d, and the remaining three edges 40d1, 40d3, 40d4 are completely or mostly within the heat dissipation patch 100d, But not limited to this. Therefore, the opening 142d1 of the second adhesive layer 140d is configured to correspond to the edge 40d1 completely inside the heat dissipation chip 100d, and the opening 142d2 exposes the second edge E22 of the heat dissipation metal layer 130, so that the second adhesive layer 140d and the predetermined defect The four edges 40d1 , 40d2 , 40d3 , 40d4 of the die-cut area 40d create a minimum extent of contact. In short, the heat dissipation patch 100d of this embodiment reduces the contact area between the cutter 200 (please refer to FIG. 1C ) and the second adhesive layer 140d while retaining the largest range of the second adhesive layer 140d to maintain a better bonding force. to the minimum, so as to effectively reduce the probability that the second adhesive layer 140d remains on the cutter 200 and cause damage to the cutter 200, and then can Improve the service life of punching and pulling tools.

圖3B是根據本發明的一實施例的散熱貼片的仰視示意圖。請同時參考圖3A與圖3B，本實施例的散熱貼片100e和上述的散熱貼片100d相似，兩者的差異在於：在本實施例中，第二膠層140e的一個第二部分148e僅局部覆蓋散熱金屬層130的第二邊緣E21，使得開口142e1呈近似凸字形的半封閉式開口。 FIG. 3B is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention. Please refer to FIG. 3A and FIG. 3B at the same time. The heat dissipation patch 100e of this embodiment is similar to the above-mentioned heat dissipation patch 100d. The second edge E21 of the heat dissipation metal layer 130 is partially covered, so that the opening 142e1 is a semi-closed opening approximately convex.

圖4是根據本發明的一實施例的散熱貼片的仰視示意圖。請同時參考圖1D與圖4，本實施例的散熱貼片100f和上述的散熱貼片100a相似，兩者的差異在於：在本實施例中，第二膠層140f更具有一個第二部分148f，其中第二部分148f完全覆蓋散熱金屬層130的一個第二邊緣E22。開口142f的數量為一個，且開口142f與第二部分148f分別位於晶片黏貼部144的兩側。開口142f位於二個第一部分146f與晶片黏貼部144之間且暴露出散熱金屬層130的另一個第二邊緣E21。此處，第二邊緣E21、E22為散熱金屬層130的二個長邊。更詳細而言，第二部分148f連接晶片黏貼部144與二個第一部分146f。舉例來說，本實施例的散熱貼片100f所對應設置的薄膜覆晶封裝結構10(請參考圖1A)的預定缺陷衝切區40f，在方向Y上非置中對應散熱貼片100f與晶片30，且在方向X上超出散熱貼片100f，使得預定缺陷衝切區40f的一個邊緣40f1大部分位於散熱貼片100f之內，而其他三個邊緣40f2、40f3、40f4皆完全位於散熱貼片100f之外，但不以此為限。因此，第二膠層140f只需有一個開口142f對應預定缺陷衝切區 40f的邊緣40f1，即可使第二膠層140f與預定缺陷衝切區40f的四個邊緣40f1、40f2、40f3、40f4產生最小範圍的接觸。簡言之，本實施例的散熱貼片100f在保留最大範圍的第二膠層140f以維持較佳之貼合力的同時，將刀具200(請參考圖1C)與第二膠層140f的接觸面積降至最低，以有效地降低第二膠層140f殘留於刀具200上導致刀具200損壞的機率，進而可提高衝切打拔工具的使用壽命。 FIG. 4 is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention. Please refer to FIG. 1D and FIG. 4 at the same time. The heat dissipation patch 100f of this embodiment is similar to the above-mentioned heat dissipation patch 100a. The difference between the two is that in this embodiment, the second adhesive layer 140f further has a second portion 148f , wherein the second portion 148f completely covers a second edge E22 of the heat dissipation metal layer 130 . The number of the opening 142f is one, and the opening 142f and the second portion 148f are respectively located on two sides of the wafer bonding portion 144 . The opening 142f is located between the two first portions 146f and the die attaching portion 144 and exposes another second edge E21 of the heat dissipation metal layer 130 . Here, the second edges E21 and E22 are two long sides of the heat dissipation metal layer 130 . More specifically, the second portion 148f connects the die attaching portion 144 and the two first portions 146f. For example, the predetermined defect punching area 40f of the film-on-chip packaging structure 10 (please refer to FIG. 1A ) corresponding to the heat dissipation patch 100f of this embodiment is not centered in the direction Y, corresponding to the heat dissipation patch 100f and the chip. 30, and beyond the heat dissipation patch 100f in the direction X, so that one edge 40f1 of the predetermined defect punching area 40f is mostly located within the heat dissipation patch 100f, while the other three edges 40f2, 40f3, 40f4 are all completely located in the heat dissipation patch 100f, but not limited thereto. Therefore, the second adhesive layer 140f only needs to have one opening 142f corresponding to the predetermined defect punching area. The edge 40f1 of 40f can make the second glue layer 140f contact with the four edges 40f1, 40f2, 40f3, 40f4 of the predetermined defect punching area 40f in a minimum range. In short, the heat dissipation patch 100f of this embodiment reduces the contact area between the cutter 200 (please refer to FIG. 1C ) and the second adhesive layer 140f while retaining the largest range of the second adhesive layer 140f to maintain better bonding force. to the minimum, so as to effectively reduce the probability of the second adhesive layer 140f remaining on the cutter 200 and cause the cutter 200 to be damaged, thereby improving the service life of the punching and pulling tool.

圖5A是根據本發明的一實施例的散熱貼片的仰視示意圖。請同時參考圖4與圖5A，本實施例的散熱貼片100g和上述的散熱貼片100f相似，兩者的差異在於：在本實施例中，第二膠層140g的開口142g與第二部分148g位於晶片黏貼部144的同一側，且開口142g位於晶片黏貼部144、二個第一部分146g與第二部分148g之間。舉例來說，本實施例的散熱貼片100g在方向Y上非置中對應於晶片30，而是散熱金屬層130的第二邊緣E22的區域對應於晶片30所在位置，換言之，第二膠層140g的晶片黏貼部144剛好位於散熱金屬層130的第二邊緣E22處。散熱貼片100g所對應設置的薄膜覆晶封裝結構10(請參考圖1A)的預定缺陷衝切區40g，在方向Y上亦非置中對應於散熱貼片100g，使得預定缺陷衝切區40g的一個邊緣40g2完全位於散熱貼片100g之外，而其他三個邊緣40g1、40g3、40g4則完全或大部分位於散熱貼片100g之內，但不以此為限。因此，第二膠層140g只需有一個開口142g對應預定缺陷衝切區40g的邊緣40g1，且開口142g與第二 部分148g皆位於晶片黏貼部144的同一側，即可使第二膠層140g與預定缺陷衝切區40g的四個邊緣40g1、40g2、40g3、40g4產生最小範圍的接觸。 FIG. 5A is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention. Please refer to FIG. 4 and FIG. 5A at the same time. The heat dissipation patch 100g of this embodiment is similar to the above-mentioned heat dissipation patch 100f. 148g is located on the same side of the die attaching portion 144, and the opening 142g is located between the die attaching portion 144, the two first portions 146g and the second portion 148g. For example, the heat dissipating patch 100g of this embodiment is not centered in the direction Y and corresponds to the chip 30, but the area of the second edge E22 of the heat dissipating metal layer 130 corresponds to the position of the chip 30, in other words, the second adhesive layer The die bonding portion 144 of 140 g is just located at the second edge E22 of the heat dissipation metal layer 130 . The predetermined defect punching area 40g of the film-on-chip packaging structure 10 (please refer to FIG. 1A ) corresponding to the heat dissipation patch 100g is not centered in the direction Y corresponding to the heat dissipation patch 100g, so that the predetermined defect punching area 40g One edge 40g2 of one side is located completely outside the heat dissipation patch 100g, while the other three edges 40g1, 40g3, 40g4 are completely or mostly located within the heat dissipation patch 100g, but not limited thereto. Therefore, the second adhesive layer 140g only needs to have one opening 142g corresponding to the edge 40g1 of the predetermined defective die-cutting area 40g, and the opening 142g and the second The parts 148g are all located on the same side of the wafer bonding part 144, so that the second glue layer 140g can have minimum contact with the four edges 40g1, 40g2, 40g3, 40g4 of the predetermined defect die-cutting area 40g.

圖5B是根據本發明的一實施例的散熱貼片的仰視示意圖。請同時參考圖5A與圖5B，本實施例的散熱貼片100h和上述的散熱貼片100g相似，兩者的差異在於：在本實施例中，晶片30所在位置較遠離散熱金屬層130的第二邊緣E22，使得第二膠層140h具有二個第二部分148h1、148h2，且二個第二部分148h1、148h2完全覆蓋散熱金屬層130的二個第二邊緣E21、E22。更詳細而言，第二部分148h2連接晶片黏貼部144與二個第一部分146h，且開口142h位於晶片黏貼部144、二個第一部分146h與第二部分148h1之間。 FIG. 5B is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention. Please refer to FIG. 5A and FIG. 5B at the same time. The heat dissipation patch 100h of this embodiment is similar to the above-mentioned heat dissipation patch 100g. Two edges E22 , so that the second adhesive layer 140h has two second portions 148h1 , 148h2 , and the two second portions 148h1 , 148h2 completely cover the two second edges E21 , E22 of the heat dissipation metal layer 130 . In more detail, the second portion 148h2 connects the die bonding portion 144 and the two first portions 146h, and the opening 142h is located between the die bonding portion 144, the two first portions 146h and the second portion 148h1.

圖6是根據本發明的一實施例的散熱貼片的仰視示意圖。請參考圖6，本實施例的散熱貼片100i的第二膠層140i具有二個第一部分146i1、146i2平行晶片黏貼部144的延伸方向D，且二個第一部分146i1、146i2覆蓋散熱金屬層130的相對二個第一邊緣E1。此處，二個第一邊緣E1為散熱金屬層130的二個長邊。開口142i的數量為一個，且開口142i位於一個第一部分146i1與晶片黏貼部144之間。詳細來說，第二膠層140i的開口142i由散熱金屬層130的一個第二邊緣E2延伸至另一個第二邊緣E2，而將第一部分146i1與晶片黏貼部144完全間隔開。第一部分146i2則與晶片黏貼部144相連接。此處，二個第二邊緣E2為散熱金屬 層130的二個短邊。舉例來說，本實施例的散熱貼片100i所對應設置的薄膜覆晶封裝結構10(請參考圖1A)的預定缺陷衝切區40i，在方向Y上非置中對應於散熱貼片100i與晶片30，且在方向X上超出散熱貼片100i，使得預定缺陷衝切區40i的一個邊緣40i1大部分位於散熱貼片100i之內，而其他三個邊緣40i2、40i3、40i4皆完全位於散熱貼片100i之外，但不以此為限。因此，第二膠層140i只需有一個開口142i對應預定缺陷衝切區40i的邊緣40i1，即可使第二膠層140i與預定缺陷衝切區40i的四個邊緣40i1、40i2、40i3、40i4產生最小範圍的接觸。如此配置下，第二膠層140i的第一部分146i1、146i2與開口142i可完全避開預定缺陷衝切區40i的四個邊緣40i1、40i2、40i3、40i4。簡言之，本實施例的散熱貼片100i在保留最大範圍的第二膠層140i以維持較佳之貼合力的同時，將刀具200(請參考圖1C)與第二膠層140i的接觸面積降至最低，以有效地降低第二膠層140i殘留於刀具200上導致刀具200損壞的機率，進而可提高衝切打拔工具的使用壽命。 FIG. 6 is a schematic bottom view of a heat dissipation patch according to an embodiment of the present invention. Please refer to FIG. 6 , the second adhesive layer 140i of the heat dissipation patch 100i in this embodiment has two first parts 146i1, 146i2 parallel to the extending direction D of the chip attaching part 144, and the two first parts 146i1, 146i2 cover the heat dissipation metal layer 130 The opposite two first edges E1. Here, the two first edges E1 are the two long sides of the heat dissipation metal layer 130 . The number of the opening 142i is one, and the opening 142i is located between a first portion 146i1 and the die bonding portion 144 . In detail, the opening 142i of the second adhesive layer 140i extends from one second edge E2 to the other second edge E2 of the heat dissipation metal layer 130 , and completely separates the first portion 146i1 from the die attaching portion 144 . The first portion 146i2 is connected to the die attaching portion 144 . Here, the two second edges E2 are heat dissipation metal The two short sides of layer 130. For example, the predetermined defect punching area 40i of the film-on-chip packaging structure 10 (please refer to FIG. 1A ) corresponding to the heat dissipation patch 100i in this embodiment is not centered in the direction Y, corresponding to the heat dissipation patch 100i and Wafer 30, and in the direction X beyond the heat dissipation paste 100i, so that one edge 40i1 of the predetermined defect punching area 40i is mostly located within the heat dissipation paste 100i, while the other three edges 40i2, 40i3, 40i4 are all completely located within the heat dissipation paste 100i, but not limited to. Therefore, the second adhesive layer 140i only needs to have one opening 142i corresponding to the edge 40i1 of the predetermined defect punching area 40i, so that the second adhesive layer 140i can be connected to the four edges 40i1, 40i2, 40i3, 40i4 of the predetermined defect punching area 40i. Produces minimal contact. Under such configuration, the first portions 146i1, 146i2 and the opening 142i of the second adhesive layer 140i can completely avoid the four edges 40i1, 40i2, 40i3, 40i4 of the predetermined defect die-cutting area 40i. In short, the heat dissipating patch 100i of this embodiment reduces the contact area between the tool 200 (please refer to FIG. 1C ) and the second adhesive layer 140i while retaining the largest range of the second adhesive layer 140i to maintain better bonding force. to the minimum, so as to effectively reduce the probability of the second glue layer 140i remaining on the cutter 200 and cause the cutter 200 to be damaged, thereby improving the service life of the punching and pulling tool.

綜上所述，在本發明的散熱貼片的設計中，將配置於散熱金屬層上的第二膠層形成至少一開口，使得散熱貼片設置於可撓性線路載板上時，第二膠層可具有對應晶片設置區的晶片黏貼部與至少覆蓋散熱金屬層的相對二個第一邊緣的二個第一部分，且至少一開口對應預定缺陷衝切區的至少一邊緣。也就是說，本發明的第二膠層並不是全面性地覆蓋散熱金屬層，而是具有對應預定缺陷衝切區的邊緣的開口設計。藉此，當衝切打拔機構在進 行衝孔時，可減少其刀具經過第二膠層的範圍，以降低刀具上殘留黏膠而導致刀具損壞的機率，進而提高衝切工具的使用壽命。此外，也可減少衝切後衝孔周圍剩餘的第二膠層的量，避免剩餘的第二膠層在整卷的薄膜覆晶封裝結構捲繞加壓時產生溢膠而污染良品的問題。 To sum up, in the design of the heat dissipation patch of the present invention, at least one opening is formed in the second adhesive layer disposed on the heat dissipation metal layer, so that when the heat dissipation patch is placed on the flexible circuit carrier, the second The glue layer may have a chip bonding portion corresponding to the chip setting area and two first portions covering at least two opposite first edges of the heat dissipation metal layer, and at least one opening corresponds to at least one edge of the predetermined defect punching area. That is to say, the second adhesive layer of the present invention does not completely cover the heat dissipation metal layer, but has an opening design corresponding to the edge of the predetermined defect punching area. In this way, when the punching and pulling mechanism is in progress When punching, it can reduce the range where the tool passes through the second glue layer, so as to reduce the probability of tool damage caused by residual glue on the tool, and thus improve the service life of the punching tool. In addition, it can also reduce the amount of the remaining second adhesive layer around the punching hole after punching, avoiding the problem of the remaining second adhesive layer overflowing and polluting good products when the entire roll of the film-on-chip packaging structure is rolled and pressed.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

30:晶片 30: Wafer

40a:預定缺陷衝切區 40a: Predetermined defect punching area

40a1:邊緣 40a1: edge

100a:散熱貼片 100a: heat dissipation patch

110:絕緣保護層 110: insulating protective layer

130:散熱金屬層 130: heat dissipation metal layer

140a:第二膠層 140a: the second adhesive layer

142a:開口 142a: opening

144:晶片黏貼部 144: Wafer sticking part

144a、144b:端部 144a, 144b: ends

146a:第一部分 146a: Part I

D:延伸方向 D: Extension direction

E1:第一邊緣 E1: first edge

E2:第二邊緣 E2: second edge

Y:方向 Y: Direction

Claims (10)

一種散熱貼片，包括： 一絕緣保護層； 一散熱金屬層，具有彼此相對的一第一側面與一第二側面； 一第一膠層，配置於該絕緣保護層與該散熱金屬層之間，該第一膠層覆蓋該散熱金屬層的該第一側面，且該散熱金屬層透過該第一膠層貼附於該絕緣保護層上；以及 一第二膠層，配置於該散熱金屬層的該第二側面上，其中該第二膠層具有一晶片黏貼部、相對的二個第一部分與至少一開口，該至少一開口暴露出該散熱金屬層且位於該晶片黏貼部旁並沿著該晶片黏貼部的一延伸方向延伸，該二個第一部分至少覆蓋該散熱金屬層的相對二個第一邊緣。 A heat dissipation patch, comprising: an insulating protective layer; A heat dissipation metal layer has a first side and a second side opposite to each other; A first adhesive layer, configured between the insulating protective layer and the heat dissipation metal layer, the first adhesive layer covers the first side surface of the heat dissipation metal layer, and the heat dissipation metal layer is attached to the heat dissipation metal layer through the first adhesive layer on the insulating layer; and A second adhesive layer is disposed on the second side of the heat dissipation metal layer, wherein the second adhesive layer has a chip bonding portion, two opposite first portions and at least one opening, the at least one opening exposes the heat dissipation The metal layer is located beside the chip bonding part and extends along an extension direction of the chip bonding part, and the two first parts cover at least two opposite first edges of the heat dissipation metal layer. 如請求項1所述的散熱貼片，其中該第二膠層的該二個第一部分垂直該晶片黏貼部的該延伸方向並連接該晶片黏貼部的二個端部。The heat dissipation chip according to claim 1, wherein the two first portions of the second adhesive layer are perpendicular to the extending direction of the die attaching portion and connect two ends of the die attaching portion. 如請求項2所述的散熱貼片，其中該第二膠層的該至少一開口的數量為二個，分別位於該晶片黏貼部的兩側。The heat dissipation chip according to claim 2, wherein the number of the at least one opening of the second adhesive layer is two, which are respectively located on two sides of the die bonding part. 如請求項3所述的散熱貼片，其中該散熱金屬層具有垂直連接該二個第一邊緣的相對二個第二邊緣，且該二個開口分別暴露出該散熱金屬層的該二個第二邊緣。The heat dissipation patch as claimed in claim 3, wherein the heat dissipation metal layer has two opposite second edges vertically connecting the two first edges, and the two openings respectively expose the two second edges of the heat dissipation metal layer Two edges. 如請求項3所述的散熱貼片，其中該第二膠層更具有至少一第二部分，該散熱金屬層具有垂直連接該二個第一邊緣的相對二個第二邊緣，該至少一第二部分至少局部覆蓋該散熱金屬層的該二個第二邊緣的其中之一，該二個開口的至少其中之一位於該晶片黏貼部、該二個第一部分與該至少一第二部分之間。The heat dissipation chip according to claim 3, wherein the second adhesive layer further has at least one second portion, the heat dissipation metal layer has two opposite second edges vertically connecting the two first edges, and the at least one first edge Two parts at least partly cover one of the two second edges of the heat dissipation metal layer, at least one of the two openings is located between the die attaching part, the two first parts and the at least one second part . 如請求項2所述的散熱貼片，其中該第二膠層更具有至少一第二部分，該散熱金屬層具有垂直連接該二個第一邊緣的相對二個第二邊緣，該至少一第二部分至少局部覆蓋該散熱金屬層的該二個第二邊緣的其中之一，且該至少一開口的數量為一個。The heat dissipation patch according to claim 2, wherein the second adhesive layer further has at least one second portion, the heat dissipation metal layer has two opposite second edges vertically connecting the two first edges, and the at least one first edge The two parts at least partially cover one of the two second edges of the heat dissipation metal layer, and the number of the at least one opening is one. 如請求項6所述的散熱貼片，其中該開口與該至少一第二部分分別位於該晶片黏貼部的兩側，且該開口暴露出該二個第二邊緣的其中之另一。The heat dissipation chip according to claim 6, wherein the opening and the at least one second portion are respectively located on two sides of the die bonding portion, and the opening exposes the other of the two second edges. 如請求項6所述的散熱貼片，其中該開口與該至少一第二部分位於該晶片黏貼部的同一側，且該開口位於該晶片黏貼部、該二個第一部分與該至少一第二部分之間。The heat dissipation chip according to claim 6, wherein the opening and the at least one second part are located on the same side of the die attaching part, and the opening is located at the die attaching part, the two first parts and the at least one second part between sections. 如請求項1所述的散熱貼片，其中該第二膠層的該二個第一部分平行該晶片黏貼部的該延伸方向，該至少一開口位於該二個第一部分的至少其中之一與該晶片黏貼部之間。The heat dissipation patch as claimed in claim 1, wherein the two first parts of the second adhesive layer are parallel to the extending direction of the chip bonding part, and the at least one opening is located between at least one of the two first parts and the Between the die attach parts. 一種薄膜覆晶封裝結構，包括： 如請求項1至請求項9中任一項所述的散熱貼片； 一可撓性線路載板，具有相對的一第一表面與一第二表面以及定義於該第一表面的一晶片設置區； 一晶片，配置於該晶片設置區內並與該可撓性線路載板電性連接；以及 一預定缺陷衝切區，該預定缺陷衝切區大於該晶片設置區，且該晶片設置區位於該預定缺陷衝切區內； 其中該散熱貼片設置於該可撓性線路載板的該第一表面或該第二表面上，該散熱貼片的該第二膠層的該晶片黏貼部對應該晶片設置區，該至少一開口對應該預定缺陷衝切區的至少一邊緣。 A chip-on-film packaging structure, comprising: The heat dissipation patch as described in any one of claim 1 to claim 9; A flexible circuit carrier has a first surface opposite to a second surface and a chip setting area defined on the first surface; a chip, arranged in the chip installation area and electrically connected with the flexible circuit carrier; and a predetermined defect trimming area, the predetermined defect trimming area is larger than the wafer placement area, and the wafer placement area is located in the predetermined defect trimming area; Wherein the heat dissipation patch is arranged on the first surface or the second surface of the flexible circuit carrier, the chip bonding part of the second adhesive layer of the heat dissipation patch corresponds to the chip installation area, and the at least one The opening corresponds to at least one edge of the predetermined defect die-cutting area.
TW110145955A 2021-12-08 2021-12-08 Heat dissipating sheet and chip on film package structure TWI779956B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150287691A1 (en) * 2010-11-12 2015-10-08 Unimicron Technology Corp. Method of fabricating package structure
TWI618205B (en) * 2015-05-22 2018-03-11 南茂科技股份有限公司 Chip on film package and heat dissipation method thereof
CN212967208U (en) * 2020-06-23 2021-04-13 东莞市明盛电气有限公司 Heat-resisting silica gel electric wire
WO2021227727A1 (en) * 2020-05-13 2021-11-18 京东方科技集团股份有限公司 Display module and display apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150287691A1 (en) * 2010-11-12 2015-10-08 Unimicron Technology Corp. Method of fabricating package structure
TWI618205B (en) * 2015-05-22 2018-03-11 南茂科技股份有限公司 Chip on film package and heat dissipation method thereof
WO2021227727A1 (en) * 2020-05-13 2021-11-18 京东方科技集团股份有限公司 Display module and display apparatus
CN212967208U (en) * 2020-06-23 2021-04-13 东莞市明盛电气有限公司 Heat-resisting silica gel electric wire

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