TWI767829B - Chip package - Google Patents

Abstract

A chip package includes a stack of chips contained in a vaporization chamber consisting of a cover and a plate. The chips are alternately arranged with intermediate layers. A capillary mechanism is provided on a horizontal portion of an internal face of the cover. Nets are provided on vertical portions of the internal face of the cover. The nets extend around the capillary mechanism. Each of the intermediate layers includes protuberances extending from edges. The protuberances are in contact with the nets. A channel is defined between any adjacent two of the protuberances. The channels travel past the intermediate layers. Coolant is filled in the vaporization chamber. The coolant is turned into vapor from liquid after absorbing heat. The vapor ascends to the cover via the channels. The coolant is returned into liquid from vapor after transferring heat to the cover. The liquid descends to the plate. Thus, the coolant is circulated in the vaporization chamber. Each of the intermediate layers includes a capillary structure to facilitate the circulation of the coolant.

Description

Semiconductor three-dimensional packaging structure with vapor chamber

The present invention relates to a semiconductor packaging technology, in particular to a three-dimensional packaging structure, which utilizes a vapor chamber or a so-called uniform temperature structure to generate the heat dissipation effect of a semiconductor chip.

The three-dimensional packaging structure is adopted to gather more semiconductor chips together to meet the requirements of small size and strong function. After being powered on, the semiconductor chip generates high heat, which can delay computing efficiency and even shorten its lifespan. How to dissipate heat has become an urgent issue for semiconductor chips.

In US Patent No. 20200105644, a heat dissipation device is attached to a semiconductor three-dimensional package structure, and a cooling liquid with a lower temperature is continuously supplemented into a flow channel to take away the heat of the package structure. Although, the design of this water cooling method can improve the heat dissipation efficiency. However, the force of the cooling device to push the coolant flow comes from a pump, and the bulky cooling device obviously cannot keep up with the advanced technology of miniaturization of the package structure.

Taiwan Patent No. 202121618 proposes a stacked structure, combined with the heat dissipation structure of Taiwan Patent No. 202002201, adding a heat conduction structure inside the three-dimensional package to improve the heat dissipation problem. Specifically, a heat dissipation layer is added to each layer of the stack of semiconductor chips. The heat dissipation layer is a thermal interface material with thermal conductivity. The heat conduction effect of the semiconductor chips is achieved through electrical connection structures such as through-silicon vias or copper pillars. The disadvantage is that the effect of heat conduction and heat dissipation is limited. In particular, when multiple layers are stacked, the heat dissipation of the lower-layer semiconductor wafer is not as good, and the effect is greatly reduced.

The best solution for solving the heat dissipation problem at present is a vapor chamber structure or a uniform temperature structure. The vapor chamber structure utilizes the thermal cycle between the gas phase and the liquid phase of the cooling fluid to achieve rapid heat dissipation. Therefore, the vapor chamber is used in the three-dimensional packaging technology of semiconductors, which can improve the heat dissipation efficiency of multiple high-performance chips.

For example, Japanese Patent No. 5554444 (Publication No. 2015050323) and Taiwan Patent No. 202002031 both mention a cover, which is used in the three-dimensional packaging structure of semiconductors to achieve the heat dissipation effect of the vapor chamber.

Also, Taiwan Patent No. I672775 (Application No. 106119235), in a three-dimensional package structure, at least one cooling channel is designed to surround the stacked semiconductor chips. The fluid that undergoes phase change in the cooling channel takes away the heat of the semiconductor wafer and has the effect of dissipating heat, so the cooling channel functions as a vapor chamber.

There is also a semiconductor packaging structure and assembly structure, a required vapor chamber is provided between the semiconductor wafer and the packaging substrate, and the vapor chamber takes away the heat of the semiconductor wafer, and has filed patent applications in many countries, such as US No. 20200111728 and No. 20200111728. China No. 111009493 and other cases.

In the aforementioned vapor chamber patents, the thermal interface material or the encapsulating colloid is used as the medium to indirectly combine the vapor chamber structure with the semiconductor packaging structure. In this way, the thermal conductivity of the medium greatly affects the heat dissipation effect of the vapor chamber structure.

In addition, the public information of US Patent No. 20190393193 discloses a semiconductor package with a vapor chamber function, mainly in a space of an electrical connection structure, and the vapor chamber is provided between a plurality of integrated circuits. However, the flow space of the vapor chamber is limited to a narrow space where the integrated circuits are separated from each other, resulting in poor heat dissipation efficiency of the semiconductor package as a whole.

There is also a semiconductor package with an interposer attached to the semiconductor, as disclosed in US Pat. No. 7,002,247. Wherein, the interposer has two plates containing core structures such as grooves, and the inner sealed volume that constitutes the interposer directly contacts the backside of the semiconductor, thereby forming a vapor chamber in an attempt to reduce the heat of the semiconductor wafer and achieve temperature uniformity. Unfortunately, the semiconductor package only relies on the attachment structure on the surface of the wafer, which easily damages the semiconductor wafer and relatively weakens the overall supporting structure.

In view of this, the inventor of the present application provides a new generation of three-dimensional packaging structure, the main purpose of which is: the vapor chamber structure encapsulates the semiconductor chip and the cooling fluid, so that the cooling fluid directly takes away the heat of the semiconductor chip, so the heat dissipation effect is more efficient than the prior art.

In order to achieve the above objectives, the semiconductor three-dimensional packaging structure of the present invention includes:

a base plate;

A plurality of semiconductor chips are stacked on the bottom plate through a plurality of interposers, the interposer has a top capillary structure and a bottom capillary structure, the periphery of the interposer is provided with a set of convex portions, and the two convex portions are separated by a concave portion;

A set of capillary structures and a set of nets are arranged on the inside of a cover, and the nets cover the capillary structures. When the cover is combined with the bottom plate to form a vapor chamber, the cover covers all the semiconductor wafers, and all the interposers contact the networking so that the recess from the upper interposer to the lower interposer becomes a flow path to the vapor chamber; and

An appropriate amount of cooling fluid is added into the vapor chamber, and a liquid-to-gaseous thermal cycle is performed between the set of capillary structures, the set of flow channels, the top capillary structure and the bottom capillary structure to achieve the heat dissipation effect of the semiconductor wafer.

In this way, the cover of the present invention is combined with the bottom plate to form a vapor chamber, and the semiconductor wafer and the cooling fluid are encapsulated in the vapor chamber to form a three-dimensional packaging structure. The cooling fluid performs a thermal cycle of liquid to gaseous state in the vapor chamber, which directly takes away the heat of the semiconductor wafer, and the heat dissipation effect is naturally more efficient than the previous technology.

In order to make the objects, features and advantages of the present invention easy to understand, one or more preferred embodiments are presented and described in detail as follows in conjunction with the accompanying drawings.

Next, the embodiments of the present application will be described with reference to the accompanying drawings. In the drawings, the same or similar structures or elements are denoted by the same reference numerals. It is foreseeable that the described embodiments are only some examples of the present application, not all of the embodiments. Other embodiments that can be obtained by deduction based on the described examples, or modified or changed structures as needed, all fall within the scope of protection of this case.

In the following description, directional terms such as "up", "down", "left", "right", "front", "rear", "inner", "outer" and "side" refer only to the directions of the drawings. . The use of directional terms is for better and clearer description and understanding of the present case, and does not indicate or imply that the devices or elements described must have specific orientations, structures and operations, and therefore cannot be construed as limitations on the technical content of the present case.

Unless there are specific and clear specifications and limitations, in the following description, "installed", "connected", "connected" or "disposed on" should be understood in a broad sense, such as fixed connection, detachable connection, integral connection, mechanical connection , directly connected, indirectly connected, or connected between two elements. For those skilled in the art of the present application, with common knowledge or experience, they can understand the specific meanings of the above terms in various embodiments and even in the present application.

In the following description, "plurality" means two or more, unless otherwise specified.

FIG. 1 is a top view showing a first embodiment of the package structure 10 of the present invention. Above the packaging structure 10 is a cover 11 , the cover 11 is a cube, and four corners of the cube have a hole 12 .

In this embodiment, the cover 11 is made of one of copper, copper alloy and other thermally conductive metals. In some embodiments, the surface of the cover 11 is formed by coating the surface of the cover 11 with one of copper, copper alloy and other thermally conductive metals, which also has thermal conductivity.

FIG. 2 is a bottom view. Below the package structure 10 is a bottom plate 20 with the same shape as the cover 11 . A group of electrical pins 21 are arrayed in the center of the bottom plate 20 , and the group of electrical pins 21 are arranged in a square ring. . Four spacers 22 are formed at four corners of the bottom plate 20 .

As shown in Figures 4 and 10, the package structure 10 is cut into two parts. Seen from the perspective view, the inside of the cover 11 has five surfaces enclosing an inner space. The bottom plate 20 closes the opening of the cover 11 , and the two are combined to form a closed vapor chamber 13 . A leak-proof structure 23 is located between the bottom plate 20 and the cover 11 to prevent leakage of the vapor chamber 13 .

In this embodiment, a group of capillary structures 15 are etched inside the cover 11 . The capillary structure 15 is a plurality of staggered slits and is formed on one of the five surfaces inside the cover 11 . In this way, the set of capillary structures 15 covers the five surfaces of the inner side of the cover 11 . In some embodiments, the capillary structures 15 are formed on the surface of the cover 11 by means of laser engraving, stamping and die casting.

In addition, a set of metal meshes 14 are bonded to the inside of the cover 11 . The mesh 14 is fixed to one of the five faces on the inside of the cover 11 by one of welding or adhesive means, without destroying or blocking the capillary structure 15 of that face. In this way, the network 14 shields the capillary structure 15 inside the cover 11 .

As shown in FIGS. 3 and 5 , in the vapor chamber 13 of the package structure 10 , a semiconductor wafer stack structure and an appropriate amount of cooling fluid (not shown) are packaged.

In this embodiment, the cooling fluid is ultrapure water. The ultrapure water has a thermal conductivity, and in the steam chamber 13 with a fixed volume, the change of liquid phase to gas phase is carried out, so an appropriate amount of ultrapure water may be added to the steam chamber 13 . In certain embodiments, the cooling fluid is selected from one of ethanol, butane and mixtures thereof.

The semiconductor wafer stacking structure referred to here generally refers to a three-dimensional structure in which a plurality of semiconductor wafers are stacked through a plurality of interposers and disposed on the base plate 20 . These interposers are stacked into a three-layer structure, and the lower interposer 33 , the middle interposer 32 and the upper interposer 30 are defined from bottom to top, which is helpful for the description of the structure and avoids confusion. In this embodiment, the interposer is selected from one of a ceramic substrate, an aluminum nitride ceramic substrate, an alumina ceramic substrate, a silicon oxide ceramic substrate and a silicon nitride ceramic substrate.

The upper interposer 30 is taken as an example, the central position of the top surface is a working area 40, the working area 40 is a square area, and a group of thermally conductive pillars 43 are arrayed around the square area. By means of etching, laser engraving, stamping and die casting, a top capillary structure 31 is formed on the top surface of the upper interposer 30. The top capillary structure 31 is a plurality of slits staggered in rows and columns, avoiding the group of Thermally conductive post 43 .

Next, see FIG. 7 , the bottom surface of the upper interposer 30 also has a working area 40 , which is composed of a seating area 41 and a group of conductive pillars 42 . The group of conductive pillars 42 surrounds the square seating area 41 , and the group of thermally conductive pillars 43 surrounds the group of conductive pillars 42 . By means of etching, laser engraving, stamping and die casting, a bottom capillary structure 35 is formed on the bottom surface of the upper interposer 30 , and the bottom capillary structure 35 is also a plurality of slits staggered in rows and columns, avoiding the group of conductive pillars 42 and the set of thermally conductive pillars 43 . In addition, the upper interposer 30 is provided with a set of convex parts 36 around it, and two convex parts 36 are separated by a concave part 37 , so the upper interposer 30 has a set of concave parts 37 around it.

From Figs. 5, 6 and 10, the structure of the middle interposer 32 is substantially the same as that of the upper interposer 30, except that the convex portion 36 of the middle interposer 32 is shifted from the convex portion 36 of the upper interposer 30, so that the middle interposer 32 , The concave portions 37 of the upper two interposers are staggered from each other.

The structure of the lower interposer 33 is substantially the same as that of the middle interposer 32 , with the difference that the convex portions 36 and the concave portions 37 of the lower interposer and the middle interposer are also designed by dislocation.

When the lid 11 covers the semiconductor wafer stack structure, the upper, middle and lower interposers 30 , 32 , and 33 contact the network 14 with protrusions 36 , which are arranged in steps from top to bottom. At the same time, the concave portion 37 staggered from the upper interposer 30 to the lower interposer 33 becomes a flow channel 34 , and the flow channel 34 maintains an inclined angle and is connected to the vapor chamber 13 . As such, the semiconductor wafer stack has a set of flow channels 34 around the periphery.

As shown in FIGS. 8 and 9 , the set of thermally conductive pillars 43 penetrates from the upper interposer 30 to the lower interposer 33 through the middle interposer 32 . The thermally conductive pillar 43 is a copper pillar with excellent thermal conductivity. A tin point (not shown) is attached to the end of the copper pillar, which can fuse and bond the corresponding electrical pins 21 of the base plate 20 . In the semiconductor wafer stack structure, the thermally conductive pillars 43 are non-conductive, and have thermal conductivity with the electrical pins 21 .

The semiconductor wafer 44 is located in the seating area 41 . Among them, some electronic circuits (not shown) are arranged inside each interposer, and a power (or signal) is input (or output) between the semiconductor wafer 44 and the group of conductive pillars 42 . The conductive pillars 42 of the upper interposer 30 are connected to the electrical pins 21 of the substrate 20 via the conductive pillars 42 of the middle and lower interposers 32 and 33 ; The posts 42 are connected to the electrical pins 21 of the chassis 20 ; the conductive posts 42 of the lower interposer 33 are directly connected to the electrical pins 21 of the chassis 20 . Therefore, the package structure 10 has conductive properties.

After conduction, the semiconductor chips 44 of each layer operate logically and generate high temperature. The lower interposer 33 is at the bottom of the semiconductor wafer stack structure and accumulates more heat than other interposers.

Heat is transferred from high temperature to low temperature. The heat of the semiconductor wafer 44 is thermally conducted from the upper, middle and lower interposers 30 , 32 and 33 to the cover 11 through the net 14 for heat dissipation to the outside. At the same time, the heat of the semiconductor wafer 44 evaporates the ultrapure water, changes from liquid to gas, and fills the vapor chamber 13 . The steam passes through the bottom capillary structure 35 of the middle interlayer 32 and the top capillary structure 31 of the lower interposer 33, and travels between the middle and lower interposers 32 and 33, and flows from the flow channel 34 along the direction of arrow 50 in Fig. 6. flow, which directly removes heat from the semiconductor wafer 44 portion. The steam between the upper and middle interposers 30 and 32 flows into the steam in the flow channel 34 and flows to the net 14 above the semiconductor wafer stack structure in the direction of arrow 50 in FIG. 6 . The steam flows into the capillary structure 15 through the mesh and contacts the cover 11 to generate heat conduction with the low temperature outside.

As shown in FIG. 10, the cooled water vapor condenses into ultrapure water and adheres to the meshes and the slit-like capillary structure 15 of the mesh 14 according to the surface tension. According to the capillary phenomenon, the ultrapure water spreads to the net 14 along the capillary structure 15 , and flows from the horizontal position inside the cover 11 to the vertical position on the periphery to the bottom plate 20 .

The ultrapure water follows the mesh 14 to the first contact, usually the protrusion 36 of the upper interposer 30 . Under the action of surface tension, the ultrapure water flowing to the top surface of the upper interposer 30 will soak into the capillary structure 31 on the top surface. According to the capillary action, the ultrapure water droplets spread to all the top capillary structures 31 , so as to be distributed on the surface of the upper interposer 30 .

Of course, the rest of the ultrapure water continues to flow under the flow channel 34 , and contacts the convex portion 36 of the intermediate layer 32 along the mesh 14 . Under the guidance of the capillary structure 31 on the top surface, it also diffuses to the top surface of the interposer 32 . The remaining water droplets pass through the concave portion 37 along the mesh 14, flow to the convex portion 36 of the lower interlayer 33, and spread to the entire top surface along the capillary structure 31 on the top surface.

In this way, the ultrapure water undergoes a thermal cycle of liquid phase to gas phase conversion between the set of capillary structures 15, the set of flow channels 34, the top capillary structure 31 and the bottom capillary structure 35, so as to achieve the heat dissipation effect of the semiconductor wafer .

As shown in FIGS. 11 and 12 , the structure of the second embodiment of the package structure 10 of the present invention is substantially the same as that of the first embodiment, except that a set of fasteners 51 couples a set of heat dissipation fins 52 to the cover 11 Externally, the heat dissipation effect of the package structure 10 is improved.

Those skilled in the art can understand and make changes to the above-mentioned embodiments without departing from the broad concept of the present case. Therefore, this case is not limited to the specific embodiments disclosed in the specification, and any modifications made according to the spirit and technical scope of this case should be covered and protected by the text content defined in the scope of the patent application.

10: Package structure

11: Cover

12: Hole

13: Steam Room

14: Net

15: capillary structure

20: Bottom plate

21: Electrical pins

22: Spacer

23: Leak-proof structure

30: Upper interposer

31: Top capillary structure

32: Middle Interposer

33: Lower interposer

34: runner

35: Bottom capillary structure

36: convex part

37: Recess

40: Workspace

41: Sitting area

42: Conductive column

43: Thermal column

44: Semiconductor wafer

50: Arrow

51: Fasteners

52: cooling fins

FIG. 1 is a top view of the first embodiment of the package structure of the present invention. Fig. 2 is a bottom view of the embodiment of Fig. 1 . Figure 3 cuts off the top of the lid and overlooks the interior of the package. Fig. 4 sees through the lid to observe the internal structure of the package structure. Fig. 5 is a cross-sectional view taken along line A-A of Fig. 3. Fig. 6 specifically depicts the flow passage portion of Fig. 5 on an enlarged scale. Figure 7 shows the bottom surface of a single interposer from a bottom view. Figure 8 shows a stacked interposer and semiconductor wafer. Fig. 9 cuts away the package structure to observe the internal structure. Figure 10 depicts the vapor chamber passing through the mesh and capillary structure as part of the thermal cycle. Figures 11 and 12 observe the second embodiment of the packaging structure of the present invention from different angles.

30: Upper interposer

31: Top capillary structure

32: Middle Interposer

33: Lower interposer

34: runner

35: Bottom capillary structure

50: Arrow

Claims (9)

A semiconductor three-dimensional packaging structure with a vapor chamber, comprising: a bottom plate (20); a plurality of semiconductor chips (44) and a plurality of interposers, through which two semiconductor chips (44) are inserted through each interposer, so that the Several semiconductor wafers (44) are stacked on the base plate (20), each of the interposers has a top capillary structure (31) and a bottom capillary structure (35), and each interposer is provided with a plurality of protrusions (36) around the periphery and a plurality of concave parts (37), each of which is between two convex parts (36); a cover (11) inside has a plurality of capillary structures (15) and a plurality of nets (14), the nets (14) Covering the capillary structures (15), when the lid (11) and the bottom plate (20) enclose a vapor chamber (13), the lid (11) covers the semiconductor wafers (44), the The interlayer contacts the meshes (14) with the convex portion (36), the concave portions (37) communicated with each other from top to bottom become a flow channel (34) connected to the vapor chamber (13); and an appropriate amount of cooling The fluid is added into the vapor chamber (13), and liquid is carried out between the capillary structures (15), the flow channels (34), the top capillary structures (31) and the bottom capillary structures (35) The gaseous thermal cycle is converted to achieve the heat dissipation effect of the semiconductor wafers (44). The three-dimensional semiconductor packaging structure with vapor chamber according to claim 1, wherein the concave portions (37) of the interposers from the upper layer to the lower layer are staggered from each other, maintaining the inclined flow channels (34), so that the convexities The parts (36) are arranged in a stepped state from the upper layer to the lower layer. The semiconductor three-dimensional packaging structure with vapor chamber according to claim 1, wherein the cover (11) is made of one of copper, copper alloy and other thermally conductive metals. The semiconductor three-dimensional package structure with vapor chamber according to claim 1, wherein one of copper, copper alloy and other thermally conductive metals is coated on the surface of the cover (11). The three-dimensional semiconductor packaging structure with vapor chamber as claimed in claim 1, wherein the capillary structures (15) are staggered slits formed on the surface of the cover (11) by one of etching, laser engraving, stamping and die casting. . The semiconductor three-dimensional packaging structure with vapor chamber according to claim 1, wherein the cooling fluid is selected from one of ultrapure water, ethanol, butane and mixtures thereof. The three-dimensional semiconductor package structure with vapor chamber as claimed in claim 1, wherein each of the interposers is selected from one of a ceramic substrate, an aluminum nitride ceramic substrate, an alumina ceramic substrate, a silicon oxide ceramic substrate and a silicon nitride ceramic substrate. The three-dimensional semiconductor packaging structure with vapor chamber according to claim 1, wherein a plurality of thermally conductive pillars (43) pass through the stacked interposers in an array. The semiconductor three-dimensional packaging structure with vapor chamber according to claim 1, wherein a plurality of heat dissipation fins (52) are externally combined with the cover (11).

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