TW202310253A - Chip package - Google Patents

Abstract

A chip package includes a stack of chips contained in a vaporization chamber consisting of a cover and a plate. The chips are alternately arranged with intermediate layers. A capillary mechanism is provided on a horizontal portion of an internal face of the cover. Nets are provided on vertical portions of the internal face of the cover. The nets extend around the capillary mechanism. Each of the intermediate layers includes protuberances extending from edges. The protuberances are in contact with the nets. A channel is defined between any adjacent two of the protuberances. The channels travel past the intermediate layers. Coolant is filled in the vaporization chamber. The coolant is turned into vapor from liquid after absorbing heat. The vapor ascends to the cover via the channels. The coolant is returned into liquid from vapor after transferring heat to the cover. The liquid descends to the plate. Thus, the coolant is circulated in the vaporization chamber. Each of the intermediate layers includes a capillary structure to facilitate the circulation of the coolant.

Description

Semiconductor three-dimensional packaging structure with vapor chamber

The invention relates to semiconductor packaging technology, in particular to a three-dimensional packaging structure, which utilizes a vapor chamber or a uniform temperature structure to produce a heat dissipation effect of a semiconductor chip.

A three-dimensional packaging structure is adopted to gather more semiconductor chips together to meet the requirements of small size and strong functions. After being powered on, the semiconductor chip generates high heat, which will delay the computing efficiency and even reduce the service life. How to dissipate heat has become an urgent problem to be solved for semiconductor chips.

In U.S. Patent No. 20200105644, a heat sink is attached to a semiconductor three-dimensional package structure, and a cooling fluid with a lower temperature is continuously replenished to a flow channel to take away heat from the package structure. Although, this water cooling design can improve heat dissipation efficiency. However, the power of the cooling device to promote the flow of cooling fluid comes from a pump, and the bulky cooling device obviously cannot keep up with the advanced technology of miniaturization of packaging structure.

Taiwan Patent No. 202121618 proposes a stacking structure, combined with the heat dissipation structure of Taiwan Patent No. 202002201, a heat conduction structure is added inside the three-dimensional package to improve heat dissipation. Specifically, each layer of the semiconductor chip stack is equipped with a heat dissipation layer. The heat dissipation layer is a thermal interface material with heat conduction efficiency. Through silicon vias or copper pillars and other electrical connection structures, the heat conduction effect of the semiconductor chip is achieved. The disadvantage is that the heat conduction cooling effect is limited. In particular, when stacking multiple layers, the lower layer of semiconductor wafers cannot dissipate heat, and the effect is greatly reduced.

At present, a better solution to the heat dissipation problem is a vapor chamber structure or a uniform temperature structure. The structure of the steam chamber utilizes the thermal cycle of the gas phase and the liquid phase of the cooling fluid to achieve a rapid heat dissipation effect. Therefore, the vapor chamber is used in the three-dimensional packaging technology of semiconductors, which can improve the heat dissipation efficiency of multiple high-performance chips.

For example, Japanese Patent No. 5554444 (publication No. 2015050323) and Taiwan Patent No. 202002031 both mention a cover, which is used in the three-dimensional packaging structure of semiconductors to achieve the heat dissipation effect of the vapor chamber.

Also, in Taiwan Patent No. I672775 (Application No. 106119235), at least one cooling channel is designed in the three-dimensional packaging structure to surround the stacked semiconductor chips. The fluid that undergoes a phase change in the cooling channel takes away the heat of the semiconductor chip and has a heat dissipation effect, so the cooling channel is equivalent to the function of the vapor chamber.

There is also a semiconductor packaging structure and assembly structure, in which a required vapor chamber is provided between the semiconductor wafer and the packaging substrate, the vapor chamber takes away the heat of the semiconductor wafer, and patent applications have been filed in many countries, such as US No. 20200111728 and China No. 111009493 and other cases.

In the aforementioned vapor chamber patents, the vapor chamber structure is indirectly combined with the semiconductor packaging structure by using thermal interface material or encapsulation colloid as a medium. In this way, the thermal conductivity of the medium greatly affects the heat dissipation effect of the vapor chamber structure.

In addition, the public information of US Patent No. 20190393193 discloses a semiconductor package with a vapor chamber function, mainly in a space of an electrical connection structure, and the vapor chamber is arranged between multiple integrated circuits. However, the flow space of the vapor chamber is limited to the narrow space where the integrated circuits are separated from each other, resulting in poor heat dissipation efficiency of the semiconductor package as a whole.

There is also a semiconductor package with an interposer attached to the semiconductor, as disclosed in US Patent No. 7,002,247. Wherein, the interposer has two plates including a core structure such as grooves, and the internal sealed volume constituting the interposer directly contacts the back of the semiconductor, thereby forming a vapor chamber in an attempt to reduce the heat of the semiconductor wafer and achieve a uniform temperature effect. Unfortunately, the semiconductor package only relies on the attachment structure on the surface of the chip, which easily damages the semiconductor chip and relatively weakens the overall supporting structure.

In view of this, the inventor of this case provides a new generation of three-dimensional packaging structure, the main purpose of which is: the vapor chamber structure encapsulates the semiconductor chip and the cooling fluid, allowing the cooling fluid to directly take away the heat of the semiconductor chip, so the heat dissipation effect is more efficient than the previous technology.

Due to the achievement of the above purpose, the three-dimensional semiconductor packaging structure of the present invention includes:

a bottom plate;

A plurality of semiconductor wafers are stacked on the bottom plate through a plurality of intermediary layers, the intermediary layer has a capillary structure on the top surface and a capillary structure on the bottom surface, a group of convex portions are provided on the periphery of the intermediary layer, and a concave portion is separated between the two convex portions;

There is a group of capillary structures and a group of nets on the inside of a cover. The network covers the capillary structures. When the cover combines with the bottom plate to form a vapor chamber, the cover covers all the semiconductor wafers, and all the interposers contact the semiconductor wafers with convex parts. Networking, the recess from the upper interposer to the lower interposer becomes a flow path to the vapor chamber; and

An appropriate amount of cooling fluid is added into the vapor chamber, and a thermal cycle of liquid-to-gas transition is performed between the group of capillary structures, the group of flow channels, the capillary structure on the top surface, and the capillary structure on the bottom surface, so as to achieve the cooling effect of the semiconductor wafer.

In this way, the cover and the bottom plate of the present invention enclose the vapor chamber, and the semiconductor chip and the cooling fluid are encapsulated in the vapor chamber to form a three-dimensional packaging structure. The cooling fluid undergoes a thermal cycle in which the liquid state is converted into a gas state in the vapor chamber, directly taking away the heat of the semiconductor wafer, and the heat dissipation effect is naturally more efficient than the previous technology.

In order to make the purpose, features and advantages of the present invention easy to understand, one or more preferred embodiments will be described in detail as follows in conjunction with the attached drawings.

Next, in conjunction with the accompanying drawings, describe the embodiment of this case. In the drawings, the same or similar structures or units are denoted by the same reference numerals. It is foreseeable that the described embodiments are only some examples of this case, not all embodiments. Other embodiments that can be deduced based on the examples described above, or structures that can be modified or changed as needed, all belong to the scope of protection of this case.

In the following descriptions, directional terms such as "upper", "lower", "left", "right", "front", "rear", "inner", "outer" and "side" refer only to the directions of the drawings . The use of directional terms is for a better and clearer description and understanding of this case, and does not express or imply that the device or component described must have a specific orientation, structure, and operation, so it cannot be understood as a limitation on the technical content of this case.

In the following descriptions, "mounted", "connected", "connected" or "set on" should be interpreted in a broad sense, such as fixed connection, detachable connection, integral connection, mechanical connection, unless there are specific and clear specifications and limitations , directly connected, indirectly connected, or internally connected between two elements. Those skilled in the field of this case can understand the specific meanings of the above terms in each embodiment and even this case by virtue of common knowledge or experience.

Unless otherwise specified, in the following description, "plurality" means two or more.

FIG. 1 is a top view showing a first embodiment of a package structure 10 of the present invention. Above the packaging structure 10 is a cover 11, the cover 11 is a cube, and each of the four corners of the cube has a hole 12.

In this embodiment, the cover 11 is made of one of copper, copper alloy and other heat-conducting metals. In some embodiments, the surface of the cover 11 is made of one of copper, copper alloy and other thermally conductive metals coated with a polymer material, which also has thermal conductivity.

Figure 2 is a bottom view. Below the packaging structure 10 is a base plate 20 with the same shape as the cover 11. A set of electrical pins 21 are arrayed at the center of the base plate 20. The set of electrical pins 21 are arranged in a square ring. . Four spacers 22 are formed on four corners of the bottom plate 20 .

As shown in Figures 4 and 10, the packaging structure 10 is cut into two parts. It can be seen from the perspective view that there are five surfaces inside the cover 11 enclosing an inner space. The bottom plate 20 closes the opening of the cover 11 , and the two are combined to form a sealed vapor chamber 13 . An anti-leakage structure 23 is between the bottom plate 20 and the cover 11 to prevent the steam chamber 13 from leaking.

In this embodiment, a group of capillary structures 15 are etched inside the cover 11 . The capillary structure 15 is a plurality of staggered slits formed on one of the five inner sides of the cover 11 . In this way, the group of capillary structures 15 covers the five inner sides of the cover 11 . In some embodiments, the set of capillary structures 15 is formed on the surface of the cover 11 by means of one of laser engraving, stamping and die-casting.

In addition, a group of metal nets 14 are bonded to the inside of the cover 11 . Through one of welding or adhesive means, the mesh 14 is fixed to one of the five inner sides of the cover 11 without damaging or blocking the capillary structure 15 of this side. In this way, the netting 14 shields the capillary structure 15 inside the cover 11 .

As shown in FIGS. 3 and 5 , a semiconductor chip stack structure and a proper amount of cooling fluid (not shown) are packaged in the vapor chamber 13 of the packaging structure 10 .

In this embodiment, the cooling fluid is ultrapure water. The ultrapure water has a thermal conductivity, and in the steam chamber 13 with a fixed volume, the change of liquid phase and gas phase is carried out, so the steam chamber 13 can be filled with an appropriate amount of ultrapure water. In some embodiments, the cooling fluid is selected from one of ethanol, butane and mixtures thereof.

The semiconductor chip stacking structure referred to herein generally refers to a three-dimensional structure in which multiple semiconductor chips are stacked through multiple intermediary layers and disposed on the bottom plate 20 . These interposers are stacked into a three-layer structure, and the lower interposer 33 , the middle interposer 32 , and the upper interposer 30 are defined from bottom to top, which helps to describe the structure and avoid confusion. In this embodiment, the intermediary layer is selected from one of ceramic substrates, aluminum nitride ceramic substrates, alumina ceramic substrates, silicon oxide ceramic substrates, and silicon nitride ceramic substrates.

Taking the interposer 30 as an example, the central position of the top surface is a working area 40 , the working area 40 is a square area, and a group of heat conducting columns 43 are arrayed around the square area. Through etching, laser engraving, stamping and die-casting, a top surface capillary structure 31 is formed on the top surface of the upper interposer 30. The top surface capillary structure 31 is a plurality of slits interlaced in rows and columns, avoiding the group Thermally conductive column 43.

Then see FIG. 7 , the upper interposer 30 also has a working area 40 on the bottom surface, which is composed of a seating area 41 and a group of conductive pillars 42 . The group of conductive pillars 42 surrounds the square seating area 41 , and the group of thermally conductive pillars 43 surrounds the group of conductive pillars 42 . Through etching, laser engraving, stamping and die-casting, a bottom capillary structure 35 is formed on the bottom surface of the upper interposer 30, and the bottom capillary structure 35 is also a plurality of slits interlaced in rows and columns, avoiding the group of conductive pillars 42 and the group of heat conducting columns 43 . In addition, the upper interposer 30 has a set of protrusions 36 around it, and two protrusions 36 are separated by a recess 37 , so there is a set of recesses 37 around the upper interposer 30 .

From Figures 5, 6, and 10, the structure of the middle interposer 32 is roughly the same as that of the upper interposer 30, the difference being that the protrusions 36 of the middle interposer 32 are offset from the protrusions 36 of the upper interposer 30, so that , The recesses 37 of the upper two interlayers are staggered from each other.

The structure of the lower interposer 33 is substantially the same as that of the middle interposer 32 , the difference lies in that the protrusions 36 and the recesses 37 of the lower and middle interposers are also designed in a dislocation manner.

When the cover 11 covers the semiconductor chip stack structure, the upper, middle and lower interlayers 30 , 32 , 33 contact the networking 14 with the protrusions 36 , and the protrusions 36 are arranged in steps from top to bottom. At the same time, the concave portion 37 staggered from the upper interposer 30 to the lower interposer 33 becomes a channel 34 , and the channel 34 maintains an inclined angle and is connected to the vapor chamber 13 . In this way, a group of flow channels 34 are formed around the semiconductor wafer stack structure.

As shown in FIGS. 8 and 9 , the group of thermally conductive columns 43 penetrates from the upper interposer 30 through the middle interposer 32 to the lower interposer 33 . The heat conduction column 43 is a copper column with excellent thermal conductivity, and a tin point (not shown) is attached to the end of the copper column, which can melt and bond the corresponding electrical pin 21 of the base plate 20 . In the stacked semiconductor chip structure, the heat conduction column 43 is non-conductive, and has a heat conduction function with the electrical pin 21 .

The semiconductor wafer 44 is located in the seating area 41 . Wherein, some electronic circuits (not shown) are arranged inside each interposer, and an electric power (or signal) is input (or output) between the semiconductor wafer 44 and the group of conductive pillars 42 . The conductive posts 42 of the upper interposer 30 are connected to the electrical pins 21 of the bottom plate 20 via the conductive posts 42 of the middle and lower interposers 32 and 33; The posts 42 are connected to the electrical pins 21 of the base plate 20 ; the conductive posts 42 of the lower interposer 33 are directly connected to the electrical pins 21 of the base plate 20 . Therefore, the package structure 10 has a conductive property.

After conduction, the semiconductor wafer 44 of each layer operates logically and generates high temperature. The lower interposer 33 is at the bottom of the stacked structure of semiconductor wafers and accumulates more heat than other interposers.

Heat transfer from high temperature to low temperature. The heat of the semiconductor wafer 44 is conducted from the upper, middle and lower interlayers 30 , 32 , 33 through the mesh 14 to the cover 11 to dissipate heat to the outside. Simultaneously, the heat of the semiconductor wafer 44 evaporates the ultrapure water, which is converted from a liquid state to a gaseous state, and fills the vapor chamber 13 . The steam passes through the bottom capillary structure 35 of the middle interposer 32 and the top capillary structure 31 of the lower interposer 33, and travels between the middle and lower interposers 32 and 33, and flows along the direction of the arrow 50 in FIG. 6 through the flow channel 34. The flow directly takes away the heat of the semiconductor wafer 44 part. The steam between the upper and middle interposers 30, 32 flows into the flow channel 34, and flows to the net 14 above the semiconductor wafer stack structure in the direction of the arrow 50 in FIG. 6 . The steam flows into the capillary structure 15 through the mesh, and contacts the cover 11 to generate heat conduction with the low temperature outside.

As shown in Fig. 10, the cooled water vapor condenses into ultrapure water, which adheres to the mesh and slit-like capillary structure 15 of the net 14 according to the surface tension. According to the capillary phenomenon, the ultrapure water spreads to the net 14 along the capillary structure 15 , and flows from the horizontal position inside the cover 11 to the vertical position around the cover 11 to the bottom plate 20 .

The ultrapure water travels along the mesh 14 to the first contact, typically the bump 36 of the upper interposer 30 . Under the effect of surface tension, the ultrapure water flowing to the top surface of the upper intermediate layer 30 will soak into the capillary structure 31 on the top surface. According to capillary action, the ultrapure water droplets diffuse to the entire capillary structure 31 on the top surface, thereby being distributed on the surface of the upper intermediate layer 30 .

Of course, the rest of the ultrapure water continues to flow below the flow channel 34 , and contacts the convex portion 36 of the middle intermediary layer 32 along the net 14 . Guided by the capillary structure 31 on the top surface, it will also diffuse to the top surface of the middle interposer 32 . The remaining water droplets pass through the concave portion 37 along the net 14 , flow to the convex portion 36 of the lower intermediary layer 33 , and diffuse along the capillary structure 31 on the top surface to the entire top surface.

In this way, the ultrapure water performs a thermal cycle of liquid-phase conversion to gas phase between the group of capillary structures 15, the group of flow channels 34, the top surface capillary structure 31 and the bottom surface capillary structure 35, so as to achieve the heat dissipation effect of the semiconductor wafer. .

As shown in Figures 11 and 12, the structure of the second embodiment of the package structure 10 of the present invention is substantially the same as that of the first embodiment, the difference lies in that a group of fasteners 51 combine a group of cooling fins 52 with the cover 11 Externally, the heat dissipation effect of the package structure 10 is improved.

Those skilled in the art can understand and make changes to the above-disclosed embodiments without departing from the broad concepts of the present disclosure. Therefore, this case is not limited to the specific embodiments disclosed in the specification, and all modifications made according to the spirit and technical scope of this case shall be covered and protected by the textual content defined in the scope of the patent application.

10: Package structure 11: cover 12: hole 13: Steam room 14: net 15: capillary structure 20: Bottom plate 21: Electrical pin 22: spacer 23: leak-proof structure 30: Upper intermediary layer 31: capillary structure on the top surface 32: Middle Interposer 33: Lower intermediary layer 34: Runner 35: Bottom capillary structure 36: convex part 37: concave part 40: work area 41: Seating area 42: Conductive column 43: thermal column 44: Semiconductor wafer 50: arrow 51: Fasteners 52: cooling fins

FIG. 1 is a top view of the first embodiment of the packaging structure of the present invention. Fig. 2 is a bottom view of the embodiment of Fig. 1. Figure 3 cuts away the top surface of the lid and overlooks the internal composition of the package structure. Figure 4 sees through the cover to observe the internal structure of the package structure. Fig. 5 is a sectional view cut along line A-A of Fig. 3 . Fig. 6 specifically depicts the enlarged scale of the flow path in Fig. 5. FIG. 7 observes the bottom surface of a single interposer from an upward view. Figure 8 shows a stacked interposer and semiconductor wafer. Figure 9 cuts open the package structure to observe the internal structure. Figure 10 depicts the vapor chamber as part of the thermal cycle through the mesh and capillary structure. Figures 11 and 12 observe the second embodiment of the packaging structure of the present invention from different angles.

30: Upper intermediary layer

31: capillary structure on the top surface

32: Middle Interposer

33: Lower intermediary layer

34: Runner

35: Bottom capillary structure

50: arrow

Claims (9)

A semiconductor three-dimensional packaging structure with a vapor chamber, comprising: a bottom plate (20); A plurality of semiconductor wafers (44) are stacked on the base plate (20) through a plurality of intermediary layers, the intermediary layer has a top surface capillary structure (31) and a bottom surface capillary structure (35), and the periphery of the intermediary layer has a A group of convex parts (36), two convex parts (36) separated by a concave part (37); A cover (11) has a set of capillary structures (15) and a set of nets (14) inside, and the set of nets (14) covers the capillary structures (15), when the cover (11) combines with the bottom plate (20) to form a Vapor chamber (13), the cover (11) covers all semiconductor wafers (44), and all interposers contact the network (14) with convex parts (36), from the upper interposer (30) to the lower interposer The recess (37) of (33) becomes a flow channel (34) connected to the vapor chamber (13); and An appropriate amount of cooling fluid is added into the vapor chamber (13), and the liquid state is converted between the group of capillary structures (15), the group of flow channels (34), the top surface capillary structure (31) and the bottom surface capillary structure (35) The heat circulation in the gaseous state achieves the cooling effect of the semiconductor wafer (44). The three-dimensional packaging structure for semiconductors with vapor chambers as described in Claim 1, wherein the recesses (37) from the upper interposer (30) to the lower interposer (33) are staggered to maintain an inclined flow channel (34), so that the upper layer The protrusions (36) from the intermediary layer (30) to the lower intermediary layer (33) are arranged in a stepped state. The semiconductor three-dimensional package structure with a vapor chamber according to claim 1, wherein the cover (11) is made of one of copper, copper alloy and other heat-conducting metals. The semiconductor three-dimensional package structure with a vapor chamber according to claim 1, wherein one of copper, copper alloy and other heat-conducting metals is coated on the surface of the cover (11). According to claim item 1, the semiconductor three-dimensional package structure with a vapor chamber, wherein the group of capillary structures (15) are staggered slits formed on the cover (11) by means of etching, laser engraving, stamping and die-casting )surface. The three-dimensional semiconductor package structure with a vapor chamber as claimed in Claim 1, wherein the cooling fluid is selected from one of ultrapure water, ethanol, butane and mixtures thereof. According to claim 1, the semiconductor three-dimensional packaging structure with a vapor chamber, wherein the intermediary layer is selected from one of ceramic substrates, aluminum nitride ceramic substrates, alumina ceramic substrates, silicon oxide ceramic substrates, and silicon nitride ceramic substrates. The semiconductor three-dimensional packaging structure with a vapor chamber according to Claim 1, wherein a group of heat conducting columns (43) passes through all stacked interlayers in an array. The semiconductor three-dimensional packaging structure with a vapor chamber as claimed in Claim 1, wherein a group of heat dissipation fins (52) are combined outside the cover (11).

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