CN105938821B

CN105938821B - Thermally enhanced heat sink

Info

Publication number: CN105938821B
Application number: CN201610117616.6A
Authority: CN
Inventors: 林柏尧; 林文益; 吕学德; 游明志
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2015-03-03
Filing date: 2016-03-02
Publication date: 2020-04-28
Anticipated expiration: 2036-03-02
Also published as: CN105938821A

Abstract

A three-dimensional integrated circuit (3DIC) includes a first substrate and a heat dissipation structure embedded in the first substrate. The 3DIC also comprises a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreading structure. The 3DIC also comprises a plurality of memory cells on the die, wherein the die is interposed between the plurality of memory cells and the first substrate, and the plurality of memory cells are thermally connected to the heat spreading structure through the die. The 3DIC also comprises an external cooling unit located on the plurality of memory units, wherein the plurality of memory units is interposed between the die and the external cooling unit, and the die is thermally connected to the external cooling unit through the plurality of memory units. Embodiments of the present invention relate to thermally enhanced heat sinks.

Description

Thermally enhanced heat sink

Priority declaration

This application is a continuation-in-part application of U.S. application No. 12/782,814, 12/782,814, filed on 19/2010, which prior application (i.e., U.S. application No. 12/782,814) claims priority to U.S. provisional application No. 61/229,958, filed on 30/7/2009, the entire contents of which are incorporated herein by reference.

Technical Field

The present invention relates generally to a heat spreader and, more particularly, to a thermally enhanced heat spreader embedded in a substrate for flip chip and 3DIC packaging.

Background

As the packaging density of microelectronic devices increases with technological advances, manufacturers continue to shrink the size of microelectronic devices to meet the demand for smaller electronic devices, such as three-dimensional integrated circuit (3DIC) packages, or package-on-package (PoP). Another trend in modern microelectronic devices is to increase the use of higher power consuming circuits, such as in modern CPU chips or application processors. To accommodate more densely packed and higher power consumption microelectronic devices, it is desirable to improve the thermal dissipation performance of 3DIC packages using Through Substrate Vias (TSVs) or PoP technology.

Heat sinks, sometimes referred to as heat spreaders, are typically made of materials with higher thermal conductivity, such as copper, which has been used to meet the need for improved heat dissipation in 3DIC packages. In some cases, the 3DIC package comprises at least one memory chip on a logic chip. Although copper, which has a relatively high thermal conductivity, is a common solution for lids for heat sinks on the exterior surface of 3DIC packages, heat dissipation between memory chips and logic chips presents a thermal shrinkage problem.

The increased use of more densely packed microelectronic devices, such as memory chips on logic chips, causes localized areas between chips or on chips with relatively high heat build-up (e.g., "hot spots") to cause degradation of electrical performance or even device failure.

Disclosure of Invention

According to an embodiment of the present invention, there is provided a three-dimensional integrated circuit (3DIC) including: a first substrate; a heat spreader embedded in the first substrate; a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreader; a plurality of memory cells located on the die, wherein the die is located between the plurality of memory cells and the first substrate, and the plurality of memory cells are thermally connected to the heat spreader through the die; and an external cooling unit on the plurality of memory units, wherein the plurality of memory units are located between the die and the external cooling unit, and the die is thermally connected to the external cooling unit through the plurality of memory units.

There is also provided, in accordance with another embodiment of the present invention, a three-dimensional integrated circuit (3DIC) including: a first substrate; a heat dissipation structure embedded in the first substrate, wherein the heat dissipation structure comprises: a heat spreader, a Thermal Interface Material (TIM) over at least a first surface of the heat spreader, and a plurality of first vias in contact with the thermal interface material; a die electrically connected to the first substrate, wherein the plurality of first vias are connected to the die; a plurality of conductive vias electrically connected to the die, wherein at least one conductive via of the plurality of conductive vias extends through the first substrate between the first portion of the heat spreader and the second portion of the heat spreader; a plurality of conductive elements on the first substrate, wherein the plurality of conductive elements are on a surface of the first substrate opposite the die and are electrically connected to corresponding ones of the plurality of conductive vias.

According to yet another embodiment of the present invention, there is also provided a method of forming a three-dimensional integrated circuit (3DIC), the method comprising: patterning a substrate to define at least one cavity in the substrate; embedding a heat spreader in the at least one cavity, wherein a portion of the substrate extends through the heat spreader; defining a plurality of vias in the substrate, wherein the plurality of vias are connected to the heat spreader; defining a plurality of conductive vias in the substrate, wherein at least one conductive via of the plurality of conductive vias extends through the portion of the substrate that extends through the heat spreader; and bonding a die on the substrate, wherein the die is connected to the plurality of vias and the die is electrically connected to the plurality of conductive vias.

Drawings

The features, aspects, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which:

fig. 1 is a cross-sectional view of a microelectronic package having a heat spreader in accordance with at least one embodiment.

Fig. 2 is an expanded view of fig. 1.

Fig. 3 is a cross-sectional view of a microelectronic package having a heat spreader in accordance with at least one embodiment.

Fig. 4A is a cross-sectional view of a three-dimensional integrated circuit (3DIC) including a heat spreader, according to some embodiments.

Fig. 4B is a cross-sectional view of a 3DIC including a heat spreader according to some embodiments.

Fig. 4C is a cross-sectional view of a 3DIC including a heat spreader according to some embodiments.

Fig. 5A is a cross-sectional view and a top view of a 3DIC including a heat spreader according to some embodiments.

Fig. 5B is a cross-sectional view and a top view of a 3DIC including a heat spreader according to some embodiments.

Fig. 6A is a cross-sectional view and a top view of a 3DIC including a heat spreader according to some embodiments.

Fig. 6B is a cross-sectional view and a top view of a 3DIC including a heat spreader according to some embodiments.

Fig. 7A is a cross-sectional view of a 3DIC including a heat spreader according to some embodiments.

Fig. 7B is a cross-sectional view and a top view of a 3DIC including a heat spreader according to some embodiments.

Fig. 7C is a cross-sectional view and a top view of a 3DIC including a heat spreader according to some embodiments.

Fig. 8A-8J are cross-sectional views of a 3DIC including a heat spreader at various stages of fabrication according to some embodiments.

Detailed Description

In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. However, one of ordinary skill in the art will recognize that embodiments may be practiced without these specific details. In some instances, well-known structures and processes are not described in detail to avoid unnecessarily obscuring the embodiments.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale, and, of course, are merely for purposes of illustration.

Fig. 1 is a cross-sectional view of a microelectronic package 5 having a heat spreader in accordance with at least one embodiment. The microelectronic package 5 may include a die 20 having a first surface containing a plurality of electrical contacts in electrical communication with active circuitry for a predetermined application and a second surface generally opposite the first surface. The first surface of the die 20 may be mounted by flip-chip mounting the first surface of the die 20 with the substrate 10 using a bonding member such as a copper pillar or solder bump 30 to electrically connect with the carrier substrate 10. Suitable materials for substrate 10 include, but are not limited to, epoxy-bonded glass fibers and organic substrates (e.g., including a core layer composed of glass epoxy or glass polyimide-based copper traces and resin). An underfill material 40, such as an epoxy, may fill and seal in the gap between the die 20 and the substrate 10, encapsulating the solder bumps 30. The underfill material 40 provides mechanical support for the bonding members (e.g., solder bumps), electrical isolation, and protects the active circuitry from the environment. Although not shown, the substrate 10 may also electrically connect the die 20 to an external circuit or printed circuit board via solder balls or via sockets or via other interconnection schemes.

Microelectronic package 5 may also include a Thermal Interface Material (TIM)50 disposed in thermally conductive contact with the second surface of die 20. A heat sink 60 may be placed in thermally conductive contact with the thermal interface material 50. Providing the thermal interface material 50 as an interface between the die 20 and the heat spreader 60 facilitates various aspects including, but not limited to, improving thermal conductivity of the completed microelectronic package 5 and reducing the risk of die damage. Since the surfaces of the die 20 and the heat spreader 60 are not flat, directly juxtaposing the heat spreader 60 to the die 20 will result in an increase in the thermal resistance of the composite assembly. A suitable thermal interface material 50 is interposed between and in uniform contact with the heat spreader 60 and the surface of the die 20 to enhance thermal conductivity. Furthermore, die damage may be elevated due to variations in the thickness of the heat spreader 60 and the die 20, and in some cases, cause excessive stress of the heat spreader 60 to the die 20. Thus, providing the thermal interface material 50 between the heat spreader 60 and the die 20 relieves the heat spreader 60 from exerting pressure on the die 20. When disposed between the heat spreader 60 and the die 20, a suitable thermal interface material 50 has high thermal conductivity and improves thermal contact. Examples of suitable thermal interface materials 50 include, but are not limited to, thermal grease such as silver filled epoxy, polymer solder hybrid thermal interface materials, and indium foil. The thickness of the thermal interface material 50 will vary depending on the performance requirements of the bond pad 20. In one embodiment, the thickness of the thermal interface material 50 ranges from about 50 microns to about 100 microns.

Still referring to fig. 1, a heat sink 60 is disposed in thermally conductive contact with the thermal interface material 50. The heat sink 60 includes a cover 61 having an internal vapor chamber 65 defined therein by an outer wall or top wall 62 and an inner wall or bottom wall 64, the bottom wall 64 being attached to the top wall 62 (along their common edges) to hermetically seal the chamber 65 at their interface of engagement. According to an aspect, the steam chamber 65 extends transversely and longitudinally through the cover 61. In fig. 1, the longitudinal direction is the horizontal direction and the transverse direction is in the plane of the figure. In one embodiment, the top wall 62 and the bottom wall 64 comprise plates of a substantially uniform thickness of thermally conductive material and are spaced apart by about 0.5mm to about 1mm to form a void space or vapor chamber 65 therebetween. In some embodiments, the depth and/or width of the vapor chamber 65 may vary, for example narrowing or widening in a particular direction.

The two-phase vaporizable liquid remains in the chamber 65 and serves as the working fluid WF for the radiator 60. Working fluid WF may include freon, water, ethanol, or similar liquid capable of evaporating and possessing a relatively high latent heat to dissipate heat from die 20.

The lower coefficient of thermal expansion of the cover 61 is substantially similar to the lower coefficient of thermal expansion of the carrier substrate 10. According to one embodiment, the lid 61, including the top wall 62 and the bottom wall 64, is made of a material having a low Coefficient of Thermal Expansion (CTE), such as copper, a copper alloy, copper tungsten (CuW), or silicon aluminum carbide (AlSiC). Other suitable materials may be used for the cover 61 as long as the material possesses at least a low coefficient of thermal expansion and a high thermal conductivity. The thickness of the cover 61 depends on several factors including, but not limited to, the rate of heat dissipation of the die 20, the thermal conductivity of the heat dissipating material, the presence of an external heat sink, the desired size of the finished microelectronic package 5, and the surface area of the die 20.

The cover 61 is mounted to the substrate 10 by an attachment frame 70, the attachment frame 70 serving to support the cover 61 over the substrate 10 and the die 20. The height of the attachment frame 70 is selected so that there is a gap between the surface of the cover 61 and the substrate 10. The top surface of the substrate 10 is dimensioned to receive at least the die 20. To prevent delamination of the heat spreader 60 from the substrate 10, the lower coefficient of thermal expansion of the attachment frame 70 is substantially similar to the lower coefficient of thermal expansion of the carrier substrate 10. According to one embodiment, the attachment frame 70 comprises a material having a low Coefficient of Thermal Expansion (CTE), such as, for example, copper, a copper alloy, copper tungsten (CuW), or silicon aluminum carbide (AlSiC). Other suitable materials may be used for the attachment frame 70 as long as the material possesses at least a low coefficient of thermal expansion. The attachment frame 70 may be configured in different ways, including but not limited to the illustration shown in FIG. 1 and may be configured in different forms or shapes and is not limited to the description in FIG. 1.

The cover 61 is fixedly secured to the attachment frame 70 by one or more fastening means 80. The fastening means 80 may comprise rivets, screws, solder, adhesive or other means for fastening the cover 61 to the attachment frame 70. The attachment frame 70 is mounted to the substrate by an adhesive 75.

Fig. 2 depicts an expanded view of a microelectronic package 5 including a heat spreader 60, according to some embodiments.

Fig. 3 is a cross-sectional view of a microelectronic package 5 having a heat spreader 60, according to another embodiment. Instead of fastening the cover 61 to the substrate 10 with the attachment frame 70, the cover 61 itself serves as a securing mechanism and as a support for the cover 61 over the substrate 10 and the die 20. The cover 61 includes a mounting flange 72 formed along the peripheral edge of the cover 61 or on all sides of the cover 61 for securing the cover 61 to the substrate. The mounting flange 72 may be configured in other forms or shapes than those shown in fig. 3.

To prevent delamination of the heat spreader 60 from the substrate 10, the lower coefficient of thermal expansion of the mounting flange 72 is substantially similar to the lower coefficient of thermal expansion of the carrier substrate 10. According to one embodiment, the mounting flange 72 comprises a material having a relatively low Coefficient of Thermal Expansion (CTE), such as, for example, copper, a copper alloy, copper tungsten (CuW), or silicon aluminum carbide (AlSiC), copper silicon carbide (CuSiC). Other suitable materials may be used for the mounting flange 72, so long as the material possesses at least a low coefficient of thermal expansion. The mounting flange is secured to the substrate 10 by an adhesive 75.

As shown in fig. 1 and 2, a substantially flat absorption layer 67 is provided in the chamber 65, the absorption layer 67 being for receiving the working fluid WF. According to one embodiment, the absorbent layer 67 is disposed substantially along the interior or inner sidewall of the chamber 65. In some embodiments, the absorbent layer 67 is disposed substantially along the inner surfaces of the top wall 62 and the bottom wall 64 of the cover 61. The absorption layer 67 is made by weaving a metal wire having a large number of pores (not shown) therein to generate a capillary force for transporting the working fluid WF. Alternatively, the absorber layer 67 may be made by other methods (e.g., sintering metal powder). In some embodiments, the absorbent layer may have an average thickness of about 0.1mm to about 0.5 mm.

In operation, as die 20 (or other electronic component) held in thermal contact with the heat sink operates and generates heat, working fluid WF contained in absorbing layer 67 corresponding to the location of the thermal contact is heated and evaporated. The vapor V then diffuses to fill the vapor chamber 65, and wherever the vapor V comes into contact with the colder surface of the chamber 65, the vapor V releases its latent heat of vaporization and condenses to a liquid. The condensate flows back to the thermal contact location by capillary forces generated by the absorbent layer 67. The condensate then frequently evaporates and condenses to form a cycle to remove heat generated by the die 20 or other electronic components. This structure effectively spreads the thermal energy throughout the heat sink 60 so that the thermal energy can be removed or dissipated, for example, by a conventional finned heat sink or pipe attached to the top wall 62 of the cover 61.

Accordingly, aspects of the heat spreader 60 provide a flip-chip microelectronic package 5 having enhanced ability to spread heat generated by the die 20 (or other electronic components) at hot spots on the device to a larger surface area. It should be understood that the heat sink 60 may vary widely from one design to another. It should also be understood that the cover 61 of the heat sink is not limited to any one of the cover configurations shown in the figures.

Fig. 4A is a cross-sectional view of a three-dimensional integrated circuit (3DIC)400 including a heat spreader 60 according to some embodiments. The 3DIC400 includes similar components as the package 5 (fig. 1). Like elements have like reference numerals. The 3DIC400 comprises a stack 410 of memory cells electrically connected by conductive paths 415. The external cooling unit 420 is thermally connected to the stack 410 of storage units. The stack 410 of memory cells is electrically and thermally connected to the die 20. The die 20 is connected to the heat spreader 60 through the TIM50 by vias 430. In some embodiments, the heat spreader 60, TIM50, and via 430 are collectively referred to as a heat spreading structure. A Through Substrate Via (TSV)440 extends through the substrate 450 to provide an electrical connection between the die 20 or stack of memory cells 410 and the conductive bump 460. Heat spreader 60 is connected to conductive bump 460 through TIM 50. The substrate 470 is connected to the substrate 450 by conductive bumps 460. The portion of substrate 450 between die 20 and heat spreader 60 is wiring layer 480. Routing layer 480 includes electrical routing paths to allow signals to propagate from conductive bumps 460 to die 20 or stack 410 of memory cells. The routing layer 480 includes a plurality of redistribution layers (RDLs) 485 that connect the conductive bumps 460 to the stack 410 of dies 20 or memory cells to facilitate signal transmission between various devices within the 3DIC 400.

Conductive paths 415 provide paths for thermal conduction between individual memory cells of stack 410 of memory cells. The heat spreader 60 is configured to absorb thermal energy through the vias 430 and to transfer the thermal energy throughout the substrate 450 or into the conductive bumps 460. In some embodiments, substrate 450 comprises an organic material having a low thermal conductivity. Smaller electronic devices such as mobile communication devices or tablet computers are manufactured using organic material substrates. Effective control of thermal energy helps to increase the useful life and accurate operation of smaller electronic devices. In some embodiments, the heat spreader 60 is also configured to transfer thermal energy to the substrate 470 through the electrically conductive element 460.

The area of the heat spreader 60 is larger than the area of the die 20. In some embodiments, the area of the heat spreader 60 is greater than about twice the area of the die 20. In some embodiments, the ratio of the area of the heat spreader 60 to the area of the die 20 is in the range from about 2 to about 4. If the ratio of the area of the heat spreader 60 to the area of the die 20 is too small, the heat spreader may not effectively dissipate heat from the die. If the ratio of the area of the heat spreader 60 to the area of the die 20 is too large, the overall size of the 3DIC400 is increased without a significant increase in heat dissipation capability. In some embodiments, the distance S between the top surface of the heat sink 60 and the bottom surface of the heat sink 60 ranges from about 0.2mm to about 1.0mm to provide sufficient volume for fluid evaporation to effectively conduct heat and avoid unnecessarily increasing the size of the 3DIC 400. In some embodiments, the absorber layer 67 (fig. 1) of the heat spreader 60 in the 3DIC400 has an average thickness of about 0.1mm to about 0.25mm to provide sufficient fluid transfer through the heat spreader 60 and avoid unnecessarily increasing the size of the 3DIC 400.

The external cooling unit 420 is configured to dissipate thermal energy from the stack 410 of storage units on the opposite side of the heat sink 60. In some embodiments, the external cooling unit 420 includes fins for dissipating radiant heat to the ambient environment. In some embodiments, the external cooling unit 420 comprises at least one thermally conductive plate for transferring thermal energy to the surrounding environment. In some embodiments, the external cooling unit 420 includes another suitable heat transfer structure to help reduce the thermal energy generated by the stack 410 of storage units. The 3DIC400 has an increased capacity to dissipate heat generated by the stack 410 of dies and memory units as compared to a 3DIC that does not include a heat spreader located on a side of the dies 20 opposite the external heating unit 420. In some cases, in a 3DIC that does not include a heat spreader 60, the difference between the temperature of the memory unit of the stack of memory units 410 closest to the external cooling unit 420 and the temperature of the die 20 is greater than 20 degrees celsius. In some cases, the temperature difference is between 20 degrees celsius and 30 degrees celsius. In some cases, the high temperature difference results in operating the die 20 at a temperature above the desired operating temperature range. In contrast, the temperature difference between the memory unit of the stack 410 of memory units in the 3DIC400 that is closest to the external cooling unit 420 and the die 20 is less than about 17 degrees celsius. In some cases, the temperature difference is between about 10 degrees celsius and about 15 degrees celsius. The reduced temperature of the die 20 in the 3DIC400 facilitates operating the stack 410 of die 20 and memory units within a desired temperature operating range to increase reliability as compared to a 3DIC that does not include the heat spreader 60. For example, in some embodiments, the devices within the 3DIC400 are designed to operate within a preferred operating temperature ranging from about 85 degrees celsius to about 105 degrees celsius. A temperature difference greater than 20 degrees celsius means that at least a portion of the devices within the operational 3DIC will be at a temperature outside of the preferred operating temperature. As a result, the reliability of the 3DIC will be reduced. The heat spreader 60 within the 3DIC helps to maximize the number of devices within the 3DIC400 operating within a preferred operating temperature range by reducing the temperature difference at various points within the 3 DIC.

An enlarged portion of stack 410 of memory cells is included in fig. 4A. The stack of memory cells 410 includes a plurality of individual memory cells connected by conductive elements 415b, the conductive elements 415b being part of the conductive paths 415. In some embodiments, conductive elements 415b comprise micro-bumps, copper pillars, or other suitable conductive elements. As part of the conductive path 415, vias 415a extend through individual memory cells of the stack 410 of memory cells and are connected together by conductive elements 415b between memory cells of the stack of memory cells. The conductive paths 415 provide paths for electrical signals to be transferred between the memory cells and the die 20 as well as for thermal conduction. In some embodiments, the stack of memory cells 410 includes Random Access Memory (RAM) such as dynamic RAM (dram), static RAM (sram), flash memory, magnetoresistive memory, or other suitable memory types. In some embodiments, stack 410 of memory cells is replaced with a different type of device, such as a logic circuit device or other device similar to die 20.

The external cooling unit 420 is configured to transfer heat generated in the stack 410 of memory units and the die 20 to the external environment. In some embodiments, the area of the external cooling unit 420 is larger than the area of the die 20 or the stack 410 of memory cells. In some embodiments where there is no electrical connection on the surface of the substrate 470 opposite the stack of memory cells 410, the external cooling unit 420 is located on the side of the stack of memory cells 410 opposite the heat sink 60 and on the side of the substrate 470 opposite the heat sink. In some embodiments, the structure of the external cooling unit 420 opposite the die 20 on the stack 410 of memory cells is the same as the structure of the external cooling unit opposite the die on the substrate 470. In some embodiments, the structure of the external cooling unit 420 opposite the die 20 on the stack 410 of memory cells is different from the structure of the external cooling unit opposite the die on the substrate 470.

The vias 430 comprise a thermally conductive material. In some embodiments, vias 430 comprise copper, tungsten, or another suitable thermally conductive material. In some embodiments, vias 430 are configured to propagate electrical signals from die 20 to substrate 450. The density of the vias 430 is greater than 3%. The density of the vias 430 is defined by the total area of the vias located under the die 20 divided by the total area of the die 20. In some embodiments, the density of the through-holes 430 ranges from about 3% to about 20%. If the density of the vias 430 is too low, it may not provide a sufficient thermal path for the heat spreader 60 to effectively control heat in the 3DIC 400. In some embodiments, if the density of the vias 430 is too high, the production cost will increase without significantly increasing the heat dissipation capability, and the electrical performance capability or mechanical strength in the 3DIC400 decreases. In some embodiments where vias 430 do not propagate electrical signals, vias 430 are replaced by thermally conductive plates.

In some embodiments, vias 430 are formed by patterning substrate 450 to define a plurality of openings. In some embodiments, the substrate 450 is patterned by etching, laser drilling, or another suitable patterning technique. The plurality of openings are filled with a thermally conductive material. In some embodiments, the opening is filled using PVD, sputtering, CVD, or another suitable formation process. The vias 430 are connected to the die 20 by conductive elements such as solder bumps, copper pillars, or other suitable conductive elements. In some embodiments, vias 430 are connected to die 20 by a bonding process that includes reflow or another suitable process.

Conductive vias 440 or substrate 450 are configured to provide electrical connections between die 20 and conductive elements 460. In some embodiments, conductive via 440 is electrically connected to die 20 through via 430 through RDL 485 in routing layer 480. In some embodiments, conductive via 440 is electrically connected to die 20 through RDL 485 by elements other than via 430. In some embodiments, conductive via 440 comprises copper, aluminum, tungsten, or another suitable conductive material.

Substrate 450 is configured to support heat spreader 60, vias 430, and conductive vias 440. In some embodiments, at least one opening for receiving heat spreader 60 is formed in substrate 450 by etching, laser drilling, or another suitable material removal process. In some embodiments, the wiring layer 480 located over the heat spreader 60 is formed by oxide deposition, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or another suitable formation process. The wiring layer 480 is then patterned using a material removal process such as etching or laser drilling. The openings in the patterned wiring layer 480 are then filled with a conductive material to form RDLs 485. A via 430 is also formed in the wiring layer 480. In some embodiments, RDL 485 and/or via 430 are formed by a damascene process, such as a dual damascene process. Vias 430 and/or RDL 485 are then connected to die 20 by a bonding process. In some embodiments, substrate 450 comprises an organic material. In some embodiments, substrate 450 comprises a semiconductor material such as silicon, silicon germanium, or another suitable semiconductor material. In some embodiments, substrate 450 is doped. In some embodiments, substrate 450 is undoped or unintentionally doped.

The TIM50 provides a substantially planar surface between the heat spreader 60 and the substrate 450. The substantially planar surface helps reduce mechanical stress between the heat spreader 60 and the substrate 450 by distributing the weight of the heat spreader evenly across the substrate 450. The TIM50 also helps to form a portion of the substrate 450 between the heat spreader 60 and the die 20 by providing a more uniform surface for forming a portion of the substrate 450. Substrate 470 is electrically connected to substrate 450 through conductive element 460. In some embodiments, the substrate 470 includes: elemental semiconductors including crystalline silicon, polycrystalline silicon, crystalline germanium, polycrystalline germanium, amorphous-structured silicon, or amorphous-structured germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material or combination thereof. In some embodiments, the alloy semiconductor substrate has a graded SiGe feature in which the Si and Ge compositions vary from one ratio at one location to another ratio at another location of the graded SiGe feature. In some embodiments, the alloy SiGe is formed over a silicon substrate. In some embodiments, substrate 470 is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure. In some examples, the semiconductor substrate includes a doped epi layer or buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure. In some embodiments, substrate 470 is a Printed Circuit Board (PCB). In some embodiments, substrate 470 includes at least one functional circuit. In some embodiments, substrate 470 uses radiative heat transfer to dissipate heat to the surrounding environment.

The conductive element 460 electrically connects the substrate 450 to the substrate 470. In some embodiments, the conductive element 460 is a conductive element such as C₄Solder bumps of the bumps. In some embodiments, the conductive elements 460 are copper pillars or other suitable conductive elements.

Fig. 4B is a cross-sectional view of the 3DIC400' and the heat spreader 60, according to some embodiments. In contrast to the 3DIC400, the 3DIC400' comprises dies 20 stacked on each other and omits a stack 410 of memory units. The dies 20 are connected to each other by conductive elements such as solder bumps, copper pillars, micro-bumps, or other suitable conductive elements. Conductive paths 415' extend through the die 20 to conduct thermal energy and electrical signals between the die 20.

Fig. 4C is a cross-sectional view of the 3DIC400 "and the heat spreader 60, according to some embodiments. In contrast to the 3DIC400, the 3DIC400 ″ includes a stack 410 of multiple dies 20 and multiple memory units connected to the same heat spreader 60. The area of heat spreader 60 is greater than the total area of the plurality of dies 20. In some embodiments, the area of the heat spreader 60 is at least twice the total area of the plurality of dies 20. In some embodiments, the ratio of the area of the heat spreader 60 to the total area of the plurality of dies 20 ranges from about 2 to about 4.

Fig. 5A is a cross-sectional view and a top view of a 3DIC 500 comprising a heat spreader 60a and a heat spreader 60b, according to some embodiments. The 3DIC 500 is similar to the 3DIC400 and like elements have like reference numerals. In some embodiments, the 3DIC 500 comprises an external cooling unit 420 located above the stack 410 of memory units. In contrast to the 3DIC400 (fig. 4), the 3DIC 500 comprises a heat spreader 60a and a heat spreader 60b that are divided into two parts. In some embodiments, heat sink 60a and heat sink 60b are collectively referred to as a heat dissipation structure. A portion of substrate 450 extends between at least portions of heat spreader 60a and heat spreader 60 b. At least one conductive via 440 extends through substrate 450 between heat spreader 60a and heat spreader 60 b.

The total area of heat spreader 60a and heat spreader 60b is greater than the area of die 20. In some embodiments, the total area of heat spreader 60a and heat spreader 60b is at least twice the area of die 20. In some embodiments, the ratio of the total area of the first portion 60a and the second portion 60b to the area of the die 20 ranges from about 2 to about 4.

In some embodiments, the first portion 60a is completely separated from the second portion 60 b. In some embodiments, at least one connecting area connects the first portion 60a and the second portion 60 b. The connection area connects the vapor chamber of the first portion 60a to the vapor chamber of the second portion 60 b.

The 3DIC 500 includes a less complex routing scheme by including a conductive via 440extending between the heat spreader 60a and the heat spreader 60b as compared to the 3DIC 400. The routing scheme provides electrical connections between the die 20 and the substrate 470. The opening between the heat spreader 60a and the heat spreader 60b provides a more direct electrical connection between the die 20 and the substrate 470, which reduces the complexity of the routing scheme of the 3DIC 500. Reducing the complexity of the routing scheme reduces the cost and the complexity of designing the 3DIC 500 compared to the 3DIC 400. In some embodiments, reducing the complexity of the routing scheme also reduces the overall size of the 3DIC 500 as compared to the 3DIC 400.

Fig. 5B is a cross-sectional view and a top view of a 3DIC 500' comprising a heat spreader 60a and a heat spreader 60B, according to some embodiments. In contrast to the 3DIC 500, the 3DIC 500' comprises a plurality of dies 20 and a plurality of stacks 410 of memory units, each of which is connected to a separate heat spreader 60a or heat spreader 60 b. The total area of

heat spreaders

60a and 60b is greater than the total area of the plurality of dies 20. In some embodiments, the total area of

heat spreaders

60a and 60b is at least twice the total area of the plurality of dies 20. In some embodiments, the ratio of the total area of

heat spreaders

60a and 60b to the total area of the plurality of dies 20 ranges from about 2 to about 4. The 3DIC 500' includes a one-to-one ratio between the number of dies 20 and the number of

heat spreaders

60a and 60 b. In some embodiments, multiple dies 20 are connected to the

same heat spreader

60a or 60 b. In some embodiments,

heat spreaders

60a and 60b are connected to a single die 20. In some embodiments, heat spreader 60a is connected to multiple dies 20 and heat spreader 60b is connected to a single die 20.

Fig. 6A is a cross-sectional view and a top view of a 3DIC600 comprising heat spreaders 60a to 60d according to some embodiments. In some embodiments, heat spreaders 60a to 60d, TIM50, and via 430 are collectively referred to as a heat spreading structure. In some embodiments, the 3DIC600 comprises an external cooling unit 420 located above the stack 410 of memory units. The 3DIC600 is similar to the 3DIC400 and like elements have like reference numerals. In contrast to the 3DIC400 (fig. 4), the 3DIC600 includes four-part heat spreaders 60a to 60 d. A portion of substrate 450 extends between at least portions of adjacent portions 60 a-60 d. At least one conductive via 440 extends through substrate 450 between adjacent portions 60 a-60 d.

The total area of heat spreaders 60a to 60d is greater than the area of die 20. In some embodiments, the total area of heat spreaders 60a to 60d is at least twice the area of die 20. In some embodiments, the ratio of the total area of heat spreaders 60a to 60d to the area of die 20 ranges from about 2 to about 4.

In some embodiments, each of the portions 60 a-60 d is completely separate from the second portion 60 b. In some embodiments, at least one of the portions 60 a-60 d is connected to at least another one of the portions 60 a-60 d.

Similar to the 3DIC 500 (fig. 5), the opening between the heat spreaders 60a to 60d helps to reduce the complexity of the wiring scheme of the 3DIC600 compared to the 3DIC 400. In some embodiments, the 3DIC600 comprises more or less than four portions. Increasing the number of openings between heat spreader 60a to heat spreader 60d provides greater access to the direct routing of the conductive paths between die 20 and substrate 470. However, increasing the number of openings between the heat spreaders 60a to 60d removes the portion of the heat spreader closest to the die 20, which reduces the efficiency of absorbing thermal energy from the die.

Fig. 6B is a cross-sectional view and a top view of a 3DIC600' comprising heat spreaders 60a to 60d according to some embodiments. In contrast to the 3DIC600, the 3DIC600' comprises a plurality of dies 20 and a plurality of stacks 410 of memory units, each of which is connected to a heat spreader 60a to a heat spreader 60 d. The total area of heat spreaders 60a to 60d is greater than the total area of the plurality of dies 20. In some embodiments, the total area of heat spreaders 60a to 60d is at least twice the total area of the plurality of dies 20. In some embodiments, the ratio of the total area of heat spreaders 60a to 60d to the total area of the plurality of dies 20 ranges from about 2 to about 4. The 3DIC600' includes a one to two ratio between the number of dies 20 and the number of heat spreaders 60a to 60 d. In some embodiments, multiple dies 20 are connected to the

same heat spreader

60a, 60b, 60c, or 60 d. In some embodiments,

multiple heat spreaders

60a, 60b, 60c, or 60d are connected to a single die 20. In some embodiments, some of the heat spreaders 60a to 60d are connected to multiple dies 20 and other heat spreaders 60a to 60d are connected to a single die 20.

Fig. 7A is a cross-sectional view of a 3DIC700 comprising a heat spreader 710. In some embodiments, heat spreader 710, TIM50, and via 430 are collectively referred to as a heat spreading structure. The 3DIC700 is similar to the 3DIC400 (fig. 4). Like elements have like reference numerals. In contrast to the 3DIC400, the 3DIC700 includes a graphite heat spreader 710. The heat spreader 710 surrounds the plurality of islands 715 to allow routing of the conductive vias 440. Islands 715 are the portions of substrate 450 that remain for subsequent patterning of substrate 450 (forming heat spreader 710).

Compared to other heat sinks, such as heat sink 60 (fig. 4),

heat sinks

60a and 60b (fig. 5), or heat sinks 60 a-60 d (fig. 6), heat sink 710 does not include a vapor chamber, and heat sink 710 is easier to integrate into the manufacturing process because no specialized structure is separately manufactured or purchased. The use of the heat sink 710 also helps the heat sink to accommodate previously designed wiring schemes while avoiding redesign of the heat sink.

The heat spreader 710 is formed by patterning the substrate 450 to form a plurality of cavities. In some embodiments, the locations of the plurality of cavities are determined based on a predetermined routing scheme for the 3DIC 700. In some embodiments, the substrate 450 is patterned using laser drilling. In some embodiments, the substrate 450 is patterned using an etching process or another suitable patterning technique. Graphite material is then formed in the plurality of cavities. The unpatterned portion of substrate 450 defines the location of islands 715 in heat spreader 710. In some embodiments, the graphite material is formed by CVD, PVD, spin coating, or another suitable forming process. In some embodiments, the graphite material in each of the plurality of cavities is thermally coupled to the graphite material in each other cavity of the plurality of cavities. In some embodiments, at least a portion of the graphite material in at least one of the plurality of cavities is thermally separated from at least another portion of the graphite material in a different one of the plurality of cavities.

In some embodiments, heat spreader 710 is formed by etching a single cavity in substrate 450. Graphite material is formed in a single cavity. The graphite material is then patterned to provide islands 715 for routing of the conductive vias 440. In some embodiments, the graphite material is patterned using laser drilling, etching, or another suitable patterning process. In some embodiments, the height H of the heat spreader 710 ranges from about 0.2mm to about 1.0mm to provide sufficient heat dissipation capability without unnecessarily increasing the size of the 3DIC 700. In some embodiments, the height H of the heat spreader 710 ranges from about 0.8mm to about 1.0 mm.

Fig. 7B is a cross-sectional view and a top view of a 3DIC700 comprising a heat spreader 710. In a top view of the 3DIC700, the islands 715 are arranged in a two-dimensional array. In some embodiments, the islands 715 are randomly arranged. In some embodiments, the islands 715 are arranged in a regular pattern, a quasi-regular pattern, or another suitable combination.

Fig. 7C is a cross-sectional view and a top view of a 3DIC700' comprising a heat spreader 710. In contrast to the 3DIC700, the 3DIC700' includes extensions 725 arranged in a regular grid pattern. Extension 725 is the portion of substrate 450 that extends between portions of heat spreader 710. The extension 725 extends in two orthogonal directions. In contrast to islands 715, extensions 725 extend continuously across heat sink 710. In some embodiments, the extension 725 does not extend continuously across the heat sink 710. In some embodiments, the extension 725 extends in a single direction across the heat sink 710. In some embodiments, the extensions 725 are arranged in an irregular grid layout, wherein the spacing between adjacent extensions 725 is different.

Fig. 8A to 8J are sectional views of the 3DIC at various stages of manufacture. Like reference numerals in fig. 8A to 8J correspond to like elements described above. For brevity, some of the reference numerals in fig. 8A to 8J are not repeated in each drawing. Fig. 8A includes substrate 450 prior to forming an opening in substrate 450. Fig. 8B includes an opening 810 in substrate 450. Opening 810 is for receiving a heat sink. Fig. 8B also includes an opening 820 in the substrate 450. Openings 820 are used for vias 440. In some embodiments, opening 810 and opening 820 are formed simultaneously. In some embodiments, opening 810 and opening 820 are formed sequentially.

Openings

810 and 820 are formed in substrate 450 by a material removal process. In some embodiments, the material removal process includes etching, laser drilling, or another suitable material removal process. In some embodiments, opening 810 is a plurality of openings. In some embodiments, at least a portion of substrate 450 remains between a first portion of opening 810 and a second portion of opening 810. In some embodiments, the remainder of substrate 450 includes intersecting extensions, e.g., extension 725. In some embodiments, the remaining portion of substrate 450 includes islands, e.g., island 715. In some embodiments including a plurality of openings 810, the plurality of openings 810 are connected to each other. In some embodiments including a plurality of openings 810, each opening of the plurality of openings is separated from other openings of the plurality of openings by a portion of the first substrate. In some embodiments, additional openings are formed in islands or extensions of substrate 450 to provide routing between portions of the heat spreader.

Fig. 8C includes heat sink 60 positioned in opening 810. In some embodiments, heat sink 60 is replaced by heat sinks 60 a-60 d or heat sink 710. In some embodiments, the heat sink 60 includes a vapor chamber. In some embodiments, the heat spreader comprises graphite.

Fig. 8D includes a via 440 formed in opening 820. At least one second through hole 440 forming the through hole 440 surrounds the periphery of the heat sink 60. In some embodiments, the vias 440 are formed by filling holes in the substrate 450 with a conductive material.

Fig. 8E includes a TIM50 formed over the top and bottom surfaces of a heat spreader 60. In some embodiments, the TIM50 is formed by spin coating, printing, PVD, or another suitable formation process.

Fig. 8F includes a wiring layer 480 formed over the first surface of substrate 450. The routing layer 480 provides electrical connections for propagating signals between structures connected to the substrate 450. Routing layer 480 includes at least one RDL, such as RDL 485 (fig. 4A) or a via (e.g., via 430). Each RDL is electrically connected to at least one via 440. In some embodiments, the routing layer 480 also includes vias for connecting to vias 440 formed in islands 715 or extensions 725. In some embodiments, the RDL and/or vias of wiring layer 480 are formed by the same process as vias 440. In some embodiments, the RDL and/or vias of wiring layer 480 are formed by a different process than vias 440.

Fig. 8G includes a wiring layer 480 formed on the second surface of the substrate 450. In some embodiments, the substrate 450 is removably attached to a temporary carrier (not shown) to facilitate formation of the wiring layer 480 on the second surface of the substrate 450.

Fig. 8H includes a stack 410 of die 20 and memory cells bonded to a substrate 450 through a routing layer 480 on a first surface of substrate 450. In some embodiments, the die 20 and the stack 410 of memory cells are bonded together prior to bonding the die 20 to the substrate 450. In some embodiments, die 20 is bonded to substrate 450 before stack of memory cells 410 is bonded to die 20. The die 20 is connected to RDLs and/or vias in the routing layer 480 on the first surface of the first substrate. In some embodiments, die 20 is bonded to substrate 450 by a reflow process. In some embodiments, RDLs and/or vias in routing layer 480 on the first surface thermally connect die 20 with heat spreader 60. In some embodiments, more than one die package (e.g., die 20 and stack 410 of memory cells) is bonded to the first surface of substrate 450. In some embodiments, a plurality of logic devices are bonded to the first surface of the substrate 450.

Fig. 8I includes a conductive element 460 bonded to a substrate 450 through a wiring layer 480 on a second surface of the substrate 450. In some embodiments, the conductive element 460 is bonded to the second surface of the substrate 450 by a reflow process.

Fig. 8J includes a substrate 470 bonded to the substrate 450 by conductive elements 460. In some embodiments, substrate 470 is bonded to substrate 450 by a reflow process. The substrate 470 is electrically connected to the die 20 and the stack 410 of memory cells by the second via 440 and/or via 430 and RDL 485 through the routing layer 480 on the first and second surfaces of the first substrate. Fig. 8A-8J provide examples of processes for forming a 3DIC similar to 3DIC400 (fig. 4A). In some embodiments, the process flow is modified to form other 3 DICs, such as 3DIC400 '(fig. 4B), 3DIC400 "(fig. 4C), 3DIC 500 (fig. 5A), 3DIC 500' (fig. 5B), 3DIC600 (fig. 6A), 3DIC600 '(fig. 6B), 3DIC700 (fig. 7A), 3DIC700' (fig. 7C).

In some embodiments, the order of the operations of fig. 8A-8J is changed. In some embodiments, the operations of fig. 8A-8J are removed or the operations of fig. 8A-8J are joined together into a single operation. In some embodiments, additional operations, such as including an external cooling unit, are added to the process flow of fig. 8A-8J. In some embodiments, external cooling unit 420 is added after substrate 470 is bonded to substrate 450. In some embodiments, the external cooling unit 420 is bonded to the stack of memory cells 410 before the die 20 is bonded to the substrate 450. In some embodiments, after die 20 is bonded to substrate 450, external cooling unit 420 is bonded to stack of memory cells 410.

One aspect of the present description relates to a three-dimensional integrated circuit (3 DIC). The 3DIC comprises a first substrate and a heat spreader embedded in the first substrate. The 3DIC also comprises a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreader. The 3DIC further comprises a plurality of memory units located on the die, wherein the die is located between the plurality of memory units and the first substrate, and the plurality of memory units are thermally connected to the heat spreader through the die. The 3DIC further comprises an external cooling unit located on the plurality of memory units, wherein the plurality of memory units are located between the die and the external cooling unit, and the die is thermally connected to the external cooling unit through the plurality of memory units.

Another aspect of the present description relates to a three-dimensional integrated circuit (3 DIC). The 3DIC comprises a first substrate. The 3DIC also comprises a heat dissipation structure embedded in the first substrate. The heat dissipation structure includes a heat spreader, a Thermal Interface Material (TIM) over at least a first surface of the heat spreader, and a plurality of first vias in contact with the TIM. The 3DIC also comprises a die electrically connected to the first substrate, wherein the plurality of first vias are connected to the die. The 3DIC also comprises a plurality of conductive vias electrically connected to the die, wherein at least one conductive via of the plurality of conductive vias extends through the first substrate between the first portion of the heat spreader and the second portion of the heat spreader. The 3DIC further comprises a plurality of conductive elements located on the first substrate, wherein the plurality of conductive elements are located on a surface of the first substrate opposite the die and the plurality of conductive elements are electrically connected to corresponding ones of the plurality of conductive vias.

Yet another aspect of the present description relates to a method of forming a three-dimensional integrated circuit (3 DIC). The method includes patterning a substrate to define at least one cavity in the substrate. The method also includes embedding a heat spreader in the at least one cavity, wherein a portion of the substrate extends through the heat spreader. The method also includes defining a plurality of vias in the substrate, wherein the plurality of vias are thermally connected to the heat spreading structure. The method also includes defining a plurality of conductive vias in the substrate, wherein at least one conductive via of the plurality of conductive vias extends through a portion of the heat spreader extension substrate. The method also includes bonding a die on the substrate, wherein the die is thermally connected to the plurality of vias and the die is electrically connected to the plurality of conductive vias.

In the three-dimensional integrated circuit described above, further comprising a plurality of vias extending into the first substrate, wherein the plurality of vias thermally connect the die to the heat spreader.

In the three-dimensional integrated circuit described above, at least one via of the plurality of vias is configured to electrically connect the first substrate to the die.

In the three-dimensional integrated circuit described above, the density of the die is greater than 3%.

In the three-dimensional integrated circuit described above, at least one via of the plurality of vias is electrically isolated from the die.

In the three-dimensional integrated circuit described above, the total area of the heat spreader is at least two times greater than the area of the die.

In the above three-dimensional integrated circuit, the heat spreader includes graphite.

In the three-dimensional integrated circuit described above, further comprising: a plurality of conductive elements on the first substrate, wherein the heat spreader is between the die and the plurality of conductive elements; and at least one conductive via electrically connecting the die to a respective conductive element of the plurality of conductive elements, wherein the at least one conductive via extends through the island of the first substrate, which extends through the heat spreader.

In the above three-dimensional integrated circuit, the heat spreader includes at least one vapor cell.

In the above three-dimensional integrated circuit, the at least one vapor cell is a plurality of vapor cells.

In the three-dimensional integrated circuit described above, further comprising: a plurality of conductive elements on the first substrate, wherein the heat spreader is between the die and the plurality of conductive elements; and at least one conductive via electrically connecting the die to respective ones of the plurality of conductive elements, wherein the at least one conductive via extends through the first substrate between adjacent ones of the plurality of vapor cells.

In the above three-dimensional integrated circuit, the at least one vapor cell comprises a vapor cell comprising a plurality of connected portions, wherein the plurality of connected portions define at least one opening between the plurality of connected portions.

In the three-dimensional integrated circuit described above, further comprising: a plurality of conductive elements on the first substrate, wherein the heat spreader is between the die and the plurality of conductive elements; and at least one conductive via electrically connecting the die to a respective conductive element of the plurality of conductive elements, wherein the at least one conductive via extends through the at least one opening.

In the three-dimensional integrated circuit described above, further comprising: a plurality of conductive elements on the first substrate, wherein the heat spreader is between the die and the plurality of conductive elements; and a plurality of conductive vias electrically connecting the die to respective ones of the plurality of conductive elements, wherein each conductive via of the plurality of conductive vias is located around a periphery of the heat spreader.

In the above three-dimensional integrated circuit, further comprising a second substrate electrically connected to the die through the first substrate.

In the above three-dimensional integrated circuit, a second external cooling unit is further included, the second external cooling unit being thermally connected to the second substrate on a surface of the second substrate opposite to the first substrate.

In the three-dimensional integrated circuit described above, the density of the plurality of first vias is greater than 3%.

In the three-dimensional integrated circuit described above, the total area of the heat dissipation structures is at least two times greater than the area of the die.

The foregoing disclosure is described with reference to exemplary embodiments. It will, however, be evident that various modifications, structures, processes, and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the claims that follow. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It is to be understood that the present embodiments may be utilized in various other combinations and environments and may be altered or modified within the scope of the invention.

Claims

1. A three-dimensional integrated circuit (3DIC), comprising:

a first substrate including a plurality of cavity portions;

a plurality of heat dissipation parts embedded in the plurality of cavity parts, respectively, wherein at least one of the plurality of heat dissipation parts is separated from or connected to other parts of the plurality of heat dissipation parts;

a die electrically connected to the first substrate, wherein the die is thermally connected to the plurality of heat dissipation portions;

a plurality of memory cells on the die, wherein the die is located between the plurality of memory cells and the first substrate, and the plurality of memory cells are thermally connected to the plurality of heat dissipation portions through the die; and

an external cooling unit on the plurality of memory units, wherein the plurality of memory units are between the die and the external cooling unit, and the die is thermally connected to the external cooling unit through the plurality of memory units.

2. The three-dimensional integrated circuit of claim 1, further comprising a plurality of vias extending into the first substrate, wherein the plurality of vias thermally connect the die to the plurality of heat dissipation portions.

3. The three-dimensional integrated circuit of claim 2, wherein at least one via of the plurality of vias is configured to electrically connect the first substrate to the die.

4. The three-dimensional integrated circuit of claim 2, wherein a density of the plurality of vias is greater than 3%.

5. The three-dimensional integrated circuit of claim 2, wherein at least one via of the plurality of vias is electrically isolated from the die.

6. The three-dimensional integrated circuit of claim 1, wherein a total area of the plurality of heat dissipation portions is at least two times greater than an area of the die.

7. The three-dimensional integrated circuit of claim 1, wherein the plurality of heat dissipating portions comprise graphite.

8. The three-dimensional integrated circuit of claim 7, further comprising:

a plurality of conductive elements on the first substrate, wherein the plurality of heat dissipating portions are located between the die and the plurality of conductive elements; and

at least one conductive via electrically connecting the die to a respective conductive element of the plurality of conductive elements, wherein the at least one conductive via extends through the island of the first substrate, which extends through the plurality of heat dissipating portions.

9. The three-dimensional integrated circuit of claim 1, wherein the plurality of heat dissipating portions comprises a plurality of vapor cells.

10. The three-dimensional integrated circuit of claim 9, further comprising:

at least one conductive via electrically connecting the die to a respective conductive element of the plurality of conductive elements, wherein the at least one conductive via extends through the first substrate between adjacent ones of the plurality of vapor cells.

11. The three-dimensional integrated circuit of claim 9, wherein the plurality of vapor cells comprises a vapor cell including a plurality of connected portions, wherein the plurality of connected portions define at least one opening between the plurality of connected portions.

12. The three-dimensional integrated circuit of claim 11, further comprising:

at least one conductive via electrically connecting the die to a respective conductive element of the plurality of conductive elements, wherein the at least one conductive via extends through the at least one opening.

13. The three-dimensional integrated circuit of claim 1, further comprising:

a plurality of conductive vias electrically connecting the die to respective ones of the plurality of conductive elements, wherein each conductive via of the plurality of conductive vias is located around a periphery of the plurality of heat dissipation portions.

14. The three-dimensional integrated circuit of claim 1, further comprising a second substrate electrically connected to the die through the first substrate.

15. The three-dimensional integrated circuit of claim 14, further comprising a second external cooling unit thermally connected to the second substrate on a surface of the second substrate opposite the first substrate.

16. A three-dimensional integrated circuit (3DIC), comprising:

a first substrate including a plurality of cavity portions;

a heat dissipation structure embedded in the first substrate, wherein the heat dissipation structure comprises:

a plurality of heat dissipation parts embedded in the plurality of cavity parts, respectively, wherein at least one of the plurality of heat dissipation parts is separated from or connected to the other part of the plurality of heat dissipation parts,

a Thermal Interface Material (TIM) over at least a first surface of the plurality of heat dissipating portions, and

a plurality of first vias in contact with the thermal interface material;

a die electrically connected to the first substrate, wherein the plurality of first vias are connected to the die;

a plurality of conductive vias electrically connected to the die, wherein at least one of the plurality of conductive vias extends through the first substrate between a first portion of the plurality of heat dissipating portions and a second portion of the plurality of heat dissipating portions;

a plurality of conductive elements on the first substrate, wherein the plurality of conductive elements are on a surface of the first substrate opposite the die and are electrically connected to corresponding ones of the plurality of conductive vias.

17. The three-dimensional integrated circuit of claim 16, wherein a density of the plurality of first vias is greater than 3%.

18. The three-dimensional integrated circuit of claim 16, wherein a total area of the heat dissipation structures is at least two times greater than an area of the die.

19. A method of forming a three-dimensional integrated circuit (3DIC), the method comprising:

patterning a substrate to define a plurality of cavities in the substrate;

embedding a plurality of heat dissipation portions in the plurality of cavities, wherein portions of the substrate extend through the plurality of heat dissipation portions, wherein at least one of the plurality of heat dissipation portions is separated from or connected to other portions of the plurality of heat dissipation portions;

defining a plurality of vias in the substrate, wherein the plurality of vias are connected to the plurality of heat dissipating portions;

defining a plurality of conductive vias in the substrate, wherein at least one conductive via of the plurality of conductive vias extends through the portion of the substrate that extends through the plurality of heat dissipating portions; and

bonding a die on the substrate, wherein the die is connected to the plurality of vias and the die is electrically connected to the plurality of conductive vias.