CN115810594A - Semiconductor three-dimensional packaging structure with steam chamber - Google Patents

Abstract

The invention provides a semiconductor three-dimensional packaging structure with a steam chamber, wherein a cover is combined with a bottom plate to form the steam chamber, and a plurality of three-dimensional structures stacked by intermediate layers for configuring semiconductor chips are packaged in the steam chamber. A group of capillary structures are formed on the inner side of the cover, and a group of nets are combined on the inner side of the cover and cover the group of capillary structures. Each interposer has a set of protrusions spaced by a recess, and all interposers contact the set of protrusions, and the recesses from the upper interposer to the lower interposer form a flow path to the vapor chamber. And a proper amount of cooling fluid is added into the vapor chamber, and the cooling fluid carries out liquid-state to gas-state conversion thermal circulation from the flow channel to the group of capillary structures, so that the heat dissipation effect of the semiconductor wafer is achieved. The top and bottom surfaces of each interposer also have capillary structures that direct the high temperature gases of the two interposers through flow channels to the vapor chamber as part of the thermal cycle.

Description

Semiconductor three-dimensional packaging structure with vapor chamber

Technical Field

The present invention relates to semiconductor packaging technology, and more particularly to a three-dimensional package structure, which utilizes a vapor chamber or a temperature-equalizing structure to generate a heat dissipation effect of a semiconductor chip.

Background

The three-dimensional packaging structure is adopted to gather more semiconductor chips together, so that the requirements of small volume and strong function are met. After power-on, the semiconductor chip generates high heat, which delays the operation efficiency and even reduces the lifetime. How to dissipate heat becomes a problem to be solved for the semiconductor chip.

In U.S. Pat. No. 20200105644, a heat dissipation device is attached to a semiconductor three-dimensional package structure, whereby a coolant with a relatively low temperature is continuously supplied to a flow channel to carry away heat of the package structure. Although, the design of this water cooling method can improve the heat dissipation efficiency. However, the force of the heat dissipation device for pushing the cooling liquid to flow comes from a pump, and the heat dissipation device is bulky, and obviously cannot keep up with the advanced technology of the miniaturization of the packaging structure.

Taiwan patent No. 202121618 proposes a stacked structure, which combines with the heat dissipation structure of taiwan patent No. 202002201 to add a heat conduction structure inside the three-dimensional package to improve the heat dissipation problem. Specifically, each layer of the semiconductor chip stack is provided with a heat dissipation layer, the heat dissipation layer is a thermal interface material with heat conduction efficiency, and the heat conduction effect of the semiconductor chip is achieved through an electrical connection structure such as a through silicon via or a copper column. The disadvantage is that the heat conduction and dissipation effect is limited. In particular, when stacking multiple layers, the lower semiconductor chip has poor heat dissipation and the effect is greatly reduced.

The better solution to the heat dissipation problem at present is a vapor chamber structure or called temperature equalization structure. The steam chamber structure achieves a quick heat dissipation effect by utilizing the thermal circulation of a gas phase and a liquid phase of cooling fluid. Therefore, the vapor chamber is applied to the three-dimensional packaging technology of semiconductors, and can improve the heat dissipation efficiency of a plurality of high-performance chips.

For example, japanese patent No. 5554444 (kokai No. 2015050323) and taiwan patent No. 202002031 both propose a cover body applied to a semiconductor three-dimensional package structure to achieve the heat dissipation effect of the vapor chamber.

In taiwan patent No. I672775 (application No. 106119235), at least one cooling channel is designed to surround the stacked semiconductor wafers in a three-dimensional package structure. The fluid phase-changed in the cooling channel takes away heat from the semiconductor wafer to provide a heat dissipation effect, so that the cooling channel functions as a vapor chamber.

There is also a semiconductor package structure and an assembly structure in which a desired vapor chamber is provided between a semiconductor wafer and a package substrate, and the vapor chamber takes away heat of the semiconductor wafer, and patent applications such as us 20200111728 and chinese 111009493 are filed in many countries.

In each of the above vapor chamber patents, the thermal interface material or encapsulant is used as a medium to indirectly bond the vapor chamber structure to the semiconductor package structure. Thus, the heat conductivity of the medium has great influence on the heat dissipation effect of the steam chamber structure.

In addition, U.S. patent No. 20190393193 discloses a semiconductor package having a vapor chamber function, which is provided between a plurality of integrated circuits, mainly in a space of an electrical connection structure. However, the flow space of the vapor chamber is limited to a narrow space where the integrated circuits are separated from each other, and the heat dissipation efficiency of the entire semiconductor package is poor.

Still another type of semiconductor package has an interposer attached to the semiconductor, as disclosed in U.S. patent No. 7,002, 247. The interposer has two plates containing core structures such as grooves, and the inner sealed volume constituting the interposer is in direct contact with the back surface of the semiconductor chip, thereby forming a vapor chamber for reducing heat of the semiconductor chip and achieving uniform temperature. Unfortunately, the semiconductor package is susceptible to damage to the semiconductor die by the attachment structures on the die surface alone, relatively weakening the overall support structure.

Disclosure of Invention

In view of the above, the present inventors provide a new generation of three-dimensional package structure, which mainly aims at: the vapor chamber structure encapsulates the semiconductor chip and the cooling fluid, so that the cooling fluid directly takes away the heat of the semiconductor chip, thereby the heat dissipation effect is more efficient than the prior art.

In view of the above, the present invention provides a three-dimensional semiconductor package structure having a vapor chamber, comprising:

a base plate;

a plurality of semiconductor chips are stacked on the bottom plate through a plurality of intermediate layers, each intermediate layer is provided with a top surface capillary structure and a bottom surface capillary structure, the periphery of each intermediate layer is provided with a group of convex parts, and the two convex parts are separated by a concave part;

a group of capillary structures and a group of nets are arranged on the inner side of the cover, the group of nets shield the capillary structures, when the cover is combined with the bottom plate to form a steam chamber, the cover covers all the semiconductor chips, all the intermediate layers contact the group of nets through convex parts, and a flow channel connected to the steam chamber is formed from the upper intermediate layer to the concave part of the lower intermediate layer; and

and proper amount of cooling fluid is added into the vapor chamber, and liquid-state-to-gas-state thermal circulation is performed among the capillary structures, the flow channels, the top capillary structure and the bottom capillary structure, so that the heat dissipation effect of the semiconductor wafer is achieved.

The semiconductor three-dimensional packaging structure with the steam chamber is characterized in that the concave parts of the upper interposer and the lower interposer are staggered, and inclined flow channels are kept, so that the convex parts of the upper interposer and the lower interposer are arranged in a step state.

The semiconductor three-dimensional packaging structure with the steam chamber is characterized in that the cover is made of one of copper, copper alloy and other heat conducting metals.

The semiconductor three-dimensional packaging structure with the steam chamber is characterized in that one of copper, copper alloy and other heat conducting metals is covered on the surface of the cover.

The semiconductor three-dimensional packaging structure with the vapor chamber is characterized in that the group of capillary structures are staggered slits and are formed on the surface of the cover through one of etching, laser engraving, stamping and die casting.

The semiconductor three-dimensional packaging structure with the vapor chamber is characterized in that the cooling fluid is selected from one of ultrapure water, ethanol, butane and a mixture thereof.

The semiconductor three-dimensional packaging structure with the steam chamber is characterized in that the intermediate layer is selected from one of a ceramic substrate, an aluminum nitride ceramic substrate, an aluminum oxide ceramic substrate, a silicon oxide ceramic substrate and a silicon nitride ceramic substrate.

The semiconductor three-dimensional packaging structure with the vapor chamber is characterized in that a group of heat conduction columns penetrate through all stacked interposers in an array.

The semiconductor three-dimensional packaging structure with the steam chamber is characterized in that a group of radiating fins are combined outside the cover.

Therefore, the cover and the bottom plate are combined to form a steam chamber, and the semiconductor chip and the cooling fluid are packaged in the steam chamber to form a three-dimensional packaging structure. The cooling fluid is subjected to liquid-to-gas thermal circulation in the vapor chamber to directly take away heat of the semiconductor chip, and the heat dissipation effect is naturally more efficient than that of the prior art.

The present invention may be embodied in several forms and should not be construed as limited to the embodiments set forth herein.

Drawings

Fig. 1 is a top view of a first embodiment of the package structure of the present invention.

Fig. 2 is a bottom view of the embodiment of fig. 1.

Fig. 3 is a schematic diagram of the internal configuration of the package structure with the top surface of the lid cut away and overlooked.

Fig. 4 is a schematic view of the internal constitution of the package structure viewed through the lid.

Fig. 5 isbase:Sub>A sectional view taken along linebase:Sub>A-base:Sub>A of fig. 3.

Fig. 6 is a schematic diagram showing in detail the flow channel portion of fig. 5 on an enlarged scale.

FIG. 7 is a bottom view of a single interposer.

FIG. 8 is a schematic diagram showing a stacked interposer and semiconductor die.

Fig. 9 is a schematic diagram of a structure of a cut-away package structure to observe the inside.

Fig. 10 is a schematic drawing depicting the vapor chamber through the mesh and capillary structure as part of a thermal cycle.

Fig. 11 and 12 are schematic diagrams of a second embodiment of the package structure of the present invention viewed from different angles.

Fig. 13 is a partially enlarged view of fig. 3.

Description of the reference numerals: a package structure 10; a cover 11; a hole 12; a vapor chamber 13; a mesh 14; a capillary structure 15; a base plate 20; an electrical pin 21; a spacer 22; a leakage preventing structure 23; an upper interposer 30; a top capillary structure 31; a middle interposer 32; a lower interposer 33; a flow passage 34; a bottom surface capillary structure 35; a convex portion 36; a recess 37; a working area 40; a seating area 41; conductive posts 42; a heat-conducting column 43; a semiconductor wafer 44; arrows 50; a fastener 51; and heat dissipating fins 52.

Detailed Description

Next, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same or similar structures or elements are denoted by the same reference numerals. It is to be understood that the embodiments described are only exemplary of some, and not all, of the embodiments described herein. Other embodiments can be derived based on the described examples, or configurations can be modified or changed as needed and still fall within the scope of the present disclosure.

In the following description, directional terms such as "up", "down", "left", "right", "front", "back", "inside", "outside", and "side" refer to the directions of the drawings. The use of directional terms is intended to better and more clearly describe and understand the present disclosure, and to not imply or imply that a particular orientation, configuration or operation of a device or element is required or necessary, and should not be considered limiting with respect to the present disclosure.

Unless specified or limited by specific and explicit specifications or definitions, the following description "mounted," "connected," or "disposed at 8230a" shall be taken to mean a broad definition, such as a fixed connection, a releasable connection, an integral connection, a mechanical connection, a direct connection, an indirect connection, or a connection within two elements. Those skilled in the art will understand the above terms in various embodiments and even the specific meanings of the present application based on common knowledge or experience.

In the following description, "plurality" means two or more unless otherwise specified.

Fig. 1 is a top view of a package structure 10 according to a first embodiment of the present invention. Above the package structure 10 is a cover 11, the cover 11 is a cube, and four corners of the cube are respectively provided with a hole 12.

In the present embodiment, the cover 11 is made of one of copper, copper alloy and other heat conductive metals. In some embodiments, the surface of the lid 11 is made of a polymer material coated with copper, copper alloy, or other heat conductive metal, and has thermal conductivity.

Fig. 2 is a bottom view of the package structure 10, wherein a bottom plate 20 having the same shape as the cover 11 is disposed under the package structure, a set of electrical pins 21 is arrayed at the center of the bottom plate 20, and the set of electrical pins 21 are arranged in a square ring. Four pads 22 are formed at the four corners of the base plate 20.

As shown in fig. 4 and 10, the package structure 10 is cut into two parts. The cover 11 has five sides enclosing an inner space, seen in perspective view, inside. The base plate 20 closes the opening of the lid 11 and combines to enclose a closed vapor chamber 13. A leak-proof structure 23 is provided between the bottom plate 20 and the lid 11 to prevent leakage from the steam chamber 13.

In this embodiment, a set of capillary structures 15 is etched into the cover 11. The set of capillary structures 15 is five in number and formed on five sides of the inside of the cover 11. Each capillary structure 15 is a plurality of slits staggered across the respective faces of the cover 11. In some embodiments, the set of capillary structures 15 is formed on the surface of the cover 11 by one of laser engraving, stamping, and die casting.

Further, a set of metal meshes 14 is bonded to the inside of the cover 11. The set of wires 14 is five in number and extends on five sides of the inside of the cover 11. Each web 14 is secured to the respective face of the cover 11 by welding or adhesive means without damaging or blocking the capillary structure 15. In this way, the mesh 14 shields the capillary structure 15.

As shown in fig. 3 and 5, the vapor chamber 13 of the package structure 10 encloses a semiconductor wafer stack and an appropriate amount of cooling fluid (not shown).

The semiconductor chip stacked structure herein refers to a three-dimensional structure in which a plurality of semiconductor chips are stacked via a plurality of interposers and is disposed on a base plate 20. These interposers are stacked into a three-layer structure, and the lower interposer 33, the middle interposer 32 and the upper interposer 30 are defined from bottom to top, which is helpful for describing the structure and avoiding confusion. In the present embodiment, the interposer is selected from one of a ceramic substrate, an aluminum nitride ceramic substrate, an aluminum oxide ceramic substrate, a silicon oxide ceramic substrate, and a silicon nitride ceramic substrate.

In the example of the interposer 30, the top surface is centrally located with a working area 40, the working area 40 is a square area, and a set of heat-conducting pillars 43 are arrayed around the square area. A top capillary structure 31 is formed on the top surface of the upper interposer 30 by one of etching, laser engraving, stamping and die casting, wherein the top capillary structure 31 is a plurality of slits with staggered rows and columns, avoiding the set of heat-conducting pillars 43.

Referring to fig. 7, the bottom surface of the upper interposer 30 also has a working region 40, which is composed of a landing region 41 and a set of conductive posts 42. The set of conductive posts 42 surrounds the square seating area 41, and the set of conductive posts 43 surrounds the set of conductive posts 42. A bottom surface capillary structure 35 is formed on the bottom surface of the upper interposer 30 by one of etching, laser engraving, stamping and die casting, and the bottom surface capillary structure 35 is also a plurality of slits crossing rows and columns, avoiding the set of conductive pillars 42 and the set of conductive pillars 43. In addition, since the upper interposer 30 has a pair of protrusions 36 on its periphery, and two protrusions 36 are separated by one recess 37, a pair of recesses 37 is formed on the periphery of the upper interposer 30.

From fig. 5, 6, 10, and 13, the structure of the middle interposer 32 is substantially the same as the upper interposer 30, with the difference: the protrusions 36 of the middle interposer 32 are offset from the protrusions 36 of the upper interposer 30 such that the recesses 37 of the middle and upper interposers are offset from each other.

The lower interposer 33 is substantially identical in structure to the middle interposer 32, with the following differences: the convex part 36 and the concave part 37 of the lower and middle two-layer interposer are also designed to be offset.

When the lid 11 covers the stacked semiconductor chip structure, the upper, middle and lower interposers 30, 32 and 33 contact the stack 14 with the bumps 36, and the bumps 36 are arranged in a step-wise manner from top to bottom. Meanwhile, the recess 37, which is offset from the upper interposer 30 to the lower interposer 33, becomes a flow channel 34, and the flow channel 34 is connected to the vapor chamber 13 while maintaining an inclination angle. Thus, the periphery of the semiconductor chip stack structure has a set of runners 34.

As shown in fig. 8 and 9, the set of heat-conducting pillars 43 penetrates from the upper interposer 30 to the lower interposer 33 through the middle interposer 32. The heat-conducting post 43 is a copper post with excellent thermal conductivity, and a tin point (not shown) is attached to the end of the copper post and can be fused with the corresponding electrical pin 21 of the bottom plate 20. In the semiconductor chip stack structure, the heat-conducting pillars 43 are electrically non-conductive and have a heat-conducting function with the electrical terminals 21.

The semiconductor wafer 44 is located in the seating region 41. Wherein some electronic circuits (not shown) are disposed inside each interposer, and an electric power (or signal) is inputted (or outputted) between the semiconductor wafer 44 and the set of conductive pillars 42. The conductive posts 42 of the upper interposer 30 are connected to the electrical pins 21 of the backplane 20 via the conductive posts 42 of the middle and lower interposers 32, 33; the conductive posts 42 of the middle interposer 32 are connected to the electrical pins 21 of the backplane 20 via the conductive posts 42 of the lower interposer 33; the conductive posts 42 of the lower interposer 33 are directly connected to the electrical pins 21 of the backplane 20. Therefore, the package structure 10 has a conductive property.

As shown in fig. 5, 6, 10 and 13, in the present embodiment, the cooling fluid is ultrapure water. The ultrapure water has a thermal conductivity, and changes the liquid phase into the gas phase in the vapor chamber 13 having a constant volume, so that an appropriate amount of ultrapure water is added to the vapor chamber 13. In certain embodiments, the cooling fluid is selected from one of ethanol, butane, and mixtures thereof.

It is assumed that ultrapure water is present below the vapor chamber 13. According to the capillary phenomenon, the ultrapure water comes to the top surface of the inside of the cover 11 against the gravity along the capillary structure 15 around the cover 11. The mesh 14 is in contact with each of the projections 36 with a gap, so that ultrapure water rises from the lower interposer 33 to the upper interposer 30 via the gap via the intermediate interposer 32, and is diffused to the top surface capillary structure 31 and the bottom surface capillary structure 35 of each of the interposers 30, 32, 33.

In fig. 8 and 9, after the conduction, the semiconductor chips 44 of the respective layers are logically operated and generate a high temperature. The lower interposer 33 accumulates more heat at the bottom of the semiconductor die stack than other interposers. Therefore, the semiconductor chip 44 on the bottom layer is thermally conducted to the lower intermediary layer 33, and the ultrapure water on the lower intermediary layer 33 is heated, transformed from liquid state to gas state, and diffused to the periphery along the top surface capillary structure 31 and the bottom surface capillary structure 35. With the characteristic of high temperature to low temperature, the vapor flows from the flow channel 34 to the top surface of the inside of the lid 11 in the direction of arrow 50 (see fig. 6), carrying away the heat of the bottom semiconductor wafer 44.

Meanwhile, the semiconductor wafer 44 in the middle of the semiconductor wafer stack is thermally conducted to the middle interposer 32, so that the ultrapure water in the top surface capillary structure 31 and the bottom surface capillary structure 35 is converted from liquid state to high temperature steam, and the steam flows from the flow channel 34 to the top surface of the inner side of the cover 11 in the direction of the arrow 50 (see fig. 6), taking away the heat of the middle semiconductor wafer 44.

The top semiconductor wafer 44 indirectly contacts the top surface of the inside of the cover 11 through the mesh 14, and also contacts the upper interposer 30. Therefore, a part of the top semiconductor wafer 44 is thermally conducted to the mesh 14 and then dissipated to the outside through the cover 11, and the rest is thermally conducted to the upper interposer 30, so that the ultrapure water in the top capillary structure 31 and the bottom capillary structure 35 is converted into high-temperature steam from liquid state, mixed with the gases from the middle and lower interposers 32, 33 and passes through the mesh, thereby thermally convecting the ultrapure water in the capillary structure 15 of the cover 11. The ultrapure water is heat-exchanged to become a high-temperature gas, which can be thermally conducted to the wall of the capillary structure 15, and then dissipated to the outside through the lid 11 to be cooled.

As shown in fig. 10 and 13, the reduced temperature steam is condensed into ultrapure water. A part of the ultrapure water continues to undergo thermal convection with the high-temperature gas at the capillary structure 15 of the cover 11. The ultrapure water is referred to as the wetting liquid for the mesh 14, and means the mesh 14 to which the remaining ultrapure water can adhere to the inside top surface of the cover 11. Under gravity, the ultrapure water falls in a water droplet state. Falling onto the top surface of the upper intermediate layer 30, and the ultrapure water exchanges with the upper intermediate layer 30 and is evaporated from a liquid state into a high-temperature gas to rise again. The heat is dissipated by the capillary action of the gap between the top surface capillary structure 31 and the bottom surface capillary structure 35 of the upper interposer 30, and the semiconductor wafer 44 on the top or middle layer is taken away again by the falling portion where the protrusion 36 contacts the contact line 14.

Some ultrapure water may drip on the projection 36 of the intermediate or lower interposer 32, 33 through the flow path 34. Generally, the heat can be diffused to the top surface capillary structures 31 of the middle and lower interposers 32, 33, or to the bottom surface capillary structures 35 of the middle and lower interposers 32, 33 through the gaps of the contact lines 14 of the bumps 36, and the heat can be taken away from the middle or lower semiconductor chip 44.

Thus, the ultrapure water is subjected to liquid-phase-to-gas-phase thermal circulation among the set of capillary structures 15, the set of flow channels 34, the top surface capillary structure 31 and the bottom surface capillary structure 35, so as to achieve the heat dissipation effect of the semiconductor wafer.

As shown in fig. 11 and 12, the second embodiment of the package structure 10 of the present invention has substantially the same structure as the first embodiment, and the difference lies in: a set of fasteners 51 couples a set of heat dissipation fins 52 to the outside of the cover 11, thereby improving the heat dissipation effect of the package structure 10.

The foregoing description is intended to be illustrative rather than limiting, and it will be appreciated by those skilled in the art that many modifications, variations or equivalents may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (9)

1. A three-dimensional semiconductor packaging structure with a vapor chamber is characterized by comprising:

a base plate;

a plurality of semiconductor chips are stacked on the bottom plate through a plurality of intermediate layers, each intermediate layer is provided with a top surface capillary structure and a bottom surface capillary structure, the periphery of each intermediate layer is provided with a group of convex parts, and two convex parts are separated by a concave part;

a group of capillary structures and a group of nets are arranged on the inner side of the cover, the group of nets shield the capillary structures, when the cover is combined with the bottom plate to form a steam chamber, the cover covers all the semiconductor chips, all the intermediate layers contact the group of nets through convex parts, and a flow channel connected to the steam chamber is formed from the upper intermediate layer to the concave part of the lower intermediate layer; and

and proper amount of cooling fluid is added into the vapor chamber, and liquid-state-to-gas-state thermal circulation is performed among the capillary structures, the flow channels, the top capillary structure and the bottom capillary structure, so that the heat dissipation effect of the semiconductor wafer is achieved.

2. The three-dimensional semiconductor package structure with vapor chambers according to claim 1, wherein the recesses of the upper interposer to the lower interposer are staggered to maintain the inclined flow channels such that the protrusions of the upper interposer to the lower interposer are arranged in a stepped manner.

3. The three-dimensional semiconductor package with vapor chamber according to claim 1, wherein the lid is made of one of copper, copper alloy and other heat conductive metal.

4. The three-dimensional semiconductor package with vapor chamber according to claim 1, wherein one of copper, copper alloy and other heat conductive metal is coated on the surface of the lid.

5. The semiconductor package with vapor chamber of claim 1, wherein the set of capillary structures are staggered slits formed in the surface of the lid by one of etching, laser engraving, stamping, and die casting.

6. The semiconductor three-dimensional package structure with a vapor chamber of claim 1, wherein the cooling fluid is selected from one of ultra-pure water, ethanol, butane, and a mixture thereof.

7. The three-dimensional semiconductor package structure with a vapor chamber according to claim 1, wherein the interposer is selected from one of a ceramic substrate, an aluminum nitride ceramic substrate, an aluminum oxide ceramic substrate, a silicon oxide ceramic substrate, and a silicon nitride ceramic substrate.

8. The three-dimensional semiconductor package with a vapor chamber according to claim 1, wherein a set of heat conducting pillars are arrayed through all the stacked interposers.

9. The three-dimensional semiconductor package with a vapor chamber according to claim 1, wherein a set of heat dissipation fins is attached to the outside of the lid.

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