JP2001024125A - Flat semiconductor device - Google Patents

Flat semiconductor device

Info

Publication number
JP2001024125A
JP2001024125A JP11195461A JP19546199A JP2001024125A JP 2001024125 A JP2001024125 A JP 2001024125A JP 11195461 A JP11195461 A JP 11195461A JP 19546199 A JP19546199 A JP 19546199A JP 2001024125 A JP2001024125 A JP 2001024125A
Authority
JP
Japan
Prior art keywords
electrode lead
semiconductor device
flat semiconductor
coolant
partition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11195461A
Other languages
Japanese (ja)
Inventor
Riichi Sawano
理一 澤野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP11195461A priority Critical patent/JP2001024125A/en
Publication of JP2001024125A publication Critical patent/JP2001024125A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To improve cooling of semiconductor chips by giving a cooling function to electrode lead elements which are components of a flat semiconductor device and exhibit the performances of the large capacity semiconductor device sufficiently. SOLUTION: A flat semiconductor device comprises a plurality of semiconductor chips 2 arranged on the same plane, hard metal terminals 3, electrode lead elements 4 and a package container 6 made of insulating material. A plurality of partition fins 13 and coolant passages 14 are formed in each electrode lead element 4, and coolant is supplied from the outside through a coolant entrance 15 and a coolant exit 16 to remove heat generated by the semiconductor chips from the electrode lead element.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電力用に適用する
加圧接触型の平形半導体素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type flat semiconductor device applied to electric power.

【0002】[0002]

【従来の技術】まず、頭記した平形半導体素子の従来構
造を図5に示し、図6に沸騰冷却方式を採用した平形半
導体素子スタックの従来構成を示す。図5において、平
形半導体素子1は、同一面上に配列した複数個の半導体
チップ2と、各半導体チップ2ごとにその主面を両側か
ら挟んで電極面に接触する硬金属端子3、各硬金属端子
3を一括して両側から半導体チップ2の主面に圧接する
上下一対の電極導出体4と、各電極導出体4の外周縁に
気密接合した封止金属板5と、電極導出体4の周囲を囲
繞して前記封止金属板5の間に介装して気密室を形成す
る絶縁物製の外囲容器6とから構成されている。
2. Description of the Related Art First, a conventional structure of a flat semiconductor device described above is shown in FIG. 5, and FIG. 6 shows a conventional structure of a flat semiconductor device stack employing a boiling cooling method. In FIG. 5, a flat semiconductor element 1 includes a plurality of semiconductor chips 2 arranged on the same surface, a hard metal terminal 3 contacting an electrode surface with the main surface of each semiconductor chip 2 sandwiched from both sides, A pair of upper and lower electrode leads 4 that press the metal terminals 3 together from both sides against the main surface of the semiconductor chip 2, a sealing metal plate 5 hermetically bonded to the outer periphery of each electrode lead 4, and an electrode lead 4 And an outer container 6 made of an insulating material, which is interposed between the sealing metal plates 5 to form an airtight chamber.

【0003】ここで、硬金属端子3は、例えばMoなど
の硬質金属を素材として製作されたものであり、半導体
チップ2の主面に加圧接触した際に偏加圧に起因するチ
ップ割れを防ぐようにしている。また、電極導出体4は
半導体チップ2ヘの通電と、半導体チップ2に発生する
熱を外部に伝える役目を有し、導電性,伝熱性の高い銅
などの金属板を成形加工したものが使用されている。な
お、図示例の構造では、硬金属端子3が各半導体チップ
2に対して個々に設けてあるが、複数の半導体チップご
とに共通な硬金属端子を設けたものもある。
Here, the hard metal terminal 3 is made of a hard metal such as Mo, for example. When the hard metal terminal 3 comes into pressure contact with the main surface of the semiconductor chip 2, chip cracks caused by uneven pressurization are prevented. I try to prevent it. Further, the electrode lead-out body 4 has a role of conducting electricity to the semiconductor chip 2 and transmitting heat generated in the semiconductor chip 2 to the outside, and is formed by forming a metal plate such as copper having high conductivity and heat conductivity. Have been. Although the hard metal terminals 3 are individually provided for the respective semiconductor chips 2 in the structure of the illustrated example, some hard metal terminals are provided for each of the plurality of semiconductor chips.

【0004】また、図6において、7は平形半導体素子
1を両側からサンドイッチ式に挟んで重ね合わせたヒー
トシンクとしての冷却体、8は平形半導体素子1と冷却
体7のスタック組立体の両端に配した加圧端板、9はそ
の締付スタッド、10は皿ばね、11はボールであり、
中空ブロックになる冷却体7は冷媒管7aを介して凝縮
放熱器12の冷媒液溜部12aに連結れさている。
[0006] In FIG. 6, reference numeral 7 denotes a cooling body as a heat sink in which the flat semiconductor element 1 is sandwiched from both sides in a sandwich manner, and 8 is provided at both ends of a stack assembly of the flat semiconductor element 1 and the cooling body 7. 9 is a tightening stud, 10 is a disc spring, 11 is a ball,
The cooling body 7 which becomes a hollow block is connected to a refrigerant liquid reservoir 12a of the condensation radiator 12 via a refrigerant pipe 7a.

【0005】かかる構成で、半導体チップ2で発生した
熱は半導体チップ2に圧接している硬金属端子3,およ
び電極導出体4を伝熱経路として冷却体7に伝熱した
後、中空冷却体7の内部に封入した冷媒の沸騰,凝縮の
相変化により凝縮放熱器12から系外に放熱して除熱さ
れる。
In this configuration, the heat generated in the semiconductor chip 2 is transferred to the cooling body 7 using the hard metal terminals 3 and the electrode lead-out members 4 pressed against the semiconductor chip 2 as heat transfer paths, and then the hollow cooling body Due to the phase change of the boiling and condensation of the refrigerant sealed in the inside of the, heat is radiated from the condensation radiator 12 to the outside of the system and is removed.

【0006】[0006]

【発明が解決しようとする課題】ところで、前記した平
形半導体素子スタックではその冷却性で次に記すような
問題点がある。すなわち、平形半導体素子が適用される
装置の高機能化,大容量化に伴い、平形半導体素子1に
発生する損失熱量はますます増大する傾向にある。一
方、平形半導体素子1の内部,および半導体素子1と冷
却体6との間の伝熱経路には熱抵抗が存在し、特に半導
体素子1の電極導出体4と冷却体6との間の接触面の熱
抵抗は大きくて局部的にもばらつきがあることから、半
導体素子の発熱量が増大すると平形半導体素子1の内部
(半導体チップ2/電極導出体4の表面)の温度勾配が
大きくなり、半導体チップ2の温度が許容限界に達して
しまう。したがって、半導体チップ2を許容温度以下に
保って運転するには冷媒温度を下げる必要があるが、こ
のために冷却体7,凝縮放熱器12が大型化する。
However, the above-mentioned flat semiconductor element stack has the following problems due to its cooling property. In other words, the heat loss generated in the flat semiconductor element 1 tends to increase more and more as the function of the device to which the flat semiconductor element is applied becomes higher and the capacity increases. On the other hand, thermal resistance exists in the flat semiconductor element 1 and in the heat transfer path between the semiconductor element 1 and the cooling body 6, and particularly, the contact between the electrode lead 4 and the cooling body 6 of the semiconductor element 1. Since the thermal resistance of the surface is large and varies locally, when the heat generation of the semiconductor element increases, the temperature gradient inside the flat semiconductor element 1 (the surface of the semiconductor chip 2 / the surface of the electrode lead body 4) increases, The temperature of the semiconductor chip 2 reaches an allowable limit. Therefore, in order to operate the semiconductor chip 2 at a temperature equal to or lower than the allowable temperature, it is necessary to lower the refrigerant temperature. However, the cooling body 7 and the condensing radiator 12 increase in size.

【0007】本発明は、上記の点に鑑みがみなされたも
のであり、その目的は前記課題を解決し、平形半導体素
子の構成部品である電極導出体に冷却機能を持たせて半
導体チップの冷却効率を高め、大容量の半導体素子の性
能を十分に発揮できるように改良した平形半導体素子を
提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to solve the above-mentioned problems and to provide a cooling function to an electrode lead body, which is a component of a flat semiconductor device, to provide a semiconductor chip. It is an object of the present invention to provide a flat semiconductor device improved in cooling efficiency and capable of sufficiently exhibiting the performance of a large-capacity semiconductor device.

【0008】[0008]

【課題を解決するための手段】上述した目的を達成する
ために、本発明によれば、同一面上に配列した複数個の
半導体チップと、各半導体チップの両主面に重ね合わせ
てその電極に接触する硬金属端子と、各硬金属端子を一
括して両側から半導体チップの主面に圧接する二枚の電
極導出体と、該電極導出体の周囲を囲繞し、各電極導出
体に気密接合してその周上に張り出した封止金属板との
間で気密室を形成する絶縁物製の外囲容器とからなる平
形半導体素子において、前記電極導出体の内部に複数条
の隔壁フイン,および各隔壁フィンに沿った複数条の冷
媒通路を形成し、かつ電極導出体の外周側面に前記冷媒
通路に通じる冷媒入口,出口を設ける(請求項1)もの
とし、具体的には次記のような態様で構成することがで
きる。
According to the present invention, there is provided a semiconductor device comprising: a plurality of semiconductor chips arranged on the same surface; Hard metal terminals, two hard metal terminals which are collectively pressed from both sides against the main surface of the semiconductor chip, and a periphery of the electrode lead body, which is hermetically sealed with each electrode lead body. In a flat semiconductor device comprising an insulating outer container which forms an airtight chamber between a sealing metal plate joined and protruding on the periphery thereof, a plurality of partition fins, In addition, a plurality of refrigerant passages are formed along each partition fin, and refrigerant inlets and outlets communicating with the refrigerant passages are provided on the outer peripheral side surface of the electrode lead-out body (claim 1). It can be configured in such a manner.

【0009】(1) 電極導出体の内部に形成した隔壁フィ
ンを半導体チップの配列と平行にパターン形成する(請
求項2)。 (2) 電極導出体の内部に形成した隔壁フインを半導体チ
ップの配列に対して斜めにパターン形成する(請求項
3)。
(1) The partition fin formed inside the electrode lead body is patterned in parallel with the arrangement of the semiconductor chips. (2) The partition fin formed inside the electrode lead body is patterned obliquely to the arrangement of the semiconductor chips.

【0010】(3) 前記した隔壁フインと冷媒との間の伝
熱面積を大きくするように、フィンの表面を凹凸面とな
す(請求項4)。 (4) 半導体チップの両側に配した一対の電極導出体につ
いて、その一方の電極導出体に形成した隔壁フィンと他
方の導出体に形成した隔壁フィンとが互いに交差する向
きにパターン形成する(請求項5)。
(3) The surface of the fin is made uneven so that the heat transfer area between the partition fin and the coolant is increased. (4) With respect to a pair of electrode lead-out bodies disposed on both sides of the semiconductor chip, pattern formation is performed so that partition wall fins formed on one of the electrode lead-out bodies and partition wall fins formed on the other lead-out body cross each other (claim). Item 5).

【0011】(5) 冷媒入口と出口を電極導出体の対角上
に振り分けてその周面に設ける(請求項6)。 (6) 冷媒流通路に面した電極導出体の内部表面に絶縁層
を被覆形成し、冷媒として導電性のある水が使えるよう
にする(請求項7)。
(5) The coolant inlet and outlet are distributed on the diagonal of the electrode lead-out body and provided on the peripheral surface thereof. (6) An insulating layer is formed on the inner surface of the electrode lead body facing the coolant flow passage, so that conductive water can be used as the coolant.

【0012】上記の構成によれば、平形半導体素子の構
成部品である電極導出体自身に冷却機能を持たせたこと
により、従来構造の平形半導体素子と比べて電極導出体
内部における伝熱抵抗が小さくなる。これにより、半導
体チップと冷媒との間の温度差(=熱抵抗)を小さく抑
えて冷却効率の大幅な向上が図れるとともに、平形半導
体素子でスタックを組む場合でも従来使用していた冷却
体を省略してスタック組立体を小形,コンパクトに構成
することが可能となる。
According to the above structure, the electrode lead body itself, which is a component of the flat semiconductor element, has a cooling function, so that the heat transfer resistance inside the electrode lead body is lower than that of the flat semiconductor element having the conventional structure. Become smaller. As a result, the temperature difference (= thermal resistance) between the semiconductor chip and the coolant can be suppressed to a great extent, and the cooling efficiency can be greatly improved. As a result, the stack assembly can be made compact and compact.

【0013】また、この場合に前項(4) のように、一方
の電極導出体に形成した隔壁フィンと他方の導出体に形
成した隔壁フィンとが互いに交差する向きにパターン形
成することにより、スタック組立体で隣合う平形半導体
素子の電極導出体の隔壁フィンが互いに相手側の電極導
出体を補強し合うに働くので、電極導出体の反り,およ
びこの反りに起因する加圧力のばらつきが効果的に防げ
る。さらに、(5) 項のように冷媒入口と出口を電極導出
体の対角上に振り分けて設けることで、電極導出体の内
部に形成した各条の冷媒通路が略同じ長さになって冷媒
を均等に通流させることができる。
Further, in this case, as described in the above item (4), the partition fin formed on one electrode lead and the partition fin formed on the other lead are patterned in a direction crossing each other, thereby forming a stack. Since the partition fins of the electrode leads of the adjacent flat semiconductor element in the assembly work to reinforce each other's electrode leads, the warpage of the electrode leads and the variation in the pressing force caused by this warp are effective. Can be prevented. Furthermore, by arranging the coolant inlet and outlet on the diagonal of the electrode lead-out body as described in the item (5), the coolant passage of each strip formed inside the electrode lead-out body becomes substantially the same length, and Can be made to flow evenly.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施の形態を図1
〜図4に示す各実施例に基づいて説明する。なお、実施
例の図中で図5に対応する部材には同じ符号を付してそ
の詳細な説明は省略する。
FIG. 1 is a block diagram showing an embodiment of the present invention.
A description will be given based on each embodiment shown in FIGS. In the drawings of the embodiment, members corresponding to those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

【0015】〔実施例1〕図1(a),(b) は本発明の請求
項1,2,6に対応する実施例を示すものである。この
実施例においては、平形半導体素子1は基本的に図5に
示した従来構造と同様であるが、半導体チップ2,硬金
属端子3を両側から挟持した加圧ブロックとしての電極
導出体4について、その内部には格子状に並ぶ半導体チ
ップ2の配列と平行に複数条の隔壁フィン13,および
該隔壁フィン13に沿った冷媒通流路14が電極導出体
4のほぼ全面域に亘ってパターン形成されており、さら
に電極導出体4の外周側面には前記冷媒通路14に通じ
る冷媒入口15,および出口16が対角上の各コーナー
部に開口している。
Embodiment 1 FIGS. 1A and 1B show an embodiment corresponding to claims 1, 2 and 6 of the present invention. In this embodiment, the flat semiconductor element 1 is basically the same as the conventional structure shown in FIG. 5, but an electrode lead-out body 4 as a pressure block sandwiching a semiconductor chip 2 and hard metal terminals 3 from both sides. A plurality of partition fins 13 and a coolant passage 14 along the partition fins 13 are formed in the inside of the electrode lead body 4 over substantially the entire area thereof in parallel with the arrangement of the semiconductor chips 2 arranged in a grid. In addition, a coolant inlet 15 and an outlet 16 communicating with the coolant passage 14 are opened at diagonally opposite corners on the outer peripheral side surface of the electrode lead-out body 4.

【0016】かかる構成で、冷媒入口15より流入した
冷媒は図示矢印のように各冷媒通路14に分流し、隔壁
フィン13の表面に沿って流れた後に再び合流して冷媒
出口16より流出する。なお、電極導出体4の冷媒出口
16から流出した冷媒は半導体素子スタックとは別置の
放熱器に移動し、ここで外部空気との間で熱交換して冷
やされた後、再び半導体素子の電極導出体4に還流して
その冷媒入口15へ流入するように循環する。
In this configuration, the refrigerant flowing from the refrigerant inlet 15 is divided into the refrigerant passages 14 as shown by arrows in the drawing, flows along the surface of the partition fins 13 and then joins again and flows out from the refrigerant outlet 16. In addition, the refrigerant flowing out from the refrigerant outlet 16 of the electrode lead body 4 moves to a radiator provided separately from the semiconductor element stack, exchanges heat with external air and is cooled, and then the semiconductor element stack is again cooled. It circulates so as to return to the electrode lead-out body 4 and flow into the refrigerant inlet 15.

【0017】ここで、平形半導体素子1の通電に伴って
半導体チップ2で発生した損失熱は、半導体チップ2の
両面に接している硬金属端子3から電極導出体4に伝熱
し、その隔壁フィン13の表面から冷媒通路14を流れ
る冷媒に熱貫流して系外に放熱される。
Here, the heat loss generated in the semiconductor chip 2 due to the energization of the flat semiconductor element 1 is transferred from the hard metal terminals 3 in contact with both surfaces of the semiconductor chip 2 to the electrode lead-out body 4, and the partition fins are formed. The heat flowing through the refrigerant flowing from the surface of the refrigerant passage 13 through the refrigerant passage 14 is radiated to the outside of the system.

【0018】このように、平形半導体素子1の構成部品
である電極導出体4を活用してその内部に隔壁フィン1
4,冷媒通路15を分散形成し、この冷媒通路15に外
部から冷媒を流すことにより、半導体チップ2と電極導
出体4の隔壁フィン14に至る伝熱経路の熱抵抗が小さ
く、かつ隔壁フィン14と冷媒通路15に流れる冷媒と
の間に大きな伝熱面積か確保されるので、半導体チップ
2を効率よく冷却できる。
As described above, the partitioning fins 1 are provided inside the flattened semiconductor element 1 by utilizing the electrode lead-out body 4 as a component.
4, the coolant passages 15 are formed in a dispersed manner, and a coolant flows from the outside to the coolant passages 15 so that the heat resistance of the heat transfer path from the semiconductor chip 2 to the partition fins 14 of the electrode lead-out body 4 is small, and the partition fins 14 Since a large heat transfer area is secured between the semiconductor chip 2 and the refrigerant flowing through the refrigerant passage 15, the semiconductor chip 2 can be efficiently cooled.

【0019】次に、前記構成を基本とした本発明の幾つ
かの応用実施例を図2,図3,図4で説明する。 〔実施例2〕図2は本発明の請求項3に対応した実施例
を示すものである。この実施例においては、隔壁フイン
13,および冷媒通路14が、半導体チップ2の配列
(図1(b) 参照)に対して斜めに延在するようパターン
形成されている。これにより、電極導出体4の対角コー
ナーに配置した冷媒入口15と出口16の間で冷媒がほ
ぼ直線的に流れるので、図1のパターン構成と比べて冷
媒の流路抵抗を低く抑えることができる。
Next, several applied embodiments of the present invention based on the above configuration will be described with reference to FIGS. [Embodiment 2] FIG. 2 shows an embodiment corresponding to claim 3 of the present invention. In this embodiment, the partition fins 13 and the coolant passages 14 are patterned so as to extend obliquely with respect to the arrangement of the semiconductor chips 2 (see FIG. 1B). As a result, the refrigerant flows substantially linearly between the refrigerant inlet 15 and the refrigerant outlet 16 arranged at the diagonal corners of the electrode lead-out body 4, so that the flow resistance of the refrigerant can be suppressed lower than in the pattern configuration of FIG. it can.

【0020】〔実施例3〕図3は本発明の請求項4に対
応した実施例を示すものである。この実施例では、隔壁
フィン13について、冷媒通路14に面したフィン表面
に凹凸面13aが形成されている。なお、この凹凸面1
3aは例えばサンドブラスト処理などにより形成した微
小な凹凸面も含むものとする。
[Embodiment 3] FIG. 3 shows an embodiment according to claim 4 of the present invention. In this embodiment, the partition wall fin 13 has an uneven surface 13a formed on the surface of the fin facing the refrigerant passage. In addition, this uneven surface 1
Reference numeral 3a also includes a fine uneven surface formed by, for example, sandblasting.

【0021】このように、隔壁フィン13の表面に凹凸
面13aを形成することにより、冷媒通路14に流れる
冷媒と隔壁フィン13との間の伝熱面積が増すととも
に、冷媒通流時に攪拌効果が生じてフィン/冷媒間の熱
伝達が促進される。また、冷媒が沸騰伝熱する場合で
も、隔壁フィン13の表面に形成した凸部が冷媒の核沸
騰,および蒸気気泡の離脱を促進させ、安定した核沸騰
を維持して伝熱性能が向上する。
By forming the uneven surface 13a on the surface of the partition fin 13, the heat transfer area between the refrigerant flowing in the refrigerant passage 14 and the partition fin 13 is increased, and the stirring effect is exerted when the refrigerant flows. This promotes heat transfer between the fins / coolant. Further, even when the refrigerant performs boiling heat transfer, the convex portion formed on the surface of the partition wall fins 13 promotes nucleate boiling of the refrigerant and separation of vapor bubbles, maintains stable nucleate boiling, and improves heat transfer performance. .

【0022】なお、図示例では隔壁フィン13が図1の
実施例1と同じパターンに形成されているが、図2に示
した実施例2の斜めパターンに対しても同様に実施でき
ることは勿論である。
In the illustrated example, the partition fins 13 are formed in the same pattern as that of the first embodiment shown in FIG. 1. However, it is needless to say that the same can be applied to the oblique pattern of the second embodiment shown in FIG. is there.

【0023】〔実施例4〕次に、本発明の請求項5に対
応する実施例について説明する。先に図5で述べたよう
に、平形半導体素子1は半導体チップ2,硬金属端子3
をその両側から二枚の電極導出体4で挟んだ構成にな
る。そこで、この実施例では、二枚のうち一方の電極導
出体4に形成した先記の各実施例の隔壁フィン13と、
他方の電極導出体4に形成した隔壁フィン13とが互い
に交差するような向きにパターン形成して平形半導体素
子1を組立てるものとする。
Embodiment 4 Next, an embodiment according to claim 5 of the present invention will be described. As described above with reference to FIG. 5, the flat semiconductor element 1 includes the semiconductor chip 2 and the hard metal terminals 3.
Is sandwiched between two electrode lead-out bodies 4 from both sides thereof. Therefore, in this embodiment, the partition wall fin 13 of each of the above-described embodiments formed on one of the two electrode lead-out bodies 4,
The flat semiconductor element 1 is assembled by forming a pattern so that the partition fins 13 formed on the other electrode lead-out body 4 intersect each other.

【0024】このような配置構成とすることで、複数個
の平形半導体素子1でスタックを組立てた場合に、隣接
し合う半導体素子1の電極導出体4の隔壁フィン13が
相手側の電極導出体4の反り易い方向を相互に補強し合
うようになる。これにより電極導出体4の反り、および
この反りに起因して半導体チップ2への加圧力がばらつ
くのを効果的に防止できる。
With such an arrangement, when a stack is assembled with a plurality of flat semiconductor elements 1, the partition fins 13 of the electrode lead bodies 4 of the adjacent semiconductor elements 1 are connected to the other electrode lead bodies. 4 reinforce each other in the easily warped directions. Thereby, it is possible to effectively prevent the electrode lead-out body 4 from warping and the pressure applied to the semiconductor chip 2 due to the warping.

【0025】〔実施例4〕次に、本発明の請求項7に対
応する実施例を図4に示す。この実施例では、電極導出
体4の内部に形成した冷媒通路14の全域でその内面を
覆うように、電極導出体4の内部壁面に樹脂,あるいは
セラミクス等の電気的な絶縁層17が被覆形成されてい
る。これにより、電極導出体/冷媒間が電気的に絶縁さ
れるため、例えば水のような導電性を有する冷媒も使用
可能となる。なお、以上述べた各実施例では、平形半導
体素子の外形形状が角型であるが、外形形状が丸型の平
形半導体素子についても同様に実施することができる。
[Embodiment 4] Next, FIG. 4 shows an embodiment corresponding to claim 7 of the present invention. In this embodiment, an electrical insulating layer 17 made of resin or ceramics is formed on the inner wall surface of the electrode lead-out body 4 so as to cover the entire inner surface of the coolant passage 14 formed inside the electrode lead-out body 4. Have been. As a result, since the electrode lead-out body / refrigerant is electrically insulated, a conductive refrigerant such as water can be used. In each of the embodiments described above, the outer shape of the flat semiconductor device is square, but the same can be applied to a flat semiconductor device having a round outer shape.

【0026】[0026]

【発明の効果】以上述べたように、本発明の構成によれ
ば、平形半導体素子の通電部品である電極導出体の内部
に冷媒通路と隔壁フインを設けてここに冷媒を直接通流
させるよう構成したことにより、従来構造の平形半導体
素子と比べて、電極導出体内部における伝熱抵抗を低め
て半導体チップと冷媒との間の温度差(=熱抵抗)を小
さく抑えることができ、これにより半導体素子の冷却効
率が大幅に改善されるとともに、半導体素子内部の温度
上昇も低く抑えられるので、半導体チップの許容温度に
対して余裕が大きくとれ、平形半導体素子の信頼性向上
が図れる。
As described above, according to the structure of the present invention, a coolant passage and a partition fin are provided inside an electrode lead-out body, which is a current-carrying part of a flat semiconductor device, so that the coolant flows directly through the passage. With this configuration, the heat transfer resistance inside the electrode lead-out body can be reduced and the temperature difference between the semiconductor chip and the coolant (= thermal resistance) can be reduced as compared with the conventional flat semiconductor element. Since the cooling efficiency of the semiconductor element is greatly improved, and the temperature rise inside the semiconductor element is also suppressed to a low level, a margin is allowed for the allowable temperature of the semiconductor chip, and the reliability of the flat semiconductor element can be improved.

【0027】また、複数の平形半導体素子でスタックを
組む場合でも、従来のスタック構造で半導体素子間に介
装していた冷却体を省略してスタックを小形,コンパク
トに構成することも可能である。
Even when a stack is formed by a plurality of flat semiconductor elements, the stack can be made small and compact by omitting the cooling body interposed between the semiconductor elements in the conventional stack structure. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1に係わる平形半導体素子の構
造図であり、(a) は縦断面図、(b) は(a) 図の矢視X−
X断面図
FIGS. 1A and 1B are structural views of a flat semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a longitudinal sectional view, and FIG.
X sectional view

【図2】本発明の実施例2に係わる電極導出体の隔壁フ
ィンのパターンを表した横断平面図
FIG. 2 is a cross-sectional plan view illustrating a pattern of partition fins of an electrode lead-out body according to a second embodiment of the present invention.

【図3】本発明の実施例3に係わる電極導出体の隔壁フ
ィンのパターンを表した横断平面図
FIG. 3 is a cross-sectional plan view illustrating a pattern of partition fins of an electrode lead-out body according to Embodiment 3 of the present invention.

【図4】本発明の実施例4に係わる電極導出体の冷媒通
路の断面図
FIG. 4 is a sectional view of a refrigerant passage of an electrode lead-out body according to a fourth embodiment of the present invention.

【図5】平形半導体素子の従来例の組立構造の断面図FIG. 5 is a sectional view of a conventional assembly structure of a flat semiconductor element.

【図6】図5の平形半導体素子で組んだ沸騰冷却方式に
よる半導体素子スタックの組立構成図
6 is an assembling configuration diagram of a semiconductor element stack by a boiling cooling method assembled by the flat semiconductor elements of FIG. 5;

【符号の説明】[Explanation of symbols]

1 平形半導体素子 2 半導体チップ 3 硬金属端子 4 電極導出体 5 封止金属板 6 外囲容器 13 隔壁フィン 13a 凹凸面 14 冷媒通路 15 冷媒入口 16 冷媒出口 17 絶縁層 DESCRIPTION OF SYMBOLS 1 Flat semiconductor element 2 Semiconductor chip 3 Hard metal terminal 4 Electrode lead body 5 Sealing metal plate 6 Enclosure container 13 Partition fin 13a Irregular surface 14 Refrigerant passage 15 Refrigerant inlet 16 Refrigerant outlet 17 Insulating layer

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】同一面上に配列した複数個の半導体チップ
と、各半導体チップの両主面に重ね合わせてその電極に
接触する硬金属端子と、各硬金属端子を一括して両側か
ら半導体チップの主面に圧接する二枚の電極導出体と、
該電極導出体を囲繞し、各電極導出体に気密接合してそ
の周上に張り出した封止金属板との間で気密室を形成す
る絶縁物製の外囲容器とからなる平形半導体素子におい
て、前記電極導出体の内部に複数条の隔壁フイン,およ
び各隔壁フィンに沿った複数条の冷媒通路を形成し、か
つ電極導出体の外周側面に前記冷媒通路に通じる冷媒入
口,出口を設けたことを特徴とす平形半導体素子。
1. A semiconductor device comprising: a plurality of semiconductor chips arranged on the same surface; a hard metal terminal which is superimposed on both main surfaces of each semiconductor chip and comes into contact with its electrode; Two electrode lead bodies pressed against the main surface of the chip,
A flat semiconductor element comprising an outer container made of an insulator surrounding the electrode lead-out body and hermetically bonded to each electrode lead-out body and forming an airtight chamber between the metal lead-out and a sealing metal plate protruding on the periphery thereof. A plurality of partition fins and a plurality of coolant passages along each partition fin are formed inside the electrode lead body, and a coolant inlet and an outlet communicating with the coolant passage are provided on an outer peripheral side surface of the electrode lead body. A flat semiconductor device characterized by the above-mentioned.
【請求項2】請求項1記載の平形半導体素子において、
電極導出体の内部に形成した隔壁フィンを半導体チップ
の配列と平行にパターン形成したことを特徴とする平形
半導体素子。
2. The flat semiconductor device according to claim 1, wherein
A flat semiconductor device, wherein partition fins formed inside an electrode lead body are formed in a pattern in parallel with the arrangement of semiconductor chips.
【請求項3】請求項1記載の平形半導体素子において、
電極導出体の内部に形成した隔壁フインを半導体チップ
の配列に対して斜めにパターン形成したことを特徴とす
る平形半導体素子。
3. The flat semiconductor device according to claim 1, wherein
A flat semiconductor device, wherein a partition fin formed inside an electrode lead body is pattern-formed obliquely to an arrangement of semiconductor chips.
【請求項4】請求項2,または3記載の平形半導体素子
において、隔壁フインの表面を凹凸面となしたことを特
徴とする平形半導体素子。
4. A flat semiconductor device according to claim 2, wherein the surface of the partition wall fin is made uneven.
【請求項5】請求項1ないし4のいずれかに記載の平形
半導体素子において、半導体チップの両側に配した一対
の電極導出体に対して、その一方の電極導出体に形成し
た隔壁フィンと他方の導出体に形成した隔壁フィンとが
互いに交差する向きにパターン形成したことを特徴とす
る平形半導体素子。
5. A flat semiconductor device according to claim 1, wherein a pair of electrode lead-out members arranged on both sides of the semiconductor chip is provided with a partition fin formed on one of the electrode lead-out members and the other. And a partition fin formed on the lead-out body of (1) is patterned in a direction crossing each other.
【請求項6】請求項1ないし5のいずれかに記載の平形
半導体素子において、冷媒入口と出口を電極導出体の対
角上に振り分けて設けたことを特徴とする平形半導体素
子。
6. The flat semiconductor device according to claim 1, wherein a coolant inlet and a coolant outlet are distributed on a diagonal of the electrode lead-out body.
【請求項7】請求項1ないし6のいずれかに記載の平形
半導体素子において、冷媒流通路に面した電極導出体の
内部表面に絶縁層を被覆形成したことを特徴とする平形
半導体素子。
7. The flat semiconductor device according to claim 1, wherein an inner surface of the electrode lead body facing the coolant flow passage is coated with an insulating layer.
JP11195461A 1999-07-09 1999-07-09 Flat semiconductor device Pending JP2001024125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11195461A JP2001024125A (en) 1999-07-09 1999-07-09 Flat semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11195461A JP2001024125A (en) 1999-07-09 1999-07-09 Flat semiconductor device

Publications (1)

Publication Number Publication Date
JP2001024125A true JP2001024125A (en) 2001-01-26

Family

ID=16341470

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2001024125A (en)

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JP2006229180A (en) * 2005-01-24 2006-08-31 Toyota Motor Corp Semiconductor module and device
JP2008311496A (en) * 2007-06-15 2008-12-25 Toyota Motor Corp Cooling structure of semiconductor device
WO2011018882A1 (en) 2009-08-10 2011-02-17 Fuji Electric Systems Co., Ltd. Semiconductor module and cooling unit
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006058860A2 (en) * 2004-11-29 2006-06-08 Siemens Aktiengesellschaft Heat exchange device for a semiconductor component and method for producing said heat exchange device
WO2006058860A3 (en) * 2004-11-29 2006-08-17 Siemens Ag Heat exchange device for a semiconductor component and method for producing said heat exchange device
JP2006229180A (en) * 2005-01-24 2006-08-31 Toyota Motor Corp Semiconductor module and device
US8213179B2 (en) 2007-06-15 2012-07-03 Toyota Jidosha Kabushiki Kaisha Semiconductor element cooling structure
JP4719187B2 (en) * 2007-06-15 2011-07-06 トヨタ自動車株式会社 Semiconductor device cooling structure
JP2008311496A (en) * 2007-06-15 2008-12-25 Toyota Motor Corp Cooling structure of semiconductor device
WO2011018882A1 (en) 2009-08-10 2011-02-17 Fuji Electric Systems Co., Ltd. Semiconductor module and cooling unit
US8933557B2 (en) 2009-08-10 2015-01-13 Fuji Electric Co., Ltd. Semiconductor module and cooling unit
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CN109426049B (en) * 2017-08-21 2021-03-05 深圳光峰科技股份有限公司 Liquid cooling circulation heat abstractor, liquid cooling circulation heat dissipation system and optical projection system
JP2020004894A (en) * 2018-06-29 2020-01-09 三菱重工業株式会社 Semiconductor device cooling structure and electronic device cooling structure
JP7075837B2 (en) 2018-06-29 2022-05-26 三菱重工業株式会社 Cooling structure of semiconductor elements and cooling structure of electronic devices
CN110875265A (en) * 2018-08-15 2020-03-10 株式会社东芝 Semiconductor device and power converter

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