TWI765489B - Mems device, manufacturing method of the same and integrated mems using the same - Google Patents

Mems device, manufacturing method of the same and integrated mems using the same Download PDF

Info

Publication number
TWI765489B
TWI765489B TW109145665A TW109145665A TWI765489B TW I765489 B TWI765489 B TW I765489B TW 109145665 A TW109145665 A TW 109145665A TW 109145665 A TW109145665 A TW 109145665A TW I765489 B TWI765489 B TW I765489B
Authority
TW
Taiwan
Prior art keywords
layer
dielectric layer
opening
mems device
groove structure
Prior art date
Application number
TW109145665A
Other languages
Chinese (zh)
Other versions
TW202124254A (en
Inventor
張恆中
黃芝傑
蔡智雅
林靖淵
Original Assignee
財團法人工業技術研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 財團法人工業技術研究院 filed Critical 財團法人工業技術研究院
Publication of TW202124254A publication Critical patent/TW202124254A/en
Priority to US17/412,160 priority Critical patent/US11939212B2/en
Application granted granted Critical
Publication of TWI765489B publication Critical patent/TWI765489B/en

Links

Images

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/0035Packages or encapsulation for maintaining a controlled atmosphere inside of the chamber containing the MEMS
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00047Cavities
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261Processes for packaging MEMS devices
    • B81C1/00277Processes for packaging MEMS devices for maintaining a controlled atmosphere inside of the cavity containing the MEMS
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00Specific applications of microelectromechanical systems
    • B81B2201/02Sensors
    • B81B2201/0264Pressure sensors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Micromachines (AREA)

Abstract

A MEMS device includes a substrate having at least one contact. The MEMS device also includes a first dielectric layer disposed on the substrate. The MEMS device further includes at least one metal layer disposed on the first dielectric layer, and at least a portion of the metal layer electrically connected to the contact. The MEMS device includes a second dielectric layer disposed on the first dielectric layer and the metal layer and having a notch structure. The MEMS device also includes a structure layer disposed on the second dielectric layer and having an opening. The opening is disposed to correspond to the notch structure, and the cross-sectional area of the bottom of the opening is smaller than the cross-sectional area of the top of the notch structure. The MEMS device further includes a filling layer, and at least a portion of the filling layer is disposed in the opening and the notch structure. The second dielectric layer, the structure layer and the filling layer define a chamber.

Description

微機電系統裝置、其製造方法與使用其之整合式微機電系統Microelectromechanical system device, method of manufacturing the same, and integrated microelectromechanical system using the same

本揭露實施例是有關於一種微機電系統(microelectromechanical system, MEMS)裝置、其製造方法與使用其之整合式微機電系統,且特別是有關於一種具有良好封孔品質的微機電系統裝置、其製造方法與使用其之整合式微機電系統。Embodiments of the present disclosure relate to a microelectromechanical system (MEMS) device, a method for fabricating the same, and an integrated MEMS device using the same, and more particularly, to a MEMS device with good sealing quality, and its fabrication A method and an integrated microelectromechanical system using the same.

微機電系統(MEMS)裝置通常包含用以感測一物理條件(諸如力、加速度、壓力、溫度或振動)之機械元件(固定元件及/或可移動元件)及用以處理電訊號之電子元件。因此,MEMS裝置常作為一感測器,並被廣泛用於諸如汽車系統、慣性導引系統、家用電器、各種裝置之保護系統及諸多其他工業、科學及工程系統等應用中。Microelectromechanical systems (MEMS) devices typically include mechanical elements (fixed and/or movable) to sense a physical condition (such as force, acceleration, pressure, temperature, or vibration) and electronic elements to process electrical signals . Therefore, MEMS devices are often used as sensors and are widely used in applications such as automotive systems, inertial guidance systems, household appliances, protection systems for various devices, and many other industrial, scientific, and engineering systems.

現有的MEMS裝置雖大致符合需求,但並非在每個方面皆令人滿意。舉例而言,當MEMS裝置作為壓力感測器時,可能需要提供氣密的空腔,因而需要良好的封孔品質。然而,為了達到此目的,在製造現有的MEMS裝置時可能產生製程時間過長、製程繁複等問題。Existing MEMS devices, while generally meeting the needs, are not satisfactory in every respect. For example, when a MEMS device is used as a pressure sensor, it may be necessary to provide an air-tight cavity, thus requiring good sealing quality. However, in order to achieve this purpose, problems such as long process time and complicated process may occur when manufacturing the existing MEMS device.

在本揭露的一些實施例中,透過在介電層中設置凹槽結構及在結構層中設置與凹槽結構對應的開口,可使填充層(即用於封孔的結構)連續且均勻地填充於此開口與凹槽結構中,以完成封孔。藉由本揭露實施例的微機電系統裝置與其製造方法,能有效防止封孔接縫(seam)與空心結構的產生,進而提高封孔品質並提升整體的穩定性。此外,不需要繁複的製程,能有效縮短製程時間並降低成本。In some embodiments of the present disclosure, by arranging groove structures in the dielectric layer and arranging openings corresponding to the groove structures in the structure layer, the filling layer (ie, the structure for sealing holes) can be made continuous and uniform. Fill in the opening and groove structure to complete the sealing. By means of the MEMS device and the manufacturing method thereof of the disclosed embodiments, the generation of seams and hollow structures can be effectively prevented, thereby improving the sealing quality and improving the overall stability. In addition, no complicated process is required, which can effectively shorten the process time and reduce the cost.

本揭露實施例包含一種微機電系統裝置。微機電系統裝置包含一基板,基板具有至少一接點。微機電系統裝置也包含一第一介電層,第一介電層設置於基板上。微機電系統裝置更包含至少一金屬層,金屬層設置於第一介電層上,且至少部分金屬層電性連接於接點。微機電系統裝置包含一第二介電層,第二介電層設置於第一介電層與金屬層上並具有一凹槽結構。微機電系統裝置也包含一結構層,結構層設置於第二介電層上並具有一開口。開口對應於凹槽結構設置,且開口之底部的截面積小於凹槽結構之頂部的截面積。微機電系統裝置更包含一填充層,填充層設置於開口與凹槽結構中。第二介電層、結構層與填充層界定一空腔。Embodiments of the present disclosure include a MEMS device. The MEMS device includes a substrate, and the substrate has at least one contact. The MEMS device also includes a first dielectric layer disposed on the substrate. The MEMS device further includes at least one metal layer, the metal layer is disposed on the first dielectric layer, and at least part of the metal layer is electrically connected to the contacts. The MEMS device includes a second dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the metal layer and has a groove structure. The MEMS device also includes a structure layer disposed on the second dielectric layer and having an opening. The openings are disposed corresponding to the groove structures, and the cross-sectional area of the bottom of the opening is smaller than the cross-sectional area of the top of the groove structure. The MEMS device further includes a filling layer, and the filling layer is arranged in the opening and the groove structure. The second dielectric layer, the structure layer and the filling layer define a cavity.

本揭露實施例包含一種微機電系統裝置的製造方法。此微機電系統裝置的製造方法包含提供一基板,基板具有至少一接點。此微機電系統裝置的製造方法也包含在基板上形成一第一介電層。第一介電層具有至少一通孔,通孔暴露接點的部分頂表面。此微機電系統裝置的製造方法更包含在第一介電層上形成至少一金屬層。至少部分金屬層電性連接於接點。此微機電系統裝置的製造方法包含在第一介電層與金屬層上形成一第二介電層。第二介電層具有一凹槽結構。此微機電系統裝置的製造方法也包含在第二介電層上與凹槽結構中形成一犧牲層。此微機電系統裝置的製造方法更包含在第二介電層與犧牲層上形成一結構層。此微機電系統裝置的製造方法包含將部分結構層移除以形成一開口,開口暴露出位於凹槽結構中的犧牲層。此微機電系統裝置的製造方法也包含將犧牲層移除以暴露凹槽結構。開口之底部的截面積小於凹槽結構之頂部的截面積。此微機電系統裝置的製造方法更包含在開口與凹槽結構中形成一填充層。至少部分填充層形成於開口與凹槽結構中,且第二介電層、結構層與填充層界定一空腔。Embodiments of the present disclosure include a method for manufacturing a MEMS device. The manufacturing method of the MEMS device includes providing a substrate, and the substrate has at least one contact. The manufacturing method of the MEMS device also includes forming a first dielectric layer on the substrate. The first dielectric layer has at least one through hole that exposes a portion of the top surface of the contact. The manufacturing method of the MEMS device further includes forming at least one metal layer on the first dielectric layer. At least part of the metal layer is electrically connected to the contact. The manufacturing method of the MEMS device includes forming a second dielectric layer on the first dielectric layer and the metal layer. The second dielectric layer has a groove structure. The method of fabricating the MEMS device also includes forming a sacrificial layer on the second dielectric layer and in the groove structure. The manufacturing method of the MEMS device further includes forming a structure layer on the second dielectric layer and the sacrificial layer. The manufacturing method of the MEMS device includes removing part of the structure layer to form an opening exposing the sacrificial layer in the groove structure. The method of fabricating the MEMS device also includes removing the sacrificial layer to expose the groove structure. The cross-sectional area of the bottom of the opening is smaller than the cross-sectional area of the top of the groove structure. The manufacturing method of the MEMS device further includes forming a filling layer in the opening and groove structure. At least part of the filling layer is formed in the opening and the groove structure, and the second dielectric layer, the structure layer and the filling layer define a cavity.

本揭露實施例包含一種微機電系統裝置的製造方法。此微機電系統裝置的製造方法包含提供一基板,基板具有至少一接點。此微機電系統裝置的製造方法也包含在基板上形成一第一介電層。第一介電層具有至少一通孔,通孔暴露接點的部分頂表面。此微機電系統裝置的製造方法更包含在第一介電層上形成至少一第一金屬層。至少部分第一金屬層電性連接於接點。此外,此微機電系統裝置的製造方法包含在第一介電層與第一金屬層上形成一第二介電層。此微機電系統裝置的製造方法也包含在第二介電層上形成一犧牲層。此微機電系統裝置的製造方法更包含在第二介電層與犧牲層上形成一結構層。再者,此微機電系統裝置的製造方法包含將部分結構層移除以形成一第一開口,第一開口暴露出該犧牲層的部分頂表面。此微機電系統裝置的製造方法也包含透過第一開口將部分犧牲層移除以形成一第二開口,第二開口暴露出第二介電層的部分頂表面。此微機電系統裝置的製造方法更包含透過第二開口將部分第二介電層移除以形成一凹槽結構。第一開口之底部的截面積小於凹槽結構之頂部的截面積。此外,此微機電系統裝置的製造方法包含將犧牲層移除。此微機電系統裝置的製造方法也包含形成一填充層。至少部分填充層形成於第二開口與凹槽結構中,且第二介電層、結構層與填充層界定一空腔。Embodiments of the present disclosure include a method for manufacturing a MEMS device. The manufacturing method of the MEMS device includes providing a substrate, and the substrate has at least one contact. The manufacturing method of the MEMS device also includes forming a first dielectric layer on the substrate. The first dielectric layer has at least one through hole that exposes a portion of the top surface of the contact. The manufacturing method of the MEMS device further includes forming at least one first metal layer on the first dielectric layer. At least part of the first metal layer is electrically connected to the contact. In addition, the manufacturing method of the MEMS device includes forming a second dielectric layer on the first dielectric layer and the first metal layer. The method of fabricating the MEMS device also includes forming a sacrificial layer on the second dielectric layer. The manufacturing method of the MEMS device further includes forming a structure layer on the second dielectric layer and the sacrificial layer. Furthermore, the method of fabricating the MEMS device includes removing part of the structural layer to form a first opening exposing part of the top surface of the sacrificial layer. The method of fabricating the MEMS device also includes removing a portion of the sacrificial layer through the first opening to form a second opening that exposes a portion of the top surface of the second dielectric layer. The manufacturing method of the MEMS device further includes removing part of the second dielectric layer through the second opening to form a groove structure. The cross-sectional area of the bottom of the first opening is smaller than the cross-sectional area of the top of the groove structure. In addition, the method of fabricating the MEMS device includes removing the sacrificial layer. The method of fabricating the MEMS device also includes forming a filling layer. At least part of the filling layer is formed in the second opening and groove structure, and the second dielectric layer, the structure layer and the filling layer define a cavity.

本揭露實施例包含一種整合式微機電系統。此整合式微機電系統複數個前述的微機電系統裝置。微機電系統裝置共用同一基板。Embodiments of the present disclosure include an integrated micro-electro-mechanical system. The integrated MEMS is a plurality of the aforementioned MEMS devices. The MEMS devices share the same substrate.

以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例,以簡化說明。當然,這些特定的範例並非用以限定。例如,若是本揭露實施例敘述了一第一特徵部件形成於一第二特徵部件之上或上方,即表示其可能包含上述第一特徵部件與上述第二特徵部件是直接接觸的實施例,亦可能包含了有附加特徵部件形成於上述第一特徵部件與上述第二特徵部件之間,而使上述第一特徵部件與第二特徵部件可能未直接接觸的實施例。The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the embodiment of the present disclosure describes that a first feature part is formed on or above a second feature part, it means that it may include an embodiment in which the first feature part and the second feature part are in direct contact. Embodiments may be included in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

應理解的是,額外的操作步驟可實施於所述方法之前、之間或之後,且在所述方法的其他實施例中,部分的操作步驟可被取代或省略。It should be understood that additional operational steps may be performed before, during, or after the method, and in other embodiments of the method, some of the operational steps may be substituted or omitted.

此外,其中可能用到與空間相關用詞,例如「在… 下方」、「下方」、「較低的」、「在… 上方」、「上方」、「較高的」及類似的用詞,這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵部件與另一個(些)元件或特徵部件之間的關係,這些空間相關用詞包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。In addition, it may use spatially related terms such as "below", "below", "lower", "above", "above", "higher" and similar terms, These spatially relative terms are used for convenience in describing the relationship between one element or feature(s) and another element(s) or feature(s) in the figures, and these spatially relative terms include differences between devices in use or operation Orientation, and the orientation depicted in the drawings. When the device is turned in a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

在說明書中,「約」、「大約」、「大抵」之用語通常表示在一給定值或範圍的20%之內,或10%之內,或5%之內,或3%之內,或2%之內,或1%之內,或0.5%之內。在此給定的數量為大約的數量,亦即在沒有特定說明「約」、「大約」、「大抵」的情況下,仍可隱含「約」、「大約」、「大抵」之含義。In the specification, the terms "about", "approximately" and "approximately" usually mean within 20%, or within 10%, or within 5%, or within 3% of a given value or range, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, the meanings of "about", "approximately" and "approximately" can still be implied without the specific description of "about", "approximately" and "approximately".

除非另外定義,在此使用的全部用語(包括技術及科學用語)具有與此篇揭露所屬之一般技藝者所通常理解的相同涵義。能理解的是,這些用語,例如在通常使用的字典中定義的用語,應被解讀成具有與相關技術及本揭露的背景或上下文一致的意思,而不應以一理想化或過度正式的方式解讀,除非在本揭露實施例有特別定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be construed to have meanings consistent with the relevant art and the context or context of the present disclosure, and not in an idealized or overly formal manner interpretation, unless there is a special definition in the embodiments of the present disclosure.

以下所揭露之不同實施例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的,並非用以限定所討論的不同實施例及/或結構之間有特定的關係。Different embodiments disclosed below may reuse the same reference symbols and/or labels. These repetitions are for the purpose of simplicity and clarity and are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

第1圖至第8圖是根據一些實施例繪示在製造微機電系統裝置100的各個階段之剖面示意圖。要特別注意的是,為了更清楚顯示本揭露實施例的特徵,第1圖至第8圖中可能省略部分部件。FIGS. 1-8 are schematic cross-sectional views illustrating various stages of manufacturing the MEMS device 100 according to some embodiments. It should be noted that, in order to more clearly show the features of the embodiments of the present disclosure, some components may be omitted in FIGS. 1 to 8 .

參照第1圖,首先,提供一基板10,基板10可具有至少一接點12。在一些實施例中,基板10可包含矽,但本揭露實施例並非以此為限。舉例而言,在一些其他的實施例中,基板10可包含一些其他的元素半導體(例如,鍺)。基板10亦可包含化合物半導體(例如,碳化矽、砷化鎵、砷化銦或磷化銦)。基板10亦可包含合金半導體(例如,矽化鍺、碳化矽鍺(silicon germanium carbide)、磷砷化鎵(gallium arsenic phosphide)或磷化銦鎵(gallium indium phosphide))。Referring to FIG. 1 , first, a substrate 10 is provided, and the substrate 10 may have at least one contact 12 . In some embodiments, the substrate 10 may include silicon, but the embodiments of the present disclosure are not limited thereto. For example, in some other embodiments, the substrate 10 may include some other elemental semiconductor (eg, germanium). The substrate 10 may also include compound semiconductors (eg, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide). The substrate 10 may also include an alloy semiconductor (eg, germanium silicide, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide).

在一些實施例中,基板10可包含絕緣層上半導體(semiconductor on insulator, SOI),例如:絕緣層上矽或絕緣層上鍺。前述包含絕緣層上半導體的基板可包含底板、設置於上述底板上之埋藏氧化層以及設置於上述埋藏氧化層上之半導體層。在一些實施例中,基板10可包含單晶基板、多層基板(multi-layer substrate)、其他適當之基板或前述之組合,但本揭露實施例並非以此為限。In some embodiments, the substrate 10 may include a semiconductor on insulator (SOI), such as silicon-on-insulator or germanium-on-insulator. The aforementioned substrate including the semiconductor-on-insulator layer may include a base plate, a buried oxide layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In some embodiments, the substrate 10 may include a single crystal substrate, a multi-layer substrate, other suitable substrates, or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto.

在一些實施例中,基板10可包含如硼、鋁、鎵、銦、鉈之P型摻質,或者如砷、磷、銻之N型摻質。這些摻質可在基板10中形成摻雜區,摻雜區可例如形成接點12的一部分,但本揭露實施例並非以此為限。在一些實施例中,基板10可視為微機電系統裝置100的一晶片(chip)。In some embodiments, the substrate 10 may include P-type dopants such as boron, aluminum, gallium, indium, thallium, or N-type dopants such as arsenic, phosphorus, and antimony. These dopants can form doped regions in the substrate 10 , and the doped regions can, for example, form a part of the contacts 12 , but the embodiments of the present disclosure are not limited thereto. In some embodiments, the substrate 10 can be regarded as a chip of the MEMS device 100 .

參照第1圖,接著,在基板10上形成一第一介電層20。在一些實施例中,第一介電層20的材料可包含例如氧化矽之氧化物、例如氮化矽之氮化物、其他合適的材料或前述之組合,但本揭露實施例並非以此為限。在一些實施例中,可透過一沉積製程將第一介電層20沉積於基板10上,沉積製程可包含金屬有機化學氣相沉積(metal organic chemical vapor phase deposition, MOCVD)、原子層沉積(atomic layer deposition, ALD)、分子束磊晶(molecular beam epitaxy, MBE)、液相磊晶(liquid phase epitaxy, LPE)、類似的製程或前述之組合,但本揭露實施例並非以此為限。Referring to FIG. 1 , next, a first dielectric layer 20 is formed on the substrate 10 . In some embodiments, the material of the first dielectric layer 20 may include oxides such as silicon oxide, nitrides such as silicon nitride, other suitable materials, or combinations thereof, but the embodiments of the present disclosure are not limited thereto . In some embodiments, the first dielectric layer 20 may be deposited on the substrate 10 through a deposition process, the deposition process may include metal organic chemical vapor deposition (MOCVD), atomic layer deposition (atomic layer deposition) layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto.

參照第2圖,在第一介電層20中形成至少一通孔20H,通孔20H可對應於接點12設置並暴露接點12的部分頂表面。在一些實施例中,可對第一介電層20進行一圖案化製程以形成通孔20H。舉例來說,可在第一介電層20上設置遮罩層(未繪示),接著使用前述遮罩層作為蝕刻遮罩進行蝕刻製程,以將第一介電層20蝕刻出通孔20H。在一些實施例中,遮罩層可包含光阻,例如正型光阻(positive photoresist)或負型光阻(negative photoresist)。遮罩層可為單層或多層結構。遮罩層的形成可包含沉積製程、光微影製程、其他適當之製程或前述之組合,但本揭露實施例並非以此為限。Referring to FIG. 2 , at least one through hole 20H is formed in the first dielectric layer 20 , and the through hole 20H may be disposed corresponding to the contact 12 and expose a portion of the top surface of the contact 12 . In some embodiments, a patterning process may be performed on the first dielectric layer 20 to form the vias 20H. For example, a mask layer (not shown) can be provided on the first dielectric layer 20 , and then an etching process can be performed using the aforementioned mask layer as an etching mask to etch the first dielectric layer 20 to form the through holes 20H . In some embodiments, the mask layer may include photoresist, such as positive photoresist or negative photoresist. The mask layer can be a single-layer or multi-layer structure. The formation of the mask layer may include a deposition process, a photolithography process, other suitable processes, or a combination of the foregoing, but the embodiment of the present disclosure is not limited thereto.

在一些實施例中,沉積製程包含旋轉塗佈(spin-on coating)、化學氣相沉積(chemical vapor phase deposition, CVD)、原子層沉積、類似的製程或前述之組合。在一些實施例中,光微影製程可包含光阻塗佈(例如旋轉塗佈)、軟烘烤(soft baking)、光罩對準(mask aligning)、曝光(exposure)、曝光後烘烤(post-exposure baking, PEB)、顯影(developing)、清洗(rinsing)、乾燥(例如硬烘烤)、其他合適的製程或前述之組合,但本揭露實施例並非以此為限。In some embodiments, the deposition process includes spin-on coating, chemical vapor phase deposition (CVD), atomic layer deposition, similar processes, or a combination of the foregoing. In some embodiments, the photolithography process may include photoresist coating (eg spin coating), soft baking, mask aligning, exposure, post-exposure bake ( post-exposure baking (PEB), developing (developing), rinsing (rinsing), drying (eg hard baking), other suitable processes, or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto.

在一些實施例中,前述蝕刻製程可包含乾式蝕刻製程、濕式蝕刻製程或前述之組合。舉例來說,乾式蝕刻製程可包含反應性離子蝕刻(reactive ion etch, RIE)、感應耦合式電漿(inductively-coupled plasma, ICP)蝕刻、中子束蝕刻(neutral beam etch, NBE)、電子迴旋共振式(electron cyclotron resonance, ECR)蝕刻、類似的蝕刻製程或前述之組合,但本揭露實施例並非以此為限。In some embodiments, the aforementioned etching process may include a dry etching process, a wet etching process, or a combination thereof. For example, the dry etching process may include reactive ion etching (RIE), inductively-coupled plasma (ICP) etching, neutron beam etching (NBE), electron cyclotron Electron cyclotron resonance (ECR) etching, a similar etching process, or a combination of the foregoing, but the embodiment of the present disclosure is not limited thereto.

參照第2圖,接著,在第一介電層20上形成一金屬層30,其中至少部分金屬層30電性連接於接點12。具體而言,如第2圖所示,金屬層30包括一第一部分31與一第二部分32,第一部分31通過第一介電層20的通孔20H與接點12直接接觸,而第二部分32藉由第一介電層20與接點12分離。亦即,金屬層30的第一部分31可電性連接於接點12,金屬層30的第二部分32可與接點12電性絕緣,但本揭露實施例並非以此為限。舉例來說,金屬層30的第一部分31可用於將接點12與後續形成的結構電性連接。Referring to FIG. 2 , next, a metal layer 30 is formed on the first dielectric layer 20 , wherein at least part of the metal layer 30 is electrically connected to the contact 12 . Specifically, as shown in FIG. 2 , the metal layer 30 includes a first portion 31 and a second portion 32 , the first portion 31 is in direct contact with the contact 12 through the through hole 20H of the first dielectric layer 20 , and the second portion 31 Portion 32 is separated from contact 12 by first dielectric layer 20 . That is, the first portion 31 of the metal layer 30 may be electrically connected to the contact 12 , and the second portion 32 of the metal layer 30 may be electrically insulated from the contact 12 , but the embodiment of the present disclosure is not limited thereto. For example, the first portion 31 of the metal layer 30 may be used to electrically connect the contact 12 to a subsequently formed structure.

在一些實施例中,金屬層30的材料可包含金(Au)、鎳(Ni)、鉑(Pt)、鈀(Pd)、銥(Ir)、鈦(Ti)、鉻(Cr)、鎢(W)、鋁(Al)、銅(Cu)、其他合適的材料、前述之合金或前述之組合,但本揭露實施例並非以此為限。在一些實施例中,可透過物理氣相沉積、化學氣相沉積、原子層沉積、蒸鍍(evaporation)、濺鍍(sputtering)、類似的製程或前述之組合將金屬材料形成於第一介電層20上,但本揭露實施例並非以此為限。接著,對金屬材料進行圖案化製程,以形成如第2圖所示之金屬層30的第一部分31與第二部分32。圖案化製程的範例如前所述,故不再贅述。In some embodiments, the material of the metal layer 30 may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten ( W), aluminum (Al), copper (Cu), other suitable materials, the aforementioned alloys or the aforementioned combinations, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the metallic material may be formed on the first dielectric by physical vapor deposition, chemical vapor deposition, atomic layer deposition, evaporation, sputtering, similar processes, or a combination of the foregoing. layer 20, but the embodiment of the present disclosure is not limited thereto. Next, a patterning process is performed on the metal material to form the first portion 31 and the second portion 32 of the metal layer 30 as shown in FIG. 2 . The example of the patterning process is as described above, so it is not repeated here.

參照第3圖,在第一介電層20與金屬層30上形成一第二介電層40,第二介電層40具有一凹槽結構42。類似地,第二介電層40的材料可包含例如氧化矽之氧化物、例如氮化矽之氮化物、其他合適的材料或前述之組合,但本揭露實施例並非以此為限。在一些實施例中,第二介電層40的材料可與第一介電層20相同或不同,可依實際需求而定。在一些實施例中,可透過一沉積製程將第二介電層40沉積於第一介電層20與金屬層30上,沉積製程的範例如前所述,故不再贅述。此外,可對第二介電層40進行圖案化製程以形成凹槽結構42。舉例來說,可在第二介電層40上設置遮罩層(未繪示),接著使用前述遮罩層作為蝕刻遮罩進行蝕刻製程,以形成凹槽結構42。在一些實施例中,前述蝕刻製程可包含乾式蝕刻製程、濕式蝕刻製程或前述之組合。Referring to FIG. 3 , a second dielectric layer 40 is formed on the first dielectric layer 20 and the metal layer 30 , and the second dielectric layer 40 has a groove structure 42 . Similarly, the material of the second dielectric layer 40 may include an oxide such as silicon oxide, a nitride such as silicon nitride, other suitable materials, or a combination of the foregoing, but the embodiment of the present disclosure is not limited thereto. In some embodiments, the material of the second dielectric layer 40 may be the same as or different from that of the first dielectric layer 20, which may be determined according to actual requirements. In some embodiments, the second dielectric layer 40 can be deposited on the first dielectric layer 20 and the metal layer 30 through a deposition process. Examples of the deposition process are as described above, and are not repeated here. In addition, a patterning process may be performed on the second dielectric layer 40 to form the groove structure 42 . For example, a mask layer (not shown) may be disposed on the second dielectric layer 40 , and then an etching process may be performed using the aforementioned mask layer as an etching mask to form the groove structure 42 . In some embodiments, the aforementioned etching process may include a dry etching process, a wet etching process, or a combination thereof.

如第3圖所示,在一些實施例中,第二介電層40的凹槽結構42可暴露第一介電層20的部分頂表面,但本揭露實施例並非以此為限。在一些實施例中,凹槽結構42也可設置於第一介電層20上方,而不會暴露第一介電層20;或者,凹槽結構42也可暴露金屬層30的第二部分32的部分頂表面,可依實際需求而定。As shown in FIG. 3 , in some embodiments, the groove structure 42 of the second dielectric layer 40 may expose part of the top surface of the first dielectric layer 20 , but the embodiments of the present disclosure are not limited thereto. In some embodiments, the groove structure 42 may also be disposed over the first dielectric layer 20 without exposing the first dielectric layer 20 ; alternatively, the groove structure 42 may also expose the second portion 32 of the metal layer 30 part of the top surface, which can be determined according to actual needs.

在一些實施例中,凹槽結構42的側壁42S可大致上垂直於第一介電層20與第二介電層40的頂表面,但本揭露實施例並非以此為限。在第3圖所示的實施例中,凹槽結構42可具有恆定的(constant)的截面積。亦即,凹槽結構42在不同深度的截面積可與凹槽結構42之頂部的截面積42TA大致上相同,但本揭露實施例並非以此為限。In some embodiments, the sidewalls 42S of the groove structure 42 may be substantially perpendicular to the top surfaces of the first dielectric layer 20 and the second dielectric layer 40 , but the embodiments of the present disclosure are not limited thereto. In the embodiment shown in FIG. 3, the groove structure 42 may have a constant cross-sectional area. That is, the cross-sectional area of the groove structure 42 at different depths may be substantially the same as the cross-sectional area 42TA of the top of the groove structure 42 , but the embodiment of the present disclosure is not limited thereto.

參照第4圖,在第二介電層40上與凹槽結構42中形成一犧牲層50。具體而言,可在凹槽結構42的底表面與部分側壁42S上及第二介電層40的部分頂表面上形成犧牲層50。在一些實施例中,犧牲層50的材料可包含氧化矽、光阻、聚醯亞胺(polyimide)、鍺、其他合適的材料或前述之組合,但本揭露實施例並非以此為限。在一些實施例中,犧牲層50與第一介電層20、金屬層30及第二介電層40可具有高度的蝕刻選擇比。因此,在後續將犧牲層50移除的過程中,可防止第一介電層20、金屬層30及第二介電層40受到損傷。在一些實施例中,可透過沉積製程在第二介電層40上與凹槽結構42中形成犧牲層50,沉積製程的範例如前所述,故不再贅述。Referring to FIG. 4 , a sacrificial layer 50 is formed on the second dielectric layer 40 and in the groove structure 42 . Specifically, the sacrificial layer 50 may be formed on the bottom surface and part of the sidewalls 42S of the groove structure 42 and on part of the top surface of the second dielectric layer 40 . In some embodiments, the material of the sacrificial layer 50 may include silicon oxide, photoresist, polyimide, germanium, other suitable materials, or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the sacrificial layer 50 and the first dielectric layer 20 , the metal layer 30 and the second dielectric layer 40 may have a high etch selectivity ratio. Therefore, in the subsequent process of removing the sacrificial layer 50 , the first dielectric layer 20 , the metal layer 30 and the second dielectric layer 40 can be prevented from being damaged. In some embodiments, the sacrificial layer 50 can be formed on the second dielectric layer 40 and in the groove structure 42 through a deposition process. Examples of the deposition process are as described above, and thus will not be repeated here.

參照第5圖,在第二介電層40與犧牲層50上形成一結構層60。具體而言,結構層60可形成於第二介電層40的頂表面與犧牲層50的頂表面,並填滿凹槽結構42剩餘的空間。在一些實施例中,結構層60的材料可包含多晶矽、磊晶矽、矽鍺、其他合適的半導體材料或前述之組合,但本揭露實施例並非以此為限。在一些實施例中,結構層60與犧牲層50也可具有高度的蝕刻選擇比。在一些實施例中,可透過沉積製程在第二介電層40與犧牲層50上與凹槽結構42中形成結構層60,沉積製程的範例如前所述,故不再贅述。在一些實施例中,結構層60可視為微機電基板的一部分。Referring to FIG. 5 , a structural layer 60 is formed on the second dielectric layer 40 and the sacrificial layer 50 . Specifically, the structure layer 60 may be formed on the top surface of the second dielectric layer 40 and the top surface of the sacrificial layer 50 and fill the remaining space of the groove structure 42 . In some embodiments, the material of the structure layer 60 may include polysilicon, epitaxial silicon, silicon germanium, other suitable semiconductor materials, or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the structural layer 60 and the sacrificial layer 50 may also have a high etch selectivity ratio. In some embodiments, the structure layer 60 can be formed on the second dielectric layer 40 and the sacrificial layer 50 and in the groove structure 42 through a deposition process. Examples of the deposition process are as described above, and are not repeated here. In some embodiments, structural layer 60 may be considered part of a microelectromechanical substrate.

參照第6圖,將部分結構層60移除以形成一開口62。具體而言,開口62對應於凹槽結構42(即開口62位於凹槽結構42的上方),且開口62可暴露出位於凹槽結構42中的犧牲層50。在一些實施例中,可對結構層60進行一圖案化製程以形成開口62。舉例來說,可在結構層60上設置遮罩層(未繪示),接著使用前述遮罩層作為蝕刻遮罩進行乾蝕刻製程,以在結構層60中形成開口62。在此,乾蝕刻製程中使用的蝕刻氣體例如包含CF4 、O2 、SF6 、C4 F8 、Ar、Cl2 、BCl3 、其他合適的蝕刻氣體或前述之組合,但本揭露實施例並非以此為限。Referring to FIG. 6 , a portion of the structural layer 60 is removed to form an opening 62 . Specifically, the opening 62 corresponds to the groove structure 42 (ie, the opening 62 is located above the groove structure 42 ), and the opening 62 can expose the sacrificial layer 50 located in the groove structure 42 . In some embodiments, a patterning process may be performed on the structural layer 60 to form the openings 62 . For example, a mask layer (not shown) may be disposed on the structure layer 60 , and then a dry etching process may be performed using the aforementioned mask layer as an etching mask to form the opening 62 in the structure layer 60 . Here, the etching gas used in the dry etching process includes, for example, CF 4 , O 2 , SF 6 , C 4 F 8 , Ar, Cl 2 , BCl 3 , other suitable etching gases, or a combination of the foregoing, but the embodiments of the present disclosure Not limited to this.

參照第7圖,將犧牲層50移除。具體而言,將位於凹槽結構42中及位於第二介電層40與結構層60之間的犧牲層50移除,以暴露凹槽結構42。舉例來說,可對犧牲層50進行濕蝕刻製程,以將犧牲層50移除。在此,濕蝕刻製程中使用的蝕刻液例如包含硫酸(H2 SO4 )、磷酸(H3 PO4 )、氫氟酸(HF)、雙氧水(H2 O2 )、氨水(NH4 OH)等,但本揭露實施例並非以此為限。由於犧牲層50與第一介電層20、金屬層30、第二介電層40及結構層60均具有高度的蝕刻選擇比,在將犧牲層50移除的過程中,可防止第一介電層20、金屬層30、第二介電層40及結構層60受到損傷。在一些實施例中,部分的犧牲層50也可能被保留。舉例來說,如第7圖所示,被保留的犧牲層50可視為一犧牲層剩餘部分50R,犧牲層剩餘部分50R位於第二介電層40與結構層60之間,但本揭露實施例並非以此為限。在一些其他實施例中,犧牲層50可被完全地移除。Referring to FIG. 7, the sacrificial layer 50 is removed. Specifically, the sacrificial layer 50 located in the groove structure 42 and between the second dielectric layer 40 and the structural layer 60 is removed to expose the groove structure 42 . For example, a wet etching process may be performed on the sacrificial layer 50 to remove the sacrificial layer 50 . Here, the etching solution used in the wet etching process includes, for example, sulfuric acid (H 2 SO 4 ), phosphoric acid (H 3 PO 4 ), hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ), ammonia water (NH 4 OH) etc., but the embodiments of the present disclosure are not limited thereto. Since the sacrificial layer 50 has a high etching selectivity ratio to the first dielectric layer 20 , the metal layer 30 , the second dielectric layer 40 and the structural layer 60 , in the process of removing the sacrificial layer 50 , the first dielectric layer can be prevented from being removed. The electrical layer 20 , the metal layer 30 , the second dielectric layer 40 and the structural layer 60 are damaged. In some embodiments, portions of the sacrificial layer 50 may also remain. For example, as shown in FIG. 7 , the remaining sacrificial layer 50 can be regarded as a remaining part 50R of the sacrificial layer, and the remaining part 50R of the sacrificial layer is located between the second dielectric layer 40 and the structural layer 60 , but the embodiment of the present disclosure Not limited to this. In some other embodiments, the sacrificial layer 50 may be completely removed.

如第7圖所示,在一些實施例中,開口62之底部的截面積62BA小於凹槽結構42之頂部42TA的截面積。由於在前述步驟中,犧牲層50會佔據第二介電層40與結構層60之間的部分空間,因此在將犧牲層50移除後,開口62之側壁621與側壁622的最底部並非位於同一平面上。在此,將結構層60的最底表面60B延伸,並將開口62之側壁621延伸,前述兩個延伸面與開口62之側壁622共同圍繞形成的空間的最底部的截面積可定義為開口62之底部的截面積62BA(如第7圖所示)。As shown in FIG. 7 , in some embodiments, the cross-sectional area 62BA of the bottom of the opening 62 is smaller than the cross-sectional area of the top 42TA of the groove structure 42 . Since the sacrificial layer 50 occupies part of the space between the second dielectric layer 40 and the structural layer 60 in the foregoing steps, after the sacrificial layer 50 is removed, the sidewalls 621 and the bottom of the sidewalls 622 of the opening 62 are not located at on the same plane. Here, the bottommost surface 60B of the structural layer 60 is extended, and the sidewall 621 of the opening 62 is extended. The cross-sectional area of the bottommost space formed by the two extending surfaces and the sidewall 622 of the opening 62 can be defined as the opening 62 The bottom cross-sectional area is 62BA (as shown in Figure 7).

如第7圖所示,在一些實施例中,開口62之底部的截面積62BA小於開口62之頂部的截面積62TA。具體而言,開口62在不同的深度的截面積並非恆定的,其可為連續變化。舉例而言,如第7圖所示,在此階段之剖面中,開口62之側壁621與側壁622可呈現為兩個斜面,但本揭露實施例並非以此為限。As shown in FIG. 7 , in some embodiments, the cross-sectional area 62BA of the bottom of the opening 62 is smaller than the cross-sectional area 62TA of the top of the opening 62 . Specifically, the cross-sectional area of the opening 62 at different depths is not constant, but may vary continuously. For example, as shown in FIG. 7 , in the cross-section at this stage, the sidewall 621 and the sidewall 622 of the opening 62 may be presented as two inclined surfaces, but the embodiment of the present disclosure is not limited to this.

參照第8圖,形成一填充層70,以形成本揭露實施例的一種微機電系統裝置100。具體而言,至少部分填充層70可形成於開口62與凹槽結構42中,亦即,可連續地形成並填滿開口62與凹槽結構42所在的空間,使第二介電層40、結構層60與填充層70可界定一空腔80。換言之,空腔80可部分或完全取代原先犧牲層50在第二介電層40與結構層60之間所佔據的空間。亦即,空腔80位於第二介電層40、結構層60與填充層70之間。此外,如第8圖所示,在一些實施例中,空腔80位於第二介電層40、犧牲層剩餘部分50R、結構層60與填充層70之間,因此,空腔80的高度g可大致上等於犧牲層剩餘部分50R的厚度。Referring to FIG. 8, a filling layer 70 is formed to form a MEMS device 100 according to an embodiment of the present disclosure. Specifically, at least part of the filling layer 70 can be formed in the opening 62 and the groove structure 42 , that is, the space where the opening 62 and the groove structure 42 are located can be continuously formed and filled, so that the second dielectric layer 40 , The structure layer 60 and the filling layer 70 may define a cavity 80 . In other words, the cavity 80 can partially or completely replace the space originally occupied by the sacrificial layer 50 between the second dielectric layer 40 and the structural layer 60 . That is, the cavity 80 is located between the second dielectric layer 40 , the structural layer 60 and the filling layer 70 . In addition, as shown in FIG. 8, in some embodiments, the cavity 80 is located between the second dielectric layer 40, the remaining portion 50R of the sacrificial layer, the structural layer 60 and the filling layer 70, thus, the height g of the cavity 80 is may be substantially equal to the thickness of the remaining portion 50R of the sacrificial layer.

在一些實施例中,填充層70的材料可包含氧化矽、氮化矽、光阻、聚醯亞胺、其他合適的材料或前述之組合,但本揭露實施例並非以此為限。在一些實施例中,可透過沉積製程在開口62與凹槽結構42中形成一填充層70,沉積製程的範例如前所述,故不再贅述。在此,填充層70可視為微機電系統裝置100的封孔結構。此外,如第8圖所示,部分填充層70也可形成於結構層60上,但本揭露實施例並非以此為限。In some embodiments, the material of the filling layer 70 may include silicon oxide, silicon nitride, photoresist, polyimide, other suitable materials, or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto. In some embodiments, a filling layer 70 can be formed in the opening 62 and the groove structure 42 through a deposition process. Examples of the deposition process are as described above, and thus are not repeated here. Here, the filling layer 70 can be regarded as a sealing structure of the MEMS device 100 . In addition, as shown in FIG. 8 , part of the filling layer 70 may also be formed on the structure layer 60 , but the embodiment of the present disclosure is not limited thereto.

如第8圖所示,在一些實施例中,凹槽結構42暴露第一介電層20的部分頂表面,因此填充層70可直接接觸第一介電層20,但本揭露實施例並非以此為限。在其他實施例中,凹槽結構42可設置於第一介電層20上方,而不會暴露第一介電層20,因此填充層70可直接接觸第二介電層40。As shown in FIG. 8 , in some embodiments, the groove structure 42 exposes a part of the top surface of the first dielectric layer 20 , so the filling layer 70 can directly contact the first dielectric layer 20 , but the embodiment of the present disclosure does not This is limited. In other embodiments, the groove structure 42 can be disposed above the first dielectric layer 20 without exposing the first dielectric layer 20 , so that the filling layer 70 can directly contact the second dielectric layer 40 .

在一般不具有凹槽結構的微機電系統裝置中,於形成(沉積)填充層70的過程中,由於對應於開口62中央的部分的形成(沉積)速度大於遠離開口62中央的部分的形成(沉積)速度,容易形成封孔接縫。相對地,由於本揭露實施例之微機電系統裝置100包含對應於開口62的凹槽結構42,能有效防止封孔接縫的產生。In a MEMS device that generally does not have a groove structure, in the process of forming (depositing) the filling layer 70, since the formation (deposition) speed of the part corresponding to the center of the opening 62 is higher than that of the part far from the center of the opening 62 ( deposition) speed, easy to form sealed seams. On the contrary, since the MEMS device 100 of the disclosed embodiment includes the groove structure 42 corresponding to the opening 62 , the generation of the sealing seam can be effectively prevented.

再者,於本揭露的一些實施例中,由於開口62之底部的截面積62BA小於開口62之頂部的截面積62TA,能使填充層70更均勻地在形成於開口62中,避免在填充層70尚未填滿凹槽結構42與開口62前提早閉合造成空心結構。Furthermore, in some embodiments of the present disclosure, since the cross-sectional area 62BA of the bottom of the opening 62 is smaller than the cross-sectional area 62TA of the top of the opening 62 , the filling layer 70 can be formed in the opening 62 more uniformly, avoiding the formation of the filling layer 62 . 70 The hollow structure is formed by prematurely closing before filling the groove structure 42 and the opening 62 .

因此,在本揭露實施例之微機電系統裝置100中,可透過在第二介電層40中設置凹槽結構42及在結構層60中設置與凹槽結構42對應的開口62,使填充層70(即用於封孔的結構)連續且均勻地填滿此開口62與凹槽結構42,以完成封孔。亦即,藉由本揭露實施例的微機電系統裝置100與其製造方法,能有效防止封孔接縫與空心結構的產生,進而提高封孔品質並提升微機電系統裝置100整體的穩定性。此外,不需要繁複的製程,能有效縮短製程時間並降低成本。Therefore, in the MEMS device 100 of the disclosed embodiment, the filling layer can be formed by arranging the groove structure 42 in the second dielectric layer 40 and arranging the opening 62 corresponding to the groove structure 42 in the structure layer 60 . The opening 62 and the groove structure 42 are filled continuously and uniformly with the hole 70 (ie, the structure for sealing the hole) to complete the hole sealing. That is, the MEMS device 100 and the manufacturing method thereof of the disclosed embodiments can effectively prevent the generation of sealing seams and hollow structures, thereby improving the sealing quality and the overall stability of the MEMS device 100 . In addition, no complicated process is required, which can effectively shorten the process time and reduce the cost.

如第8圖所示,在一些實施例中,結構層60的開口62處在凹槽結構42中的投影具有一端部60E1(或60E2),此端部60E1(或60E2)與凹槽結構42的頂端42E在平行於第二介電層40之頂表面(或結構層60的最底表面60B)的方向D上的最短距離d1(或d2)大於或等於犧牲層50(或犧牲層剩餘部分50R)的厚度(即空腔80的高度g),但本揭露實施例並非以此為限。在本揭露實施例中,端部60E1(或60E2)與凹槽結構42的頂端42E在平行於第二介電層40之頂表面(或結構層60的最底表面60B)的方向D上的最短距離d1(或d2)可視凹槽結構42的深度進行調整,在此不多加贅述。As shown in FIG. 8 , in some embodiments, the projection of the opening 62 of the structural layer 60 in the groove structure 42 has an end 60E1 (or 60E2 ), the end 60E1 (or 60E2 ) and the groove structure 42 The shortest distance d1 (or d2) of the top end 42E in the direction D parallel to the top surface of the second dielectric layer 40 (or the bottommost surface 60B of the structural layer 60 ) is greater than or equal to the sacrificial layer 50 (or the remaining part of the sacrificial layer 60 ). 50R) (ie, the height g of the cavity 80 ), but the embodiment of the present disclosure is not limited thereto. In the disclosed embodiment, the end portion 60E1 (or 60E2 ) and the top end 42E of the groove structure 42 are in the direction D parallel to the top surface of the second dielectric layer 40 (or the bottommost surface 60B of the structure layer 60 ). The shortest distance d1 (or d2 ) can be adjusted according to the depth of the groove structure 42 , which is not repeated here.

在前述實施例中,凹槽結構42的側壁42S大致上垂直於第一介電層20與第二介電層40的頂表面,但本揭露實施例並非以此為限。第9圖是根據另一實施例繪示凹槽結構44的剖面示意圖。同時,為了更清楚顯示凹槽結構44的特徵,第9圖中亦繪示鄰近凹槽結構44的其他部件。In the aforementioned embodiments, the sidewalls 42S of the groove structures 42 are substantially perpendicular to the top surfaces of the first dielectric layer 20 and the second dielectric layer 40 , but the embodiments of the present disclosure are not limited thereto. FIG. 9 is a schematic cross-sectional view illustrating the groove structure 44 according to another embodiment. Meanwhile, in order to show the features of the groove structure 44 more clearly, other components adjacent to the groove structure 44 are also shown in FIG. 9 .

參照第9圖,凹槽結構44的側壁44S並非垂直於第二介電層40的頂表面。在一些實施例中,第二介電層40之頂表面與凹槽結構44的側壁44S所夾的角度θ可介於90至150度,但本揭露實施例並非以此為限。當第二介電層40之頂表面與凹槽結構44的側壁44S所夾的角度θ為90度時,凹槽結構44的側壁44S即大致垂直於第二介電層40的頂表面。Referring to FIG. 9 , the sidewalls 44S of the groove structures 44 are not perpendicular to the top surface of the second dielectric layer 40 . In some embodiments, the angle θ between the top surface of the second dielectric layer 40 and the sidewalls 44S of the groove structure 44 may be between 90 and 150 degrees, but the embodiment of the present disclosure is not limited thereto. When the angle θ between the top surface of the second dielectric layer 40 and the sidewall 44S of the groove structure 44 is 90 degrees, the sidewall 44S of the groove structure 44 is substantially perpendicular to the top surface of the second dielectric layer 40 .

類似地,結構層60的開口62處在凹槽結構44中的投影具有一端部60E1(或60E2),此端部60E1(或60E2)與凹槽結構44的頂端44E在平行於第二介電層40之頂表面的方向D上的最短距離d1(或d2)大於或等於犧牲層50(或犧牲層剩餘部分50R)的厚度(即空腔80的高度g),在此不多加贅述。Similarly, the projection of the opening 62 of the structural layer 60 into the groove structure 44 has an end 60E1 (or 60E2 ) that is parallel to the top 44E of the groove structure 44 in parallel with the second dielectric The shortest distance d1 (or d2 ) in the direction D of the top surface of the layer 40 is greater than or equal to the thickness of the sacrificial layer 50 (or the remaining portion 50R of the sacrificial layer) (ie, the height g of the cavity 80 ), which is not repeated here.

第10圖是根據又一實施例繪示凹槽結構46的剖面示意圖。參照第10圖,凹槽結構46的側壁46S可具有一弧度。第9圖與第10圖之實施例繪示本揭露實施例之凹槽結構的不同範例,但本揭露實施例之凹槽結構也可形成為其他不同的形狀,可視實際需求而定。FIG. 10 is a schematic cross-sectional view illustrating the groove structure 46 according to yet another embodiment. Referring to FIG. 10, the sidewall 46S of the groove structure 46 may have an arc. The embodiments of FIGS. 9 and 10 illustrate different examples of the groove structure of the disclosed embodiment, but the groove structure of the disclosed embodiment can also be formed into other different shapes, depending on actual requirements.

第11圖是根據一些實施例繪示微機電系統裝置102的剖面示意圖。第11圖所示之微機電系統裝置102的結構與製造方法類似於第8圖所示之微機電系統裝置100,其不同之處在於微機電系統裝置102的凹槽結構42是暴露金屬層30的第二部分32的部分頂表面,使填充層70可直接接觸部分金屬層30(即金屬層30的第二部分32),但本揭露實施例並非以此為限。FIG. 11 is a schematic cross-sectional view illustrating the MEMS device 102 according to some embodiments. The structure and manufacturing method of the MEMS device 102 shown in FIG. 11 are similar to the MEMS device 100 shown in FIG. 8 , the difference is that the groove structure 42 of the MEMS device 102 exposes the metal layer 30 A part of the top surface of the second part 32 of the metal layer 70 can directly contact part of the metal layer 30 (ie, the second part 32 of the metal layer 30 ), but the embodiment of the present disclosure is not limited thereto.

第12圖至第22圖是根據一些實施例繪示在製造整合式微機電系統1的各個階段之剖面示意圖。第23圖是整合式微機電系統1的部分俯視圖。類似地,為了更清楚顯示本揭露實施例的特徵,第12圖至第23圖中可能省略部分部件。FIGS. 12-22 are schematic cross-sectional views illustrating various stages of manufacturing the integrated MEMS 1 according to some embodiments. FIG. 23 is a partial top view of the integrated MEMS 1 . Similarly, in order to more clearly show the features of the embodiments of the present disclosure, some components may be omitted in FIGS. 12 to 23 .

在本揭露的一些實施例中,整合式微機電系統1可包含複數個微機電系統裝置(例如,微機電系統裝置106與微機電系統裝置108)。這些微機電系統裝置的結構可類似於第8圖所示的微機電系統裝置100或第11圖所示的微機電系統裝置102,並可透過第1圖至第8圖所示的製造方法所形成,但本揭露實施例並非以此為限。第12圖至第22圖可呈現與第1圖至第8圖所示之實施例不同的製造微機電系統裝置106與微機電系統裝置108的方法。In some embodiments of the present disclosure, the integrated MEMS device 1 may include a plurality of MEMS devices (eg, the MEMS device 106 and the MEMS device 108 ). The structure of these MEMS devices can be similar to the MEMS device 100 shown in FIG. 8 or the MEMS device 102 shown in FIG. 11, and can be produced by the manufacturing method shown in FIGS. 1 to 8. formed, but the embodiments of the present disclosure are not limited thereto. FIGS. 12-22 may present methods of fabricating MEMS device 106 and MEMS device 108 that are different from the embodiments shown in FIGS. 1-8.

參照第12圖,首先,提供一基板10,基板10可具有複數個接點12。接著,在基板10上形成一第一介電層20。基板10與第一介電層20的材料與形成方法的範例如前所述,在此不多加贅述。Referring to FIG. 12 , first, a substrate 10 is provided, and the substrate 10 may have a plurality of contacts 12 . Next, a first dielectric layer 20 is formed on the substrate 10 . Examples of the materials and forming methods of the substrate 10 and the first dielectric layer 20 are as described above, and are not repeated here.

參照第13圖,在第一介電層20中形成複數個通孔20H,通孔20H可對應於接點12設置並暴露接點12的部分頂表面。接著,在第一介電層20上形成一金屬層30,其中至少部分金屬層30電性連接於接點12。具體而言,如第13圖所示,金屬層30包括複數個第一部分31與複數個第二部分32,第一部分31通過第一介電層20的通孔20H與接點12直接接觸,而第二部分32藉由第一介電層20與接點12分離。亦即,金屬層30的第一部分31可電性連接於接點12,金屬層30的第二部分32可與接點12電性絕緣,但本揭露實施例並非以此為限。第一介電層20與金屬層30的材料與形成方法的範例如前所述,在此不多加贅述。Referring to FIG. 13 , a plurality of through holes 20H are formed in the first dielectric layer 20 , and the through holes 20H may be disposed corresponding to the contacts 12 and expose a portion of the top surface of the contacts 12 . Next, a metal layer 30 is formed on the first dielectric layer 20 , wherein at least part of the metal layer 30 is electrically connected to the contact 12 . Specifically, as shown in FIG. 13 , the metal layer 30 includes a plurality of first parts 31 and a plurality of second parts 32 , the first parts 31 are in direct contact with the contacts 12 through the through holes 20H of the first dielectric layer 20 , and The second portion 32 is separated from the contact 12 by the first dielectric layer 20 . That is, the first portion 31 of the metal layer 30 may be electrically connected to the contact 12 , and the second portion 32 of the metal layer 30 may be electrically insulated from the contact 12 , but the embodiment of the present disclosure is not limited thereto. Examples of the materials and forming methods of the first dielectric layer 20 and the metal layer 30 are as described above, and will not be repeated here.

參照第14圖,在第一介電層20與金屬層30上形成一第二介電層40。接著,在第二介電層40上形成一犧牲層50。類似地,犧牲層50與第一介電層20、金屬層30及第二介電層40可具有高度的蝕刻選擇比。因此,在後續將犧牲層50移除的過程中,可防止第一介電層20、金屬層30及第二介電層40受到損傷。第二介電層40與犧牲層50的材料與形成方法的範例如前所述,在此不多加贅述。Referring to FIG. 14 , a second dielectric layer 40 is formed on the first dielectric layer 20 and the metal layer 30 . Next, a sacrificial layer 50 is formed on the second dielectric layer 40 . Similarly, the sacrificial layer 50 and the first dielectric layer 20 , the metal layer 30 and the second dielectric layer 40 may have a high etch selectivity ratio. Therefore, in the subsequent process of removing the sacrificial layer 50 , the first dielectric layer 20 , the metal layer 30 and the second dielectric layer 40 can be prevented from being damaged. Examples of the materials and forming methods of the second dielectric layer 40 and the sacrificial layer 50 are as described above, and details are not repeated here.

參照第15圖,在第二介電層40與犧牲層50上形成一結構層60。類似地,結構層60與犧牲層50也可具有高度的蝕刻選擇比,且結構層60可視為微機電基板的一部分。結構層60的材料與形成方法的範例如前所述,在此不多加贅述。Referring to FIG. 15 , a structural layer 60 is formed on the second dielectric layer 40 and the sacrificial layer 50 . Similarly, the structural layer 60 and the sacrificial layer 50 can also have a high etch selectivity ratio, and the structural layer 60 can be regarded as part of the MEMS substrate. Examples of the materials and forming methods of the structural layer 60 are as described above, and are not repeated here.

參照第16圖,將部分結構層60移除以形成一開口62。如第16圖所示,開口62可暴露出犧牲層50的部分頂表面50T。在一些實施例中,可對結構層60進行一圖案化製程以將部分結構層60移除並形成開口62。圖案化製程的範例如前所述,在此不多加贅述。此外,如第16圖所示,在對結構層60進行圖案化製程時,也可同時形成開口64。開口64可暴露出第二介電層40的部分頂表面40T,且可透過開口64將後續形成的微機電系統裝置106與微機電系統裝置108分開,但本揭露實施例並非以此為限。Referring to FIG. 16 , a portion of the structural layer 60 is removed to form an opening 62 . As shown in FIG. 16 , the opening 62 may expose a portion of the top surface 50T of the sacrificial layer 50 . In some embodiments, a patterning process may be performed on the structure layer 60 to remove portions of the structure layer 60 and form the openings 62 . Examples of the patterning process are as described above, and are not repeated here. In addition, as shown in FIG. 16 , when the patterning process is performed on the structure layer 60 , the openings 64 may also be formed simultaneously. The opening 64 can expose a part of the top surface 40T of the second dielectric layer 40 , and the MEMS device 106 and the MEMS device 108 formed later can be separated through the opening 64 , but the embodiment of the present disclosure is not limited thereto.

參照第17圖,透過開口62將部分犧牲層50移除以形成開口52,開口52暴露出第二介電層40的部分頂表面40T。舉例來說,可對犧牲層50進行一圖案化製程以將部分犧牲層50移除並形成開口52。圖案化製程的範例如前所述,在此不多加贅述。Referring to FIG. 17 , a portion of the sacrificial layer 50 is removed through the opening 62 to form an opening 52 that exposes a portion of the top surface 40T of the second dielectric layer 40 . For example, a patterning process may be performed on the sacrificial layer 50 to remove portions of the sacrificial layer 50 and form openings 52 . Examples of the patterning process are as described above, and are not repeated here.

參照第18圖,透過開口52將部分第二介電層40移除以形成一凹槽結構42。舉例來說,可對第二介電層40進行一圖案化製程(例如,包含一側向蝕刻製程)以將部分第二介電層40移除並形成凹槽結構42。圖案化製程的範例如前所述,在此不多加贅述。Referring to FIG. 18 , a part of the second dielectric layer 40 is removed through the opening 52 to form a groove structure 42 . For example, a patterning process (eg, including a lateral etching process) may be performed on the second dielectric layer 40 to remove a portion of the second dielectric layer 40 and form the groove structure 42 . Examples of the patterning process are as described above, and are not repeated here.

參照第19圖,將犧牲層50移除。舉例來說,可對犧牲層50進行濕蝕刻製程,以將犧牲層50移除。濕蝕刻製程的範例如前所述,在此不多加贅述。類似地,由於犧牲層50與第一介電層20、金屬層30、第二介電層40及結構層60均具有高度的蝕刻選擇比,在將犧牲層50移除的過程中,可防止第一介電層20、金屬層30、第二介電層40及結構層60受到損傷。在本實施例中,可將犧牲層50完全移除,但本揭露實施例並非以此為限。在一些其他的實施例中,部分的犧牲層50也可能被保留。Referring to FIG. 19, the sacrificial layer 50 is removed. For example, a wet etching process may be performed on the sacrificial layer 50 to remove the sacrificial layer 50 . The examples of the wet etching process are as described above, and are not repeated here. Similarly, since the sacrificial layer 50 and the first dielectric layer 20 , the metal layer 30 , the second dielectric layer 40 and the structural layer 60 all have a high etching selectivity ratio, during the process of removing the sacrificial layer 50 , it can prevent The first dielectric layer 20 , the metal layer 30 , the second dielectric layer 40 and the structural layer 60 are damaged. In this embodiment, the sacrificial layer 50 can be completely removed, but the embodiment of the present disclosure is not limited thereto. In some other embodiments, portions of the sacrificial layer 50 may also remain.

如第19圖所示,在一些實施例中,開口62之底部的截面積62BA小於凹槽結構42之頂部42TA的截面積。此外,在一些實施例中,開口62之底部的截面積62BA小於開口62之頂部的截面積62TA。具體而言,開口62在不同的深度的截面積並非恆定的,其可為連續變化。舉例而言,如第19圖所示,在此階段之剖面中,開口62之側壁621與側壁622可呈現為兩個斜面,但本揭露實施例並非以此為限。As shown in FIG. 19 , in some embodiments, the cross-sectional area 62BA of the bottom of the opening 62 is smaller than the cross-sectional area of the top 42TA of the groove structure 42 . Furthermore, in some embodiments, the cross-sectional area 62BA of the bottom of the opening 62 is smaller than the cross-sectional area 62TA of the top of the opening 62 . Specifically, the cross-sectional area of the opening 62 at different depths is not constant, but may vary continuously. For example, as shown in FIG. 19 , in the cross-section at this stage, the sidewall 621 and the sidewall 622 of the opening 62 may be presented as two inclined surfaces, but the embodiment of the present disclosure is not limited to this.

在本實施例中,凹槽結構42的側壁42S大致上垂直於第二介電層40的頂表面40T(及/或第一介電層20的頂表面),但本揭露實施例並非以此為限。在一些其他的實施例中,也可透過調整(或控制)濕蝕刻製程,使凹槽結構42類似於第9圖所示的凹槽結構44或第10圖所示的凹槽結構46。凹槽結構42的形狀、深度可依實際需求調整。In this embodiment, the sidewalls 42S of the groove structures 42 are substantially perpendicular to the top surface 40T of the second dielectric layer 40 (and/or the top surface of the first dielectric layer 20 ), but this is not the case in the embodiment of the present disclosure limited. In some other embodiments, the wet etching process can be adjusted (or controlled) to make the groove structure 42 similar to the groove structure 44 shown in FIG. 9 or the groove structure 46 shown in FIG. 10 . The shape and depth of the groove structure 42 can be adjusted according to actual needs.

參照第20圖,形成一填充層70。具體而言,至少部分填充層70可形成於開口62與凹槽結構42中,亦即,可連續地形成並填滿開口62與凹槽結構42所在的空間,使第二介電層40、結構層60與填充層70可界定一空腔80。換言之,空腔80可部分或完全取代原先犧牲層50在第二介電層40與結構層60之間所佔據的空間。亦即,空腔80位於第二介電層40、結構層60與填充層70之間。填充層70的材料與形成方法的範例如前所述,在此不多加贅述。Referring to FIG. 20, a filling layer 70 is formed. Specifically, at least part of the filling layer 70 can be formed in the opening 62 and the groove structure 42 , that is, the space where the opening 62 and the groove structure 42 are located can be continuously formed and filled, so that the second dielectric layer 40 , The structure layer 60 and the filling layer 70 may define a cavity 80 . In other words, the cavity 80 can partially or completely replace the space originally occupied by the sacrificial layer 50 between the second dielectric layer 40 and the structural layer 60 . That is, the cavity 80 is located between the second dielectric layer 40 , the structural layer 60 and the filling layer 70 . Examples of the material and forming method of the filling layer 70 are as described above, and are not repeated here.

在此,填充層70可視為微機電系統裝置106與微機電系統裝置108的封孔結構。此外,如第20圖所示,部分填充層70也可形成於結構層60上,並形成於開口64所暴露出的第二介電層40的部分頂表面40T及開口64的側壁上,但本揭露實施例並非以此為限。Here, the filling layer 70 can be regarded as the sealing structure of the MEMS device 106 and the MEMS device 108 . In addition, as shown in FIG. 20 , part of the filling layer 70 may also be formed on the structural layer 60 and on the part of the top surface 40T of the second dielectric layer 40 and the sidewalls of the opening 64 exposed by the opening 64 , but The embodiments of the present disclosure are not limited thereto.

如第20圖所示,在一些實施例中,凹槽結構42可設置於第一介電層20上方,而不會暴露第一介電層20,因此填充層70可直接接觸第二介電層40,但本揭露實施例並非以此為限。As shown in FIG. 20, in some embodiments, the groove structure 42 may be disposed above the first dielectric layer 20 without exposing the first dielectric layer 20, so that the filling layer 70 may directly contact the second dielectric layer layer 40, but the embodiment of the present disclosure is not limited thereto.

在一般不具有凹槽結構的微機電系統(裝置)中,於形成(沉積)填充層70的過程中,由於對應於開口62中央的部分的形成(沉積)速度大於遠離開口62中央的部分的形成(沉積)速度,容易形成封孔接縫。相對地,在本實施例中,凹槽結構42是透過開口52所形成,而開口52是透過開口62所形成,使得凹槽結構42可對應於開口62。因此,在形成填充層70時,凹槽結構42能有效防止封孔接縫的產生。In a MEMS (device) that generally does not have a groove structure, in the process of forming (depositing) the filling layer 70 , the formation (deposition) speed of the portion corresponding to the center of the opening 62 is higher than that of the portion far from the center of the opening 62 . Formation (deposition) speed, easy formation of sealed seams. In contrast, in this embodiment, the groove structure 42 is formed through the opening 52 , and the opening 52 is formed through the opening 62 , so that the groove structure 42 can correspond to the opening 62 . Therefore, when the filling layer 70 is formed, the groove structure 42 can effectively prevent the generation of sealing seams.

再者,於本揭露的一些實施例中,由於開口62之底部的截面積62BA小於開口62之頂部的截面積62TA,能使填充層70更均勻地在形成於開口62中,避免在填充層70尚未填滿凹槽結構42與開口62前提早閉合造成空心結構。Furthermore, in some embodiments of the present disclosure, since the cross-sectional area 62BA of the bottom of the opening 62 is smaller than the cross-sectional area 62TA of the top of the opening 62 , the filling layer 70 can be formed in the opening 62 more uniformly, avoiding the formation of the filling layer 62 . 70 The hollow structure is formed by prematurely closing before filling the groove structure 42 and the opening 62 .

在此階段中,即已完成整合式微機電系統1的微機電系統裝置106。在一些實施例中,微機電系統裝置106可作為一壓力感測器,但本揭露實施例並非以此為限。在後續第21圖至第22圖的階段中,是針對微機電系統裝置108進行。At this stage, the MEMS device 106 of the integrated MEMS 1 has been completed. In some embodiments, the MEMS device 106 can be used as a pressure sensor, but the embodiments of the present disclosure are not limited thereto. In the subsequent stages of FIGS. 21 to 22 , it is performed for the MEMS device 108 .

參照第21圖,在一些實施例中,可將部分填充層70移除以形成開口72,開口72暴露出結構層60的部分頂表面60T。舉例來說,如第21圖所示,可將預定形成微機電系統裝置108之處的部分填充層70移除以形成開口72,但在預定形成微機電系統裝置106之處的填充層70則完整保留。Referring to FIG. 21 , in some embodiments, a portion of the filling layer 70 may be removed to form an opening 72 that exposes a portion of the top surface 60T of the structural layer 60 . For example, as shown in FIG. 21, a portion of the fill layer 70 where the MEMS device 108 is to be formed may be removed to form the opening 72, but the fill layer 70 where the MEMS device 106 is to be formed is Complete reservation.

接著,可在填充層70上形成一金屬層90,其中至少部分金屬層90形成於開口72中。具體而言,如第21圖所示,金屬層90可包含一第一部分90-1與一第二部分90-2,第一部分90-1與結構層60直接接觸(即,第一部分90-1可設置於開口72中),而第二部分90-2與填充層70直接接觸(但與結構層60分開)。金屬層90的材料與形成方法的範例可與金屬層30相同或相似,在此不多加贅述。Next, a metal layer 90 may be formed on the filling layer 70 , wherein at least a portion of the metal layer 90 is formed in the opening 72 . Specifically, as shown in FIG. 21, the metal layer 90 may include a first portion 90-1 and a second portion 90-2, and the first portion 90-1 is in direct contact with the structural layer 60 (ie, the first portion 90-1 may be disposed in the opening 72), while the second portion 90-2 is in direct contact with the filling layer 70 (but separated from the structural layer 60). Examples of the material and forming method of the metal layer 90 may be the same as or similar to those of the metal layer 30 , and details are not repeated here.

參照第22圖,在一些實施例中,可在填充層70與金屬層90上形成一第三介電層92。具體而言,如第22圖所示,第三介電層92可覆蓋填充層70與金屬層90,但本揭露實施例並非以此為限。第三介電層92的材料與形成方法的範例可與第一介電層20或第二介電層40相同或相似,在此不多加贅述。Referring to FIG. 22 , in some embodiments, a third dielectric layer 92 may be formed on the filling layer 70 and the metal layer 90 . Specifically, as shown in FIG. 22 , the third dielectric layer 92 may cover the filling layer 70 and the metal layer 90 , but the embodiment of the present disclosure is not limited thereto. Examples of materials and forming methods of the third dielectric layer 92 may be the same as or similar to those of the first dielectric layer 20 or the second dielectric layer 40 , and details are not repeated here.

在此階段中,即已完成整合式微機電系統1的微機電系統裝置108。在一些實施例中,微機電系統裝置108可作為一溫度感測器(temperature sensor),但本揭露實施例並非以此為限。At this stage, the MEMS device 108 of the integrated MEMS 1 has been completed. In some embodiments, the MEMS device 108 can be used as a temperature sensor, but the embodiments of the present disclosure are not limited thereto.

同時參照第22圖與第23圖,整合式微機電系統1可包含微機電系統裝置106與微機電系統裝置108。微機電系統裝置106與微機電系統裝置108可共用同一基板10。此外,微機電系統裝置106可作為一壓力感測器,而微機電系統裝置108可作為一溫度感測器。亦即,根據本揭露的一些實施例,可在整合式微機電系統1中同時形成至少兩種不同結構或功能的微機電系統裝置。相對地,在傳統的微機電系統中,不同的微機電系統裝置需要個別形成後,再透過另一電路板彼此整合。相較於傳統的微機電系統,透過本揭露實施例的製造方法可有效降低整合式微機電系統1的整體尺寸並簡化製程步驟。22 and 23 simultaneously, the integrated MEMS device 1 may include a MEMS device 106 and a MEMS device 108 . The MEMS device 106 and the MEMS device 108 may share the same substrate 10 . In addition, the MEMS device 106 can be used as a pressure sensor, and the MEMS device 108 can be used as a temperature sensor. That is, according to some embodiments of the present disclosure, at least two MEMS devices with different structures or functions can be simultaneously formed in the integrated MEMS 1 . In contrast, in the conventional MEMS, different MEMS devices need to be formed individually and then integrated with each other through another circuit board. Compared with the conventional MEMS, the manufacturing method of the disclosed embodiment can effectively reduce the overall size of the integrated MEMS 1 and simplify the process steps.

要注意的是,空腔80的位置與形狀並非限定於第23圖所示,可依實際需求進行調整。It should be noted that the position and shape of the cavity 80 are not limited to those shown in FIG. 23 , and can be adjusted according to actual needs.

第24圖至第25圖是根據一些其他的實施例繪示在製造整合式微機電系統1的不同階段之剖面示意圖。舉例來說,第24圖至第25圖所示的步驟可取代第17圖至第18圖所示的步驟,但本揭露實施例並非以此為限。此外,第24圖至第25圖僅以一個微機電系統裝置表示,此微機電系統裝置可以代表微機電系統裝置106或微機電系統裝置108。FIGS. 24 to 25 are schematic cross-sectional views illustrating different stages of manufacturing the integrated MEMS 1 according to some other embodiments. For example, the steps shown in FIG. 24 to FIG. 25 may replace the steps shown in FIG. 17 to FIG. 18 , but the embodiment of the present disclosure is not limited thereto. In addition, FIGS. 24 to 25 represent only one MEMS device, which may represent the MEMS device 106 or the MEMS device 108 .

參照第24圖,透過開口62將部分犧牲層50移除以形成開口52’。在此,開口52’的頂面積並未與開口62的底面積相等。在此步驟中,將決定後續形成的凹槽結構的位置與深度,舉例來說,如第24圖所示,在本實施例中,開口52’可暴露第一介電層20的部分頂表面20T,但本揭露實施例並非以此為限。Referring to FIG. 24, a portion of the sacrificial layer 50 is removed through the opening 62 to form the opening 52'. Here, the top area of opening 52' is not equal to the bottom area of opening 62. In this step, the position and depth of the subsequently formed groove structure will be determined. For example, as shown in FIG. 24 , in this embodiment, the opening 52 ′ can expose part of the top surface of the first dielectric layer 20 20T, but the embodiments of the present disclosure are not limited to this.

參照第25圖,透過開口52’對第二介電層40進行一圖案化製程(例如,包含一側向蝕刻製程)以將部分第二介電層40移除並形成凹槽結構42’。接著,可接續如第19圖與第20圖的步驟,將犧牲層50(部分或完全)移除,並形成填充層70。在本實施例中,凹槽結構42’可暴露第一介電層20的部分頂表面,因此填充層70可直接接觸第一介電層20,但本揭露實施例並非以此為限。Referring to FIG. 25, a patterning process (eg, including a lateral etching process) is performed on the second dielectric layer 40 through the opening 52' to remove part of the second dielectric layer 40 and form the groove structure 42'. Next, the sacrificial layer 50 may be removed (partially or completely) following the steps shown in FIGS. 19 and 20 to form a filling layer 70 . In this embodiment, the groove structure 42' may expose a part of the top surface of the first dielectric layer 20, so the filling layer 70 may directly contact the first dielectric layer 20, but the embodiment of the present disclosure is not limited thereto.

第26圖至第29圖是根據一些其他的實施例繪示在製造整合式微機電系統1的不同階段之剖面示意圖。舉例來說,第26圖至第29圖所示的步驟可取代第21圖至第22圖所示的步驟,但本揭露實施例並非以此為限。此外,第29圖僅以一個微機電系統裝置110表示,此微機電系統裝置110可以取代第22圖所示的微機電系統裝置106或微機電系統裝置108。FIGS. 26 to 29 are schematic cross-sectional views illustrating different stages of manufacturing the integrated MEMS 1 according to some other embodiments. For example, the steps shown in FIGS. 26 to 29 may replace the steps shown in FIGS. 21 to 22, but the embodiment of the present disclosure is not limited thereto. In addition, FIG. 29 only shows one MEMS device 110 , and the MEMS device 110 can replace the MEMS device 106 or the MEMS device 108 shown in FIG. 22 .

參照第26圖,在一些實施例中,可將部分填充層70移除以形成開口72,開口72暴露出結構層60的部分頂表面60T。接著,可在填充層70上形成一金屬層90,金屬層90形成於開口72中。Referring to FIG. 26 , in some embodiments, a portion of the filling layer 70 may be removed to form an opening 72 that exposes a portion of the top surface 60T of the structural layer 60 . Next, a metal layer 90 may be formed on the filling layer 70 , and the metal layer 90 is formed in the opening 72 .

參照第27圖,在一些實施例中,可在填充層70與金屬層90上形成一第三介電層92。具體而言,如第27圖所示,第三介電層92可覆蓋填充層70與金屬層90,但本揭露實施例並非以此為限。Referring to FIG. 27 , in some embodiments, a third dielectric layer 92 may be formed on the filling layer 70 and the metal layer 90 . Specifically, as shown in FIG. 27 , the third dielectric layer 92 may cover the filling layer 70 and the metal layer 90 , but the embodiment of the present disclosure is not limited thereto.

參照第28圖,在一些實施例中,可將部分第三介電層92移除以形成開口94,開口94暴露出位於金屬層90的部分頂表面90T。Referring to FIG. 28 , in some embodiments, a portion of the third dielectric layer 92 may be removed to form an opening 94 that exposes a portion of the top surface 90T of the metal layer 90 .

接著,可在第三介電層92上形成金屬層96,其中至少部分金屬層96形成於開口94中。具體而言,如第28圖所示,金屬層96可包含一第一部分96-1與一第二部分96-2,第一部分96-1電性連接於金屬層90(即,第一部分96-1可設置於開口94中並與金屬層90直接接觸),而第二部分96-2與金屬層90電性絕緣。金屬層96的材料與形成方法的範例可與金屬層30或金屬層90相同或相似,在此不多加贅述。Next, a metal layer 96 may be formed on the third dielectric layer 92 , wherein at least a portion of the metal layer 96 is formed in the opening 94 . Specifically, as shown in FIG. 28, the metal layer 96 may include a first portion 96-1 and a second portion 96-2, and the first portion 96-1 is electrically connected to the metal layer 90 (ie, the first portion 96-1 1 may be disposed in the opening 94 and in direct contact with the metal layer 90 ), while the second portion 96 - 2 is electrically insulated from the metal layer 90 . Examples of materials and forming methods of the metal layer 96 may be the same as or similar to those of the metal layer 30 or the metal layer 90 , and details are not repeated here.

參照第29圖,在一些實施例中,可在金屬層96的第二部分96-2上形成一吸濕層98,以形成微機電系統裝置110。在一些實施例中,吸濕層98的材料可包含LiCl、Se、Ge、TiO2 、ZnCr2 O4、MgCr2 O4 、Al2 O3 、環氧樹脂(epoxy)及多孔質金屬氧化膜等,但本揭露實施例並非以此為限。在一些實施例中,吸濕層98可透過一沉積製程與一圖案化製程形成於金屬層96的第二部分96-2上,但本揭露實施例並非以此為限。Referring to FIG. 29, in some embodiments, a hygroscopic layer 98 may be formed on the second portion 96-2 of the metal layer 96 to form the MEMS device 110. Referring to FIG. In some embodiments, the material of the hygroscopic layer 98 may include LiCl, Se, Ge, TiO 2 , ZnCr 2 O 4 , MgCr 2 O 4 , Al 2 O 3 , epoxy resin, porous metal oxide film, etc. , but the embodiments of the present disclosure are not limited thereto. In some embodiments, the moisture absorption layer 98 may be formed on the second portion 96-2 of the metal layer 96 through a deposition process and a patterning process, but the embodiments of the present disclosure are not limited thereto.

在一些實施例中,微機電系統裝置110可例如為一濕度感測器(humidity sensor),但本揭露實施例並非以此為限。在一些其他的實施例中,微機電系統裝置110可例如為一氣體感測器(gas sensor)。舉例來說,氣體感測器的感測材料可包含WO3 、SnO2 等,但本揭露實施例並非以此為限。微機電系統裝置110可以取代第22圖所示的微機電系統裝置106與微機電系統裝置108的至少其中之一,或者與此兩者並存於第22圖所示的整合式微機電系統1中。亦即,在本揭露的實施例中,整合式微機電系統1可整合具有不同感測功能的微機電系統裝置。In some embodiments, the MEMS device 110 may be, for example, a humidity sensor, but the embodiments of the present disclosure are not limited thereto. In some other embodiments, the MEMS device 110 may be, for example, a gas sensor. For example, the sensing material of the gas sensor may include WO 3 , SnO 2 , etc., but the embodiment of the present disclosure is not limited thereto. The MEMS device 110 may replace at least one of the MEMS device 106 and the MEMS device 108 shown in FIG. 22 , or coexist in the integrated MEMS device 1 shown in FIG. 22 . That is, in the embodiments of the present disclosure, the integrated MEMS 1 can integrate MEMS devices with different sensing functions.

綜上所述,在本揭露的一些實施例中,透過在第二介電層中設置凹槽結構及在結構層中設置與凹槽結構對應的開口,可使填充層(即用於封孔的結構)連續且均勻地填充於此開口與凹槽結構中,以完成封孔。此外,藉由本揭露實施例的微機電系統裝置與其製造方法,能有效防止封孔接縫與空心結構的產生,進而提高封孔品質並提升整體的穩定性。再者,不需要繁複的製程,能有效縮短製程時間並降低成本。To sum up, in some embodiments of the present disclosure, by arranging the groove structure in the second dielectric layer and arranging the opening corresponding to the groove structure in the structure layer, the filling layer (that is, used for sealing the hole) can be formed. structure) is continuously and uniformly filled in this opening and groove structure to complete the sealing. In addition, by using the MEMS device and the manufacturing method thereof of the disclosed embodiments, the generation of sealing seams and hollow structures can be effectively prevented, thereby improving the sealing quality and improving the overall stability. Furthermore, no complicated manufacturing process is required, which can effectively shorten the manufacturing time and reduce the cost.

再者,根據本揭露的一些實施例,可在整合式微機電系統1中同時形成至少兩種不同結構或功能的微機電系統裝置。相較於傳統的微機電系統,透過本揭露實施例的製造方法可有效降低整合式微機電系統的整體尺寸並簡化製程步驟。Furthermore, according to some embodiments of the present disclosure, at least two MEMS devices with different structures or functions can be simultaneously formed in the integrated MEMS 1 . Compared with the traditional MEMS, the manufacturing method of the embodiment of the present disclosure can effectively reduce the overall size of the integrated MEMS and simplify the process steps.

以上概述數個實施例的部件,以便在本揭露所屬技術領域中具有通常知識者可以更理解本揭露實施例的觀點。在本揭露所屬技術領域中具有通常知識者應該理解,他們能以本揭露實施例為基礎,設計或修改其他製程和結構以達到與在此介紹的實施例相同之目的及/或優勢。在本揭露所屬技術領域中具有通常知識者也應該理解到,此類等效的結構並無悖離本揭露的精神與範圍,且他們能在不違背本揭露之精神和範圍之下,做各式各樣的改變、取代和替換。因此,本揭露之保護範圍當視後附之申請專利範圍所界定者為準。另外,雖然本揭露已以數個較佳實施例揭露如上,然其並非用以限定本揭露。The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the present disclosure pertains can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure pertains should appreciate that they can, based on the embodiments of the present disclosure, design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments described herein. Those with ordinary knowledge in the technical field to which the present disclosure pertains should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes without departing from the spirit and scope of the present disclosure. Various changes, substitutions and substitutions. Therefore, the scope of protection of the present disclosure should be determined by the scope of the appended patent application. In addition, although the present disclosure has been disclosed above with several preferred embodiments, it is not intended to limit the present disclosure.

整份說明書對特徵、優點或類似語言的引用,並非意味可以利用本揭露實現的所有特徵和優點應該或者可以在本揭露的任何單個實施例中實現。相對地,涉及特徵和優點的語言被理解為其意味著結合實施例描述的特定特徵、優點或特性包括在本揭露的至少一個實施例中。因而,在整份說明書中對特徵和優點以及類似語言的討論可以但不一定代表相同的實施例。Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that can be realized with the present disclosure should or can be realized in any single embodiment of the present disclosure. Conversely, language referring to features and advantages is understood to mean that a particular feature, advantage or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, represent the same embodiment.

再者,在一個或多個實施例中,可以任何合適的方式組合本揭露的所描述的特徵、優點和特性。根據本文的描述,相關領域的技術人員將意識到,可在沒有特定實施例的一個或多個特定特徵或優點的情況下實現本揭露。在其他情況下,在某些實施例中可辨識附加的特徵和優點,這些特徵和優點可能不存在於本揭露的所有實施例中。Furthermore, the described features, advantages and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. From the description herein, one skilled in the relevant art will appreciate that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure.

1:整合式微機電系統 100,102,106,108,110:微機電系統裝置 10:基板 12:接點 20:第一介電層 20H:通孔 30:金屬層 31:第一部分 32:第二部分 40:第二介電層 40T:頂表面 42,42’,44,46:凹槽結構 42E,44E:頂端 42S,44S,46S:側壁 42TA:頂部的截面積 50:犧牲層 50R:犧牲層剩餘部分 50T:頂表面 52,52’:開口 60:結構層 60B:結構層的最底表面 60E1,60E2:端部 60T:頂表面 62:開口 62BA:底部的截面積 62TA:頂部的截面積 621,622:側壁 64:開口 70:填充層 72:開口 80:空腔 90:金屬層 90-1:第一部分 90-2:第二部分 92:第三介電層 94:開口 96:金屬層 96-1:第一部分與 96-2:第二部分 D:方向 d1,d2:距離 g:高度 θ:角度1: Integrated MEMS 100, 102, 106, 108, 110: MEMS devices 10: Substrate 12: Contact 20: First Dielectric Layer 20H: Through hole 30: Metal layer 31: Part One 32: Part II 40: Second Dielectric Layer 40T: Top surface 42, 42', 44, 46: groove structure 42E, 44E: Top 42S, 44S, 46S: Sidewalls 42TA: Cross-sectional area at the top 50: Sacrificial Layer 50R: The remainder of the sacrificial layer 50T: Top surface 52,52': opening 60: Structural Layer 60B: Bottom most surface of the structural layer 60E1, 60E2: end 60T: Top surface 62: Opening 62BA: Cross-sectional area of the bottom 62TA: Cross-sectional area at the top 621, 622: Sidewalls 64: Opening 70: Filler layer 72: Opening 80: cavity 90: metal layer 90-1: Part One 90-2: Part II 92: The third dielectric layer 94: Opening 96: Metal layer 96-1: Part I and 96-2: Part II D: direction d1,d2: distance g: height θ: angle

以下將配合所附圖式詳述本揭露實施例。應注意的是,各種特徵部件並未按照比例繪製且僅用以說明例示。事實上,元件的尺寸可能經放大或縮小,以清楚地表現出本揭露實施例的技術特徵。 第1圖至第8圖是根據一些實施例繪示在製造微機電系統裝置的各個階段之剖面示意圖。 第9圖是根據另一實施例繪示凹槽結構的剖面示意圖。 第10圖是根據又一實施例繪示凹槽結構的剖面示意圖。 第11圖是根據一些實施例繪示微機電系統裝置的剖面示意圖。 第12圖至第22圖是根據一些實施例繪示在製造整合式微機電系統的各個階段之剖面示意圖。 第23圖是整合式微機電系統的部分俯視圖。 第24圖至第25圖是根據一些其他的實施例繪示在製造整合式微機電系統的不同階段之剖面示意圖。 第26圖至第29圖是根據一些其他的實施例繪示在製造整合式微機電系統的不同階段之剖面示意圖。The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be enlarged or reduced to clearly represent the technical features of the embodiments of the present disclosure. FIGS. 1-8 are schematic cross-sectional views illustrating various stages of fabricating a MEMS device according to some embodiments. FIG. 9 is a schematic cross-sectional view illustrating a groove structure according to another embodiment. FIG. 10 is a schematic cross-sectional view illustrating a groove structure according to yet another embodiment. FIG. 11 is a schematic cross-sectional view illustrating a MEMS device according to some embodiments. FIGS. 12-22 are schematic cross-sectional views illustrating various stages in the fabrication of an integrated MEMS system, according to some embodiments. FIG. 23 is a partial top view of the integrated MEMS. FIGS. 24-25 are schematic cross-sectional views illustrating different stages of manufacturing an integrated MEMS system according to some other embodiments. FIGS. 26 to 29 are schematic cross-sectional views illustrating different stages of manufacturing an integrated MEMS system according to some other embodiments.

100:微機電系統裝置100: MEMS Devices

10:基板10: Substrate

12:接點12: Contact

20:第一介電層20: First Dielectric Layer

30:金屬層30: Metal layer

31:第一部分31: Part One

32:第二部分32: Part II

40:第二介電層40: Second Dielectric Layer

42:凹槽結構42: groove structure

42E:頂端42E: Top

50R:犧牲層剩餘部分50R: The remainder of the sacrificial layer

60:結構層60: Structural Layer

60B:結構層的最底表面60B: Bottom most surface of the structural layer

60E1,60E2:端部60E1, 60E2: end

62:開口62: Opening

70:填充層70: Filler layer

80:空腔80: cavity

D:方向D: direction

d1,d2:距離d1,d2: distance

g:高度g: height

Claims (31)

一種微機電系統裝置,包括:一基板,具有至少一接點;一第一介電層,設置於該基板上;至少一第一金屬層,設置於該第一介電層上,且至少部分該第一金屬層電性連接於該接點;一第二介電層,設置於該第一介電層與該第一金屬層上並具有一凹槽結構;一結構層,設置於該第二介電層上並具有一開口,其中該開口之底部的截面積小於該開口之頂部的截面積,該開口對應於該凹槽結構設置,且該開口之底部的截面積小於該凹槽結構之頂部的截面積;以及一填充層,至少部分設置於該開口與該凹槽結構中,其中該第二介電層、該結構層與該填充層界定一空腔。 A MEMS device, comprising: a substrate with at least one contact; a first dielectric layer disposed on the substrate; at least a first metal layer disposed on the first dielectric layer and at least partially The first metal layer is electrically connected to the contact; a second dielectric layer is disposed on the first dielectric layer and the first metal layer and has a groove structure; a structure layer is disposed on the first dielectric layer and the first metal layer The two dielectric layers have an opening, wherein the cross-sectional area of the bottom of the opening is smaller than the cross-sectional area of the top of the opening, the opening is disposed corresponding to the groove structure, and the cross-sectional area of the bottom of the opening is smaller than the cross-sectional area of the groove structure and a filling layer at least partially disposed in the opening and the groove structure, wherein the second dielectric layer, the structure layer and the filling layer define a cavity. 如請求項1所述之微機電系統裝置,其中該填充層直接接觸該第一介電層或該第二介電層。 The MEMS device of claim 1, wherein the filling layer directly contacts the first dielectric layer or the second dielectric layer. 如請求項1所述之微機電系統裝置,更包括:一犧牲層剩餘部分,設置於該第二介電層與結構層之間,其中該空腔位於該第二介電層、該犧牲層剩餘部分、該結構層與該填充層之間。 The MEMS device of claim 1, further comprising: a remainder of the sacrificial layer disposed between the second dielectric layer and the structural layer, wherein the cavity is located between the second dielectric layer and the sacrificial layer The remaining part, between the structural layer and the filling layer. 如請求項3所述之微機電系統裝置,其中該結構層的該開口處在該凹槽結構中的投影具有一端部,該端部與該凹槽結構的頂端在平行於該第二介電層之頂表面的方向上的最短距離大於或等於該犧牲層剩餘部分的厚度。 The MEMS device of claim 3, wherein the projection of the opening of the structural layer in the groove structure has an end, and the end and the top of the groove structure are parallel to the second dielectric The shortest distance in the direction of the top surface of the layer is greater than or equal to the thickness of the remainder of the sacrificial layer. 如請求項1所述之微機電系統裝置,其中該第二介電層之頂表面與該凹槽結構的側壁所夾的角度介於90至150度。 The MEMS device of claim 1, wherein the angle between the top surface of the second dielectric layer and the sidewall of the groove structure is between 90 and 150 degrees. 如請求項1所述之微機電系統裝置,其中該凹槽結構的側壁具有一弧度。 The MEMS device of claim 1, wherein the sidewall of the groove structure has an arc. 如請求項1所述之微機電系統裝置,其中該第一金屬層包括一第一部分與一第二部分,該第一部分電性連接於該接點,該第二部分與該接點電性絕緣。 The MEMS device of claim 1, wherein the first metal layer includes a first portion and a second portion, the first portion is electrically connected to the contact, and the second portion is electrically insulated from the contact . 如請求項7所述之微機電系統裝置,其中該填充層直接接觸該第二部分。 The MEMS device of claim 7, wherein the filling layer directly contacts the second portion. 如請求項1所述之微機電系統裝置,其中部分該填充層設置於該結構層上。 The MEMS device of claim 1, wherein part of the filling layer is disposed on the structural layer. 一種微機電系統裝置的製造方法,包括:提供一基板,該基板具有至少一接點;在該基板上形成一第一介電層,其中該第一介電層具有至少一通孔,該通孔暴露該接點的部分頂表面;在該第一介電層上形成至少一金屬層,其中至少部分該金屬層電性連接於該接點;在該第一介電層與該金屬層上形成一第二介電層,其中該第二介電層具有一凹槽結構;在該第二介電層上與該凹槽結構中形成一犧牲層;在該第二介電層與該犧牲層上形成一結構層; 將部分該結構層移除以形成一開口,其中該開口之底部的截面積小於該開口之頂部的截面積,且該開口暴露出位於該凹槽結構中的該犧牲層;將該犧牲層移除以暴露該凹槽結構,其中該開口之底部的截面積小於該凹槽結構之頂部的截面積;以及形成一填充層,其中至少部分該填充層形成於該開口與該凹槽結構中,且該第二介電層、該結構層與該填充層界定一空腔。 A method of manufacturing a microelectromechanical system device, comprising: providing a substrate, the substrate having at least one contact; forming a first dielectric layer on the substrate, wherein the first dielectric layer has at least one through hole, the through hole exposing part of the top surface of the contact; forming at least one metal layer on the first dielectric layer, wherein at least part of the metal layer is electrically connected to the contact; forming on the first dielectric layer and the metal layer a second dielectric layer, wherein the second dielectric layer has a groove structure; a sacrificial layer is formed on the second dielectric layer and in the groove structure; the second dielectric layer and the sacrificial layer are formed A structural layer is formed on it; removing part of the structure layer to form an opening, wherein the cross-sectional area of the bottom of the opening is smaller than the cross-sectional area of the top of the opening, and the opening exposes the sacrificial layer in the groove structure; removing the sacrificial layer divided by exposing the groove structure, wherein the cross-sectional area of the bottom of the opening is smaller than the cross-sectional area of the top of the groove structure; and forming a filling layer, wherein at least part of the filling layer is formed in the opening and the groove structure, And the second dielectric layer, the structure layer and the filling layer define a cavity. 如請求項10所述之微機電系統裝置的製造方法,其中該填充層直接接觸該第一介電層或該第二介電層。 The method for manufacturing a MEMS device as claimed in claim 10, wherein the filling layer directly contacts the first dielectric layer or the second dielectric layer. 如請求項10所述之微機電系統裝置的製造方法,其中該結構層的該開口處在該凹槽結構中的投影具有一端部,該端部與該凹槽結構的頂端在平行於該第二介電層之頂表面的方向上的最短距離大於或等於該犧牲層的厚度。 The method for manufacturing a MEMS device as claimed in claim 10, wherein the projection of the opening of the structural layer in the groove structure has an end, and the end and the top of the groove structure are parallel to the first The shortest distance in the direction of the top surfaces of the two dielectric layers is greater than or equal to the thickness of the sacrificial layer. 如請求項10所述之微機電系統裝置的製造方法,其中該第二介電層之頂表面與該凹槽結構的側壁所夾的角度介於90至150度。 The method for manufacturing a MEMS device as claimed in claim 10, wherein the angle between the top surface of the second dielectric layer and the sidewall of the groove structure is between 90 and 150 degrees. 如請求項10所述之微機電系統裝置的製造方法,其中該凹槽結構的側壁具有一弧度。 The method for manufacturing a MEMS device as claimed in claim 10, wherein the sidewall of the groove structure has an arc. 如請求項10所述之微機電系統裝置的製造方法,其中在形成該第二介電層的步驟中,該第二介電層的凹槽結構暴露出部分該金屬層的頂表面。 The method for manufacturing a MEMS device as claimed in claim 10, wherein in the step of forming the second dielectric layer, the groove structure of the second dielectric layer exposes a portion of the top surface of the metal layer. 如請求項15所述之微機電系統裝置的製造方法,其中該金屬層包括一第一部分與一第二部分,該第一部分電性連接於該接點,該第二部分與該接點電性絕緣。 The method for manufacturing a MEMS device as claimed in claim 15, wherein the metal layer includes a first portion and a second portion, the first portion is electrically connected to the contact, and the second portion is electrically connected to the contact insulation. 如請求項16所述之微機電系統裝置的製造方法,其中該填充層直接接觸該第二部分。 The method for manufacturing a MEMS device as claimed in claim 16, wherein the filling layer directly contacts the second part. 一種微機電系統裝置的製造方法,包括:提供一基板,該基板具有至少一接點;在該基板上形成一第一介電層,其中該第一介電層具有至少一通孔,該通孔暴露該接點的部分頂表面;在該第一介電層上形成至少一第一金屬層,其中至少部分該第一金屬層電性連接於該接點;在該第一介電層與該第一金屬層上形成一第二介電層;在該第二介電層上形成一犧牲層;在該第二介電層與該犧牲層上形成一結構層;將部分該結構層移除以形成一第一開口,該第一開口暴露出該犧牲層的部分頂表面,其中該第一開口之底部的截面積小於該第一開口之頂部的截面積;透過該第一開口將部分該犧牲層移除以形成一第二開口,該第二開口暴露出該第二介電層的部分頂表面;透過該第二開口將部分該第二介電層移除以形成一凹槽結構;其中該第一開口之底部的截面積小於該凹槽結構之頂部的截面積;將該犧牲層移除;以及形成一填充層,其中至少部分該填充層形成於該第二開口與該凹槽結構中,且該第二介電層、該結構層與該填充層界定一空腔。 A method of manufacturing a microelectromechanical system device, comprising: providing a substrate, the substrate having at least one contact; forming a first dielectric layer on the substrate, wherein the first dielectric layer has at least one through hole, the through hole exposing a part of the top surface of the contact; forming at least a first metal layer on the first dielectric layer, wherein at least part of the first metal layer is electrically connected to the contact; the first dielectric layer and the forming a second dielectric layer on the first metal layer; forming a sacrificial layer on the second dielectric layer; forming a structural layer on the second dielectric layer and the sacrificial layer; removing part of the structural layer To form a first opening, the first opening exposes part of the top surface of the sacrificial layer, wherein the cross-sectional area of the bottom of the first opening is smaller than the cross-sectional area of the top of the first opening; The sacrificial layer is removed to form a second opening, the second opening exposes part of the top surface of the second dielectric layer; part of the second dielectric layer is removed through the second opening to form a groove structure; wherein the cross-sectional area of the bottom of the first opening is smaller than the cross-sectional area of the top of the groove structure; removing the sacrificial layer; and forming a filling layer, wherein at least part of the filling layer is formed in the second opening and the groove In the structure, the second dielectric layer, the structure layer and the filling layer define a cavity. 如請求項18所述之微機電系統裝置的製造方法,更包括: 將部分該填充層移除以形成一第三開口,該第三開口暴露出該結構層的部分頂表面;及在該填充層上形成一第二金屬層,其中至少部分該第二金屬層形成於該第三開口中。 The manufacturing method of the MEMS device as claimed in claim 18, further comprising: removing part of the filling layer to form a third opening exposing part of the top surface of the structural layer; and forming a second metal layer on the filling layer, wherein at least part of the second metal layer is formed in the third opening. 如請求項19所述之微機電系統裝置的製造方法,其中該第二金屬層包括一第一部分與一第二部分,該第一部分與該結構層直接接觸,該第二部分與該填充層直接接觸。 The method for manufacturing a MEMS device as claimed in claim 19, wherein the second metal layer comprises a first part and a second part, the first part is in direct contact with the structure layer, and the second part is in direct contact with the filling layer touch. 如請求項19所述之微機電系統裝置的製造方法,更包括:在該填充層與該第二金屬層上形成一第三介電層。 The manufacturing method of the MEMS device as claimed in claim 19, further comprising: forming a third dielectric layer on the filling layer and the second metal layer. 如請求項21所述之微機電系統裝置的製造方法,更包括:將部分該第三介電層移除以形成一第四開口,該第四開口暴露出該第二金屬層的部分頂表面;及在該第三介電層上形成一第三金屬層,其中至少部分該第三金屬層形成於該第四開口中。 The manufacturing method of the MEMS device of claim 21, further comprising: removing part of the third dielectric layer to form a fourth opening, the fourth opening exposing part of the top surface of the second metal layer ; and forming a third metal layer on the third dielectric layer, wherein at least part of the third metal layer is formed in the fourth opening. 如請求項22所述之微機電系統裝置的製造方法,其中該第三金屬層包括一第一部分與一第二部分,該第一部分電性連接於該第二金屬層,該第二部分與該第二金屬層電性絕緣。 The method for manufacturing a MEMS device as claimed in claim 22, wherein the third metal layer includes a first part and a second part, the first part is electrically connected to the second metal layer, and the second part is connected to the second part. The second metal layer is electrically insulating. 如請求項23所述之微機電系統裝置的製造方法,更包括:在該第二部分上形成一吸濕層。 The manufacturing method of the MEMS device as claimed in claim 23, further comprising: forming a moisture absorption layer on the second part. 一種整合式微機電系統,包括:複數個如請求項1~9中任一項所述的微機電系統裝置,其中該些微機電系統裝置共用同一基板。 An integrated MEMS device includes: a plurality of MEMS devices as described in any one of claims 1 to 9, wherein the MEMS devices share the same substrate. 如請求項25所述之整合式微機電系統,其中該些微機電系統裝置的其中之一更包括:一第二金屬層,設置於該結構層的部分頂表面上。 The integrated MEMS device of claim 25, wherein one of the MEMS devices further comprises: a second metal layer disposed on a part of the top surface of the structure layer. 如請求項26所述之整合式微機電系統,其中該第二金屬層包括一第一部分與一第二部分,該第一部分與該結構層直接接觸,該第二部分與該填充層直接接觸。 The integrated MEMS of claim 26, wherein the second metal layer includes a first portion and a second portion, the first portion is in direct contact with the structural layer, and the second portion is in direct contact with the filling layer. 如請求項26所述之整合式微機電系統,其中該些微機電系統裝置的其中之一更包括:一第三介電層,設置於該填充層與該第二金屬層上。 The integrated MEMS device of claim 26, wherein one of the MEMS devices further comprises: a third dielectric layer disposed on the filling layer and the second metal layer. 如請求項28所述之整合式微機電系統,其中該些微機電系統裝置的其中之一更包括:一第三金屬層,其中至少部分該第三金屬層設置於該第二金屬層的部分頂表面上。 The integrated MEMS device of claim 28, wherein one of the MEMS devices further comprises: a third metal layer, wherein at least part of the third metal layer is disposed on a part of the top surface of the second metal layer superior. 如請求項29所述之整合式微機電系統,其中該第三金屬層包括一第一部分與一第二部分,該第一部分電性連接於該第二金屬層,該第二部分與該第二金屬層電性絕緣。 The integrated MEMS of claim 29, wherein the third metal layer includes a first part and a second part, the first part is electrically connected to the second metal layer, and the second part and the second metal Layer electrical insulation. 如請求項29所述之整合式微機電系統,更包括:一吸濕層,設置於該第二部分上。 The integrated micro-electromechanical system as claimed in claim 29, further comprising: a moisture absorption layer disposed on the second part.
TW109145665A 2019-12-23 2020-12-23 Mems device, manufacturing method of the same and integrated mems using the same TWI765489B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/412,160 US11939212B2 (en) 2019-12-23 2021-08-25 MEMS device, manufacturing method of the same, and integrated MEMS module using the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW108147159 2019-12-23
TW108147159 2019-12-23

Publications (2)

Publication Number Publication Date
TW202124254A TW202124254A (en) 2021-07-01
TWI765489B true TWI765489B (en) 2022-05-21

Family

ID=76663977

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109145665A TWI765489B (en) 2019-12-23 2020-12-23 Mems device, manufacturing method of the same and integrated mems using the same

Country Status (2)

Country Link
CN (2) CN113086937B (en)
TW (1) TWI765489B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11939212B2 (en) 2019-12-23 2024-03-26 Industrial Technology Research Institute MEMS device, manufacturing method of the same, and integrated MEMS module using the same
CN113086937B (en) * 2019-12-23 2024-03-19 财团法人工业技术研究院 MEMS device and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2236456A1 (en) * 2009-03-30 2010-10-06 Nxp B.V. Front end micro cavity
TW201641415A (en) * 2015-05-29 2016-12-01 台灣積體電路製造股份有限公司 MEMS packages and methods of manufacture thereof
CN109841580A (en) * 2017-12-05 2019-06-04 恩智浦美国有限公司 Micromodule with integrated heat dissipation column, system and production method including it

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW511242B (en) * 2001-12-14 2002-11-21 Megic Corp Chip structure and process for making the same
FR2859201B1 (en) * 2003-08-29 2007-09-21 Commissariat Energie Atomique MICROMECHANICAL DEVICE COMPRISING A SUSPENDED ELEMENT ATTACHED TO A SUPPORT BY A PILLAR AND METHOD OF MANUFACTURING SUCH A DEVICE
US20070170528A1 (en) * 2006-01-20 2007-07-26 Aaron Partridge Wafer encapsulated microelectromechanical structure and method of manufacturing same
US7993950B2 (en) * 2008-04-30 2011-08-09 Cavendish Kinetics, Ltd. System and method of encapsulation
CN101661012B (en) * 2009-08-11 2013-03-13 南京理工大学 Microfilm capacitive type surface stress sensor used for biochemical detection and manufacture method thereof
TWI475642B (en) * 2010-04-06 2015-03-01 United Microelectronics Corp Integrated circuit and fabricating method thereof
US9365416B2 (en) * 2011-08-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for motion sensor
CN102963856B (en) * 2011-09-01 2016-04-27 鑫创科技股份有限公司 Micro-electro-mechanical system device and method of manufacturing the same
CN202808341U (en) * 2012-07-19 2013-03-20 水木智芯科技(北京)有限公司 Conducting structure with insulated slot through structural layer
CN103839917B (en) * 2012-11-27 2017-08-25 中芯国际集成电路制造(上海)有限公司 Mim capacitor and forming method thereof
DE102013206368A1 (en) * 2013-04-11 2014-10-16 Robert Bosch Gmbh Semiconductor chip and method for its production
US9029961B2 (en) * 2013-08-29 2015-05-12 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer level method of sealing different pressure levels for MEMS sensors
US9299671B2 (en) * 2013-10-15 2016-03-29 Invensense, Inc. Integrated CMOS back cavity acoustic transducer and the method of producing the same
CN103922273B (en) * 2014-04-30 2016-01-13 安徽北方芯动联科微系统技术有限公司 The manufacture method of stack combinations formula MEMS chip and stack combinations formula MEMS chip thereof
JP6062393B2 (en) * 2014-05-12 2017-01-18 株式会社豊田中央研究所 Semiconductor device manufacturing method and semiconductor device
EP3029724B1 (en) * 2014-12-01 2017-06-07 IMEC vzw Metallization method for semiconductor structures
US9919915B2 (en) * 2016-06-14 2018-03-20 Invensense, Inc. Method and system for MEMS devices with dual damascene formed electrodes
US10522468B2 (en) * 2017-07-31 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
CN109626318B (en) * 2018-12-21 2020-09-15 中国科学院半导体研究所 Cover plate structure, manufacturing method thereof and capacitive sensor
CN113086937B (en) * 2019-12-23 2024-03-19 财团法人工业技术研究院 MEMS device and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2236456A1 (en) * 2009-03-30 2010-10-06 Nxp B.V. Front end micro cavity
TW201641415A (en) * 2015-05-29 2016-12-01 台灣積體電路製造股份有限公司 MEMS packages and methods of manufacture thereof
CN109841580A (en) * 2017-12-05 2019-06-04 恩智浦美国有限公司 Micromodule with integrated heat dissipation column, system and production method including it

Also Published As

Publication number Publication date
CN113086937B (en) 2024-03-19
CN113086937A (en) 2021-07-09
TW202124254A (en) 2021-07-01
CN113086939A (en) 2021-07-09
CN113086939B (en) 2024-04-09

Similar Documents

Publication Publication Date Title
US7993950B2 (en) System and method of encapsulation
JP4908202B2 (en) Micro electromechanical device and sealing method and manufacturing method thereof
JP5089406B2 (en) Chip carrier substrate including capacitor and manufacturing method thereof
US8994127B2 (en) Method of fabricating isolating semiconductor structures using a layout of trenches and openings
JP2007516848A (en) Device accommodation method and corresponding apparatus
TWI765489B (en) Mems device, manufacturing method of the same and integrated mems using the same
TW201727780A (en) Manufacturing method of MEMS package
US20150284242A1 (en) Electrical component and method of manufacturing the same
US20190119105A1 (en) MEMS Method and Structure
US20110298140A1 (en) Component having a through-contact
US11939212B2 (en) MEMS device, manufacturing method of the same, and integrated MEMS module using the same
US11365117B2 (en) MEMS device and manufacturing method of the same
TWI475642B (en) Integrated circuit and fabricating method thereof
TWI833315B (en) Semiconductor device and method for fabricating thereof
TWI855295B (en) Method of manufacturing semiconductor device
JP2006245198A (en) Manufacturing method of semiconductor device
TWI750862B (en) Capacitive ultrasound transducer and manufacturing method thereof
US20230389297A1 (en) Semiconductor structure and method for forming the same
US20240092632A1 (en) Mems device and manufacturing method thereof
KR100679827B1 (en) Method of fabricating MIMMetal-Insulator-Metal capacitor
JPH045823A (en) Semiconductor device and its manufacture
CN108408683B (en) Method for manufacturing semiconductor device
CN116864447A (en) Method for manufacturing high-voltage-resistant semiconductor device and semiconductor device
TW202343686A (en) Semiconductor structure and the method for forming the same
CN118116867A (en) Manufacturing process of small-size contact hole