TWI833315B - Semiconductor device and method for fabricating thereof - Google Patents

Abstract

A method for fabricating a semiconductor device includes forming a first opening in a substrate, conformally depositing an insulating material in the first opening and the substrate, and partially removing the insulating material to form a second opening in the substrate. The substrate is exposed at the bottom of the second opening. The method further includes forming a contact in the second opening. The bottom of the contact directly contacts the substrate. The method further includes forming a bit line structure on the substrate. The bit line structure is disposed on and connected to the contact. The method further includes forming a spacer along a sidewall of the bit line structure.

Description

Semiconductor device and manufacturing method thereof

The present disclosure provides a semiconductor device and a manufacturing method thereof.

As electronic devices become thinner and lighter, semiconductor devices such as dynamic random access memory (DRAM) become more highly integrated. Therefore, the distance between elements within a semiconductor device is gradually shortened. For example, functional density (i.e., the number of interconnected devices per unit area) typically increases while geometric size (i.e., the smallest component (or line) that can be produced using a process) decreases. This scaling down process usually provides benefits by increasing production efficiency and reducing related costs.

However, this advancement in miniaturization has increased the complexity of manufacturing semiconductor devices. As the minimum feature size shrinks, the process becomes more difficult. Therefore, how to manufacture reliable semiconductor devices in the development of miniaturized semiconductor devices is a challenge.

According to some embodiments of the present disclosure, a method of fabricating a semiconductor device includes forming a first opening in a substrate, conformally depositing an insulating material in the first opening and on the substrate, and locally removing the insulating material to form an insulating layer And a second opening is defined in the base material, wherein the base material is exposed to the bottom of the second opening. The method of manufacturing a semiconductor device further includes forming a contact in the second opening, wherein a bottom of the contact directly contacts the substrate. The method of manufacturing a semiconductor device further includes forming a bit line structure on the substrate, wherein the bit line structure is located on the contact and connects the contact. The method of manufacturing a semiconductor device further includes forming spacers on sidewalls of the bit line structures.

In some embodiments, locally removing the insulating material includes removing horizontal portions of the insulating material.

In some embodiments, partially removing the insulating material further includes trimming the thickness of the insulating layer to define a cross-sectional shape of the second opening.

In some embodiments, forming the contact in the second opening includes completely filling the second opening with conductive material so that the contact has the aforementioned cross-sectional shape.

In some embodiments, the local removal of the insulating material includes using a gas etchant, wherein the gas etchant is organic, and the flow rate of the gas etchant is controlled between 5 sccm and 35 sccm.

According to other embodiments of the present disclosure, a semiconductor device includes a substrate having an active region and an isolation region, a bit line structure disposed on the substrate and protruding from the substrate, a bit line structure disposed on the substrate and along the bit line structure. Spacers extending from the sidewalls of the line structures, contacts disposed in the base material between the bit line structures and the active areas, and an insulating layer disposed in the base material and laterally surrounding the contacts. The upper surface of the contact directly contacts the bit line structure. The lower surface of the contact piece is in direct contact with the active area. An insulating layer is between the contacts and the isolation area.

In some embodiments, the spacer and the insulating layer are in direct contact with each other such that an interface exists between the spacer and the insulating layer.

In some embodiments, the cross-sectional shape of the contact is rectangular or inverted trapezoid.

In some embodiments, when the cross-sectional shape of the contact is an inverted trapezoid, the thickness of the insulating layer gradually becomes thinner from the lower part to the upper part.

In some embodiments, the projected area of the contact on the substrate is located within the projected area of the bit line structure on the substrate.

Semiconductor devices and manufacturing methods provided by embodiments of the present disclosure define and protect the contacts during the manufacturing process by forming an insulating layer between the contacts and the substrate, thereby simplifying the manufacturing process and improving the reliability of the semiconductor device. .

The following disclosure provides many different embodiments or examples to demonstrate different features of the present disclosure. Specific examples of each component of the disclosure and their arrangement will be disclosed below to simplify the description of the disclosure. Of course, these specific examples are not intended to limit the disclosure. For example, if the following inventive summary of the present disclosure describes that the first structure is formed on or above the second structure, it means that it includes the embodiment in which the first and second structures are in direct contact, and also includes the embodiment where the first structure and the second structure are in direct contact. Additional structures can also be formed between the first and second structures, and the first and second structures are not in direct contact with each other. In addition, the various examples in this disclosure description may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is for simplicity and clarity, and is not intended to limit the relationship between the various embodiments and/or the described appearance structures.

Furthermore, in order to conveniently describe the relationship between one element or feature and another element or feature in the drawings, spatially related terms can be used, such as "under", "below" and "lower". , "above", "upper" and similar terms. In addition to the orientation depicted in the drawings, spatially relative terms also cover different orientations of devices in use or operation. When the device is turned in a different orientation (for example, rotated 90 degrees or at any other orientation), the spatially relative adjectives used therein will also be interpreted in accordance with the rotated orientation.

In a conventional patterning process, the contacts and the bit line structure may be formed through the same etching process. That is to say, the etching process not only partially removes the conductive material and the insulating covering material to form the bit line structure, but also partially removes the conductive material and the insulating covering material to form the bit line structure. Contacts are removed to modify the topography of the contacts. In this case, since the etching range covers the height of the bit line structure and the height of the contact, the aspect ratio of the etching range is large. As a result, the etching process may require very high operational precision to avoid contact morphology that does not match expectations.

The present disclosure provides a method of manufacturing a semiconductor by forming an insulating layer around a contact. The predetermined topography of the insulating layer is first used to define and protect the topography of the contact. The subsequent patterning process only requires conductive material and the insulating cover material are etched to form the bit line structure. Since the contacts are set first, the aspect ratio of the subsequent etching range can be reduced, so the etching process is relatively simple to operate. In addition, the topography of the contacts can be protected by the insulating layer, thereby improving the reliability of the semiconductor structure.

1 to 7 illustrate cross-sectional views of various steps in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. It should be noted that, unless otherwise specified, when the following embodiments are illustrated or described as a series of operations or events, the order of description of these operations or events should not be limited. For example, some operations or events may be performed in a different order than those disclosed herein, some operations or events may occur simultaneously, some operations or events may not be required, and/or some operations or events may be repeated. Furthermore, the actual manufacturing process may require additional operations before, during, or after each step to completely form the semiconductor device. Therefore, this disclosure may briefly describe some of these additional operations.

Referring to FIG. 1 , in step S1 , a first opening 108 is formed in the base material 100 . The substrate 100 has several active areas 102 and several isolation areas 104, where the isolation areas 104 separate the active areas 102. The first opening 108 is formed to expose a portion of the active area 102 of the substrate 100 .

The isolation layer 106 may be formed on the substrate 100 and cover the upper surface of the active area 102 and the upper surface of the isolation area 104 . In the embodiment shown in FIG. 1 , after the isolation layer 106 is formed on the substrate 100 , the first opening 108 is formed in the substrate 100 and the isolation layer 106 .

The method of forming the first opening 108 may include a photolithography process or an etching process to remove a portion of the substrate 100 . In some embodiments, an anisotropic dry etching process is used to remove portions of the substrate 100 .

Active region 102 of substrate 100 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The active region 102 of the substrate 100 may include an elemental semiconductor, such as germanium. The active region 102 of the substrate 100 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium indium phosphide, or other suitable materials. The active region 102 of the substrate 100 may include a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, the substrate 100 may optionally have a semiconductor-on-insulator (SOI) structure.

The isolation region 104 may be formed through a shallow trench isolation (STI) process. The isolation region 104 of the substrate 100 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation region 104 may be a single-layer structure with one insulating material, a double-layer structure with two insulating materials, or a multi-layer structure with at least three insulating materials. For example, the isolation region 104 may be a three-layer structure including silicon oxide and silicon nitride. In yet another example, the isolation region 104 may include silicon oxide, silicon nitride, and silicon oxynitride.

Please refer to FIG. 2 . In step S2 , the insulating material 200 is conformally deposited in the first opening 108 (please refer to FIG. 1 ) and on the substrate 100 . After deposition, first opening 108 may be reduced to second opening 208. The substrate 100 is completely covered by the insulating material 200 without being exposed. The material of the insulating material 200 may include a dielectric material such as, but not limited to, silicon nitride.

Please refer to Figure 3. In step S3, the insulating material 200 (please refer to Figure 2) is partially removed to form an insulating layer 300. Specifically, the horizontal portion of the insulating material 200 is completely removed while retaining the vertical portion of the insulating material 200 , where the vertical portion of the insulating material 200 may form the insulating layer 300 . By completely removing the horizontal portion of the insulating material 200 , the active area 102 of the substrate 100 is exposed at the bottom of the third opening 308 .

Furthermore, in some embodiments, the removal process may further perform an etch back process on the insulating layer 300 to trim the thickness of the insulating layer 300 . The cross-sectional shape of the third opening 308 can be adjusted by trimming the thickness of the insulating layer 300 . In other words, the insulating layer 300 may define a third opening 308 in the substrate 100 . In the embodiment shown in FIG. 3 , the third opening 308 can be adjusted into a rectangular shape.

The removal process may be anisotropic etching. The removal process may be a dry etching process, in which gas etchants may be used, such as Cl ₂ , HBr, CF ₄ , CHF ₃ , CH ₂ F ₂ , _CH3 F, C ₄ F ₆ , C ₄ F ₈ , BCl ₃ , SF ₆ , H ₂ , NF ₃ , other suitable etching gas sources, or a combination of the above. In some embodiments, the gas etchant is organic to slow down the overall etching rate of the insulating material 200 during the etching process, thereby controlling the thickness of the subsequently formed insulating layer 300 and affecting the cross-sectional shape of the third opening 308 . For example, the gas etchant can be CH ₂ F ₂ , C ₄ F ₆ , C ₄ F ₈ , or similar organic gases.

When the gas etchant is an organic gas etchant, the flow rate of the organic gas etchant can be controlled in the range of 5 sccm to 35 sccm. If the flow rate of the organic gas etchant is greater than the aforementioned upper limit, the overall etching rate of the insulating material 200 in the etching process will be too slow, resulting in reduced manufacturing efficiency. If the flow rate of the organic gas etchant is less than the aforementioned lower limit, the overall etching rate of the insulating material 200 in the etching process will be too fast, and the thickness of the subsequently formed insulating layer 300 cannot be effectively controlled, and the third opening 308 cannot be effectively controlled. cross-sectional shape.

Please refer to FIG. 4 . In step S4 , the contact 400 is formed in the third opening 308 (please refer to FIG. 3 ). That is, the contact 400 may be disposed in the base material 100 . The bottom of the contact piece 400 may directly contact the substrate 100 . The portion of active area 102 that contacts contact 400 may be referred to as source area 102S. The contact 400 may be electrically connected to the source region 102S. After the contact 400 is formed, the insulating layer 300 laterally surrounds the contact 400 and is between the contact 400 and the isolation region 104 .

In some embodiments, forming the contact 400 in the third opening 308 (see FIG. 3 ) may include depositing a conductive material (not shown) in the third opening 308 and filling it beyond the third opening 308 , performing planarization. A chemical mechanical planarization (CMP) process (eg, chemical mechanical planarization, CMP) is performed to remove excess conductive material on the upper surface of the substrate 100 or the upper surface of the isolation layer 106 .

In some further embodiments, the conductive material (not shown) completely fills the third opening 308 , and therefore, the cross-sectional shape of the contact 400 may be substantially the same as the cross-sectional shape of the third opening 308 . In the embodiment shown in FIG. 4 , the cross-sectional shape of the contact 400 is rectangular, but the present disclosure is not limited to this. In other words, the topography of the contact 400 may be determined when trimming the thickness of the insulating layer 300 in step S3.

The material of the contact 400 may include tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), or the like. In some other embodiments, the material of the contact 400 may include polysilicon.

Referring to FIG. 5 , in step S5 , a conductive material 500 and an insulating covering material 502 are formed in sequence, where the conductive material 500 is interposed between the base material 100 and the insulating covering material 502 . Conductive material 500 may electrically connect contact 400 . The conductive material 500 may be at least one of a doped semiconductor, a metal, a conductive metal nitride, and a metal silicide. In some embodiments, the conductive material 500 may have a stacked structure. For example, the conductive material 500 may be a stacked structure composed of doped polysilicon and metal nitride or metal (eg, tungsten, tungsten nitride, and/or titanium nitride).

In some embodiments, insulating cover material 502 may include a dielectric material such as, but not limited to, silicon nitride. The vertical length of the insulating cover material 502 (eg, perpendicular to the direction of the substrate 100 ) may be greater than the vertical length of the conductive material 500 .

Referring to Figure 6, in step S6, the conductive material 500 and the insulating covering material 502 are patterned to form a bit line structure 604 protruding on the substrate 100, wherein the bit line structure 604 may have a conductive layer 600 (from the conductive material 500) and insulating cover layer 602 (from insulating cover material 502).

Bit line structure 604 may be located on and connected to contact 400 . Specifically, contact 400 may be interposed (eg, sandwiched) between bit line structure 604 and active region 102 of substrate 100 . In some embodiments, the upper surface of the contact 400 directly contacts the bit line structure 604 and the lower surface of the contact 400 directly contacts the active area 102 of the substrate 100 . In this way, the bit line structure 604 is electrically connected to the base material 100 through the contacts 400 .

It should be noted that the top cross-sectional area of the formed bit line structure 604 at the intersection with the contact 400 may be equal to or larger than the top cross-sectional area of the upper surface of the contact 400 , so that the contact 400 is completely protected by the bit line structure 604 Covered without being exposed, thereby reducing the possibility of short circuit or leakage. In other words, the projected area of the contact 400 on the substrate 100 may be located within the projected area of the bit line structure 604 on the substrate 100 .

The conductive material 500 and the insulating cover material 502 may be patterned by any suitable method, such as etching processes and photolithography processes. The conductive material 500 and the insulating cover material 502 may be patterned using one or more lithography processes, including dual or multi-patterning processes. Generally speaking, dual patterning or multi-patterning processes combine lithography and self-aligned processes so that the patterns to be created, for example, have better performance than those obtained using a single, direct lithography process. Smaller spacing. For example, in some embodiments, a sacrificial layer is formed over a target layer (eg, conductive material 500 or insulating cover material 502) and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, leaving spacers that can then be used in subsequent patterning processes.

Referring to FIG. 7 , in step S7 , spacers 700 are formed on the side walls of the bit line structure 604 . Specifically, the spacer 700 is disposed on the substrate 100 and extends along the sidewall of the bit line structure 604 . The spacer 700 and the insulating layer 300 are in direct contact with each other, so that an interface exists between the spacer 700 and the insulating layer 300 . The spacer 700 may have a single-layer or multi-layer structure. The material of the spacer 700 may include nitride (eg, silicon nitride (SiN)), oxynitride (eg, silicon oxynitride (SiON)), or the like. In some embodiments, the material of the spacer 700 may be the same as the material of the insulating layer 300 .

In some embodiments, the spacer 700 is a three-layer structure, such as a first layer, a second layer and a third layer formed in sequence, with the second layer sandwiched in between. The second layer can be used as a sacrificial layer and converted into an air gap during subsequent processes. Therefore, the second layer has etching selectivity relative to the first and third layers.

Please refer to FIG. 8 , which is a cross-sectional view of a semiconductor device according to other embodiments of the present disclosure. The semiconductor structure of FIG. 8 is generally similar to the semiconductor structure of FIG. 7 , except that the insulating layer 300A of FIG. 8 has a gradient thickness and the cross-sectional shape of the contact 400A is an inverted trapezoid. Except for the morphology, the relevant description of the insulating layer 300A and the contact 400A may refer to the foregoing description of the insulating layer 300 and the contact 400, and will not be described in detail here.

As mentioned above, the cross-sectional shape of the contact 400A can be adjusted by the insulating layer 300A. Therefore, in the embodiment shown in FIG. 8, the thickness of the insulating layer 300A is gradually thinned from the lower part to the upper part, and the contact is formed. The cross-sectional shape of 400A is an inverted trapezoid, and this disclosure is not limited to this. Any contact (eg, the contact 400 of FIG. 7 or the contact 400A of FIG. 8) that can be adjusted by modifying the topography of the insulating layer (eg, the insulating layer 300 of FIG. 7 or the insulating layer 300A of FIG. 8) The cross-sectional shapes are all within the scope of this disclosure.

Similarly, the top cross-sectional area of the formed bit line structure 604 at the intersection with the contact 400A is equal to or greater than the top cross-sectional area of the upper surface of the contact 400A, so that the contact 400A is completely covered by the bit line structure 604 without being exposed. exposed to reduce the possibility of short circuit or leakage. In other words, the projected area of the contact 400A on the substrate 100 may be located within the projected area of the bit line structure 604 on the substrate 100 .

Various embodiments of the present disclosure provide a method of manufacturing a semiconductor and a semiconductor device by forming an insulating layer around a contact, first defining and protecting the topography of the contact by a predetermined topography of the insulating layer, and then patterning The chemical process only requires etching of the conductive material and the insulating covering material to form the bit line structure. That is to say, since the contacts are defined and protected in advance, the aspect ratio of the etching range can be reduced, making the etching process easier to operate. In addition, the topography of the contacts can be protected by the insulating layer, thereby improving the reliability of the semiconductor structure.

The above has briefly described the features of several embodiments of the present disclosure, making it easier for those with ordinary knowledge in the art to understand the present disclosure. Anyone with ordinary skill in the art should understand that this description can be easily used as a basis for modification or design of other structures or processes so as to achieve the same purposes and/or obtain the same advantages as the embodiments of the present invention. Anyone with ordinary skill in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of the present invention, and that changes, substitutions and modifications can be made without departing from the spirit and scope of the disclosure. .

100:Substrate 102:Active area 102S: Source region 104:Isolation area 106:Isolation layer 108:First opening 200:Insulating materials 208:Second opening 300: Insulation layer 300A: Insulation layer 308:The third opening 400:Contacts 400A:Contacts 500: Conductive materials 502: Insulating covering materials 600: Conductive layer 602: Insulation covering 604:Bit line structure 700: Spacer S1, S2, S3, S4, S5, S6, S7: Steps

When reading the following implementation methods, please read the accompanying drawings to clearly understand the viewpoints of this disclosure. It should be noted that, consistent with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of discussion. Figures 1, 2, 3, 4, 5, 6 and 7 illustrate cross-sectional views of various steps in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 8 illustrates a cross-sectional view of a semiconductor device according to other embodiments of the present disclosure.

Domestic storage information (please note in order of storage institution, date, and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:Substrate 102:Active area 104:Isolation area 106:Isolation layer 300: Insulation layer 400:Contacts 600: Conductive layer 602: Insulation covering 604:Bit line structure 700: Spacer S7: Steps

Claims (9)

A method of manufacturing a semiconductor device, including: forming a first opening in a substrate; conformally depositing an insulating material in the first opening and on the substrate; partially removing the insulating material to form an insulating layer and Defining a second opening in the base material, wherein the base material is exposed to the bottom of the second opening; forming a contact piece in the second opening, wherein the bottom of the contact piece directly contacts the base material; forming A bit line structure is on the substrate, wherein the bit line structure is located on the contact and connected to the contact; and a spacer is formed on a side wall of the bit line structure. The method of manufacturing a semiconductor device as claimed in claim 1, wherein partially removing the insulating material includes removing a horizontal portion of the insulating material. The method of manufacturing a semiconductor device as claimed in claim 2, wherein partially removing the insulating material further includes trimming the thickness of the insulating layer to define a cross-sectional shape of the second opening. The method of manufacturing a semiconductor device as claimed in claim 3, wherein forming the contact in the second opening includes completely filling the second opening with a conductive material so that the contact has the cross-sectional shape. The method of manufacturing a semiconductor device as claimed in claim 1, wherein locally removing the insulating material includes using a gas etchant, wherein the gas etchant is organic, and the flow rate of the gas etchant is controlled between 5 sccm and 35 sccm. A semiconductor device, including: a base material, including: an active area; and an isolation area; a bit line structure disposed on the base material and protruding from the base material; a spacer disposed on the base material on and extending along the sidewall of the bit line structure; a contact member is disposed in the substrate and between the bit line structure and the active area, wherein an upper surface of the contact member is in direct contact The bit line structure, and the lower surface of the contact directly contacts the active area; and an insulating layer is disposed in the substrate, laterally surrounding the contact and between the contact and the isolation area, wherein The spacer and the insulating layer are in direct contact with each other, so that there is an interface between the spacer and the insulating layer, which is flush with the contact and directly contacts the upper surface of the bit line structure. The semiconductor device according to claim 6, wherein the cross-sectional shape of the contact is a rectangle or an inverted trapezoid. The semiconductor device of claim 7, wherein when the cross-sectional shape of the contact is an inverted trapezoid, the thickness of the insulating layer gradually becomes thinner from the lower part to the upper part. The semiconductor device of claim 6, wherein the projected area of the contact on the substrate is located within the projected area of the bit line structure on the substrate.

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