CN114093807A

CN114093807A - Semiconductor device and method of forming the same

Info

Publication number: CN114093807A
Application number: CN202010867954.8A
Authority: CN
Inventors: 王楠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-08-25
Filing date: 2020-08-25
Publication date: 2022-02-25

Abstract

A semiconductor device and a method of forming the same, including a substrate; the fin part is positioned on the substrate; the isolation structure is positioned on the substrate, covers partial side walls of the fin parts, and has the top surface lower than the top surface of the fin parts; the grid structure is positioned on the substrate and spans the fin part; the conducting layers are positioned on two sides of the grid structure; an initial first hard mask layer located on the top surface of the end of the gate structure; the second hard mask layer is positioned on the top surfaces of the conducting layers on the two sides of the center of the grid structure; a dielectric layer on the initial first hard mask layer and the second hard mask layer; the first through hole is positioned in the dielectric layer, and the bottom of the first through hole is exposed out of the central top surface of the gate structure; the second through hole is positioned in the dielectric layer, and the bottom of the second through hole is exposed out of the top surface of the conducting layer on one side of the end part of the grid structure; the first contact layer is positioned in the first through hole; the second contact layer is positioned in the second through hole; the semiconductor device of the invention has good performance.

Description

Semiconductor device and method of forming the same

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.

Background

Scaling of feature sizes in integrated circuits has been a driving force behind the growing semiconductor industry over the last decades. Scaling to smaller and smaller feature sizes enables increased density of functional units on the limited real estate of a semiconductor chip. For example, reducing transistor size allows for an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the urging for larger capacities is not without problems. The necessity to optimize the performance of each device becomes increasingly significant.

In the fabrication of integrated circuit devices, such as multi-gate transistors, are becoming more common as device dimensions continue to shrink. In conventional processes, multi-gate transistors are typically fabricated on a silicon substrate or a silicon-on-insulator substrate.

Scaling down the size of multi-gate transistors is not without its consequences, as the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints of the photolithographic process used to pattern the building blocks become difficult to overcome. The electrical performance of the prior art multi-gate transistors is still to be improved.

Disclosure of Invention

The invention provides a semiconductor device and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor device.

To solve the above problems, the present invention provides a semiconductor device including a substrate; a fin portion on the substrate; the isolation structure is positioned on the substrate, covers partial side walls of the fin part, and has a top surface lower than that of the fin part; the grid structure is positioned on the substrate and stretches across the fin part; the conducting layers are positioned on two sides of the grid structure; an initial first hard mask layer located on a top surface of an end of the gate structure; the second hard mask layer is positioned on the top surfaces of the conducting layers on two sides of the center of the grid structure; a dielectric layer on the initial first hard mask layer and the second hard mask layer; the first through hole is positioned in the dielectric layer, and the bottom of the first through hole is exposed out of the central top surface of the grid structure; the second through hole is positioned in the dielectric layer, and the bottom of the second through hole is exposed out of the top surface of the conducting layer on one side of the end part of the grid structure; the first contact layer is positioned in the first through hole; and the second contact layer is positioned in the second through hole.

The present invention also provides another semiconductor device including: a substrate; a fin portion on the substrate; the isolation structure is positioned on the substrate, covers partial side walls of the fin part, and has a top surface lower than that of the fin part; the grid structure is positioned on the substrate and stretches across the fin part; the conducting layers are positioned on two sides of the grid structure; the first hard mask layer is positioned on the top surface of the end part of the grid structure; an initial second hard mask layer located on top surfaces of the conductive layer on both sides of a center of the gate structure and on a top surface of the conductive layer on one side of an end of the gate structure; a dielectric layer on the first hard mask layer and the initial second hard mask layer; the first through hole is positioned in the dielectric layer, and the bottom of the first through hole is exposed out of the central top surface of the grid structure; the second through hole is positioned in the dielectric layer, and the bottom of the second through hole is exposed out of the top surface of the conducting layer on the other side of the end part of the grid structure; the first contact layer is positioned in the first through hole; and the second contact layer is positioned in the second through hole.

Optionally, the center of the gate structure is located at a center line of the gate structure, or the center of the gate structure is located at a distance of 0nm to 5nm from the center line of the gate structure, where the center line is a symmetric center line of the gate structure along a direction parallel to the extending direction of the fin portion.

Optionally, the dielectric constant of the dielectric layer is less than 2.5.

Optionally, a top surface of the gate structure is not flush with a top surface of the conductive layer.

Correspondingly, the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate is provided with a grid structure and conducting layers positioned on two sides of the grid structure; forming a dielectric layer on the gate structure and the conductive layer; and etching the dielectric layer, and forming a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole is exposed out of the top surface of the center of the grid structure, and the bottom of the second through hole is exposed out of the top surface of the conductive layer on one side of the end part of the grid structure.

Optionally, a second contact layer is formed in the second via.

Optionally, a first contact layer is formed in the first via hole.

Optionally, the dielectric constant of the dielectric layer is less than 2.5.

Optionally, before forming a dielectric layer on the first gate structure and the conductive layer, the method further includes: and forming a second hard mask layer on the tops of the conducting layers on two sides of the center of the gate structure.

Optionally, the method further includes: and forming a first hard mask layer on the top of the end part of the gate structure.

Optionally, the step of forming the first hard mask layer and the second hard mask layer includes: forming an initial first hard mask layer on the gate structure, and forming an initial second hard mask layer on the conductive layer; forming a patterning layer on the initial first hard mask layer and the initial second hard mask layer, wherein the patterning layer is provided with an opening, and the opening exposes the initial first hard mask layer on the top of the center of the gate structure and the initial second hard mask layers positioned on two sides of the center of the gate structure; or the opening exposes the initial second hard mask layer on one side of the end part of the grid structure and the initial first hard mask layer on the end part of the grid structure.

Optionally, when the initial first hard mask layer at the top of the center of the gate structure and the initial second hard mask layers at the two sides of the center of the gate structure are exposed through the opening, the method further includes: etching and removing the opening to expose the top surface of the initial first hard mask layer until the central top surface of the gate structure is exposed; and forming a first sacrificial layer on the top surface of the exposed center contact, wherein the first sacrificial layer covers the top surfaces of the initial second hard mask layers positioned at two sides of the center of the gate structure.

Optionally, after the first sacrificial layer is formed, the method further includes: removing the initial second hard mask layers on two sides of the end part of the grid structure until the top surfaces of the conducting layers on two sides of the end part of the grid structure are exposed, and forming second hard mask layers on the conducting layers on two sides of the center of the grid structure; and removing the first sacrificial layer.

Optionally, when the opening exposes the initial second hard mask layer on one side of the end of the gate structure and the initial first hard mask layer on the end of the gate structure, the method further includes: etching and removing the initial second hard mask layer exposed by the opening until the top surface of the conducting layer is exposed; and forming a second sacrificial layer on the top surface of the exposed conducting layer, wherein the second sacrificial layer covers the initial first hard mask layer positioned on the top of the end part of the grid structure.

Optionally, after the second sacrificial layer is formed, the method further includes: removing the initial first hard mask layer at the top of the center of the grid structure until the surface of the top of the center of the grid structure is exposed, and forming a first hard mask layer at the top of the end part of the grid structure; and removing the second sacrificial layer.

Optionally, the base includes a substrate, a fin portion and an isolation structure on the substrate, where the isolation structure covers a portion of a sidewall of the fin portion and a top surface of the isolation structure is lower than a top surface of the fin portion.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the semiconductor device, the first through hole and the second through hole are both positioned in the dielectric layer, the bottom of the first through hole is exposed out of the top surface of the center of the grid structure, the bottom of the second through hole is exposed out of the top surface of the conducting layer on one side of the end part of the grid structure, the first contact layer is formed in the first through hole, namely the center of the grid structure, and the second contact layer is formed in the second through hole, namely the end part of the grid structure; therefore, the method can be realized by adopting one photomask layer in the process of forming the first through hole and the second through hole, avoids using the photomask layer for multiple times, reduces the difficulty of process formation and solves the problem of inaccurate alignment of multiple photomasks; meanwhile, the second hard mask layer is only positioned on the top surfaces of the conducting layers at two sides of the center of the grid structure, the traditional structure without the second hard mask layer except the conducting layer where the second contact layer is formed is replaced, and the volume of the second hard mask layer is reduced, so that the parasitic capacitance between the metal layer 1(M1) formed subsequently and the conducting layer can be reduced, and the electrical performance of the formed semiconductor device is improved.

In the forming method, after the dielectric layer is formed on the grid structure and the conducting layer, the dielectric layer is etched, and the first through hole and the second through hole are formed in the dielectric layer, wherein the bottom of the first through hole is exposed out of the top surface of the center of the grid structure, and the bottom of the second through hole is exposed out of the top surface of the conducting layer on one side of the end part of the grid structure.

Drawings

FIGS. 1-3 are cross-sectional views of a semiconductor structure in one embodiment;

fig. 4 to 27 are schematic structural views illustrating a process of forming a semiconductor device according to a first embodiment of the present invention;

fig. 28 to 41 are schematic structural views illustrating a process of forming a semiconductor device according to a second embodiment of the present invention.

Detailed Description

The electrical performance of the MOSFET of the COAG structure in the prior art still remains to be improved. The following detailed description will be made in conjunction with the accompanying drawings.

Fig. 1-3 are cross-sectional views of a semiconductor structure in one embodiment.

FIG. 1 is a top view of FIG. 2; fig. 2 is a sectional view of fig. 1 taken along line a-a, and fig. 3 is a sectional view of fig. 1 taken along line B-B.

Referring to fig. 1 to 3, a substrate 100; a fin 101 on the substrate 100; the first gate structure crosses the fin portion 101 and comprises a gate structure 103 and a sub-gate structure 102, the sub-gate structures 102 and the gate structure 103 are distributed in parallel, and the gate structure 103 is located between the adjacent sub-gate structures 102; the gate structure 103 includes end portions I and a center II, the end portions I being adjacent to the center II, the center I being located between the adjacent end portions I; the side wall 104 is positioned on the side wall of the grid structure; the source-drain doping layer 105 is positioned in the fin portion 101 on two sides of the gate structure 103; the conducting layer 106 is positioned on the top of the source drain doping layer 105; a first hard mask layer 107 on a top surface of the gate structure; a second hard mask layer 108 on top of the conductive layer 106; a dielectric layer 109 on the first hard mask layer 107 and the second hard mask layer 108; the first contact layer 110 is positioned on top of the center II of the gate structure 103, and ensures that the first contact layer 110 is formed on the gate structure of the source region (active) to form the MOSFET of the COAG structure, and the first contact layer 110 is used for realizing the electrical connection between the gate structure and the metal layer 1(M1) formed later; and a second contact layer 111, located in the second hard mask layer 108 on the side of the end portion I of the gate structure and on the top of the conductive layer 106, for electrically connecting the conductive layer and a subsequently formed metal layer 1 (M1).

The inventor finds that, in the above embodiment, before forming the first contact layer 110 and the second contact layer 111, a first through hole needs to be formed on the top of the center II of the gate structure 103, and a second through hole needs to be formed on the top of the conductive layer 106 on the side of the end I of the gate structure, so as to provide a space for forming the first contact layer 110 and the second contact layer 111, but in the process of forming the first through hole and the second through hole, multiple photomasks are needed to implement, which has a problem of photomask coverage, and is easy to generate a pattern misalignment phenomenon, thereby increasing the difficulty of the process; moreover, when the metal layer 1(M1) is formed subsequently, the parasitic capacitance between the conductive layer and the metal layer 1(M1) and the parasitic capacitance between the gate structure and the metal layer 1(M1) are too large, which affects the electrical performance and the performance of the semiconductor device.

The inventor researches and discovers that in order to overcome the problems, in the invention, after a dielectric layer is formed on a gate structure and a conductive layer, the dielectric layer is etched, and a first through hole and a second through hole are formed in the dielectric layer, wherein the bottom of the first through hole is exposed out of the top surface of the center of the gate structure, and the bottom of the second through hole is exposed out of the top surface of the conductive layer on one side of the end part of the gate structure.

The inventors also found that a second hard mask layer is formed on the top of the conductive layer on both sides of the center of the gate structure, and no second hard mask layer is formed on the top of the conductive layer on both sides of the end of the gate structure, so that after the metal layer 1(M1) is formed subsequently, no second hard mask layer is formed between the metal layer 1(M1) and the conductive layer, thereby reducing the parasitic capacitance between the metal layer 1(M1) and the conductive layer, and enhancing the electrical performance of the semiconductor device.

Similarly, the first hard mask layer is formed at the top of the end part of the gate structure, and the first hard mask layer is not formed at the top of the center of the gate structure, so that after the metal layer 1(M1) is formed at the center, the first hard mask layer is not formed between the metal layer 1(M1) and the gate structure, and therefore the parasitic capacitance between the metal layer 1(M1) and the gate structure is reduced, and the electrical performance of the semiconductor device is enhanced.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

First embodiment

Fig. 4 to 27 are schematic structural diagrams of a process of forming a semiconductor device according to a first embodiment of the present invention.

Referring to fig. 4, a substrate 200 is provided.

In this embodiment, the base 200 includes a substrate 201 and a plurality of fins 202 located on the substrate 201 in a discrete arrangement, where the fins 202 extend along a second direction X.

In other embodiments, the fin 202 may not be formed on the substrate 201.

In this embodiment, the substrate 201 is made of monocrystalline silicon.

In other embodiments, the substrate 201 may also be polysilicon or amorphous silicon. The substrate 201 may also be made of germanium, silicon germanium, gallium arsenide, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or other semiconductor materials.

In the present embodiment, the material of the fin portion 202 is silicon; in other embodiments, the material of the fin 202 may also be a semiconductor material such as silicon germanium.

In this embodiment, the method of forming the fin 202 includes: forming a fin material film (not shown) on the substrate 201; forming a patterned layer (not shown) on the fin material film; and etching the fin material film by using the patterned layer as a mask until the surface of the substrate 201 is exposed to form a fin 202.

In this embodiment, an isolation structure 203 is further formed on the substrate 201, and the isolation structure 203 covers a portion of the sidewall of the fin 202.

In this embodiment, the isolation structure 203 is made of silicon nitride.

In other embodiments, the material of the isolation structure 203 may further include one or more of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.

In this embodiment, the isolation structure 203 functions to form electrical isolation.

The method of forming the isolation structure 203 comprises: forming an isolation structure film (not shown) covering the fin structure 202 on the substrate 201; and etching back the isolation structure film to form the isolation structure 203.

The process for forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. The isolation structure film is formed by adopting a fluid chemical vapor deposition process, so that the filling performance of the isolation structure film is better.

The steps of the fluid chemical vapor deposition process for forming the isolation structure film comprise: forming an isolated fluid layer on the substrate 201; and carrying out water vapor annealing to enable the isolation fluid layer to form an isolation structure film.

The parameters of the water vapor annealing comprise: the adopted gas comprises oxygen, ozone and gaseous water, and the annealing temperature is 350-750 ℃.

Referring to fig. 5 and 6, fig. 5 is a top view of fig. 6, fig. 6 is a cross-sectional view of fig. 5 taken along line a-a, a dummy gate structure is formed on the substrate 200, the dummy gate structure includes a dummy gate structure 204 and a sub-dummy gate structure 205, and the dummy gate structure 204 is located between adjacent sub-dummy gate structures 205.

In the present embodiment, a dummy gate structure is formed on the substrate 201 across the fin 202.

In this embodiment, the dummy gate structure includes: a dummy gate dielectric layer 206 on the fin 202, a dummy gate layer 207 on the dummy gate dielectric layer 206, and a protection layer 208 on the dummy gate layer 207.

In the present embodiment, the dummy gate structure 204 includes an end portion I and a center portion II.

In this embodiment, the material of the dummy gate dielectric layer 206 is silicon oxide.

In this embodiment, the material of the dummy gate layer 207 is polysilicon.

In this embodiment, the material of the protection layer 208 includes: silicon nitride or silicon oxide; in other embodiments, the material of the protection layer 208 may also be one or more of silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.

In this embodiment, the protection layer 208 protects the dummy gate layer 207 during the subsequent formation of the source-drain doping layer, and serves as a stop layer for the subsequent planarization of the dielectric layer.

In this embodiment, a sidewall spacer 209 is further formed on the sidewalls of the dummy gate layer 207 and the protection layer 208.

In this embodiment, the sidewall 209 is made of silicon oxide; in other embodiments, the material of the sidewall spacers 209 may also be one or more combinations of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.

The side wall 209 is used for defining the position of a source-drain doped layer formed subsequently, and the side wall 209 is used for protecting the side wall of the pseudo gate layer 207, so that the phenomenon that a subsequently formed gate layer has appearance defects and affects the electrical performance of a semiconductor structure is avoided.

The forming method of the side wall 209 comprises the following steps: forming a side wall material layer (not shown) on the top surface of the dummy gate dielectric layer 206, the side wall of the dummy gate layer 207, the side wall of the protective layer 208 and the top surface; the spacer material layer is etched back until the protective layer 208 and the top surface of the fin 202 are exposed, so as to form the spacers 209.

The forming process of the side wall material layer is one or combination of a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

The process for back etching the side wall material layer is anisotropic dry etching, and the process parameters of the dry etching are as follows: using gases containing fluorine (e.g. CH)₃F、CH₂F₂Or CHF₃) Argon and oxygen, the etching power is 200W-400W, the pressure of the etching cavity is 30 mTorr-200 mTorr, and the etching temperature is 40 ℃ to 60 ℃.

Referring to fig. 5, in the present embodiment, the dummy gate structure is only formed in the i-region of the substrate, because the first contact layer is formed on the top of the center of the gate structure between the source and drain doping layers in the subsequent process of forming the first contact layer on the gate structure, so that the length of the finally formed gate structure is shortened, the integration level of the semiconductor device is improved, and preparation is made for manufacturing the semiconductor device with higher integration level.

Referring to fig. 7, the view directions of fig. 7 and fig. 6 are the same, and the source-drain doping layers 210 are formed in the substrate 200 at two sides of the dummy gate structure 204.

In this embodiment, the fin portion 202 on both sides of the dummy gate structure 204 is etched, and the source-drain doping layer 210 is formed in the fin portion 202.

The source drain doped layer 210 has source drain doped ions.

The process for forming the source-drain doping layer 210 includes an epitaxial growth process; the process of doping the source drain dopant ions in the source drain doped layer 210 is an in-situ doping process.

When the semiconductor device is a P-type device, the source-drain doping layer 210 is made of the following materials: silicon, germanium, or silicon germanium; the source and drain doped ions are P-type ions including boron ions and BF^2-Ions or indium ions; when the semiconductor device is an N-type device, the source-drain doping layer 210 is made of the following materials: silicon, gallium arsenide, or indium gallium arsenide; the source and drain doped ions are N-type ions and comprise phosphorus ions or arsenic ions.

In this embodiment, the semiconductor device is a P-type device, the source-drain doped layer 210 is made of silicon, and the source-drain doped ions are boron ions. In other embodiments, the semiconductor device is an N-type device, the source-drain doped layer 210 is made of silicon, and the source-drain doped ions are phosphorus ions.

In this embodiment, the process of etching the fin portion 202 is an anisotropic dry etching process, and the parameters of the dry etching process include: the adopted etching gas comprises HBr and Ar, wherein the gas flow of HBr is 10 sccm-1000 sccm, and the gas flow of Ar is 10 sccm-1000 sccm.

Referring to fig. 8, an interlayer dielectric layer 211 is formed on the substrate 200 and the source-drain doping layer 210, and the interlayer dielectric layer 211 exposes the top surface of the dummy gate structure.

In this embodiment, the interlayer dielectric layer 211 is formed on the substrate 201 and the source-drain doping layer 210, and the interlayer dielectric layer 211 covers the sidewall of the dummy gate structure and exposes the top surface of the protection layer 208.

In this embodiment, the method for forming the interlayer dielectric layer 211 includes: forming an interlayer dielectric layer material layer on the substrate 201 and the source-drain doping layer 210, wherein the interlayer dielectric layer material layer covers the top surface of the dummy gate structure, and the interlayer dielectric layer material layer is flattened until the top surface of the protection layer 208 is exposed to form the interlayer dielectric layer 211.

In this embodiment, the interlayer dielectric layer 211 is made of silicon oxide; in other embodiments, the material of the interlayer dielectric layer 211 may also be a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

In this embodiment, the forming process of the interlayer dielectric layer 211 is a chemical vapor deposition process; in other embodiments, the interlayer dielectric layer 211 may be formed by one or more of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

Referring to fig. 9, the dummy gate structure is etched away until the surface of the substrate 200 is exposed, thereby forming a gate opening 212.

In this embodiment, the protective layer 208, the dummy gate layer 207 and the dummy gate dielectric layer 206 are removed, and the gate opening 212 is formed between the sidewalls 209.

In this embodiment, the process of removing the dummy gate structure is a wet etching process, and specifically, tetramethylammonium hydroxide (TMAH) is used as an etching solution.

In other embodiments, the process of removing the dummy gate structure may also be a dry etching process.

Referring to fig. 10, a gate structure is formed in the gate opening 212, and a top surface of the gate structure is lower than a top surface of the interlayer dielectric layer 211.

In this embodiment, the gate structure includes a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.

In this embodiment, the material of the gate dielectric layer includes a high-K dielectric material, such as: oxide-Al₂O₃，HfO₂，Ta₂O₅，TiO₂，ZrO₂And the like.

In other embodiments, the material of the gate dielectric layer may further include other dielectric materials with a dielectric constant higher than 3.9.

In this embodiment, the material of the gate layer is a metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.

In this embodiment, the method for forming the gate structure includes: forming the gate dielectric layer on the sidewall and the bottom of the gate opening 212, forming an initial gate material layer on the gate dielectric layer, and planarizing the initial gate material layer until the top surface of the gate material layer and the top of the interlayer dielectric layer 211 are lower than each other, thereby forming the gate structure.

In this embodiment, the gate structure fills approximately two-thirds of the gate opening 212, and the remaining space provides space for a subsequent formation of a first hard mask layer on the top surface of the gate structure.

In this embodiment, after removing the dummy gate structure, a gate structure is formed, a gate structure 213 is formed in a region corresponding to the dummy gate structure 204, and a sub-gate structure 214 is formed in a region corresponding to the sub-dummy gate structure 205, where the gate structure 213 includes an end I and a center II.

The center II of the gate structure 213 is located at a center line of the gate structure 213, or the center II of the gate structure 213 is located at a distance of 0nm to 5nm from the center line of the gate structure 213, which is a symmetric center line along the gate structure 213 in a direction parallel to the extending direction of the fin 201.

Referring to fig. 11, an initial first hard mask layer 215 is formed on the gate structure 213.

In this embodiment, an initial first hard mask layer 215 is formed on the top surfaces of the gate structure 213 and the sub-gate structure 214, and the top surface of the initial first hard mask layer 215 is flush with the top surface of the interlayer dielectric layer 211.

In the present embodiment, the material of the initial first hard mask layer 215 is silicon nitride.

In other embodiments, the material of the initial first hard mask layer 215 may also be one or more combinations of silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.

In this embodiment, the step of forming the initial first hard mask layer 215 includes: an initial first hard mask layer material is formed on the gate structure and the interlayer dielectric layer 211, the initial first hard mask layer material is planarized until the top surface of the interlayer dielectric layer 211 is exposed, and an initial first hard mask layer 215 is formed on the top surface of the gate structure 213.

In the present embodiment, the process of forming the initial first hard mask layer 215 is a chemical vapor deposition process; in other embodiments, the process of forming the initial first hard mask layer 215 may also be a physical vapor deposition process or an atomic layer deposition process.

Referring to fig. 12, the interlayer dielectric layer 211 is removed until the surface of the source-drain doping layer 210 is exposed, and a contact hole 216 is formed.

In this embodiment, the contact hole 216 provides space for the subsequent formation of a conductive layer and an initial second hard mask layer.

In this embodiment, the process of forming the contact hole 216 is a wet etching process; in other embodiments, the contact hole 216 may be formed by a dry etching process.

Referring to fig. 13, a conductive layer 217 is formed within the contact hole 216, an initial second hard mask layer 218 is formed on top of the conductive layer 217, and a top surface of the initial second hard mask layer 218 is flush with a top surface of the initial first hard mask layer 215.

In this embodiment, the material of the conductive layer 217 is a metal, including copper, tungsten, or aluminum.

In the present embodiment, the process of forming the conductive layer 217 includes a physical vapor deposition process or an electroplating process.

In this embodiment, the conductive layer 217 is used for electrically connecting the source-drain doped layer 210 to the outside.

In this embodiment, the top surface of the gate structure 213 is not flush with the top surface of the conductive layer 217.

Referring to fig. 14 to 15, fig. 15 is a top view of fig. 14, fig. 14 is a cross-sectional view of fig. 15 taken along line a-a, a patterned layer 219 is formed on the initial first hard mask layer 215 and the initial second hard mask layer 218, the patterned layer 219 having an opening 220, the opening 220 exposing the initial first hard mask layer 215 on top of the center II of the gate structure 213 and the initial second hard mask layer 218 on both sides of the center II of the gate structure 213.

In this embodiment, the material of the patterning layer 219 is photoresist, and krypton fluoride (KrF) is used; in other embodiments, argon fluoride (ArF) may also be employed.

In this embodiment, the size of the opening 220 is larger than that of the first via hole formed subsequently by about 3nm to 10nm, so that the patterning layer 219 can be ensured to expose the initial first hard mask layer 218 on the conductive layer 217 on both sides of the first contact layer formed subsequently, and the first sacrificial layer formed subsequently can be ensured to cover the exposed initial first hard mask layer.

Referring to fig. 16, the view direction of fig. 16 is the same as the view direction of fig. 14, and the opening 220 is etched away to expose the initial first hard mask layer 215 until the top surface of the center II of the gate structure 213 is exposed.

In this embodiment, the top surface of the initial first hard mask layer 215 is exposed by removing the opening 220 by etching, and the top surface of the center II of the gate structure 213 is exposed in order to form a first contact layer on the top surface of the center II of the gate structure 213, so as to ensure that the first contact layer is formed on the top surface of the gate structure in the active area (active), thereby increasing the density of the formed gate structure and improving the integration level of the semiconductor device.

In this embodiment, the process of removing the opening 220 to expose the initial first hard mask layer 215 is a dry etching process; in other embodiments, a wet etching process may be used to remove the opening 220 to expose the initial first hard mask layer 215.

In the present embodiment, the reason why the dry etching process is adopted is that: the dry etching has a high etching directionality, and the etching rate in the longitudinal direction is much greater than that in the lateral direction, so that it is ensured that the surrounding initial second hard mask layer 218 is not damaged during the process of removing the opening 220 to expose the initial first hard mask layer 215.

Referring to fig. 17, a first sacrificial layer 221 is formed on the top surface of the gate structure 213 exposing the center II, and the first sacrificial layer 221 covers the top surfaces of the initial second hard mask layers 218 on both sides of the center II of the gate structure 213.

In this embodiment, the material of the first sacrificial layer 221 is silicon germanium; in other embodiments, the material of the first sacrificial layer 221 may also be amorphous silicon, amorphous carbon, amorphous germanium, photoresist, or other organic filling layer.

In this embodiment, the top surfaces of the initial second hard mask layers 218 on both sides of the center II of the gate structure 213 are covered by the first sacrificial layer 221, so as to protect the initial second hard mask layers 218 on both sides of the center II of the gate structure 213, so that the initial second hard mask layers 218 on both sides of the center II of the gate structure 213 are not damaged in the subsequent processes.

In this embodiment, after the first sacrificial layer 221 is formed, the patterning layer 219 is removed.

In this embodiment, the process of removing the patterning layer 219 is a wet etching process; in other embodiments, ashing, etc. may be used to remove the patterned layer 219.

Referring to fig. 18 to 19, fig. 19 is a top view of fig. 18, and fig. 18 is a cross-sectional view of fig. 19 taken along line B-B, wherein the initial second hard mask layer 218 on both sides of the end portion I of the gate structure 213 is removed until the top surface of the conductive layer 217 on both sides of the end portion I of the gate structure 213 is exposed.

In this embodiment, the initial second hard mask layer 218 on both sides of the end portion I of the gate structure 213 is removed by a dry etching process.

In other embodiments, a wet etching process may be further used to remove the initial second hard mask layer 218 on both sides of the end portion I of the gate structure 213.

In this embodiment, the purpose of removing the initial second hard mask layer 218 on both sides of the end I of the gate structure 213 and only remaining the initial second hard mask layer 218 on both sides of the center II of the gate structure 213 is to reduce the volume of the high-k material on the conductive layer 217 on both sides of the end I of the gate structure 213, so that when the metal layer 1(M1) is formed subsequently, the parasitic capacitance generated between the conductive layer 217 and the metal layer 1(M1) can be reduced, thereby improving the electrical performance of the formed semiconductor device.

Referring to fig. 20, in the same view direction as fig. 17 in fig. 20, the first sacrificial layer 221 is removed, and a second hard mask layer 222 is formed on the conductive layer at two sides of the center II of the gate structure 213.

In the present embodiment, the initial second hard mask layer 218 on both sides of the end I of the gate structure 213 is removed (refer to fig. 18), only the initial second hard mask layer 218 on both sides of the center II of the gate structure 213 remains, and the remaining initial second hard mask layer 218 on both sides of the center II of the gate structure 213 is named as a second hard mask layer 222, that is, a second hard mask layer 222 is formed on the conductive layer 217 on both sides of the center II of the gate structure 213.

In this embodiment, since the second hard mask layer 222 is formed only on the conductive layer 217 on both sides of the center II of the gate structure 213, and the second hard mask layer 222 is not formed on the conductive layer 217 on both sides of the end I of the gate structure 213, the volume of the second hard mask layer 222 is greatly reduced, so that when the metal layer M1 is formed subsequently, the parasitic capacitance between the metal layer M1 and the conductive ash layer 217 is greatly reduced, thereby facilitating to improve the performance of the formed semiconductor device.

Referring to fig. 21 to 23, fig. 23 is a top view of fig. 21 and 22, fig. 21 is a cross-sectional view taken along line a-a of fig. 23, and fig. 22 is a cross-sectional view taken along line B-B of fig. 23. a dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217.

In this embodiment, the dielectric constant of the dielectric layer 223 is less than 2.5.

In this embodiment, the dielectric layer 223 covers the surfaces of the second hard mask layer 222 on two sides of the center II of the gate structure 213, the surface of the initial first hard mask layer 215 on the secondary gate structure 214, the surface of the initial first hard mask layer 215 on the end I of the gate structure 213, and the top surface of the conductive layer 217 on two sides of the end I of the gate structure 213.

In this embodiment, the dielectric constant of the dielectric layer 223 is smaller than that of the second hard mask layer 222, which is to ensure that when the metal layer 1(M1) is formed subsequently, the dielectric constant of the material between the metal layer 1(M1) and the conductive layer 217 is reduced, so that the parasitic capacitance between the metal layer 1(M1) and the conductive layer 217 can be reduced, and the electrical performance of the formed semiconductor device can be improved.

Referring to fig. 24 and 25, the view directions of fig. 24 and 21 are the same, and the view directions of fig. 25 and 22 are the same, the dielectric layer 223 is etched, a first through hole 224 and a second through hole 225 are formed in the dielectric layer 223, the bottom of the first through hole 224 is exposed out of the top surface of the center II of the gate structure 213, and the bottom of the second through hole 225 is exposed out of the top surface of the conductive layer 217 on one side of the end I of the gate structure 213.

In this embodiment, the process of etching the dielectric layer 223 is a dry etching process; in other embodiments, the dielectric layer 223 may be etched by a wet etching process.

In this embodiment, the first through hole 224 provides a space for forming a first contact layer; the second contact hole 225 provides a space for forming a second contact layer.

In this embodiment, the step of forming the first through hole 224 and the second through hole 225 includes: a photomask (mask) layer is formed on the dielectric layer 223, the photomask (mask) layer is exposed, a first through hole 224 and a second through hole 225 are formed in the dielectric layer 223, and in the process of forming the first through hole 224 and the second through hole 225, the formation of the first through hole 224 and the second through hole 225 can be simultaneously realized only by adopting the photomask layer once, so that the process of forming the photomask layer for multiple times in the traditional process is replaced, the problem of inaccurate alignment of multiple photomasks is avoided, the problem of photomask coverage (overlay) is solved, and the process flow is simplified.

Referring to fig. 26 to 27, the view directions of fig. 26 and 24 are the same, and the view directions of fig. 27 and 25 are the same, a first contact layer 226 is formed in the first via 224, and a second contact layer 227 is formed in the second via 225.

In this embodiment, the first contact layer 226 is located on the top surface of the center II of the gate structure 213 for electrically connecting the gate structure 213 with the outside, and the material of the first contact layer 226 is a metal material, and the metal material includes tungsten, copper, aluminum, titanium, nickel, cobalt, or the like.

In this embodiment, the second contact layer 227 is located on the top surface of the conductive layer 217 on the side of the end portion I of the gate structure 213, and is used for electrically connecting the conductive layer 217 with the outside, and the material of the second contact layer 227 is a metal material, and the metal material includes tungsten, copper, aluminum, titanium, nickel, cobalt, or the like.

In this embodiment, referring to fig. 23, the dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217, so that in the process of forming the first via 224 and the second via 225, only one mask layer is needed to form the first via 224 and the second via 225 at the same time, and multiple mask layers are not needed to form the first via 224 and the second via 225, thereby avoiding the problem of misalignment of multiple mask layers, reducing the process difficulty of forming the first via 224 and the second via 225, and improving the accuracy of forming the first via 224 and the second via 225.

In this embodiment, the material on the conductive layer 217 on the side of the end I of the gate structure 213 is the dielectric layer 223, instead of the conventional high-k dielectric constant material of the initial hard mask layer 218, so that after the metal layer 1(M1) is formed subsequently, the dielectric constant of the material between the metal layer 1(M1) and the conductive layer 217 is reduced, and thus the parasitic capacitance generated between the metal layer 1(M1) and the conductive layer 217 is reduced, so that the electrical performance of the semiconductor device is enhanced.

The dielectric constant of the dielectric layer 223 is less than 2.5.

In the present embodiment, the dielectric constant of the dielectric layer 223 is less than 2.5, so that the parasitic capacitance between the conductive layer 217 and the metal layer 1(M1) formed subsequently is reduced, because the dielectric constant of the material (the dielectric layer 223) between the conductive layer 217 and the metal layer 1(M1) is reduced, and thus the parasitic capacitance between the two is reduced.

Correspondingly, the invention also provides a semiconductor device, which comprises a substrate 201; a fin 202 on the substrate 201; an isolation structure 203 located on the substrate 201 and covering a portion of the sidewall of the fin 202, wherein the top surface of the isolation structure is lower than the top surface of the fin 202; a gate structure 213 located on the substrate 201 and crossing the fin 202; a conductive layer 217 positioned at both sides of the gate structure 213; an initial first hard mask layer 215 on an I-top surface of an end of the gate structure 213; a second hard mask layer 222 on the top surface of the conductive layer 217 on both sides of the center II of the gate structure 213; a dielectric layer 223 on the initial first hard mask layer 215 and the second hard mask layer 222; a first through hole 224 located in the dielectric layer 223, the bottom of which is exposed out of the top surface of the center II of the gate structure 213; a second via 225 in the dielectric layer 223, the bottom of which exposes the top surface of the conductive layer at the side of the end I of the gate structure 213; a first contact layer 226 located within the first via 224; a second contact layer 227 located within the second via 225.

In this embodiment, the dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217, so that in the process of forming the first through hole 224 and the second through hole 225, only one mask (mask) layer is needed to simultaneously form the first through hole 224 and the second through hole 225, and the first through hole 224 and the second through hole 225 are prevented from being formed by multiple mask (mask) layers, so that the problem of misalignment of multiple mask (mask) layers is avoided, the process difficulty of forming the first through hole 224 and the second through hole 225 is reduced, and the accuracy of forming the first through hole 224 and the second through hole 225 is improved.

In this embodiment, since the second hard mask layer 222 is formed only on the conductive layer 217 on both sides of the center II of the gate structure 213, and the second hard mask layer 222 is not formed on the conductive layer 217 on both sides of the end I of the gate structure 213, the volume of the second hard mask layer 222 is greatly reduced, so that when the metal layer M1 is formed subsequently, the parasitic capacitance between the metal layer M1 and the conductive layer 217 is greatly reduced, thereby contributing to improving the performance of the formed semiconductor device.

In this embodiment, the center II of the gate structure 213 is located at a center line of the gate structure 213, or the center II of the gate structure 213 is located at a distance of 0nm to 5nm from the center line of the gate structure 213, which is a symmetric center line along the gate structure in a direction parallel to the extending direction of the fin 202.

In the present embodiment, the dielectric constant of the dielectric layer is less than 2.5, and the dielectric constant of the dielectric layer 223 is less than 2.5, so that the parasitic capacitance between the conductive layer 217 and the metal layer 1(M1) formed subsequently is reduced, because the dielectric constant of the material (the dielectric layer 223) between the conductive layer 217 and the metal layer 1(M1) is reduced, and thus the parasitic capacitance between the two is reduced.

Second embodiment

The difference between this embodiment and the first embodiment is that the opening exposes the initial second hard mask layer on one side of the end of the gate structure and the initial first hard mask layer on the end of the gate structure, as shown in fig. 28 to 41.

Please refer to the process of fig. 4-13 in the first embodiment from the providing of the substrate to the formation of the initial first hard mask layer and the initial second hard mask layer.

Referring to fig. 28, a patterned layer 219 is formed on the initial first hard mask layer 215 and the initial second hard mask layer 218, the patterned layer 219 having an opening 228, the opening 228 exposing the initial second hard mask layer 218 on the side of the end I of the gate structure 213 and the initial first hard mask layer 215 on the end I of the gate structure 213.

In the present embodiment, the opening 228 also exposes the top surface of the initial hard mask layer 215 on top of the secondary gate structure 214 on the side of the initial second hard mask layer 218 on the side of the end I of the gate structure 213.

In this embodiment, the material of the patterning layer 219 is a photoresist, and argon fluoride (ArF) is used.

Referring to fig. 29, the initial second hard mask layer 218 exposed by the opening 228 is etched away until the top surface of the conductive layer 217 is exposed.

In this embodiment, the process of etching the initial second hard mask layer 218 is a dry etching process.

Referring to fig. 30, a second sacrificial layer 229 is formed on the top surface of the exposed conductive layer 217, and the second sacrificial layer 229 covers the initial first hard mask layer 215 on top of the end portion I of the gate structure 213.

In this embodiment, the second sacrificial layer 229 also covers the surface of the initial first hard mask layer 215 on top of the end portion I of the sub-gate structure 214.

In this embodiment, after the second sacrificial layer 229 is formed, the patterning layer 219 is removed.

Referring to fig. 31 to 33, fig. 33 is a top view of fig. 31 and 32, fig. 31 is a cross-sectional view of fig. 33 taken along line a-a, and fig. 32 is a cross-sectional view of fig. 33 taken along line B-B, wherein the initial first hard mask layer 215 on top of the center II of the gate structure 213 is removed until the top surface of the center II of the gate structure 213 is exposed.

In this embodiment, the process of removing the initial first hard mask layer 215 is a dry etching process; in other embodiments, a wet etching process or an etching process combining a wet etching process and a dry etching process may also be used.

In this embodiment, the initial hard mask layer 215 on the center II of the sub-gate structure 214 corresponding to the gate structure 213 is also removed until the top surface of the center II of the sub-gate structure 214 is exposed.

Referring to fig. 34, in the view direction of fig. 34 and fig. 32, the second sacrificial layer 229 is removed, and a first hard mask layer 230 is formed on top of the end portion I of the gate structure 213.

In this embodiment, the first hard mask layer 230 is also formed on top of the end portion I of the sub-gate structure 214 on the side of the conductive layer 217.

Referring to fig. 35-37, fig. 37 is a top view of fig. 35 and 36, fig. 35 is a cross-sectional view taken along line a-a of fig. 37, and fig. 36 is a cross-sectional view taken along line B-B of fig. 37, wherein a dielectric layer 223 is formed on the gate structure 213 and the conductive layer 217.

Referring to fig. 38 and 39, the view directions of fig. 38 and 35 are the same, and the view directions of fig. 39 and 36 are the same, the dielectric layer 223 is etched, a first through hole 224 and a second through hole 225 are formed in the dielectric layer 223, the bottom of the first through hole 224 is exposed out of the top surface of the center II of the gate structure 213, and the bottom of the second through hole 225 is exposed out of the top surface of the conductive layer 217 on the side of the end I of the gate structure 213.

Referring to fig. 40 to 41, the view directions of fig. 40 and fig. 38 are the same, and the view directions of fig. 41 and fig. 39 are the same, a first contact layer 226 is formed in the first via 224, and a second contact layer 227 is formed in the second via 225.

In this embodiment, referring to fig. 40 and fig. 41, it can be seen that, except that the first hard mask layer 230 is disposed on the end I of the gate structure 213 on both sides of the second contact layer 227 and the top surface of the end I of the sub-gate structure 214, the dielectric constant of the dielectric layer 223 is smaller (k is smaller than 2.5) and the dielectric constant of the material of the dielectric layer 223 is smaller (k is smaller than 2.5) instead of the first hard mask layer disposed on the top of the sub-gate structure 214, so that after the metal layer 1(M1) is formed subsequently, the dielectric constant of the material between the gate structure and the metal layer 1(M1) is reduced, thereby reducing the parasitic capacitance between the gate structure and the metal layer 1(M1) and improving the electrical performance of the semiconductor device.

Accordingly, the present invention also provides a semiconductor device comprising: a substrate 201; a fin 202 on the substrate 201; an isolation structure 203 located on the substrate 201, covering a portion of sidewalls of the fin 202 and having a top surface lower than a top surface of the fin 202; a gate structure 213 located on the substrate 201 and crossing the fin 202; a conductive layer 217 positioned at both sides of the gate structure 213; a first hard mask layer 230 on a top surface of the end portion I of the gate structure 213; an initial second hard mask layer 218 located on a top surface of the conductive layer 217 on both sides of a center II of the gate structure 213 and on a top surface of the conductive layer 217 on one side of an end I of the gate structure 213; a dielectric layer 223 on the first hard mask layer 230 and the initial second hard mask layer 218; a first through hole 224 located in the dielectric layer 223, the bottom of which is exposed out of the top surface of the center II of the gate structure 213; a second via 225 in the dielectric layer 223, the bottom of which exposes the top surface of the conductive layer 217 on the other side of the end I of the gate structure 213; a first contact layer 226 located within the first via 224; a second contact layer 227 located within the second via 226.

In this embodiment, except that the first hard mask layer 230 is disposed on the end I of the gate structure 213 and the top surface of the end I of the sub-gate structure 214 on both sides of the second contact layer 227, the dielectric layer 223 is replaced by the rest of the gate structure 213 and the rest of the sub-gate structure 214 without the first hard mask layer, and the dielectric constant of the material of the dielectric layer 223 is small (k is smaller than 2.5), so that after the metal layer 1(M1) is formed subsequently, the dielectric constant of the material between the gate structure 213 and the metal layer 1(M1) is reduced, thereby reducing the parasitic capacitance between the gate structure and the metal layer 1(M1), and improving the electrical performance of the semiconductor device.

The dielectric constant of the dielectric layer 223 is less than 2.5.

In the present embodiment, the dielectric constant of the dielectric layer 223 is less than 2.5, which aims to reduce the parasitic capacitance between the gate structure 213 and the metal layer 1(M1) formed subsequently, because the dielectric constant of the material (the dielectric layer 223) between the gate structure 213 and the metal layer 1(M1) is reduced, so that the parasitic capacitance between the two is reduced.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor device, comprising:

a substrate;

a fin portion on the substrate;

the isolation structure is positioned on the substrate, covers partial side walls of the fin part, and has a top surface lower than that of the fin part;

the grid structure is positioned on the substrate and stretches across the fin part;

the conducting layers are positioned on two sides of the grid structure;

an initial first hard mask layer located on a top surface of an end of the gate structure;

the second hard mask layer is positioned on the top surfaces of the conducting layers on the two sides of the center of the grid structure;

a dielectric layer on the initial first hard mask layer and the second hard mask layer;

the first through hole is positioned in the dielectric layer, and the bottom of the first through hole is exposed out of the central surface of the grid structure;

the second through hole is positioned in the dielectric layer, and the bottom of the second through hole is exposed out of the top surface of the conducting layer on one side of the end part of the grid structure;

the first contact layer is positioned in the first through hole;

and the second contact layer is positioned in the second through hole.

2. A semiconductor device, comprising:

a substrate;

a fin portion on the substrate;

the conducting layers are positioned on two sides of the grid structure;

the first hard mask layer is positioned on the top surface of the end part of the grid structure;

an initial second hard mask layer, which is positioned on the top surfaces of the conducting layers on two sides of the center of the gate structure and on the top surface of the conducting layer on one side of the end part of the gate structure;

a dielectric layer on the first hard mask layer and the initial second hard mask layer;

the first through hole is positioned in the dielectric layer, and the bottom of the first through hole is exposed out of the central top surface of the grid structure;

the second through hole is positioned in the dielectric layer, and the bottom of the second through hole is exposed out of the top surface of the conducting layer on the other side of the end part of the grid structure;

the first contact layer is positioned in the first through hole;

and the second contact layer is positioned in the second through hole.

3. The semiconductor device according to claim 1 or 2, wherein a center of the gate structure is located at a center line of the gate structure, or a center of the gate structure is located at a distance of 0nm to 5nm from a center line of the gate structure, the center line being along a symmetrical center line of the gate structure in a direction parallel to an extending direction of the fin portion.

4. The semiconductor device of claim 1 or 2, wherein the dielectric layer has a dielectric constant of less than 2.5.

5. The semiconductor device of claim 1 or 2, wherein a top surface of the gate structure is non-flush with a top surface of the conductive layer.

6. A method of forming a semiconductor device, comprising:

providing a substrate, wherein the substrate is provided with a grid structure and conducting layers positioned on two sides of the grid structure;

forming a dielectric layer on the gate structure and the conductive layer;

and etching the dielectric layer, and forming a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole is exposed out of the top surface of the center of the grid structure, and the bottom of the second through hole is exposed out of the top surface of the conductive layer on one side of the end part of the grid structure.

7. The method for forming a semiconductor device according to claim 6, wherein a second contact layer is formed in the second via hole.

8. The method for forming a semiconductor device according to claim 6, wherein a first contact layer is formed in the first via hole.

9. The method of forming a semiconductor device according to claim 6, wherein a dielectric constant of the dielectric layer is less than 2.5.

10. The method of forming a semiconductor device of claim 6, further comprising, prior to forming a dielectric layer over the first gate structure and the conductive layer: and forming a second hard mask layer on the tops of the conducting layers on two sides of the center of the gate structure.

11. The method for forming a semiconductor device according to claim 10, further comprising: and forming a first hard mask layer on the top of the end part of the gate structure.

12. The method of forming a semiconductor device of claim 11, wherein forming the first hard mask layer and the second hard mask layer comprises: forming an initial first hard mask layer on the gate structure, and forming an initial second hard mask layer on the conductive layer; forming a patterning layer on the initial first hard mask layer and the initial second hard mask layer, wherein the patterning layer is provided with an opening, and the opening exposes the initial first hard mask layer on the top of the center of the gate structure and the initial second hard mask layers positioned on two sides of the center of the gate structure; or the opening exposes the initial second hard mask layer on one side of the end part of the grid structure and the initial first hard mask layer on the end part of the grid structure.

13. The method of forming a semiconductor device according to claim 12, wherein the opening exposes the initial first hard mask layer on the top of the center of the gate structure and the initial second hard mask layers on both sides of the center of the gate structure, further comprising: etching and removing the opening to expose the top surface of the initial first hard mask layer until the central top surface of the gate structure is exposed; and forming a first sacrificial layer on the top surface of the exposed center contact, wherein the first sacrificial layer covers the top surfaces of the initial second hard mask layers positioned at two sides of the center of the gate structure.

14. The method for forming a semiconductor device according to claim 13, further comprising, after forming the first sacrifice layer, the steps of: removing the initial second hard mask layers on two sides of the end part of the grid structure until the top surfaces of the conducting layers on two sides of the end part of the grid structure are exposed, and forming second hard mask layers on the conducting layers on two sides of the center of the grid structure; and removing the first sacrificial layer.

15. The method of forming a semiconductor device of claim 12, wherein when the opening exposes the initial second hard mask layer on a side of an end portion of the gate structure and the initial first hard mask layer on the end portion of the gate structure, further comprising: etching and removing the initial second hard mask layer exposed by the opening until the top surface of the conducting layer is exposed; and forming a second sacrificial layer on the top surface of the exposed conducting layer, wherein the second sacrificial layer covers the initial first hard mask layer positioned on the top of the end part of the grid structure.

16. The method for forming a semiconductor device according to claim 15, further comprising, after forming the second sacrifice layer, the steps of: removing the initial first hard mask layer at the top of the center of the grid structure until the surface of the top of the center of the grid structure is exposed, and forming a first hard mask layer at the top of the end part of the grid structure; and removing the second sacrificial layer.

17. The method for forming the semiconductor device according to claim 6, wherein a center of the gate structure is located at a center line of the gate structure, or a center of the gate structure is located at a distance of 0nm to 5nm from a center line of the gate structure, the center line being along a symmetrical center line of the gate structure in a direction parallel to an extending direction of the fin portion.

18. The method of claim 6, wherein the base comprises a substrate, a fin on the substrate, and an isolation structure covering a portion of a sidewall of the fin and having a top surface lower than a top surface of the fin.