CN113593625A

CN113593625A - Memory device

Info

Publication number: CN113593625A
Application number: CN202110630960.6A
Authority: CN
Inventors: 廖忠志
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-06-30
Filing date: 2021-06-07
Publication date: 2021-11-02
Also published as: TW202203324A; US11723193B2; US20210408014A1; US20230337420A1

Abstract

A memory device includes a first transistor formed in a first region of a substrate. The first transistor includes a protruding structure protruding from the substrate, and a first source/drain (S/D) structure coupled to a first end of the protruding structure. The memory device includes a second transistor formed in a second region of the substrate. The second transistor includes a plurality of first semiconductor layers vertically spaced apart from each other, a second source/drain structure coupled to first ends of the plurality of first semiconductor layers, and a third source/drain structure coupled to second ends of the plurality of first semiconductor layers. The first region and the second region are laterally separated from each other by an isolation structure.

Description

Memory device

Technical Field

The present disclosure relates generally to semiconductor devices, and more particularly to a memory device including a non-gate all-around (non-GAA) transistor and one or more gate-all-around (GAA) transistors.

Background

An Integrated Circuit (IC) sometimes includes one-time-programmable (OTP) memory to provide a non-volatile memory (NVM), and data in the NVM is not lost due to power interruption of the IC. One type of OTP device includes an anti-fuse (anti-fuse) memory. An antifuse memory comprises a number of antifuse memory cells (cells, or bit cells) whose terminals (terminals) are unconnected before programming and shorted (e.g., connected) after programming. The anti-fuse memory may be based on metal-oxide-semiconductor (MOS) technology. For example, an anti-fuse memory cell may include a programming MOS transistor (or MOS capacitor) and at least one read MOS transistor. The gate dielectric of the program MOS transistor may be broken down to interconnect the gate of the program MOS transistor with the source or drain region (interconnect). The antifuse memory cell may represent a different data bit by reading a resultant current (RESULTANT CURRENT) flowing through the programming MOS transistor and the read MOS transistor, depending on whether the gate dielectric of the programming MOS transistor is collapsed. The anti-fuse memory cell has an advantageous feature of reverse-engineering protection (reverse-engineering) because the programmed state of the anti-fuse cell cannot be judged through reverse engineering.

Disclosure of Invention

The embodiment of the disclosure provides a memory device. The memory device includes a first transistor formed in a first region of a substrate. The first transistor includes a protruding structure protruding from the substrate, and a first source/drain (S/D) structure coupled to a first end of the protruding structure. The memory device includes a second transistor formed in a second region of the substrate. The second transistor includes a plurality of first semiconductor layers vertically spaced apart from each other, a second source/drain structure coupled to first ends of the plurality of first semiconductor layers, and a third source/drain structure coupled to second ends of the plurality of first semiconductor layers. The first region and the second region are laterally separated from each other by an isolation structure.

Embodiments of the present disclosure provide a one-time programmable (OTP) memory device. The one-time programmable memory device includes a programming transistor formed in a first region of a substrate. The otp memory device includes a first read transistor electrically connected in series to a program transistor and formed in a second region of the substrate. The first region is laterally separated from the second region by an isolation structure. The program transistor includes a first gate structure straddling a protruding structure protruding from the substrate, and the first read transistor includes a second gate structure wrapping around each of a plurality of first nanostructures vertically spaced from each other.

The embodiment of the disclosure provides a manufacturing method of a memory device. The manufacturing method of the memory device comprises the step of defining a first active area and a second active area on a substrate. The first active region and the second active region are laterally separated from each other by an isolation structure. The manufacturing method of the memory device comprises the step of forming a first transistor in the first active region. The first transistor includes a first channel formed by a protruding structure protruding from the substrate, a first active gate structure straddling the first channel, and a first source/drain structure coupled to an end of the first channel. The method of manufacturing the memory device includes forming a second transistor in the second active region. The second transistor includes a second channel formed by one or more semiconductor layers disposed above the substrate, a second active gate structure surrounding the second channel, a second source/drain structure coupled to one end of the second channel, and a third source/drain structure coupled to the other end of the second channel.

Drawings

Aspects of the disclosure can be better understood from the following description and drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is an exemplary circuit schematic of a memory cell according to some embodiments.

FIG. 2 is an exemplary circuit schematic of another memory cell according to some embodiments.

FIG. 3 is a perspective view of a memory device including the memory cell shown in FIG. 1, shown in accordance with some embodiments.

FIG. 4 is a perspective view of a memory device including the memory cell shown in FIG. 2, shown in accordance with some embodiments.

FIG. 5 illustrates various exemplary layouts for forming memory devices, according to some embodiments.

FIG. 6 illustrates various exemplary layouts for forming memory devices, according to some embodiments.

FIG. 7 illustrates various exemplary layouts for forming memory devices, according to some embodiments.

FIG. 8 illustrates various exemplary layouts for forming memory devices, according to some embodiments.

FIG. 9 illustrates various exemplary layouts for forming memory devices, according to some embodiments.

FIG. 10 illustrates various exemplary layouts for forming memory devices, according to some embodiments.

FIG. 11 is a flowchart illustrating an exemplary method of defining a first active region and a second active region of a memory device according to some embodiments.

FIG. 12 is a cross-sectional view of a memory device manufactured by the method of FIG. 11 at various stages of manufacture, according to some embodiments.

FIG. 13 is a cross-sectional view of a memory device manufactured by the method of FIG. 11 at various stages of manufacture, according to some embodiments.

FIG. 14 is a cross-sectional view of a memory device manufactured by the method of FIG. 11 at various stages of manufacture, according to some embodiments.

FIG. 15 is a cross-sectional view of a memory device manufactured by the method of FIG. 11 at various stages of manufacture, according to some embodiments.

FIG. 16 is a cross-sectional view of a memory device manufactured by the method of FIG. 11 at various stages of manufacture, according to some embodiments.

FIG. 17 is a flowchart illustrating another exemplary method of defining first and second active regions of a memory device according to some embodiments.

FIG. 18 is a flowchart illustrating an example method of fabricating a memory device following the method of FIG. 11 or 17, in accordance with some embodiments.

Fig. 19A-19C are cross-sectional views of a memory device fabricated by the method of fig. 18 at various stages of fabrication, in accordance with some embodiments.

Fig. 20-26 are cross-sectional views of a memory device fabricated by the method of fig. 18 at various stages of fabrication, in accordance with some embodiments.

Fig. 27A-27C are cross-sectional views of a memory device fabricated by the method of fig. 18 at various stages of fabrication, in accordance with some embodiments.

FIG. 28 is a cross-sectional view of a memory device manufactured by the method of FIG. 18 at various stages of manufacture, according to some embodiments.

FIG. 29 is a cross-sectional view of another embodiment of a memory device manufactured by the method of FIG. 18, according to some embodiments.

FIG. 30 is a cross-sectional view of yet another embodiment of a memory device fabricated by the method of FIG. 18, according to some embodiments.

FIG. 31 is a cross-sectional view of yet another embodiment of a memory device fabricated by the method of FIG. 18, according to some embodiments.

FIG. 32 is a cross-sectional view of yet another embodiment of a memory device fabricated by the method of FIG. 18, according to some embodiments.

Wherein the reference numerals are as follows:

100: memory unit

110: a first transistor

110G: grid electrode

110S: source electrode

110D: drain electrode

120: second transistor

120G: grid electrode

120S: source electrode

120D: drain electrode

130: programming word line

132: read word line

134: bit line

136: resistor with a resistor element

200: memory unit

210: a first transistor

210G: grid electrode

210S: source electrode

210D: drain electrode

220: second transistor

220G: grid electrode

220S: source electrode

220D: drain electrode

230: a third transistor

230G: grid electrode

230S: source electrode

230D: drain electrode

240: programming word line

242: first read word line

244: second read word line

250: bit line

300: memory device

302: programming transistor

304: read transistor

306: semiconductor substrate

306A: a first active region

306B: a second active region

308: grid structure

310: grid structure

310a to 310 d: gate stack

316-322: source/drain structure

332: projection structure

342: semiconductor layer

342a to 342 c: semiconductor layer

A-A': line segment

400: memory device

402: programming transistor

404: first reading transistor

406: second read transistor

408: semiconductor substrate

408A: a first active region

408B: a second active region

410-414: grid structure

416-424: source/drain structure

432: projection structure

442: semiconductor layer

442a to 442 c: semiconductor layer

452: semiconductor layer

452a to 452 c: semiconductor layer

500: layout

501: cell boundaries

502A: active feature

502B: active feature

504: gate features

506: gate features

508 to 514: sub-active feature

520-532: feature(s)

534: interconnect structure

536: bit line

538: programming word line

540: read word line

W₁: width of

W₂: width of

600: layout

602: dummy gate structure

604: dummy gate structure

700: layout

702: feature(s)

704: interconnect structure

800: layout

802A: active region

900: layout

901: cell boundaries

902A: active feature

902B: active feature

904 to 908: gate features

910 to 918: sub-active feature

920-928: feature(s)

930 to 934: feature(s)

940: interconnect structure

942: bit line

944: programming word line

946: first read word line

948: second read word line

W₃: width of

W₄: width of

1000: layout

1002: dummy gate structure

1004: dummy gate structure

1100: method of producing a composite material

1102-1110: operation of

1200: memory device

1202: semiconductor substrate

1202A: first region

1202B: second region

1203: top surface of the container

1304: patterned mask

1306: hard mask

1308: patterning photoresist layer

1205: bottom surface

1207: side wall

1306: hard mask

1402: groove

1502: first semiconductor layer

1502a to 1502 c: first semiconductor layer

1504: a second semiconductor layer

1504a to 1504 c: a second semiconductor layer

1602A: a first active structure

1602B: second active structure

1603A: a first active region

1603B: a second active region

1610: semiconductor layer

1610a to 1610 c: semiconductor layer

1620: semiconductor layer

1620a to 1620 c: semiconductor layer

1625A, the preparation method comprises: patterned mask

1625B, the step of: patterned mask

1630: isolation structure

1700: method of producing a composite material

1702-1712: operation of

1800: method of producing a composite material

1802 to 1820: operation of

1902: first dummy gate structure

1904: dummy gate dielectric

1906: dummy gate

1908: hard mask

1910: gate spacer

1912: second dummy gate structure

1914: dummy gate dielectric

1916: dummy gate

1918: hard mask

1920: gate spacer

2001: blocking mask

2010: semiconductor layer

2010a-2010 c: semiconductor layer

2020: semiconductor layer

2020a to 2020 c: semiconductor layer

2102: internal spacer

2202: source/drain structure

2204: source/drain structure

2210: GAA transistor

H₁: height

H₂: height

2301: blocking mask

2402: source/drain structure

2404: source/drain structure

2410: non-GAA transistor

H3: height

2500: interlayer dielectric

2702: first active grid structure

2704: gate dielectric

2706: grid metal

2712: second active grid structure

2714: gate dielectric

2716: grid metal

2800: interlayer dielectric

2802: interconnect structure

2803: dielectric hard mask

2804 to 2812: interconnect structure

2813: dielectric hard mask

2814: interconnect structure

2816: interconnect structure

2900: dummy gate structure

2902: dummy gate dielectric

2904: dummy gate

2906: spacer

2908: dielectric hard mask

2920: dummy gate structure

2922: dummy gate dielectric

2924: dummy gate

2926: spacer

2928: dielectric hard mask

3000: GAA transistor

3002: semiconductor layer

3004: source/drain structure

3006: active grid structure

3008: interconnect structure

3010: interconnect structure

3100: dummy gate structure

3102: dummy gate dielectric

3104: dummy gate

3106: spacer

3108: dielectric hard mask

3120: dummy gate structure

3122: dummy gate dielectric

3124: dummy gate

3126: spacer

3128: dielectric hard mask

3200: non-GAA transistor

3202: active grid structure

3204: gate dielectric

3206: grid metal

3208: gate spacer

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of the components and arrangements of the present disclosure are set forth below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, if the description recites a first feature formed on or over a second feature, it may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which additional features are formed between the first and second features, such that direct contact between the first and second features is not provided. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may use spatially relative terms, such as "below …," "below," "…," "above," and the like, to facilitate describing the relationship of one element or feature to another element or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be turned to a different orientation (rotated 90 degrees or otherwise) and the spatially relative terms used herein should be interpreted accordingly.

In modern semiconductor device fabrication processes, a large number of semiconductor devices, such as silicon-channel n-type field effect transistors (nfets) and silicon-germanium-channel p-type field effect transistors (pfets), are fabricated on a single wafer. The construction of non-planar transistor devices, such as fin-based transistors (commonly referred to as "finfets"), may provide higher device density and better performance than planar transistors (planar transistors). Some advanced non-planar transistor configurations, such as nanosheet (or nanowire) transistors, may further provide better performance than finfets. In contrast to finfets in which the channel is partially wrapped (wrap) by a gate structure (e.g., straddled), nanosheet transistors typically include a gate structure wrapped around the entire perimeter of one or more nanosheets to improve control of the channel current. For example, in FinFET and nanosheet transistors having similar dimensions, the nanosheet transistor can provide a larger drive current (I)_on) And a smaller sub-threshold leakage current (I)_off). Transistors having a gate structure that completely wraps around their channel are commonly referred to as gate-all-around (GAA) transistors; transistors having a gate structure that partially wraps around or covers their channel, including finfets, as well as planar transistors, are commonly referred to as non-gate full-ring (non-GAA) transistors.

In view of the relative performance of the nanosheet transistors as compared to finfets, some current memory devices have configured corresponding memory cells (cells) in a configuration of the nanosheet transistors. For example, an anti-fuse (anti-fuse) memory cell may include a programming transistor and a reading transistor, each of which is configured as a GAA transistor. However, because GAA transistors typically have multiple independent nanostructures (e.g., nanoplates, nanowires), when an antifuse memory cell is programmed, only a portion of the gate dielectric (e.g., coupled to one of the nanoplates) may be damaged, which may disadvantageously result in the antifuse memory cell having a high resistance and/or a widely varying breakdown voltage (Vbreakdown)_BD). Thus, it is possible to provideCurrent memory cells that have adopted the GAA configuration are not entirely satisfactory.

The present disclosure provides various embodiments of a memory cell. In some embodiments, the disclosed memory cells include an antifuse memory cell including a programming transistor and one or more read transistors. The program transistor is configured as a non-GAA transistor (e.g., FinFET, planar transistor) while each of the one or more read transistors is configured as a GAA transistor. Above the substrate, the non-GAA transistor and the one or more GAA transistors are separated from each other by at least one isolation structure, such as a Shallow Trench Isolation (STI). In other words, non-GAA transistors may be formed in a first active region (active region) of the substrate, and GAA transistors may be formed in a second active region, wherein the first and second active regions are separated (e.g., electrically isolated) from each other by STI. By configuring the programming transistors as non-GAA transistors and each of the read transistors as GAA transistors, as disclosed herein, the memory cells can have a more controllable breakdown voltage (e.g., a breakdown voltage that varies over a narrower range) while maintaining the performance of the GAA transistors after the memory cells are programmed.

FIG. 1 is an exemplary circuit schematic of a memory cell 100 according to some embodiments. As shown, a memory cell (sometimes referred to as a memory bit cell, memory bit, or bit) 100 includes a first transistor 110 and a second transistor 120. Each of the first transistor 110 and the second transistor 120 may include an n-type metal-oxide-semiconductor field-effect-transistor (MOSFET). Each of the first transistor 110 and the second transistor 120 may include another type of MOSFET, such as: a p-type MOSFET. In some other embodiments, at least one of the first transistor 110 and the second transistor 120 may be replaced by another type of electronic device (e.g., a MOS capacitor), but still be included in the scope of the present disclosure. The first transistor 110 and the second transistor 120 are electrically coupled in series with each other. For example, the drain 110D of the first transistor 110 is connected to the source 120S of the second transistor 120.

The memory cell 100 may be configured as a one-time-programmable (OTP) memory cell, such as an antifuse cell. It should be understood that memory cell 100 may be configured as any type of memory cell including two transistors electrically coupled in series with each other, such as a NOR-type non-volatile memory cell, a dynamic random-access memory (DRAM) cell, a two-transistor static random-access memory (SRAM) cell, and so forth.

When the memory cell 100 is configured as an anti-fuse cell, the first transistor 110 may be used as a programming transistor (and thus may also be referred to as a programming transistor 110), and the second transistor 120 may be used as a reading transistor (and thus may also be referred to as a reading transistor 120). As a result, the source 110S of the first transistor is floating (e.g., not coupled to anything), and the gate 110G of the first transistor is coupled to the programming Word Line (WLP) 130; on the other hand, the gate 120G of the second transistor is coupled to a read Word Line (WLR) 132, and the drain 120D of the second transistor is coupled to a Bit Line (BL) 134.

To program the memory cell 100, a voltage (e.g., a positive voltage corresponding to a logic high (logic high) state) is applied to the gate 120G via the read word line 132 to turn on the read transistor 120. A sufficiently high voltage (e.g., breakdown voltage (V) before, simultaneously with, or after read transistor 120 is turned on_BD) Is applied to the program wordline 130 and a low voltage (e.g.: a positive voltage corresponding to logic low) is applied to bit line 134. A low voltage (applied to bit line 134) may be transmitted to drain 110D to generate a voltage V across drain 110D and gate 110G_BDTo collapse a portion of the gate dielectric of the program transistor 110 (e.g., the portion between the drain 110D and the gate 110G). After the gate dielectric of the programming transistor 110 collapses, the portion interconnecting the gate 110 and the drain 110D exhibits a behavior corresponding to a resistance. For example, this portion may act as a resistor 136, as shown in FIG. 1Shown symbolically. Before programming (before the gate dielectric of the programming transistor 110 breaks down), no conductive path exists between the bit line 134 and the programming word line 130 when the read transistor 120 is turned on; after programming, when the read transistor 120 is turned on, a conductive path exists between the bit line 134 and the program word line 130 (e.g., via the resistor 136).

To read memory cell 100, similar to the programming operation, read transistor 120 is turned on and bit line 134 is coupled to a voltage corresponding to a logic low state. In response, a positive voltage is applied to the gate 110G of the program transistor. As described above, if the gate dielectric of the program transistor 110 does not collapse, there is no conductive path between the bit line 134 and the program word line 130. Thus, a relatively low current is conducted from the programming word line 130, through the first transistor 110 and the second transistor 120, and to the bit line 134. If the gate dielectric of the program transistor 110 is broken, a conductive path exists between the bit line 134 and the program word line 130. Thus, a relatively high current is conducted from the programming wordline 130, through the first transistor 110 (now equivalent to the resistor 136) and the second transistor 120, and to the bitline 134. Such low and high currents are sometimes referred to as I of memory cell 110, respectively_offAnd I_on. The circuit elements (e.g., sense amplifiers) coupled to the bit lines 134 may be differential I_offAnd I_on(and vice versa) and thus whether the memory cell 100 exhibits a logic high ("1") or a logic low ("0"). For example, when I_onWhen read, memory cell 100 may represent a 1; when I is_offWhen read, memory cell 100 may represent a 0.

FIG. 2 is an exemplary circuit schematic of another memory cell 200, according to some embodiments. Memory cell 200 is similar to memory cell 100 of FIG. 1, except that memory cell 200 includes an additional read transistor. As shown, the memory cell 200 includes a first transistor 210, a second transistor 220, and a third transistor 230. Each of the first transistor 210, the second transistor 220, and the third transistor 230 may include an n-type MOSFET. In some other embodiments, each of the first transistor 210, the second transistor 220, and the third transistor 230 may comprise a p-type MOSFET, but are still included within the scope of the present disclosure. The first transistor 210, the second transistor 220, and the third transistor 230 are electrically coupled in series with each other. For example, the drain 210D of the first transistor 210 is connected to the source 220S of the second transistor 220, and the drain 220D of the second transistor 220 is connected to the source 230S of the third transistor 230. The memory cell 200 may be an anti-fuse cell (as described above), wherein the first transistor 210 serves as a programming transistor of the anti-fuse cell, and the second transistor 220 and the third transistor 230 together serve as a reading transistor of the anti-fuse cell. Similar to the memory cell 100, the gate 210G of the first transistor 210 (programming transistor) is coupled to the programming wordline 240, the

gates

220G and 230G of the second and third transistors 220 and 230 (read transistors) are coupled to the first and second read wordlines (WLR1 and WLR2) 242 and 244, respectively, and the drain 230D of the third transistor 230 (read transistor) is coupled to the bit line 250. Wherein the first transistor 210 further comprises a source 210S. The operation of memory cell 200 is substantially similar to the operation of memory cell 100 and thus is not described in detail.

Referring to fig. 3, fig. 3 shows a perspective view of an exemplary memory device 300. According to some embodiments, memory device 300 may be part of an anti-fuse memory cell that includes one programming transistor and one read transistor, such as memory cell 100 of fig. 1. The perspective view of FIG. 3 is an overview of an antifuse memory cell, and thus, some features of the antifuse memory cell may not be discernable in FIG. 3. More detailed features of the memory device 300 (or a memory device similar to the memory device 300) are illustrated and discussed below with reference to the cross-sectional views of fig. 19A-29 and 32.

As shown in fig. 3, the memory device 300 includes a program transistor 302 and a read transistor 304. In some embodiments, the program transistor 302 is configured as a non-GAA transistor (e.g., a FinFET) and the read transistor is configured as a GAA transistor (e.g., a nanosheet transistor). The program transistor 302 and the read transistor 304 may be formed in respective different active regions on a semiconductor substrate 306. For example, the program transistor 302 is formed over a first active region 306A (also referred to as an active region 306A) of the semiconductor substrate 306; the read transistor 304 is formed over a second active region 306B (also referred to as active region 306B) of the semiconductor substrate 306, wherein the first active region 306A and the second active region 306B are laterally separated (e.g., along the X-direction) from each other by an isolation structure (not shown in fig. 3). Such an active region is sometimes referred to as an Oxide Diffusion (OD) region.

Specifically, the programming transistor 302 includes a gate structure 308 disposed over the first active region 306A; the read transistor 304 includes a gate structure 310 disposed over the second active region 306B. The

gate structures

308 and 310, which are parallel to each other, may be oriented and elongated along a lateral direction (e.g., Y-direction). In the first active region 306A, the program transistor 302 includes a source/drain structure 316 and a source/drain structure 318 respectively formed on the sides of the gate structure 308. In the second active region 306B, the read transistor 304 includes a source/drain structure 320 and a source/drain structure 322 respectively formed on the sides of the gate structure 310.

The gate structure 308 is formed to straddle the structure 332 (hereinafter fin or protrusion structure 332) protruding from the substrate 306, wherein the source/drain structure 316 and the source/drain structure 318 are respectively coupled to two ends of the protrusion structure 332, for example, two ends of the protrusion structure 332 along the X direction. The protruding structure 332 may serve as a channel for the programming transistor 302. The gate structure 310 is formed to wrap around a plurality of

nanostructures

342a, 342b, and 342c (e.g., nanoplatelets, nanowires, or other semiconductor layers having dimensions on the nanometer scale, and thus also referred to as semiconductor layers 342a-342c) and has source/

drain structures

320 and 322 coupled to their respective ends, e.g., along the X-direction. The semiconductor layers 342a-342c (which may sometimes be referred to as semiconductor layer 342) may collectively serve as a channel for the read transistor 304. The protrusion structure 332 and the semiconductor layers 342a-342c may be oriented and elongated along a lateral direction (e.g., the X direction) that is the same as the direction in which the source/drain structures 316-322 are aligned with each other. As such, the first active region 306A with the source/drain structures 316-318 and the protrusion structure 332 formed thereon, and the second active region 306B with the source/drain structures 320-322 and the semiconductor layers 342a-342c formed thereon, although they are laterally separated from each other, may be aligned with each other along a lateral direction (e.g., the X direction).

Still referring to fig. 3, and in more detail, in some embodiments, the gate structure 310 may include a plurality of gate stacks. Each of the gate stacks may include one or more gate dielectrics and one or more gate metals (not shown in fig. 3 for clarity of illustration). Two of the gate stacks are configured to collectively wrap around a corresponding one of the one or more semiconductor layers 342a-342 c. For example, the gate structure 310 includes

gate stacks

310a, 310b, 310c, and 310 d. The gate stacks 310a-310d may have a width (along the Y-direction) substantially similar to a width (along the Y-direction) of the gate structure 310, while the semiconductor layers 342a-342c may be characterized by a width (along the Y-direction) that is less than the width of the gate stacks 310a-310 d. Each of the gate stacks 310a-310d may further include a portion extending along the Z-direction to contact an adjacent gate stack. As such, adjacent ones of the gate stacks 310a-310d may wrap around the entire perimeter (perimeter) of the corresponding one of the semiconductor layers 342a-342 c.

For example, the gate stack 310a and the gate stack 310b may collectively wrap around at least four sides of the semiconductor layer 342a, and two sides (or ends) of the semiconductor layer 342a are coupled to the source/drain structure 320 and the source/drain structure 322, respectively; the gate stack 310b and the gate stack 310c may collectively wrap around at least four sides of the semiconductor layer 342b, and two sides (or ends) of the semiconductor layer 342b are coupled to the source/drain structure 320 and the source/drain structure 322, respectively; and the gate stack 310c and the gate stack 310d may collectively wrap around at least four sides of the semiconductor layer 342c, and two sides (or ends) of the semiconductor layer 342c are coupled to the source/drain structure 320 and the source/drain structure 322, respectively.

Referring to fig. 4, fig. 4 shows a perspective view of an exemplary memory device 400. According to some embodiments, memory device 400 may be part of an anti-fuse memory cell that includes one programming transistor and two read transistors, such as memory cell 200 of fig. 2. The perspective view of FIG. 4 is an overview of an antifuse memory cell, and thus, some features of the antifuse memory cell may not be discernable in FIG. 4. More detailed features of the memory device 400 (or a memory device similar to the memory device 400) are illustrated and discussed below with reference to fig. 30 and the cross-sectional view of fig. 31.

As shown in FIG. 4, memory device 400 includes a program transistor 402, a first read transistor 404 (also referred to as read transistor 404), and a second read transistor 406 (also referred to as read transistor 406). In some embodiments, programming transistor 402 is configured as a non-GAA transistor (e.g., a FinFET), while each of first and

second read transistors

404 and 406 is configured as a GAA transistor (e.g., a nanosheet transistor). The program transistor 402 and the first and

second read transistors

404, 406 may be formed in different active regions of the semiconductor substrate 408. For example, the program transistor 402 is formed over a first active region 408A (also referred to as an active region 408A) of the semiconductor substrate 408; the first read transistor 404 and the second read transistor 406 are formed over a second active region 408B (also referred to as an active region 408B) of the semiconductor substrate 408, wherein the first active region 408A and the second active region 408B are laterally (e.g., along the X-direction) separated from each other by an isolation structure (not shown in fig. 4). Such active regions are sometimes referred to as Oxidation Diffusion (OD) regions.

Specifically, the programming transistor 402 includes a gate structure 410 disposed over the first active region 408A; the first read transistor 404 and the second read transistor 406 respectively include a gate structure 412 and a gate structure 414 disposed above the second active region 408B. The

gate structures

410, 412, and 414 that are parallel to each other may be pointed and elongated along a lateral direction (e.g., Y-direction). In the first active region 408A, the program transistor 402 includes a source/drain structure 416 and a source/drain structure 418 respectively formed on respective sides of the gate structure 410. In the second active region 408B, the first read transistor 404 includes a source/drain structure 420 and a source/drain structure 422 respectively formed on respective sides of the gate structure 412; and the second read transistor 406 includes source/

drain structures

422 and 424 formed on respective sides of the gate structure 414. In the embodiment shown in FIG. 4, the first read transistor 404 and the second read transistor 406 may share the same source/drain structure 422. However, embodiments in which first read transistor 404 and second read transistor 406 do not share the same source/drain structure are also included within the scope of the present disclosure.

The gate structure 410 is formed as a structure 432 (hereinafter fin or protruding structure 432) that protrudes across the substrate 408, wherein the source/

drain structures

416 and 418 are respectively coupled to two ends of the protruding structure 432, for example, two ends of the protruding structure 432 along the X direction. The protruding structures 432 may serve as channels for the programming transistor 402. Gate structure 412 is formed to wrap around a plurality of

nanostructures

442a, 442b, and 442c (e.g., nanoplatelets, nanowires, or other semiconductor layers having dimensions on the nanometer scale, and thus also referred to as semiconductor layers 442a-442c) and has source/

drain structures

420 and 422 coupled to their respective ends, e.g., along the X-direction. The semiconductor layers 442a-442c (which may sometimes be referred to as semiconductor layers 442) can collectively serve as a channel for the first read transistor 404. The gate structure 414 is formed to wrap around a plurality of

other nanostructures

452a, 452b and 452c (e.g., semiconductor layers, and thus also referred to as semiconductor layers 452a-452c) and has source/

drain structures

422 and 424 coupled to their respective ends, e.g., along the X-direction. The semiconductor layers 452a-452c (which may sometimes be referred to as semiconductor layers 452) may collectively serve as a channel for the second read transistor 406. The protruding structures 432 and the semiconductor layers 442a-442c, as well as the semiconductor layers 452a-452c, may be oriented and elongated along a lateral direction (e.g., the X-direction) that is aligned with the source/drain structures 416-424. As such, the first active region 408A with the source/drain structures 416-418 and the protrusion structure 432 formed thereon, and the second active region 408B with the source/drain structures 420-424 and the semiconductor layers 442a-442c and the semiconductor layers 452a-452c formed thereon, although laterally separated from each other, may be aligned with each other along a lateral direction (e.g., the X direction).

In some embodiments, each of the

gate structures

412 and 414 may include a plurality of gate stacks. Each of the gate stacks may include one or more gate dielectrics and one or more gate metals (not shown in fig. 4 for clarity of illustration). Two of the gate stacks are configured to collectively wrap around a corresponding one of the one or more semiconductor layers. Because the

gate structures

412 and 414 are similar to the gate structure 310 discussed with reference to fig. 3, the discussion of the

gate structures

412 and 414 will not be repeated.

Fig. 5, 6, 7, and 8 illustrate various examples of design layouts for fabricating an anti-fuse cell, according to some embodiments. The layouts of fig. 5-8 may each be used to fabricate an anti-fuse memory cell having one program transistor and one read transistor, such as memory cell 100 of fig. 1. Furthermore, in some embodiments, the program transistor may be formed as a non-GAA transistor, while the read transistor may be formed as a GAA transistor. For example, the non-GAA programming transistor may be a FinFET, while the GAA read transistor may be a nanosheet transistor. However, it should be understood that the layouts of fig. 5-8 may be used to fabricate any of a variety of other transistor combinations. For example, the non-GAA programming transistor may be a planar transistor, while the GAA read transistor may be a nanowire transistor. In another example, the non-GAA programming transistor may be a FinFET and the GAA read transistor may be a nanowire transistor. In yet another example, the non-GAA program transistor may be a FinFET and the GAA read transistor may be a vertical (vertical) transistor.

As a representative example, each of the layouts of fig. 5-8 is configured to fabricate an anti-fuse memory device similar to memory device 300 shown in fig. 3, where memory device 300 includes a non-GAA program transistor and a GAA read transistor. Accordingly, a discussion of fig. 5-8 will be provided below in connection with fig. 3. It will be appreciated that the layouts shown in figures 5 to 8 have been simplified for illustrative purposes. Accordingly, each layout may include one or more other features, and such other features are likewise maintained within the scope of the present disclosure.

Referring to fig. 5, fig. 5 shows a layout 500 according to some embodiments. Layout 500 includes a feature 501 (hereinafter referred to as cell boundary 501) that defines the boundary of an antifuse memory cell. At the cell boundary 501, the layout 500 includes various features, each corresponding to one or more patterning processes (e.g., photolithography) to form physical device features.

For example, the layout 500 includes

active features

502A and 502B as well as gate features 504 and 506. The active feature 502A extending along the X-direction may be configured to define a first active region, such as the first active region 306A of fig. 3. The active feature 502B extending along the X-direction may be configured to define a second active region, such as the second active region 306B of fig. 3. Hereinafter, the

active features

502A and 502B may sometimes be referred to as active regions 502A (306A) and 502B (306B), respectively. The gate features 504 extending along the Y-direction may be configured to form a first gate structure, such as the gate structure 308 of fig. 3. The gate feature 506 extending along the Y-direction may be configured to form a second gate structure, such as the gate structure 310 of fig. 3. Hereinafter, gate features 504 and 506 may sometimes be referred to as gate structures 504(308) and 506(310), respectively. In some embodiments, the width W of the gate structure 504(308)₁(extending along the X direction) may be wider than the width W of the gate structures 506(310)₂(extending in the X direction) as shown in fig. 5. In some other embodiments, the width W₁May be equal to the width W₂。

Each gate feature may travel across a corresponding one of the active features to form one or more sub-active features on sides of the gate feature, which may be configured to form a corresponding source/drain structure. For example, in fig. 5, the gate feature 504 travels across the active feature 502A to form the sub-active features 508 and 510, wherein the sub-active features 508 and 510 may be used to form source/drain structures, such as the source/

drain structures

316 and 318 of fig. 3. The gate feature 506 travels across the active feature 502B to form

sub-active features

512 and 514, wherein the sub-active features 508 and 510 may be used to form source/drain structures, such as the source/

drain structures

320 and 322 of fig. 3. The sub-active features 508, 510, 512, and 514 may sometimes be referred to as source/drain structures 508(316), 510(318), 512(320), and 514(322), respectively, hereinafter.

In some embodiments, the portion of the active region 502A (306A) covered by the gate structure 504(308) is configured to form a channel of a non-GAA transistor, such as the protrusion structure 332 of fig. 3. The portion of the active region 502B (306B) covered by the gate structure 506(310) is configured to form a channel of a GAA transistor, such as the semiconductor layers 342a-342c of fig. 3. As such, the non-GAA programming transistor 302 (fig. 3) may be formed based on the active feature 502A and the gate feature 504 of the layout 500; and the GAA read transistor 304 (fig. 3) may be formed based on the active feature 502B and the gate feature 506 of the layout 500.

In forming the non-GAA program transistor 302 and the GAA read transistor 304, a plurality of interconnect structures may be formed to operate the program transistor 302 and the read transistor 304. For example, the drain of the program transistor 302 (e.g., source/drain structures 510(318)) and the source of the read transistor 304 (e.g., source/drain structures 512(320)) are interconnected by an interconnect structure; the gates of the program transistors 302 (e.g., gate structures 504(308)) and the read transistors 304 (e.g., gate structures 506(310)) may be connected to interconnection structures for WLP (e.g., program word line 130 of FIG. 1) and WLR (e.g., read word line 132 of FIG. 1), respectively; the drain of the read transistor 304 (e.g., source/drain structure 514(322)) may be connected to an interconnect structure that serves as a BL (e.g., bit line 134 of FIG. 1).

As shown in the example of fig. 5, layout 500 includes features that form these interconnect structures (e.g., WLP, WLR, BL, etc.), as well as additional interconnect structures that connect those interconnect structures. For example, layout 500 includes

features

520, 522, 524, and 526 that extend along the Y-direction.

Features

520, 522, 524, and 526 are configured to form interconnect structures to connect to source/drain structures 508(316), source/drain structures 510(318), source/drain structures 512(320), and source/drain structures 514(322), respectively. These interconnect structures connected to the source/drain structures are sometimes referred to as MD, where MD may be formed as a slit (slot) or trench (trench) structure. Accordingly, features 520, 522, 524, and 526 may be referred to hereinafter as MD 520, MD 522, MD 524, and MD 526, respectively.

Layout 500 further includes

features

528, 530, and 532 configured to form interconnect structures to connect to

MDs

522, 524, and 526, respectively. Such an interconnect structure is sometimes referred to as a VD, where the VD can be formed as a via (via) structure. Thus, features 528, 530, and 532 may be referred to hereinafter as VD 528, VD 530, and VD 532, respectively.

Layout 500 further includes

features

534 and 536, both extending along the X-direction. The feature 534 is configured to form an interconnect structure that interconnects the program transistor 302 and the read transistor 304 together, the feature 534 being referred to hereinafter as the interconnect structure 534. For example, the source/drain structures 510(318) of the program transistor 302 may be connected to the source/drain structures 512(320) of the read transistor 304 via MD 522, VD 528, interconnect 534, VD 530, and MD 524. The feature 536 is configured to form an interconnect structure as a BL, the feature 536 being referred to hereinafter as a bit line 536. The bit line 536 can be connected to the source/drain structure 514(322) of the read transistor 304 via VD 532 and MD 526.

Layout 500 further includes

features

538 and 540, both extending along the Y-direction.

Features

538 and 540 are arranged to form interconnect structures for WLP and WLR, respectively, features 538 and 540 are referred to hereinafter as program Wordline (WLP)538 and read Wordline (WLR) 540. The program word line 538 may be connected to the gate structure 504(308) of the program transistor 302 via an interconnect structure sometimes referred to as VG (not shown), while the read word line 540 may be connected to the gate structure 506(310) of the read transistor 304 via another VG (not shown). In some embodiments, these VGs may be formed as a via structure.

In some embodiments, MD 520-526, VD 528-532, and VG, not shown, may be disposed in a middle-end-of-line (MEOL) mesh system (network). The interconnect structure 534 and the bit lines 536 may be disposed in a first metallization (metallization) layer of a back-end-of-line (BEOL) mesh system. The program word line 538 and the read word line 540 may be disposed in a second metallization layer of a back end of line (BEOL) networking system. The second metallization layer may be disposed over the first metallization layer, and the first metallization layer may be disposed over the MEOL mesh system.

Referring to fig. 6, fig. 6 shows a layout 600 according to some embodiments. Layout 600 is similar to layout 500, except that layout 600 also includes features for forming one or more dummy gate structures. Accordingly, the discussion of FIG. 6 below will again use some of the reference symbols of FIG. 5.

As shown, layout 600 further includes

features

602 and 604, both extending along the Y-direction. The

features

602 and 604 may be configured to form dummy gate structures, the

features

602 and 604 being referred to hereinafter as

dummy gate structures

602 and 604. In some embodiments, the dummy gate structures 602-604 may be similar to the gate structures 308-310 of FIG. 3 (e.g., extending along the Y direction), but may not travel across any active region. Therefore, the dummy gate structures 602-604 will not be used as active gate structures to electrically control current flow in a completed semiconductor device (e.g., the memory device 300 of FIG. 3). As shown in fig. 6, a dummy gate structure 602 is disposed along one side of the cell boundary 501. The dummy gate structure 604 is disposed between the active regions 502A (306A) and 502B (306B).

Referring to fig. 7, fig. 7 shows a layout 700 according to some embodiments. Layout 700 is similar to layout 600 except that layout 700 also includes features that form one or more interconnect structures. Accordingly, the discussion of FIG. 7 below will again use some of the reference symbols of FIG. 6.

As shown, layout 700 further includes features 702, features 702 being configured to form an interconnect structure (e.g., VD). Hereinafter, the feature 702 may be referred to as a VD 702. Similar to VD's 528 and 530, VD 702 is configured to couple to a corresponding MD (e.g., MD 520). Layout 700 further includes features 704 that are similar to features 534, except that in addition to being connected to VDs 528 and 530, features 704 are configured to form an interconnect structure that is connected to VD 702. In other words, the feature 704 may further extend across the gate structure 504(308), such as along the X-direction across the gate structure 504 (308). Hereinafter, the features 704 may sometimes be referred to as interconnect structures 704. Source/drain structures 508(316) connected to MD 520, source/drain structures 510(318) connected to MD 522, and source/drain structures 512(320) connected to MD 524 may be interconnected with each other by forming interconnect structure 704.

Referring to fig. 8, fig. 8 shows a layout 800 according to some embodiments. Layout 800 is similar to layout 600 except that layout 800 also includes features that form active regions that are partially covered by corresponding gate structures. Accordingly, the discussion of FIG. 8 below will again use some of the reference symbols of FIG. 6.

As shown, the layout 800 includes a feature 802A, the feature 802A configured to form an active region. Hereinafter, the feature 802A may sometimes be referred to as an active region 802A. The active region 802A is similar to the active region 502A (306A) shown in fig. 5-7, except that the active region 802A is partially covered by the gate structure 504 (308). Specifically, in some embodiments, the portion of the active region 802A covered by the gate structure 504(308) is offset from the active region 502B (306B). As such, when layout 800 is used to form memory device 300 of fig. 3, memory device 300 does not have source/drain structure 316. Further, the protrusion structure 332 formed by the portion of the active region 802A covered by the gate structures 504(308) may have additional sidewalls also covered by the gate structures 504 (308). The sidewalls should already be coupled to the source/drain structures 316. The programming transistor 302 having only one source/drain structure (e.g., source/drain structure 318) coupled to its channel (e.g., protruding structure 332) may sometimes be referred to as a MOS (or MOSFET) capacitor.

Fig. 9 and 10 illustrate various examples of design layouts for fabricating an anti-fuse cell, according to some embodiments. The layouts of fig. 9 and 10 may each be used to fabricate an anti-fuse memory cell having one programming transistor and two read transistors, such as memory cell 200 of fig. 2. Furthermore, in some embodiments, the program transistor may be formed as a non-GAA transistor, while the read transistor may be formed as a GAA transistor. For example, the non-GAA programming transistors may be finfets, while each GAA read transistor may be a nanosheet transistor. However, it should be understood that the layouts of fig. 9 and 10 may be used to fabricate any of a variety of other transistor combinations, and these embodiments are also included within the scope of the present disclosure.

As a representative example, each of the layouts of fig. 9 and 10 is configured to fabricate an antifuse memory device similar to memory device 400 shown in fig. 4, where memory device 400 includes a non-GAA program transistor and two GAA read transistors. Accordingly, a discussion of fig. 9 and 10 will be provided below in conjunction with fig. 4. It should be understood that the layouts shown in fig. 9 and 10 have been simplified for illustrative purposes. Accordingly, each layout may include one or more other features, and such other features are likewise maintained within the scope of the present disclosure.

Referring to fig. 9, fig. 9 shows a layout 900 according to some embodiments. Layout 900 includes features 901 that define the boundaries of the anti-fuse memory cells (hereinafter referred to as cell boundaries 901). Above the cell boundary 901, the layout 900 includes various features, each corresponding to one or more patterning processes (e.g., photolithography processes) to form physical device features.

For example, layout 900 includes

active features

902A and 902B, and also includes gate features 904, 906, and 908. The active feature 902A extending along the X-direction may be configured to define a first active region, such as the first active region 408A of fig. 4. The active feature 902B extending along the X-direction may be configured to define a second active region, such as the second active region 408B of fig. 4. Hereinafter, the

active features

902A and 902B may sometimes be referred to as active regions 902A (408A) and 902B (408B), respectively. The gate feature 904 extending along the Y-direction may be configured to form a first gate structure, such as that of fig. 4A gate structure 410. The gate feature 906 extending along the Y-direction may be configured to form a second gate structure, such as the gate structure 412 of fig. 4. The gate feature 908 extending along the Y-direction may be configured to form a third gate structure, such as the gate structure 414 of fig. 4. Hereinafter, the gate features 904, 906, and 908 may sometimes be referred to as gate structures 904(410), 906(412), and 908(414), respectively. In some embodiments, the width W of the gate structure 904(410)₃(extending along the X direction) may be wider than the width W of the gate structures 906(412) and 908(414)₄(extending in the X-direction) as shown in fig. 9. In some other embodiments, the width W₃May be equal to the width W₄。

Each gate feature may be advanced across a corresponding one of the active features to form one or more sub-active features on the sides of the gate feature, which may be configured to form a corresponding source/drain structure. For example, in fig. 9, the gate feature 904 travels across the active feature 902A to form

sub-active features

910 and 912, which sub-active features 910 and 912 may be used to form source/drain structures, such as the source/

drain structures

416 and 418 of fig. 4. Gate features 906 and 908 respectively travel across active feature 902B to form

sub-active features

914, 916, and 918, which sub-active features 914, 916, and 918 may be used to form source/drain structures, such as source/

drain structures

420, 422, and 424 of fig. 4, respectively. The sub-active features 910, 912, 914, 916, and 918 may sometimes be referred to as source/drain structures 910(416), 912(418), 914(420), 916(422), and 918(424), respectively, hereinafter.

In some embodiments, the portion of the active region 902A (408A) covered by the gate structure 904(410) is configured to form a channel of a non-GAA transistor, such as the overhang structure 432 of fig. 4. The portion of the active region 902B (408B) covered by the gate structure 906(412) is configured to form a channel of a first GAA transistor, such as the semiconductor layers 442a-442c of fig. 4. The portion of the active region 902B (408B) covered by the gate structure 908(414) is configured to form a channel of a second GAA transistor, such as the semiconductor layers 452a-452c of fig. 4. As such, the non-GAA programming transistor 402 (fig. 4) may be formed based on the active feature 902A and the gate feature 904 of the layout 900; the GAA read transistor 404 (fig. 4) may be formed based on the active feature 902B and the gate feature 906 of the layout 900; and the GAA read transistor 406 (fig. 4) may be formed based on the active feature 902B and the gate feature 908 of the layout 900.

In forming the non-GAA program transistor 402 and the GAA read

transistor

404 and 406, a plurality of interconnect structures may be formed to operate the program transistor 402 and the

read transistor

404 and 406. For example, the drain of the program transistor 402 (e.g., source/drain structures 912(418)) and the source of the read transistor 404 (e.g., source/drain structures 914(420)) are interconnected by an interconnect structure; the gates of the program transistors 402 (e.g., gate structures 904(410)), the read transistors 404 (e.g., gate structures 906(412)), and the read transistors 406 (e.g., gate structures 908(414)) may be connected to interconnect structures that may be WLP (e.g., program wordline 240 of FIG. 2), WLR1 (e.g., first read wordline 242 of FIG. 2), and WLR2 (e.g., second read wordline 244 of FIG. 2), respectively; the drain of the read transistor 406 (e.g., source/drain structure 918(424)) may be connected to an interconnect structure that serves as a BL (e.g., bit line 250 of FIG. 2).

As shown in the example of fig. 9, layout 900 includes features that form these interconnect structures (e.g., WLP, WLR1, WLR2, BL, etc.), as well as additional interconnect structures that connect those interconnect structures. For example, layout 900 includes

features

920, 922, 924, 926, and 928 that extend along the Y-direction.

Features

920, 922, 924, 926, and 928 are configured to form interconnect structures to connect to source/drain structure 910(416), source/drain structure 912(418), source/drain structure 914(420), source/drain structure 916(422), and source/drain structure 918(424), respectively. These interconnect structures connected to the source/drain structures are sometimes referred to as MD. Accordingly, features 920, 922, 924, 926, and 928 may be referred to hereinafter as MD 920, MD 922, MD 924, MD 926, and MD 928, respectively.

Layout 900 further includes

features

930, 932, and 934 configured to form an interconnect structure to connect to

MDs

922, 924, and 928, respectively. Such an interconnect structure is sometimes referred to as a VD. Thus, the

features

930, 932, and 934 can be referred to hereinafter as VD 930, VD 932, and VD 934, respectively.

Layout 900 further includes

features

940 and 942, both extending along the X direction. Features 940 are configured to form an interconnect structure that interconnects program transistor 402 and read transistor 404 together, features 940 being referred to hereinafter as interconnect structures 940. For example, the source/drain structures 912(418) of the program transistor 402 may be connected to the source/drain structures 914(420) of the read transistor 404 via MD 922, VD 930, interconnect 940, VD 932, and MD 924. The features 942 are configured to form an interconnect structure as a BL, the features 942 being referred to hereinafter as bit lines 942. The bit line 942 is connected to the source/drain structure 918(424) of the read transistor 406 via VD 934 and MD 928.

Layout 900 further includes

features

944, 946, and 948, all extending along the Y direction.

Features

944, 946, and 948 are configured to form interconnect structures for WLP, WLR1, and WLR2, respectively, the

features

944, 946, and 948 being referred to hereinafter as a program Wordline (WLP)944, a first read wordline (WLR1)946, and a second read wordline (WLR2)948, respectively. The program word line 944 may be connected to the gate structures 904(410) of the program transistors 402 via an interconnect sometimes referred to as VG (not shown), the first read word line 946 may be connected to the gate structures 906(412) of the read transistors 404 via another VG (not shown), and the second read word line 948 may be connected to the gate structures 908(414) of the read transistors 406 via yet another VG (not shown).

In some embodiments, MD 920-928, VD 930-934, and VG, not shown, may be disposed in a middle of line (MEOL) mesh system. The interconnect structure 940 and the bit lines 942 may be disposed in a first metallization layer of a back end of line (BEOL) net system. The program wordline 538, the first read wordline 946, and the second read wordline 948 may be disposed in a second metallization layer of a back end of line (BEOL) networking system. The second metallization layer may be disposed over the first metallization layer, and the first metallization layer may be disposed over the MEOL mesh system.

Fig. 10, fig. 10 shows a layout 1000 according to some embodiments. Layout 1000 is similar to layout 900, except that layout 1000 also includes features for forming one or more dummy gate structures. Accordingly, the discussion of FIG. 10 below will again use some of the reference symbols of FIG. 9.

As shown, layout 1000 further includes features 1002 and 1004, both extending along the Y-direction. The features 1002 and 1004 may be configured to form dummy gate structures, the features 1002 and 1004 being referred to hereinafter as dummy gate structures 1002 and 1004. In some embodiments, the dummy gate structures 1002-1004 may be similar to the gate structures 410-414 of FIG. 4 (e.g., extending along the Y direction), but may not travel across any active regions. Therefore, the dummy gate structures 1002-1004 will not be used as active gate structures to electrically control current flow in a completed semiconductor device (e.g., the memory device 400 of FIG. 4). As shown in fig. 10, a dummy gate structure 1002 is disposed along one side of the cell boundary 901. The dummy gate structure 1004 is disposed between the active regions 902A (408A) and 902B (408B).

Fig. 11 shows a flow diagram of a method 1100, the method 1100 defining a first active region and a second active region on a substrate, according to one or more embodiments of the present disclosure. The first active region and the second active region may be laterally separated from each other by at least one isolation structure. In some embodiments, the first active region may include structures protruding from the substrate (e.g., fin structures), while the second active region may include a plurality of nanostructures (e.g., nanoplates, nanowires, or other semiconductor layers having dimensions on the nanometer scale) alternately stacked on top of one another. After defining the first and second active regions, the method 1100 may be continued from the method 1800 of fig. 18 to form one or more non-GAA transistors and one or more GAA transistors in the first and second active regions, respectively, as will be discussed further below.

The operations of method 1100 may be associated with cross-sectional views of memory device 1200 at various stages of fabrication as shown in fig. 12, 13, 14, 15, and 16. For example, the memory device 1200 may be similar to the memory device 300 of FIG. 3 or the memory device 400 of FIG. 4. The cross-sectional views of fig. 12 to 16 may be cross-sectional views taken along line a-a' of fig. 3 and 4. In some embodiments, memory device 1200 may be included in or otherwise coupled to a microprocessor, another memory device, and/or other Integrated Circuit (IC). In addition, fig. 12-16 are simplified to better understand the concepts of the present disclosure. Although the drawings show a memory device 1200, it should be understood that an IC may include many other devices, such as inductors (inductors), resistors, capacitors (capacitors), transistors, etc., which are not shown in fig. 12-16 for clarity of illustration.

Briefly summarizing the method 1100, the method 1100 begins with operation 1102 in which a semiconductor substrate is provided in operation 1102. Next, the method 1100 proceeds to operation 1104, where in operation 1104, the first region of the semiconductor substrate is masked (mask). The method 1100 then advances to operation 1106, where in operation 1106, a second region of the semiconductor substrate is etched to form a recess. Next, in operation 1108, a plurality of first semiconductor layers and a plurality of second semiconductor layers are epitaxially grown (epitaxially grow) in the grooves to be alternately stacked on top of one another. After growing the first semiconductor layer and the second semiconductor layer in the second region, the method 1100 proceeds to operation 1110, in which operation 1110 a first active region and a second active region are defined.

Fig. 12 is a cross-sectional view of a memory device 1200 at one of various stages of fabrication, corresponding to operation 1102 of fig. 11, in which the memory device 1200 includes a semiconductor substrate 1202.

The semiconductor substrate 1202 comprises a substrate of semiconductor material, such as silicon. Alternatively, the semiconductor substrate 1202 may comprise other elemental (e.g., germanium) semiconductor materials. The semiconductor substrate 1202 may also include compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The semiconductor substrate 1202 may comprise an alloy (alloy) semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and indium gallium phosphide. In one embodiment, the semiconductor substrate 1202 includes an epitaxial layer. For example, the semiconductor substrate 1202 may have an epitaxial layer overlying a bulk semiconductor. In addition, the semiconductor substrate 1202 may include a semiconductor-on-insulator (SOI) structure. For example, the semiconductor substrate 1202 may include a Buried Oxide (BOX) layer, and the process of forming the BOX layer may include, for example, separation by implantation (SIMOX) or other suitable techniques such as wafer bonding (bonding) and grinding (grinding).

Corresponding to operation 1104 of fig. 11, fig. 13 is a cross-sectional view of the memory device 1200 at one of the various stages of fabrication, wherein the memory device 1200 includes a patterned mask 1304 formed on a top surface 1203 of a semiconductor substrate 1202.

The patterned mask 1304 covers a first region 1202A (also referred to as region 1202A) of the semiconductor substrate 1202, and the patterned mask 1304 includes an opening that exposes a second region 1202B (also referred to as region 1202B) of the semiconductor substrate 1202. In one embodiment, the first region 1202A may include active regions defined for forming one or more non-GAA transistors (e.g., the programming transistor 302 of fig. 3, the programming transistor 402 of fig. 4) configured as n-type transistors, while the second region 1202B may include active regions defined for forming one or more GAA transistors (e.g., the read transistor 304 of fig. 3, the first read transistor 404 of fig. 4, and the second read transistor 406) configured as n-type transistors. As such, the first and second regions 1202A and 1202B may be doped with p-type dopants. It is understood that the memory device 1200 may alternatively have p-type transistors formed in the first and second regions 1202A, 1202B.

The patterned mask 1304 may be a soft mask such as a patterned photoresist (resist) layer, or a hard mask such as a dielectric material layer, or a combination thereof. In the embodiment shown in FIG. 13, the patterned mask 1304 includes a hard mask 1306 disposed over the first region 1202A, and a patterned photoresist layer 1308 lithographically formed over the hard mask 1306. The hard mask 1306 is etched to transfer the opening from the patterned photoresist layer 1308 to the hard mask 1306. For example, the hardmask 1306 may comprise silicon oxide, silicon nitride, silicon oxynitride (silicon oxynitride), silicon carbide, silicon carbonitride (silicon carbonitride), silicon oxycarbide (silicon carbonitride), other semiconductor materials, and/or other dielectric materials. In one embodiment, the thickness of the hardmask 1306 is in a range from about 1 nanometer (nm) to about 40 nm. The hardmask 1306 may be formed by: thermal oxidation (thermal oxidation), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or any other suitable method. Exemplary photolithography processes may include forming a photoresist layer, exposing the photoresist through a photolithography exposure process, performing a post-exposure bake (post-bake) process, and developing the photoresist layer to form a patterned photoresist layer. The lithography process may alternatively be replaced by other techniques, such as e-beam writing, ion-beam writing, mask-less patterning, or molecular printing. In some embodiments, the patterned photoresist layer 1308 may be directly used as an etching mask in a subsequent etching process. After patterning the hard mask 1306, the patterned photoresist layer 1308 may be removed by a suitable process, such as wet stripping (wet stripping) or plasma ashing (plasma ashing).

Figure 14 is a cross-sectional view of memory device 1200 at one of the various stages of fabrication, in which memory device 1200 is etched to form recess 1402, corresponding to operation 1106 of figure 11.

The semiconductor substrate 1202 in the second region 1202B is etched to form a recess 1402. The etch process is designed to selectively remove the semiconductor substrate 1202 in the second region 1202B using the hard mask 1306 as an etch mask. The etch process may be continued to ensure that the bottom surface 1205 of the semiconductor substrate 1202 is exposed in the recess 1402. Sidewalls 1207 of the semiconductor substrate 1202 in the first region 1202A are also exposed and define edges of the recess 1402. The etching process may include dry etching, wet etching, or a combination thereof. The patterned hard mask 1306 protects the semiconductor substrate 1202 in the first region 1202A during etching. In various examples, the etching process may include dry etching using a suitable etchant, such as fluorine-containing (fluorine-containing) etchingEtching gases or chlorine-containing etching gases, e.g. Cl₂、CCl₂F₂、CF₄、SF₆、NF₃、CH₂F₂Or other suitable etching gas. In some other examples, the etching process may include a wet etch using a suitable etchant, such as a hydrofluoric acid (HF) based solution, a sulfuric acid (H) based solution₂SO₄) A solution based on hydrochloric acid (HCl), a solution based on ammonium hydroxide (NH)₄OH), other suitable etching solutions, or combinations thereof. The etching process may include more than one step.

Corresponding to operation 1108 of fig. 11, fig. 15 is a cross-sectional view of a memory device 1200 at one of various stages of fabrication, wherein the memory device 1200 includes a plurality of first semiconductor layers 1502 (e.g.,

first semiconductor layers

1502a, 1502b, and 1502c) and a plurality of second semiconductor layers 1504 (e.g.,

second semiconductor layers

1504a, 1504b, and 1504 c).

In some embodiments, first semiconductor layers 1502a-1502c and second semiconductor layers 1504a-1504c are alternately disposed on top of one another (e.g., alternately disposed along the Z-direction) in recesses 1402 (FIG. 14) to form a stack. For example, one of the second semiconductor layers (e.g., second semiconductor layer 1504a) is disposed over one of the first semiconductor layers (e.g., first semiconductor layer 1502a), then the other first semiconductor layer (e.g., first semiconductor layer 1502b) is disposed over second semiconductor layer 1504a, and so on.

In various embodiments, the stack can include any number of alternating first semiconductor layers 1502 and second semiconductor layers 1504. The first semiconductor layer 1502 and the second semiconductor layer 1504 may have different thicknesses. One layer of the first semiconductor layer 1502 may have a different thickness from another layer. One layer of the second semiconductor layer 1504 may have a different thickness from another layer. The thickness of each of the first semiconductor layer 1502 and the second semiconductor layer 1504 may be in a range from several nanometers to several tens of nanometers. A first layer in the stack may be thicker than the other first semiconductor layer 1502 and second semiconductor layer 1504. For example, the first semiconductor layer 1502a can be thicker than the first semiconductor layers 1502b-1502c and the second semiconductor layers 1504a-1504 c. In one embodiment, the thickness of each of the first semiconductor layers 1502a-1502c is in the range of about 5nm to about 20nm, while the thickness of each of the second semiconductor layers 1504a-1504c is in the range of about 5nm to about 20 nm.

Both the first semiconductor layer 1502 and the second semiconductor layer 1504 may have different compositions (compositions). In various embodiments, the first semiconductor layer 1502 and the second semiconductor layer 1504 both have compositions that provide different oxidation rates and/or different etch selectivities from layer to layer. In one embodiment, the first semiconductor layer 1502 comprises silicon germanium (Si)_1-xGe_x) And the second semiconductor layer 1504 includes silicon (Si). In one embodiment, each of the second semiconductor layers 1504 is silicon and may be undoped or substantially dopant free (i.e., having an extrinsic (extrinsic) dopant concentration from about 0cm^-3To about 1x10¹⁷cm^-3) As an example, when the second semiconductor layer 1504 is formed (for example: silicon), no intentional doping is performed. Alternatively, the second semiconductor layer 1504 may be intentionally doped. For example, each of the second semiconductor layers 1504 may be silicon and doped with a P-type dopant such As boron (B), aluminum (Al), indium (In), and gallium (Ga) to form a P-type channel, or doped with an n-type dopant such As phosphorus (P), arsenic (As), antimony (Sb) to form an n-type channel. In some embodiments, each of the first semiconductor layers 1502 is Si_1-xGe_xComprising Ge in a molar ratio (molar ratio) of less than 50% (x < 0.5). For example, Ge may account for Si in molar ratios_1-xGe_xAbout 15% to 35% of the first semiconductor layer 1502 is composed. In addition, the first semiconductor layer 1502 may have a different composition therebetween, and the second semiconductor layer 1504 may have a different composition therebetween.

In various embodiments, the first semiconductor layer 1502 or the second semiconductor layer 1504 may include other materials, for example, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide, and alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. The materials of the first semiconductor layer 1502 and the second semiconductor layer 1504 may be selected based on providing different oxidation rates and/or etch selectivities. As described above, the first semiconductor layer 1502 and the second semiconductor layer 1504 may be doped or undoped.

In various embodiments, a first semiconductor layer 1502 and a second semiconductor layer 1504 are epitaxially grown from the bottom surface 1205 in the second region 1202B. For example, each of the first semiconductor layer 1502 and the second semiconductor layer 1504 can be grown by: a Molecular Beam Epitaxy (MBE) process, a Chemical Vapor Deposition (CVD) process such as a Metal Organic CVD (MOCVD) process, and/or other suitable epitaxial growth processes. During the epitaxial growth, the crystal structure of the semiconductor substrate 1202 extends upward (e.g., along the Z-direction), and as a result, the first semiconductor layer 1502 and the second semiconductor layer 1504 have the same crystal orientation (crystal orientation) as the semiconductor substrate 1202.

In the first region 1202A, a hard mask 1306 (fig. 14) may act as a capping layer on the top surface 1203 of the semiconductor substrate 1202 to prevent epitaxial growth from occurring in the first region 1202A. Although not shown, an optional dielectric layer may be formed to extend along the sidewalls 1207. As such, the dielectric layer may cover the sidewalls 1207, thereby preventing epitaxial growth from the sidewalls 1207 such that epitaxial growth does not occur in a lateral direction from the sidewalls 1207 into the second region 1202B. Thus, in some embodiments, epitaxial growth of the first semiconductor layer 1502 and the second semiconductor layer 1504 is confined to the second region 1202B. In some embodiments, after forming a desired number of the first semiconductor layer 1502 and the second semiconductor layer 1504 (e.g., the third second semiconductor layer 1504c), a polishing (polishing) process (e.g., a Chemical Mechanical Polishing (CMP) process) may be performed to level the first region 1202A with the second region 1202B.

Corresponding to operation 1110 of fig. 11, fig. 16 is a cross-sectional view of memory device 1200 at one of various stages of fabrication, wherein memory device 1200 includes a first active structure 1602A and a second active structure 1602B.

The first active structures 1602A may be formed in a first region 1202A where the alternately stacked semiconductor layers (e.g., the first semiconductor layer 1502 and the second semiconductor layer 1504) are not formed, and the second active structures 1602B may be formed in a second region 1202B where the alternately stacked semiconductor layers (e.g., the first semiconductor layer 1502 and the second semiconductor layer 1504) are formed. As will be discussed below, the corresponding region of the first active structure 1602A (hereinafter referred to as "first active region 1603A") is defined as a region or footprint (footprint) where one or more non-GAA transistors (e.g., the program transistor 302 of fig. 3, the program transistor 402 of fig. 4) are to be formed, and the corresponding region of the second active structure 1602B (hereinafter referred to as "second active region 1603B") is defined as a region or footprint where one or more GAA transistors (e.g., the read transistor 304 of fig. 3, the first read transistor 404 of fig. 4, and the second read transistor 406) are to be formed.

As shown in fig. 16, the first active structures 1602A are formed as fin structures protruding from the semiconductor substrate 1202, and the second active structures 1602B are formed as alternating semiconductor layer rows (columns) disposed above the semiconductor substrate 1202. In some embodiments, the first active structure 1602A may be a unitary continuous structure extending from the semiconductor substrate 1202. The first active structure 1602A may be elongated along a lateral direction (e.g., the X-direction). The second active structure 1602B includes a stack of a semiconductor layer 1610 and a semiconductor layer 1620 interleaved with each other.

In the formation of the first active structure 1602A and the second active structure 1602B, a patterned mask 1625A and a patterned mask 1625B (shown in dashed lines) may be formed in the first region 1202A and the second region 1202B, respectively, over the semiconductor substrate 1202. The patterned mask 1625A and the patterned mask 1625B may define the coverage areas of the first active structure 1602A and the second active structure 1602B (e.g., by masking the first active structure 1602A or the second active structure 1602B to be formed), and one or more etching processes may be applied to the semiconductor substrate 1202 in the first region 1202A and the first semiconductor layer 1502 and the second semiconductor layer 1504 in the second region 1202B, respectively, to form the first active structure 1602A and the second active structure 1602B. Thus, a first active region 1603A and a second active region 1603B may be defined. In some embodiments, the

semiconductor layers

1610a, 1620a, 1610b, 1620b, 1610c and 1620c may be the remaining portions of the first semiconductor layer 1502a, the second semiconductor layer 1504a, the first semiconductor layer 1502b, the second semiconductor layer 1504b, the first semiconductor layer 1502c and the second semiconductor layer 1504c, respectively. After forming first active structure 1602A and second active structure 1602B, patterned mask 1625A and patterned mask 1625B may be removed.

The one or more etching processes may include one or more dry etching processes, wet etching processes, and other suitable etching techniques. For example, the dry etching process may be performed with an oxygen-containing gas, a fluorine-containing gas (e.g., CF)₄、SF₆、CH₂F₂、CHF₃And/or C₂F₆) Chlorine-containing gas (for example: cl₂、CHCl₂、CCl₄And/or BCl₃) Bromine-containing gas (for example: HBr and/or CHBR₃) An iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. For example, a wet etch process may include etching in the following solutions: dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia (ammonia), hydrofluoric acid (HF) solution, nitric acid (nitric acid, HNO)₃) And/or acetic acid (CH)₃COOH), or other suitable wet etchant.

In some embodiments, patterned mask 1625A and patterned mask 1625B used to form first active structure 1602A and second active structure 1602B may be formed according to various active features of a layout. In various embodiments, any one of the layouts 500-1000 of fig. 5-10 may be used to form the first active structure 1602A and the second active structure 1602B and to form the corresponding first active region 1603A and the second active region 1603B. For example, after growing the first semiconductor layer 1502 and the second semiconductor layer 1504 (fig. 15) in corresponding regions over the semiconductor substrate, the

active features

502A and 502B as shown in fig. 5-8 may be used to form the first active structure 1602A and the second active structure 1602B, respectively, and thus define the first active region 1603A and the second active region 1603B, respectively. In another example, after growing the first semiconductor layer 1502 and the second semiconductor layer 1504 (fig. 15) in corresponding regions above the semiconductor substrate, the

active features

902A and 902B as shown in fig. 9-10 may be used to form the first active structure 1602A and the second active structure 1602B, respectively, and thus define the first active region 1603A and the second active region 1603B, respectively.

After forming the first active structure 1602A and the second active structure 1602B, one or more isolation structures 1630 may be formed between the first active structure 1602A and the second active structure 1602B. Isolation structures 1630 formed of an insulating material may electrically isolate adjacent active structures from each other. The insulating material may be an oxide, nitride, etc., such as silicon oxide, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), Flowable Chemical Vapor Deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-hardening to convert it to another material, such as an oxide), or the like, or a combination thereof. Other insulating materials and/or other formation processes may also be used. In one example, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. A planarization process, such as a Chemical Mechanical Polishing (CMP) process, may remove any excess insulating material and form a top surface of coplanar (coplanar) insulating material and top surfaces of patterned

masks

1625A and 1625B (not shown).

Patterned masks

1625A and 1625B may also be removed by a planarization process.

Next, an insulating material is dug (stress) to form an isolation structure 1630 as shown in fig. 16, the isolation structure 1630 sometimes referred to as a Shallow Trench Isolation (STI). Isolation structures 1630 are dug in such a way that first active structure 1602A and second active structure 1602B protrude from between adjacent isolation structures 1630. The top surface of the respective isolation Structures (STI)1630 may have a planar surface (as shown), a convex surface, a concave surface (e.g., dishing), or a combination thereof. The top surface of isolation structures 1630 may be formed flat, convex, and/or concave by appropriate etching. The isolation structures 1630 may be dug using an acceptable etch process, such as an etch process that is selective to the material of the isolation structures 1630. For example, a dry etch or a wet etch process using dilute hydrofluoric acid (DHF) may be performed to dig into the isolation structures 1630.

Fig. 17 is a flow chart illustrating another method 1700 for defining a first active region 1603A and a second active region 1603B according to one or more embodiments of the present disclosure. Similar to the method 1100 of fig. 11, the method 1700 may be continued from the method 1800 of fig. 18 to form one or more non-GAA transistors and one or more GAA transistors in the first and second active regions, respectively, as will be discussed further below. The operation of method 1700 will be briefly discussed below with reference to the cross-sectional views of fig. 12-16.

For example, the method 1700 begins with operation 1702 in which a semiconductor substrate 1202 is provided (fig. 12) in operation 1702. Next, rather than method 1100 (e.g., rather than growing first semiconductor layer 1502 and second semiconductor layer 1504 in recess 1402), method 1700 proceeds to operation 1704, where first semiconductor layer 1502 and second semiconductor layer 1504 are epitaxially grown over semiconductor substrate 1202 in operation 1704. The first semiconductor layers 1502 and the second semiconductor layers 1504 are alternately stacked on top of each other. The method 1700 then proceeds to operation 1706, where the second region 1202B is masked, followed by the first region 1202A being etched to form a recess, in operation 1708. Next, in operation 1710, a third semiconductor layer similar to the second semiconductor layer is epitaxially grown in the groove of the first region. After growing the third semiconductor layer in the first region, similar to method 1100, method 1700 proceeds to operation 1712 where, in operation 1712, first active structure 1602A and second active structure 1602B are defined.

As described above, method 1800 (fig. 18) may be continued after either of method 1100 (fig. 11) and method 1700 (fig. 17). In various embodiments, the operations of the method 1800 may form one or more non-GAA transistors and one or more GAA transistors in the first and second

active regions

1603A and 1603B, respectively.

Referring to fig. 18, fig. 18 depicts a flowchart of a method 1800 for forming at least one non-GAA transistor and at least one GAA transistor in the first active region 1603A and the second active region 1603B, respectively, according to one or more embodiments of the present disclosure. The operations of method 1800 may be associated with cross-sectional views of memory device 1200 at various stages of fabrication as shown in fig. 19A, 19B, 19C, 20, 21, 22, 23, 24, 25, 26, 27A, 27B, 27C, and 28. The cross-sectional views of fig. 19A, 20-27A, and 28 may be taken along the line a-a' shown in fig. 3 and 4; the cross-sectional views of fig. 19B and 27B may be taken along the line B-B' shown in fig. 3 and 4; and the cross-sectional views of fig. 19C and 27C may be taken along the line C-C' shown in fig. 3 and 4. Fig. 19A-28 are simplified to better understand the concepts of the present disclosure, and thus, it should be understood that the memory device 1200 may include many other devices, such as inductors, resistors, capacitors, transistors, etc., which are not shown in fig. 19A-28 for clarity of illustration.

Briefly summarizing the method 1800, the method 1800 begins with operation 1802 where a dummy gate structure is formed in operation 1802. Next, the method 1800 proceeds to operation 1804 where an end portion of the second active structure is removed in operation 1804. The method 1800 then continues to operation 1806 where, in operation 1806, inner spacers are formed in the second active structure. The method 1800 then continues with operation 1808, where in operation 1808, a source/drain structure coupled to the second active structure is formed. Next, the method 1800 proceeds to operation 1810, where in operation 1810, the end portions of the first active structure are removed. The method 1800 then continues to operation 1812 where source/drain structures coupled to the first active structure are formed in operation 1812. The method 1800 then continues to operation 1814 where an interlayer dielectric is formed in operation 1814. The method 1800 then continues to operation 1816, where the dummy gate structure is first removed, followed by removal of the first semiconductor layer from the second active structure in operation 1816. The method 1800 then continues to operation 1818 where an active gate structure is formed in operation 1818. The method 1800 then proceeds to operation 1820, where in operation 1820, an interconnect structure is formed.

Corresponding to operation 1802 of fig. 18, fig. 19A is a cross-sectional view, taken along line a-a', of memory device 1200 at one of various stages of fabrication, where memory device 1200 includes a first dummy gate structure 1902 (also referred to as dummy gate structure 1902) and a second dummy gate structure 1912 (also referred to as dummy gate structure 1912). For clarity, FIG. 19B shows a corresponding cross-sectional view of the memory device 1200 taken along line B-B '(e.g., as shown in FIGS. 3-4), and FIG. 19C shows a corresponding cross-sectional view of the memory device 1200 taken along line C-C' (e.g., as shown in FIGS. 3-4).

Each dummy gate structure includes a dummy gate dielectric, a dummy gate, and a hard mask. For example, in fig. 19A and 19B, the first dummy gate structure 1902 includes a dummy gate dielectric 1904 formed over the first active structure 1602A, a dummy gate 1906 formed over the dummy gate dielectric 1904, and a hard mask 1908 formed over the dummy gate 1906; in fig. 19A and 19C, the second dummy gate structure 1912 includes a dummy gate dielectric 1914 formed over the second active structure 1602B, a dummy gate 1916 formed over the dummy gate dielectric 1914, and a hard mask 1918 formed over the dummy gate 1916.

As shown in fig. 19A-19C, a dummy gate structure 1902 is formed on a top surface of the first active structure 1602A and surrounding sidewalls of the first active structure 1602A; and dummy gate structure 1912 is formed on the top surface of second active structure 1602B and surrounds the sidewalls of second active structure 1602B. To form dummy gate structure 1902 (the formation of dummy gate structure 1902 is used as a representative example), a dielectric layer is formed over first active structure 1602A. For example, the dielectric layer may be silicon oxide, silicon nitride, multilayers thereof, and the like, and the dielectric layer may be deposited or thermally grown. A gate layer is formed over the dielectric layer and a mask layer is formed over the gate layer. A gate layer may be deposited over the dielectric layer and then planarized, such as by CMP. A masking layer may be deposited over the gate layer. After the thin layers (e.g., dielectric layer, gate layer, and mask layer) are formed, the mask layer may be patterned using acceptable photolithography and etching techniques to form a hard mask 1908. The hard mask 1908 may then be patterned by an acceptable etch technique to the gate layer and dielectric layer to form a dummy gate 1906 and underlying dummy gate dielectric 1904, respectively. Dummy gate structures 1912 may be formed concurrently or additionally using similar operations as described above.

After forming the first dummy gate structure 1902 and the second dummy gate structure 1912,

gate spacers

1910 and 1920 may be formed to extend along the respective sidewalls of the first dummy gate structure 1902 and the second dummy gate structure 1912, respectively, as shown in fig. 19A.

Gate spacers

1910 and 1920 can be formed using a spacer pull down formation process.

Gate spacers

1910 and 1920 can also be formed by a conformably (conformal) deposited dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials, followed by a directional etch, such as a Reactive Ion Etch (RIE).

In some embodiments, the

dummy gate structures

1902 and 1912 may be formed according to the gate features of each of the layouts 500-1000 (fig. 5-10). Taking the layout 500 of fig. 5 as an example,

hard masks

1908 and 1918 may be patterned based on gate features 504 and 506, respectively. As such, the dummy gate structure 1902 may straddle or otherwise cover a central portion of the first active structure 1602A (e.g., a channel of a non-GAA transistor of the subsequently formed memory device 1200), wherein the first active structure 1602A is formed based on the active feature 502A; while dummy gate structure 1912 may straddle or otherwise cover a central portion of second active structure 1602B (e.g., a channel of a GAA transistor of subsequently formed memory device 1200), where second active structure 1602B is formed based on active feature 502B. Moreover, each of the

dummy gate structures

1902 and 1912 can have a longitudinal direction (e.g., along the Y-direction) that is substantially perpendicular to the longitudinal direction (e.g., along the X-direction) of the first active structure 1602A and the second active structure 1602B. In various embodiments,

dummy gate structures

1902 and 1912 may then be replaced with respective active gate structures, with

gate spacers

1910 and 1920 remaining substantially intact. Thus, when the memory device 1200 is completed, these active gate structures may be used as gates for non-GAA and GAA transistors, respectively, of the memory device 1200 (similar to the memory device 300 of fig. 3), as will be further illustrated in fig. 27A-27C.

Although two dummy gate structures are shown in fig. 19A-19C, it should be understood that the memory device 1200 may have more than two dummy gate structures, and these embodiments remain within the scope of the present disclosure as well. For example, when the layout 600-700 of fig. 6-7 is used to form dummy gate structures, in addition to the dummy gate structures above the active structures (formed based on gate features 504 and 506), at least one dummy gate structure may be formed between the active structures based on gate feature 604. These additional dummy gate structures also have gate spacers along their sidewalls, and may be formed over the isolation structure 1630 between the first active structure 1602A and the second active structure 1602B and not replaced by active gate structures. Thus, when the memory device 1200 is completed, this "remaining" dummy gate structure may be disposed between non-GAA and GAA transistors of the memory device 1200 (similar to the memory device 300 of fig. 3, except that at least one additional dummy gate structure is included), as will be further illustrated in fig. 29.

In another example, when the layout 900 of fig. 9 is used to form dummy gate structures, at least three dummy gate structures may be formed. The

hard masks

1908 and 1918 of fig. 19A-19C may be patterned based on the gate features 904 and 906, respectively. As such, the dummy gate structure 1902 may straddle or otherwise cover a central portion of the first active structure 1602A (e.g., a channel of a non-GAA transistor of the subsequently formed memory device 1200), wherein the first active structure 1602A is formed based on the active feature 902A; while dummy gate structure 1912 may straddle or otherwise cover a first portion of a second active structure 1602B (e.g., a channel of one of two GAA transistors of a subsequently formed memory device 1200), where the second active structure 1602B is formed based on the active features 902B. Furthermore, a third hard mask (not shown) may be patterned according to the gate features 908, and thus, another dummy gate structure (not shown) may straddle or otherwise cover a second portion of the second active structure 1602B (e.g., a channel of the other of the two GAA transistors of the subsequently formed memory device 1200). In various embodiments, the three dummy gate structures may then be replaced by respective active gate structures, wherein the gate spacers remain substantially intact. Thus, when the memory device 1200 is completed, these active gate structures may be used as gates for the non-GAA transistor, the first GAA transistor, and the second GAA transistor, respectively, of the memory device 1200 (similar to the memory device 400 of fig. 4), as will be further illustrated in fig. 30.

In yet another example, when the layout 1000 of fig. 10 is used to form dummy gate structures, at least one dummy gate structure may be formed between active structures based on the gate feature 1004 in addition to the three dummy gate structures (formed based on the gate features 904, 906, and 908) above the active structures. These additional dummy gate structures also have gate spacers along their sidewalls, and may be formed over the isolation structure 1630 between the first active structure 1602A and the second active structure 1602B and not replaced by active gate structures. Thus, when the memory device 1200 is completed, this "remaining" dummy gate structure may be disposed between the non-GAA transistor and the two GAA transistors of the memory device 1200 (similar to the memory device 400 of fig. 4, except that at least one additional dummy gate structure is included), as will be further illustrated in fig. 31.

Although the dummy gate structure 1902 shown in fig. 19A-19C straddles the first active structure 1602A with sidewalls of the first active structure 1602A exposed along the X-direction, it is understood that the memory device 1200 may include dummy gate structures extending further along the X-direction to one of the sidewalls, and these embodiments remain within the scope of the present disclosure. For example, when the layout 800 of fig. 8 is used to form a dummy gate structure, because the gate feature 504 only travels across the active feature 802A (used to form the first active structure 1602A), the dummy gate structure 1902 may extend along one of the sidewalls (along the X-direction) in addition to straddling the top surface and the sidewall (along the Y-direction) of the first active structure 1602A, where the sidewall is the opposite side of the side facing the second active structure 1602B. In various embodiments,

dummy gate structures

1902 and 1912 may then be replaced with respective active gate structures, with

gate spacers

1910 and 1920 remaining substantially intact. Thus, when the memory device 1200 is completed, these active gate structures may be used as gates for non-GAA and GAA transistors, respectively, of the memory device 1200. Specifically, a non-GAA transistor may have only one source/drain structure with a corresponding active gate structure extending along one sidewall (similar to the memory device 300 of fig. 3, except that the source/drain structure 316 is not included) formed at the other sidewall opposite the sidewall, as further shown in fig. 32. In some embodiments, such a transistor having only one source/drain structure is sometimes referred to as a MOS capacitor.

In the following, discussion of the method 1800 for fabricating the memory device 1200 will focus on the layout 500 of FIG. 5. In other words, the cross-sectional views of the memory device 1200 in fig. 20-28 will not show the additional dummy gate structure between the first active structure 1602A and the second active structure 1602B, the third active/dummy gate structure formed above the second active structure 1602B, or the MOS capacitor. Cross-sectional views of other embodiments of these memory devices 1200 can be formed based on the layouts shown in fig. 6-10 and will be shown in fig. 29-32, respectively.

Figure 20 is a cross-sectional view, corresponding to operation 1804 of figure 18, taken along line a-a' (e.g., as shown in figures 3-4) of memory device 1200 at one of various stages of fabrication, with an end portion of second active structure 1602B removed.

In some embodiments, the first active structure 1602A (or the first active region 1603A) may be covered by the blocking mask 2001 when the end portion of the second active structure 1602B is removed. A blocking mask 2001 is formed to cover the first active structure 1602A while maintaining the exposure of the second active structure 1602B. The blocking mask 2001 may be formed to have a thickness (or height) large enough so that the top surface and sidewalls of the first active structure 1602A are completely covered, as shown in fig. 20. The formation of the blocking mask 2001 may allow one or more processes to be performed only on the second active structure 1602B, as will be discussed below. The blocking mask 2001 may be formed of a material that is resistant to the etchant (etchable SiGe), such as silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials.

After covering the first active structure 1602A (or the first active region 1603A) with the blocking mask 2001, the dummy gate structure 1912 and the gate spacers 1920 may be used together as a mask to etch an end portion of the second active structure 1602B, as a result of which the second active structure 1602B in the second active region 1603B has an alternating stack of the remaining portions of the

semiconductor layers

1610 and 1620. For example, as shown in fig. 20,

semiconductor layers

2010a, 2020a, 2010B, 2020B, 2010c, and 2020c of second active structure 1602B are the remaining portions of

semiconductor layers

1610a, 1620a, 1610B, 1620B, 1610c, and 1620c, respectively. Semiconductor layers 2010a-2010c and 2020a-2020c may be collectively referred to as

semiconductor layers

2010 and 2020, respectively. In some embodiments, semiconductor layers 2010a-2010c and semiconductor layers 2020a-2020c may sometimes be referred to as nanostructures 2010a-2010c and nanostructures 2020a-2020 c.

Corresponding to operation 1806 of fig. 18, fig. 21 is a cross-sectional view, taken along line a-a' (e.g., as shown in fig. 3-4), of memory device 1200 at one of various stages of fabrication, in which memory device 1200 includes inner spacers 2102, inner spacers 2102 being formed along respective etched ends of each semiconductor layer 2010a-2010 c.

To form inner spacers 2102, respective end portions of each semiconductor layer 2010a-2010c may first be removed. During the removal of the respective end portions of the semiconductor layers 2010a-2010c, the first active structure 1602A may remain covered by the blocking mask 2001, which allows the first active structure 1602A to remain intact. A "pull-back" process may be used to remove (e.g., etch) end portions of semiconductor layers 2010a-2010c to pull back semiconductor layers 2010a-2010c to an initial pull-back distance such that the end portions of semiconductor layers 2010a-2010c terminate below gate spacer 1920 (e.g., are aligned with gate spacer 1920). Although in the embodiment shown in fig. 21, the etched ends of each semiconductor layer 2010a-2010c are approximately aligned with the sidewalls of gate spacers 1920, it should be understood that the pull-back distance (i.e., the degree to which each semiconductor layer 2010a-2010c is etched or pulled back) may be arbitrarily increased or decreased. Including Si in semiconductor layers 2020a-2020c and semiconductor layers 2010a-2010c including Si_1-xGe_xIn one example, the pullback process may include an isotropic (isotropic) etch process of hydrogen chloride (HCl) gas, which etches SiGe while not damaging Si. Thus, the semiconductor layers 2020a-2020c remain intact during this process.

Next, inner spacers 2102 may be formed along the etched end of each semiconductor layer 2010a-2010c, wherein the first active structure 1602A is covered by a blocking mask 2001. In some embodiments, the inner spacers 2102 may be conformally formed by Chemical Vapor Deposition (CVD), or by single layer doping of nitride (MLD) followed by spacer RIE. The inner spacers 2102 may be deposited using, for example, a conformal deposition process, followed by an isotropic or anisotropic (anisotropic) etch back (etch back) to remove excess spacer material on the sidewalls of the second active structure 1602B and on the surface of the semiconductor substrate 1202. The material of inner spacers 2102 may be formed from the same or different material (e.g., silicon nitride) as gate spacers 1920. For example, the inner spacer 2102 may be formed from the following materials: silicon nitride, silicon boron carbonitride (silicon carbonitride), silicon carbonitride (silicon oxycarbonitride), or any other type of dielectric material suitable for forming insulated gate sidewall spacers for transistors (e.g., dielectric materials having a dielectric constant k less than about 5).

Figure 22 is a cross-sectional view, corresponding to operation 1808 of figure 18, of the memory device 1200 at one of the various stages of manufacture taken along line a-a' (e.g., as shown in figures 3-4), wherein the memory device 1200 includes source/

drain structures

2202 and 2204 in the second active region 1603B. Source/

drain structures

2202 and 2204 are coupled to respective ends of second active structure 1602B.

The first active structure 1602A may remain covered by the blocking mask 2001 during the formation of the source/

drain structures

2202 and 2204. An epitaxial growth process may be used to form source/

drain structures

2202 and 2204 on the exposed ends of each of the semiconductor layers 2020a-2020 c. In some embodiments, the bottom surfaces of source/

drain structures

2202 and 2204 may be flush with the top surface of isolation structure 1630, as shown by the solid lines in fig. 22. Thus, source/

drain structures

2202 and 2204 may have a height H₁. In some other embodiments, the bottom surfaces of source/

drain structures

2202 and 2204 may be lower than the top surface of isolation structure 1630, as shown by the dashed lines in fig. 22. Thus, source/

drain structures

2202 and 2204 may have a height H₂。

The source/

drain structures

2202 and 2204 are electrically coupled to the semiconductor layers 2020a-2020 c. In various embodiments, the semiconductor layers 2020a-2020c may collectively serve as a channel for a GAA transistor (hereinafter, GAA transistor 2210). It should be noted that in some embodiments, GAA transistor 2210 is not yet completed at this stage of fabrication. Referring again to fig. 3, the GAA transistor 2210, when completed, may be similar to the read transistor 304 as a GAA transistor. Thus, semiconductor layers 2020a-2020c may correspond to semiconductor layers 342a-342c, respectively; and source/

drain structures

2202 and 2204 may correspond to source/

drain structures

320 and 322, respectively.

In-situ doping (ISD) may be applied to form doped source/

drain structures

2202 and 2204, thereby creating junctions for the GAA transistor 2210. n-type FETs and p-type FETs are formed by implanting different types of dopants into selected regions of the device, such as source/

drain structures

2202 and 2204, to form junctions. n-type devices may be formed by implanting arsenic (As) or phosphorous (P), while P-type devices may be formed by implanting boron (B).

Corresponding to operation 1810 of fig. 18, fig. 23 is a cross-sectional view, taken along line a-a' (e.g., as shown in fig. 3-4), of memory device 1200 at one of the various stages of fabrication, with an end portion (along the X-direction) of first active structure 1602A removed.

In some embodiments, the partially formed GAA transistor 2210 may be covered by the blocking mask 2301 while the end portion of the first active structure 1602A is removed. The blocking mask 2301 is formed to cover a portion of the formed GAA transistor 2210 while maintaining the first active structure 1602A exposed. The blocking mask 2301 may be formed to have a thickness (or height) large enough so that the partially formed GAA transistor 2210 is completely covered, as shown in fig. 23. The formation of the blocking mask 2301 may allow one or more processes to be performed only on the first active structure 1602A, as will be discussed below. The blocking mask 2301 may be formed of a material that is resistant to the etchant (e.g., etchable SiGe), such as silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials.

After the GAA transistor 2210 partially formed with the blocking mask 2301, the dummy gate structure 1902 and the gate spacers 1910 may be used together as a mask to etch end portions of the first active structure 1602A, as a result of which the sidewalls (or ends) of the first active structure 1602A along the X-direction are exposed to form corresponding source/drain structures.

Figure 24 is a cross-sectional view, taken along line a-a' (e.g., as shown in figures 3-4), of memory device 1200 at one of the various stages of fabrication, wherein memory device 1200 includes source/

drain structures

2402 and 2404 in first active region 1603A, corresponding to operation 1812 of figure 18. Source/

drain structures

2402 and 2404 are coupled to respective ends of first active structure 1602A.

During the formation of the source/

drain structures

2402 and 2404, the partially formed GAA transistor 2210 may remain covered by the blocking mask 2301. An epitaxial layer growth process may be used to form source/

drain structures

2402 and 2404 on the exposed ends of first active structure 1602A. In some embodiments, the bottom surfaces of the source/

drain structures

2402 and 2404 may be flush with the top surface of the isolation structure 1630, as shown in fig. 24. . Thus, the source/

drain structures

2402 and 2404 may have a height H₃Wherein the height H₃Approximately equal to height H₁But below the height H₂(FIG. 22).

The source/

drain structures

2402 and 2404 are electrically coupled to the first active structure 1602A. In various embodiments, the first active structure 1602A may serve as a channel for a non-GAA transistor (hereinafter referred to as a non-GAA transistor 2410). It should be noted that in some embodiments, the non-GAA transistor 2410 is not yet completed at this stage of fabrication. Referring again to fig. 3, after completion, the non-GAA transistor 2410 may be similar to the programming transistor 302 as a non-GAA transistor. Thus, the first active structure 1602A may correspond to the protruding structure 332; and source/

drain structures

2402 and 2404 may correspond to source/

drain structures

316 and 318, respectively.

In-situ doping (ISD) may be applied to form doped source/

drain structures

2402 and 2404, thereby creating junctions for the non-GAA transistor 2410. n-type FETs and p-type FETs are formed by implanting different types of dopants into selected regions of the device, such as source/

drain structures

2402 and 2404, to form junctions. n-type devices may be formed by implanting arsenic (As) or phosphorous (P), while P-type devices may be formed by implanting boron (B).

Figure 25 is a cross-sectional view, taken along line a-a' (e.g., as shown in figures 3-4), of the memory device 1200 at one of the various stages of fabrication, corresponding to operation 1814 of figure 18, in which the memory device 1200 includes an interlayer dielectric (ILD) 2500. Interlayer dielectric 2500 may sometimes be referred to as interlayer dielectric 0(ILD 0). The interlayer dielectric 2500 may be formed by: dielectric material is deposited in bulk (in bulk) over the partially formed GAA transistor 2210 and the non-GAA transistor 2410, followed by a bulk oxide polish (e.g., using CMP) back to flush with the

dummy gates

1906 and 1916, which causes the

hard masks

1908 and 1918 to be removed. As such,

dummy gates

1906 and 1916 may be exposed. The dielectric material of the interlayer dielectric 2500 includes silicon oxide, phosphosilicate Glass (PSG), borosilicate Glass (BSG), boron-doped phosphosilicate Glass (BPSG), Undoped Silicate Glass (USG), and combinations thereof.

Corresponding to operation 1816 of fig. 18, fig. 26 is a cross-sectional view, taken along line a-a' (e.g., as shown in fig. 3-4), of memory device 1200 at one of the various stages of fabrication, in which

dummy gate structures

1902 and 1912 are first removed, and then semiconductor layers 2010a-2010c are also removed.

After forming interlayer dielectric 2500 and exposing dummy gates 1906 and 1916 (fig. 25),

dummy gate structures

1902 and 1912 are removed.

Dummy gate structures

1902 and 1912 may be removed by a known etch process, such as RIE or Chemical Oxide Removal (COR). After removing the dummy gate structure 1902, the top surface of the first active structure 1602A is exposed. Although not shown in the cross-sectional view of fig. 26, it is understood that the sidewalls (facing the Y-direction) of the first active structure 1602A may also be exposed except for the top surface. Similarly, after removing the dummy gate structure 1912, a top surface of the semiconductor layer 2020c is exposed. Although not shown in the cross-sectional view of fig. 26, it is understood that sidewalls (facing the Y-direction) of each of semiconductor layers 2010a-2010c and 2020a-2020c may be exposed in addition to the top surface. Semiconductor layers 2010a-2010c are then removed by applying a selective etch, such as hydrochloric acid (HCl-after removing semiconductor layers 2010a-2010c, the respective bottom and top surfaces of each of semiconductor layers 2020a-2020c may be exposed.

Figure 27A is a cross-sectional view, taken along line a-a' (e.g., as shown in figures 3-4), of the memory device 1200 at one of the various stages of fabrication, wherein the memory device 1200 includes a first active gate structure 2702 (also referred to as active gate structure 2702) and a second active gate structure 2712 (also referred to as active gate structure 2712), corresponding to operation 1818 of figure 18. For clarity of illustration, FIG. 27B shows a cross-sectional view of the memory device 1200 taken along line B-B' (e.g., as shown in FIGS. 3-4); and figure 27C shows a cross-sectional view of the memory device 1200 taken along line C-C' (e.g., as shown in figures 3-4).

In some embodiments, each active gate structure includes a gate dielectric and a gate metal. For example, the first active gate structure 2702 comprises a gate dielectric 2704 and a gate metal 2706; the second active gate structure 2712 includes a gate dielectric 2714 and a gate metal 2716.

The gate dielectric 2704 is in direct contact with the first active structure 1602A. A gate dielectric 2714 surrounds each of the semiconductor layers 2020a-2020 c. As further shown in fig. 27B-27C, respectively, the gate dielectric 2704 is formed to straddle the top surface and sidewalls of the first active structure 1602A; while the gate dielectric 2714 is formed to wrap around each of the semiconductor layers 2020a-2020c (e.g., top/bottom surfaces and sidewalls perpendicular to the Y-direction). The

gate dielectrics

2704 and 2714 may be formed from different high-k dielectric materials or similar high-k dielectric materials. Exemplary high-k dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The

gate dielectrics

2704 and 2714 may comprise a stack of multiple high-k dielectric materials. The

gate dielectrics

2704 and 2714 can be deposited simultaneously or separately using any suitable method, including, for example, Molecular Beam Deposition (MBD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like. In some embodiments, the

gate dielectrics

2704 and 2714 may optionally comprise relatively thin oxide (e.g., SiO)_x) And (3) a layer.

The gate metal 2706 may straddle the top surface and sidewalls of the first active structure 1602A, wherein the gate dielectric 2704 is disposed between the gate metal 2706 and the first active structure 1602A. The gate metal 2716 may wrap around each of the semiconductor layers 2020a-2020c, with the gate dielectric 2714 disposed between the gate metal 2716 and the semiconductor layers 2020a-2020 c. As further shown in fig. 27B-27C, respectively, the gate metal 2706 is formed to straddle the top surface and sidewalls of the first active structure 1602A, wherein a gate dielectric is disposed between the gate metal 2706 and the first active structure 1602A; and a gate metal 2716 is formed to wrap around each of the semiconductor layers 2020a-2020c (e.g., top/bottom surfaces and sidewalls perpendicular to the Y-direction), wherein a gate dielectric 2714 is disposed between the gate metal 2716 and the semiconductor layers 2020a-2020 c. Specifically, the gate metal 2716 may include a plurality of gate metal portions that abut (abut) one another along the Z-direction. Each gate metal portion may extend not only along a horizontal plane (e.g., a plane extending from the X-direction and the Y-direction) but also along a vertical direction (e.g., the Z-direction). As such, two adjacent gate metal portions may abut (adjoin) together to surround a corresponding one of the semiconductor layers 2020a-2020c, wherein the gate dielectric 2714 is disposed between the gate metal portions and the semiconductor layers 2020a-2020 c.

The

gate metals

2706 and 2716 may be formed of different metal materials or similar metal materials. Each of the

gate metals

2706 and 2716 may comprise a stack of multiple metal materials. For example, each of the

gate metals

2706 and 2716 may be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. The work function layer may also be referred to as a work function metal. Exemplary p-type work function metals that may be included in the gate structure for p-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi₂、MoSi₂、TaSi2、NiSi₂WN, other suitable p-type work function material, or combinations thereof. Exemplary n-type work function metals that may be included in the gate structure for n-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or groups thereofAnd (6) mixing. The work function value is related to the material composition of the work function layer and, therefore, the material of the work function layer is selected to tune (tune) its work function value such that a target threshold voltage V can be achieved in the device to be formed_t. The work function layer may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and/or other suitable processes.

In some embodiments, after forming the active gate structure 2702 and the active gate structure 2712, the GAA transistor 2210 and the non-GAA transistor 2410 may be completed. For example, the GAA transistor 2210 may include a gate structure 2712, a source/drain structure 2202, and a source/drain structure 2204 as its gate, source, and drain, respectively; instead of GAA transistor 2410, it may include a gate structure 2702, a source/drain structure 2402, and a source/drain structure 2404 as its gate, source, and drain, respectively.

To operate the GAA transistor 2210 with the non-GAA transistor 2410, for example, as an antifuse memory cell, various interconnect structures may be formed. For example, non-GAA transistor 2410 may serve as a programming transistor (e.g., programming transistor 110 of FIG. 1) for an anti-fuse memory cell, while GAA transistor 2210 may serve as a read transistor (e.g., read transistor 120 of FIG. 1) for an anti-fuse memory cell. For example, various interconnect structures may be formed to allow electrical connection between the drain of the non-GAA programming transistor (source/drain structure 2404) and the source of the GAA read transistor (source/drain structure 2202), to electrically connect the gate of the non-GAA programming transistor (active gate structure 2702) to WLP, to electrically connect the gate of the GAA read transistor (active gate structure 2712) to WLR, and to electrically connect the drain of the GAA read transistor (source/drain structure 2204) to BL.

Figure 28 is a cross-sectional view, corresponding to operation 1820 of figure 18, of the memory device 1200 at one of various stages of manufacture, taken along line a-a' (e.g., as shown in figures 3-4), in which the memory device 1200 includes a plurality of interconnect structures (e.g., contacts) 2802, 2804, 2806, 2812, 2814, and 2816. In some embodiments, the

interconnect structures

2802, 2804, 2806 provide electrical connections to (to) a non-GAA programming transistor (non-GAA transistor 2410); while the

interconnect structures

2812, 2814 and 2816 provide electrical connections to a GAA read transistor (GAA transistor 2210).

As shown, the interconnect structure 2802 is coupled to the active gate structure 2702 (or gate metal 2706); interconnect structure 2804 is coupled to source/drain structure 2402; interconnect structure 2806 is coupled to source/drain structure 2404; the interconnect structure 2812 is coupled to the active gate structure 2712 (or gate metal 2716); interconnect structure 2814 is coupled to source/drain structure 2202; and interconnect structure 2816 is coupled to source/drain structure 2204.

In various embodiments, to operate the GAA transistor 2210 and the non-GAA transistor 2410 as a read transistor and a program transistor, respectively, of an anti-fuse memory cell, an interconnect structure (e.g., as may be formed by the feature 534 of fig. 5, but not shown in fig. 28) may be established between the source/drain structure 2404 (which serves as the drain of the non-GAA transistor 2410) and the source/drain structure 2202 (which serves as the source of the GAA transistor 2210) via the

interconnect structures

2806 and 2814, respectively; WLP may be electrically connected to active gate structure 2702 (which serves as the gate of non-GAA transistor 2410); WLR may be electrically connected to the active gate structure 2712 (which serves as the gate of the GAA transistor 2210); BL may be electrically connected to source/drain structure 2204, which serves as the drain of a GAA read transistor (GAA transistor 2210).

Each interconnect structure may extend through another interlayer dielectric 2800 to couple to a corresponding structure. Relative to ILD0 (interlayer dielectric 2500), interlayer dielectric 2800 formed of a dielectric material similar to interlayer dielectric 2500 may sometimes be referred to as interlayer dielectric 1(ILD 1). Interconnect structure 2802 may further extend through dielectric hard mask 2803 (e.g., silicon nitride) to couple to active gate structure 2702; while the interconnect structure 2812 may further extend through a dielectric hard mask 2813 (e.g., silicon nitride) to couple to the active gate structure 2712. These dielectric hard masks may be formed after the formation of the active gate structures and before the formation of the interconnect structures. For example, after forming the

active gate structures

2702 and 2712, an etch process may be performed to dig into the

active gate structures

2702 and 2712. The trenched active gate structure may then be filled with a dielectric material, such as silicon nitride, and then subjected to a planarization process, such as CMP, to form dielectric

hard masks

2803 and 2813.

Each of the interconnect structures 2802-2816 may comprise a metal-containing material, such as copper, aluminum, tungsten, and the like, combinations thereof, or multilayers thereof. For example, after forming the dielectric

hard masks

2803 and 2813, an interlayer dielectric 2800 can be deposited over the memory device 1200. Next, one or more contact holes (holes) are formed (e.g., by at least one patterning process) to extend through the interlayer dielectric 2800 and selectively expose each structure (e.g., active gate structure 2702, source/drain structure 2402, source/drain structure 2404, active gate structure 2712, source/drain structure 2202, source/drain structure 2204) from the dielectric

hard mask

2803 or 2813. These contact holes are then filled with a metal-containing material to form the interconnect structures 2802-2816, for example, by electroplating (electroplating), electroless plating (electroplating), or other suitable methods. After the formation of the interconnect structure, a planarization process, such as CMP, may be performed to remove excess portions of the metal-containing material.

Although each of the interconnect structures 2802-2816 is shown in fig. 28 as a single via structure, it is understood that some of the interconnect structures 2802-2816 may include multiple structures formed of similar metal-containing materials and connected to one another. For example, each of the

interconnect structures

2804, 2806, 2814, and 2816 may include MD (formed as a slot or trench structure) and VD (formed as a via structure) as described above with reference to fig. 5-10.

Although not shown, each interconnect structure may further include a barrier layer (barrier layer). For example, the bottom surface and sidewalls of each interconnect structure may be surrounded by such a barrier layer. The barrier layer may comprise a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc. may alternatively be utilized. The barrier layer may be formed using a CVD process, such as a PECVD process. However, other alternative methods, such as sputtering (sputtering), Metal Organic Chemical Vapor Deposition (MOCVD), or ALD, may alternatively be used.

FIG. 29 shows a cross-sectional view of another embodiment of a memory device 1200, which can be fabricated based on the layout 600 of FIG. 6 or the layout 700 of FIG. 7. Referring again to fig. 6-7, each of the

layouts

600 and 700 includes one or more features (e.g., features 602 and 604) that are used to form dummy gate structures that are not replaced by active gate structures.

As shown in fig. 29, memory device 1200 further includes

dummy gate structures

2900 and 2920 when compared to the embodiment shown in fig. 28 that is fabricated based on layout 500 of fig. 5.

Dummy gate structures

2900 and 2920 may be formed in operation 1802 of fig. 18 using features 602 and 604 (fig. 6-7), respectively. For example, dummy gate structures may be formed at the same time that

dummy gate structures

1902 and 1912 are formed that will be replaced by corresponding active gate structures at

operations

1816 and 1818. Accordingly, each of

dummy gate structures

2900 and 2920 includes a similar configuration as

dummy gate structures

1902 and 1912, except that

dummy gate structures

2900 and 2920 are formed over isolation structures 1630 (e.g., without covering any active regions).

For example, a dummy gate structure 2900 formed over an isolation structure 1630 on a side of the second active region 1603B opposite the first active region 1603A includes a dummy gate dielectric 2902 and a dummy gate 2904, wherein the spacer 2906 extends along sidewalls of the dummy gate structure 2900; a dummy gate structure 2920 formed over the isolation structure 1630 between the first active region 1603A and the second active region 1603B includes a dummy gate dielectric 2922 and a dummy gate 2924, wherein spacers 2926 extend along sidewalls of the dummy gate structure 2920. However,

dummy gate structures

2900 and 2920 will not be replaced by active gate structures in

operations

1816 and 1818, for example, by masking

dummy gate structures

2900 and 2920 in

operations

1816 and 1818,

dummy gate structures

2900 and 2920 will not be replaced by active gate structures. After forming

active gate structures

2702 and 2712,

active gate structures

2702 and 2712 and

dummy gate structures

2900 and 2920 may be recessed to be covered by corresponding dielectric hard masks. For example,

dummy gate structures

2900 and 2920 are covered by dielectric

hard masks

2908 and 2928, respectively.

FIG. 30 shows a cross-sectional view of another embodiment of a memory device 1200, which can be fabricated based on the layout 900 of FIG. 9. Referring again to fig. 9, the layout 900 includes an additional gate feature 908 (relative to the layout 500 of fig. 5), the gate feature 908 travels across the active feature 902B, which results in the memory device 1200 forming an active gate structure for another GAA transistor. For example, in fig. 19A-19C, after additional dummy gate structures (relative to dummy gate structures 1902 and 1912) are formed using gate feature 908 at operation 1802 of fig. 18, the remaining operations of method 1800 of fig. 18 may be used to form memory device 1200, where memory device 1200 includes one non-GAA transistor and two GAA transistors.

As shown in fig. 30, in addition to the active gate structures of the non-GAA transistor 2410 and the GAA transistor 2210, which may be formed by gate features 904 and 906, respectively, the memory device 1200 may further include another active gate structure 3006 of the GAA transistor 3000, wherein the active gate structure 3006 may be formed by gate feature 908. Because both gate features 906 and 908 travel through the active feature 902B, the

GAA transistors

2210 and 3000 formed may share the source/drain structure 2204, but have respective channels. For example, the GAA transistor 3000 includes a plurality of semiconductor layers 3002 that collectively serve as its channel. The GAA transistor 3000 includes a shared source/drain structure 2204 connected to one end of the semiconductor layer 3002, and includes a source/drain structure 3004 connected to the other end of the semiconductor layer 3002. The active gate structure 3006 and the source/drain structure 3004 are connected by

respective interconnect structures

3008 and 3010 to enable operation of the memory device 1200 that includes one non-GAA programming transistor and two GAA read transistors. For example, the second read word line (WLR2) is connected to the active gate structure 3006 of the GAA transistor 3000 via an interconnect 3008 (with the first read word line (WLR1) connected to the active gate structure of the GAA transistor 2210), and BL is connected to the source/drain structure 3004 of the GAA transistor 3000 via an interconnect 3010.

FIG. 31 shows a cross-sectional view of another embodiment of a memory device 1200, which can be fabricated based on the layout 1000 of FIG. 10. Referring again to FIG. 10, layout 1000 includes one or more additional features (e.g., features 1002 and 1004) when compared to layout 900 of FIG. 9. The features 1002 and 1004 may be configured to form a dummy gate structure that is not replaced by an active gate structure.

As shown in fig. 31, the memory device 1200 further includes

dummy gate structures

3100 and 3120 when compared to the embodiment shown in fig. 30 that is fabricated based on the layout 900 of fig. 9.

Dummy gate structures

3100 and 3120 may be formed in operation 1802 of fig. 18 using features 1002 and 1004 (fig. 10), respectively. For example, in fig. 19A-19C, dummy gate structures may be formed at the same time that

dummy gate structures

operations

1816 and 1818. Accordingly, each of the

dummy gate structures

3100 and 3120 includes a similar configuration as the

dummy gate structures

1902 and 1912, except that the

dummy gate structures

3100 and 3120 are formed over the isolation structure 1630 (e.g., without covering any active regions).

For example, a dummy gate structure 3100 formed over the isolation structure 1630 on a side of the second active region 1603B opposite the first active region 1603A includes a dummy gate dielectric 3102 and a dummy gate 3104, wherein spacers 3106 extend along sidewalls of the dummy gate structure 3100; a dummy gate structure 3120 formed over the isolation structure 1630 between the first active region 1603A and the second active region 1603B includes a dummy gate dielectric 3122 and a dummy gate 3124, wherein a spacer 3126 extends along sidewalls of the dummy gate structure 3120. However,

dummy gate structures

3100 and 3120 are not replaced by active gate structures in

operations

1816 and 1818, e.g., by masking

dummy gate structures

3100 and 3120 in

operations

1816 and 1818,

dummy gate structures

3100 and 3120 are not replaced by active gate structures. After the formation of the

active gate structures

2702, 2712, and 3006, the

active gate structures

2702, 2712, and 3006 and the

dummy gate structures

3100 and 3120 may be recessed to be covered by corresponding dielectric hard masks. For example,

dummy gate structures

3100 and 3120 are covered by dielectric

hard masks

3108 and 3128, respectively.

FIG. 32 shows a cross-sectional view of another embodiment of a memory device 1200, which can be fabricated based on the layout 800 of FIG. 8. Referring again to fig. 8, layout 800 includes a feature 802A (active feature) partially covered by gate feature 504 (as compared to layout 500-700 of fig. 5-7), which results in the formation of a non-GAA transistor having only one source/drain structure (MOS capacitor). For example, in fig. 19A-19C, after forming the first active structure 1602A in operation 1110 of fig. 11 (or operation 1712 of fig. 17) using feature 802A and then forming the dummy gate structure 1902 in operation 1802 of fig. 18 using gate feature 504, the dummy gate structure 1902 may not only straddle the first active structure 1602A, but may also extend along one of the sidewalls of the first active structure 1602A in the X-direction. The remaining operations of the method 1800 of fig. 18 may be used to form a memory device 1200, such a memory device 1200 comprising one non-GAA transistor formed as a MOS capacitor and one GAA transistor.

As shown in fig. 32, the memory device 1200 includes a non-GAA transistor 3200 formed as a MOS capacitor. The non-GAA transistor 3200 includes an active gate structure 3202, the active gate structure 3202 replacing the dummy gate structure 1902 formed by the gate feature 504 as described above. The active gate structure 3202 including the gate dielectric 3204 and the gate metal 3206 not only straddles the first active structure 1602A, but also extends along one of the sidewalls of the first active structure 1602A in the X-direction. Sidewalls of active gate structure 3202 (along the X direction) are also covered by gate spacers 3208. As such, non-GAA transistor 3200 may comprise only source/drain structure 2404 formed along one of the sidewalls (along the X-direction) of first active structure 1602A, wherein the sidewall is not covered by active gate structure 3202.

In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a first transistor formed in a first region of a substrate. The first transistor includes a protruding structure protruding from the substrate, and a first source/drain (S/D) structure coupled to a first end of the protruding structure. The memory device includes a second transistor formed in a second region of the substrate. The second transistor includes a plurality of first semiconductor layers vertically spaced apart from each other, a second source/drain structure coupled to first ends of the plurality of first semiconductor layers, and a third source/drain structure coupled to second ends of the plurality of first semiconductor layers. The first region and the second region are laterally separated from each other by an isolation structure.

In one or more embodiments, the first transistor is configured as a program transistor of the antifuse memory cell, and the second transistor is configured as a read transistor of the antifuse memory cell. In one or more embodiments, the first transistor is electrically coupled to the second transistor in series via an interconnect structure disposed above the substrate and connecting the first source/drain structure to at least one of the second source/drain structure or the third source/drain structure.

In one or more embodiments, the first transistor includes a first gate structure straddling a central portion of the protruding structure, and the second transistor includes a second gate structure including a plurality of full-ring gate stacks operatively associated with the first semiconductor layer. In one or more embodiments, the first transistor includes a fourth source/drain structure coupled to the second end of the protruding structure, wherein the fourth source/drain structure is disposed further away from the isolation structure than the first source/drain structure.

In one or more embodiments, the first transistor comprises a fin transistor and the second transistor comprises a gate full-ring transistor. In one or more embodiments, the memory device further includes at least one dummy gate structure disposed between the first region and the second region.

In one or more embodiments, the memory device further includes a third transistor formed in the second region of the substrate, the third transistor including: a plurality of second semiconductor layers vertically separated from each other, the third source/drain structure being coupled to first ends of the plurality of second semiconductor layers; and a fifth source/drain structure electrically coupled to the second end of the second semiconductor layer.

In one or more embodiments, the first transistor is configured as a program transistor of an anti-fuse memory cell, the second transistor is configured as a first read transistor of the anti-fuse memory cell, and the third transistor is configured as a second read transistor of the anti-fuse memory cell.

In one or more embodiments, the first source/drain structure has a first vertical height, and the second source/drain structure and the third source/drain structure have a second vertical height, wherein the second vertical height is greater than the first vertical height.

In another aspect of the disclosure, a one-time programmable (OTP) memory device is disclosed. The one-time programmable memory device includes a programming transistor formed in a first region of a substrate. The otp memory device includes a first read transistor electrically connected in series to a program transistor and formed in a second region of the substrate. The first region is laterally separated from the second region by an isolation structure. The program transistor includes a first gate structure straddling a protruding structure protruding from the substrate, and the first read transistor includes a second gate structure wrapping around each of a plurality of first nanostructures vertically spaced from each other.

In one or more embodiments, the protruding structure is configured to act as a channel for a program transistor and the first nanostructure is configured to act as a channel for a first read transistor. In one or more embodiments, the program transistor includes a first source/drain structure coupled to a first end of the protruding structure, and the first read transistor includes a second source/drain structure and a third source/drain structure coupled to a first end and a second end of the plurality of first nanostructures, respectively.

In one or more embodiments, the first source/drain and the second source/drain are closely adjacent to each other, but are separated from each other by an isolation structure. In one or more embodiments, the first source/drain structure has a first vertical height, and the second source/drain structure and the third source/drain structure have a second vertical height, wherein the second vertical height is greater than the first vertical height.

In one or more embodiments, the otp memory device further includes an interconnect structure disposed over the substrate and connecting the first source/drain structure to at least one of the second source/drain structure or the third source/drain structure.

In one or more embodiments, the otp memory device further includes a second read transistor electrically coupled in series to the first read transistor and formed in the second region of the substrate, wherein the second read transistor includes a third gate structure wrapped around each of the second nanostructures, and the second nanostructures are vertically separated from each other.

In one or more embodiments, the otp memory further includes at least one dummy gate structure disposed between the first region and the second region.

In yet another aspect of the present disclosure, a method of manufacturing a memory device is disclosed. The manufacturing method of the memory device comprises the step of defining a first active area and a second active area on a substrate. The first active region and the second active region are laterally separated from each other by an isolation structure. The manufacturing method of the memory device comprises the step of forming a first transistor in the first active region. The first transistor includes a first channel formed by a protruding structure protruding from the substrate, a first active gate structure straddling the first channel, and a first source/drain structure coupled to an end of the first channel. The method of manufacturing the memory device includes forming a second transistor in the second active region. The second transistor includes a second channel formed by one or more semiconductor layers disposed above the substrate, a second active gate structure surrounding the second channel, a second source/drain structure coupled to one end of the second channel, and a third source/drain structure coupled to the other end of the second channel.

In one or more embodiments, the first transistor is configured as a program transistor of the antifuse memory cell, and the second transistor is configured as a read transistor of the antifuse memory cell.

The foregoing outlines features of various embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. It should also be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.

Claims

1. A memory device, comprising:

a first transistor formed in a first region of a substrate, the first transistor comprising: a protrusion structure protruding from the substrate; and

a first source/drain structure coupled to a first end of the protruding structure; and

a second transistor formed in a second region of the substrate, the second transistor comprising: a plurality of first semiconductor layers vertically spaced apart from each other;

a second source/drain structure coupled to a first end of the first semiconductor layer; and

a third source/drain structure coupled to a second end of the first semiconductor layer;

wherein the first region and the second region are laterally separated from each other by an isolation structure.