TWI761012B - Event controlling device and operation method thereof - Google Patents

Abstract

An event controlling device includes a first selecting module, a second selecting module, a first processing module, a channel link module and an output module. The first selecting module receives a plurality of event signals and output a first event signal. The second selecting module receives the event signals and output a second event signal. The first processing module receives the first event signal and the second event signal, and performing a first logic process for the first event signal or a first inverted event signal and the second event signal or a second inverted event signal to generate a first processing signal. The channel link module has a plurality of output channels, receives the first processing signal, and designates a first output channel of the output channels to output the first processing signal. The output module receives the first processing signal, and generates a first output signal or a first synchronism output signal according to the processing signal.

Description

Event control device and method of operation thereof

The present invention relates to a control device, in particular to an event control device and an operation method thereof.

In general, event linkage between a peripheral device and another peripheral device can be performed through an event controller. However, the event controller only provides a linear relationship between the peripheral device and another peripheral device, that is, the event controller provides the event trigger signal provided by the peripheral device to the other peripheral device, so that the other peripheral device can use The corresponding operation is generated, so the processing mode of the event controller is relatively monotonous. Therefore, how to increase the flexibility and convenience of the event controller is an important issue at present.

The present invention provides an event control device and an operation method thereof, so as to increase the flexibility and use context of event connection between peripheral devices, so as to increase the convenience in use.

The present invention provides an event control device, comprising a first selection module, a second selection module, a first processing module, a channel connection module, and an output module. The first selection module receives a plurality of event signals and outputs a first event signal. The second selection module receives the event signal and outputs the second event signal. The first processing module is coupled to the first selection module and the second selection module, receives the first event signal and the second event signal, and the first processing module processes the first event signal or the first inversion event signal and the second event signal. The event signal or the second inverted event signal undergoes first logic processing to generate a first processing signal. The channel connection module is coupled to the first processing module and has a plurality of output channels. The channel connection module receives the first processing signal and outputs the first processing signal through the first output channel of the designated output channel. The output module is coupled to the channel connection module, receives the first processing signal, and generates the first output signal or the first synchronization output signal according to the first processing signal.

The present invention provides an operation method of an event control device, which includes the following steps. Through the first selection module, a plurality of event signals are received, and the first event signal is output. Through the second selection module, the event signal is received and the second event signal is output. Through the first processing module, the first logic processing is performed on the first event signal or the first inverted event signal and the second event signal or the second inverted event signal to generate the first processing signal. The first processing signal is received through the channel connecting module, and the first output channel of the plurality of output channels of the channel connecting module is designated to output the first processing signal. The first processing signal is received through the output module, and a first output signal or a first synchronization output signal is generated according to the first processing signal.

In the event control device and the operation method thereof disclosed in the present invention, at least the first event signal or the first inversion event signal and the second event signal or the second inversion event signal are subjected to the first logic processing through the first processing module, In order to generate the first processing signal, the first output channel of the designated output channel of the channel connection module outputs the first processing signal, and the output module generates the first output signal or the first synchronization output signal according to the first processing signal. In this way, the flexibility of the event connection and the usage context can be effectively increased, so as to increase the convenience of use.

In the various embodiments listed below, the same or similar elements or components will be represented by the same reference numerals.

FIG. 1 is a schematic diagram of an event control apparatus according to an embodiment of the present invention. The event control device 100 of this embodiment is suitable for event link control between peripheral devices of a microcontroller. Referring to FIG. 1 , the event control device 100 may include a first selection module 110_1 , a second selection module 110_2 , a first processing module 120 , a channel connection module 130 and an output module 140 .

The first selection module 110_1 can receive a plurality of event signals S0, S1 and a selection signal SEL1_1, and output a first event signal S0 from the event signals S0, S1 according to the selection signal SEL1_1. In this embodiment, the first selection module 110_1 may be a multiplexer. In addition, the above-mentioned event signals S0 and S1 are generated by, for example, a peripheral device, and the peripheral device is, for example, an analog to digital converter (ADC), a timer (timer), etc., but the embodiment of the present invention is not limited thereto. In addition, in some embodiments, the above-mentioned event signals S0 and S1 may be generated by the same peripheral device. In some embodiments, the above-mentioned event signals S0 and S1 may also be generated by different peripheral devices.

The second selection module 110_2 can receive the event signals S0, S1 and the selection signal SEL1_2, and output the second event signal S1 from the event signals S0, S1 according to the selection signal SEL1_2. In this embodiment, the second selection module 110_2 may be a multiplexer.

The first processing module 120 is coupled to the first selection module 110_1 and the second selection module 110_2. The first processing module 120 can receive the first event signal S0 and the second event signal S1. The first processing module 120 can perform first logic processing on the first event signal S0 or the first inverted event signal S0' and the second event signal S1 or the second inverted event signal S1' to generate the first processing signal PS1 . In this embodiment, the first inverted event signal S0' is the inverted signal of the first event signal S0, and the second inverted event signal S1' is the inverted signal of the second event signal S1.

For example, in one embodiment, the first processing module 120 may perform first logic processing on the first event signal S0 and the second event signal S1 to generate the first processing signal PS1. In one embodiment, the first processing module 120 may perform first logic processing on the first event signal S0 and the second inverted event signal S1' to generate the first processing signal PS1. In one embodiment, the first processing module 120 may perform first logic processing on the first inverted event signal S0' and the second event signal S1 to generate the first processing signal PS1. In one embodiment, the first processing module 120 may perform first logic processing on the first inversion event signal S0' and the second inversion event signal S1' to generate the first processing signal PS1.

The channel connection module 130 is coupled to the first processing module 120 and has a plurality of output channels CH0, CH1, CH2. The channel connection module 130 can receive the processing signal PS1, and designate a first output channel (eg, CH0) of the output channels CH0, CH1, and CH2 to output the first processing signal PS1.

The output module 140 is coupled to the channel connection module 130, receives the first processing signal PS1, and generates a first output signal or a first synchronization output signal SS1 according to the first processing signal PS1. In this embodiment, the first output signal is provided, for example, to the event control device 100 of the next stage, so as to perform subsequent event connection operations. For example, the first synchronization output signal SS1 is provided to the target peripheral device to instruct the target device to perform a corresponding operation. The above-mentioned target peripheral device is, for example, an analog-to-digital converter, etc., but the embodiment of the present invention is not limited thereto.

Further, the first processing module 120 may include a first inverter 121_1, a second inverter 121_2, a first selection unit 122_1, a second selection unit 122_2 and a first logic processing unit 123_1.

The first inverter 121_1 has an input terminal and an output terminal. The input terminal of the first inverter 121_1 is coupled to the first selection module 110_1 and receives the first event signal S0. The output terminal of the first inverter 121_1 generates the first event signal S0. Invert event signal S0'. That is, the first inverter 121_1 receives the first event signal S0, and inverts the first event signal S0 to generate the first inverted event signal S0'. The second inverter 121_2 has an input terminal and an output terminal. The input terminal of the second inverter 121_2 is coupled to the second selection module 110_2 and receives the second event signal S1. The output terminal of the second inverter 121_2 generates the second event signal S1. Invert event signal S1'. That is, the second inverter 121_2 receives the second event signal S1 and inverts the second event signal S1 to generate the second inverted event signal S1'.

The first selection unit 122_1 is coupled to the first selection module 110_1 and the output end of the first inverter 121_1. The first selection unit 122_1 may receive the first event signal S0, the first inversion event signal S0' and the selection signal SEL2_1, and select and output the first event signal S0 or the first inversion event signal S0' according to the selection signal SEL2_1. The second selection unit 122_2 is coupled to the output end of the second selection module 110_2 and the second inverter 121_2. The second selection unit 122_2 may receive the second event signal S1 and the second inversion event signal S1', and select to output the second event signal S1 or the second inversion event signal S1'.

The first logic processing unit 123_1 is coupled to the first selection unit 122_1 and the second selection unit 122_2. The first logic processing unit 123_1 may receive the first event signal S0 or the first inversion event signal S0' and the second event signal S1 or the second inversion event signal S1', and perform an inversion of the first event signal S0 or the first inversion event signal S1'. The event signal S0' and the second event signal S1 or the second inverted event signal S1' are subjected to first logic processing to generate a first processing signal. In this embodiment, the first logical processing may include AND processing, OR processing, anti-AND processing, mutual exclusion or processing, etc., but the embodiment of the present invention is not limited thereto.

The output module 140 may include a synchronization unit 141_1, a synchronization unit 141_2, a synchronization unit 141_3, an output selection unit 141_1, an output selection unit 142_2, and an output selection unit 142_3. The synchronization unit 141_1 is coupled to the first output channel CH0 of the channel connection module 130 , receives a signal (eg, the first processing signal PS1 ) and the clock signal CLK1 output by the first output channel CH0 , and uses the clock signal CLK1 to synchronize the first output channel CH0 . The signal output by the output channel CH0 (eg, the first processing number PS1 ) is subjected to synchronization processing to generate a synchronization output signal (eg, the first synchronization output signal SS1 ).

The synchronization unit 141_2 is coupled to the second output channel CH1 of the channel connection module 130 , receives the signal output by the second output channel CH1 and the clock signal CLK2 , and uses the clock signal CLK2 to perform the signal output from the second output channel CH1 . Synchronous processing to generate a synchronized output signal. The synchronization unit 141_3 is coupled to the third output channel CH1 of the channel connection module 130 , receives the signal output by the third output channel CH2 and the clock signal CLK3 , and uses the clock signal CLK3 to perform the signal output from the third output channel CH2 . Synchronous processing to generate a synchronized output signal. In this embodiment, the clock signal CLK1, the clock signal CLK2, and the clock signal CLK3 may be the same or different.

The output selection unit 142_1 is coupled to the first output channel CH0 of the channel connection module 130 and the synchronization unit 141_1 , and receives the signal output by the first output channel CH0 (eg, the first processing signal PS1 ) and the synchronization output signal generated by the synchronization unit 141_1 (for example, the first synchronization output signal SS1 ), and output the signal output by the first output channel CH0 (for example, the first processing signal PS1 ) as the first output signal or output the synchronization output signal (for example, the first processing signal PS1 ) generated by the synchronization unit 141_1 synchronous output signal SS1).

The output selection unit 142_2 is coupled to the second output channel CH1 of the channel connection module 130 and the synchronization unit 141_2 , receives the signal output from the second output channel CH1 and the synchronization output signal generated by the synchronization unit 141_2 , and selects the second output channel CH1 The output signal is output as the first output signal or the synchronization output signal generated by the synchronization unit 141_2. The output selection unit 142_3 is coupled to the third output channel CH2 of the channel connection module 130 and the synchronization unit 141_3, receives the signal output from the third output channel CH2 and the synchronization output signal generated by the synchronization unit 141_3, and connects the third output channel CH2 The output signal is output as the first output signal or the synchronization output signal generated by the synchronization unit 141_3.

In this embodiment, the channel connection module 130 designates the first output channel CH0 to output the first processed signal PS1, but the present invention is not limited thereto. In some embodiments, the channel connection module 130 can designate the first output channel CH1 or the second output channel to output the first processing signal PS1, which can achieve the same or similar effects.

FIG. 2 is a schematic diagram of the correspondence between the first event signal, the second event signal, the first processing signal, and the first synchronization output signal according to an embodiment of the present invention. FIG. 2 may correspond to the event control device 100 of FIG. 1 . In Fig. 2, S0 represents the first event signal, S1 represents the second event signal, PS1 represents the first processing signal, and SS1 represents the first synchronization output signal. Please refer to Figure 1 and Figure 2. The first selection module 110_1 outputs the first event signal S0, and the second selection module 110_2 outputs the second event signal S1. The selection unit 122_1 outputs the first event signal S0, and the selection unit 122_2 outputs the second event signal S1. The first logic processing unit 123_1 performs first logic processing (eg, OR logic processing) on the first event signal S0 and the second event signal S1 to generate a first processing signal PS1.

The channel connection module 130 designates the first output channel CH0 to output the first processing signal PS1. The synchronization unit 141_1 performs synchronization processing (eg, negative edge triggering) on the first processing signal PS1 by using the CLK1 to generate the first synchronization output signal SS1. However, this embodiment is not limited to this. In other embodiments, the synchronization unit 141_1 may also use the clock signal CLK1 to perform synchronization processing on the first processing signal PS1 through, for example, a positive edge trigger, so as to generate the first synchronization output signal SS1. The selection unit 142_1 can select to output the first processing signal PS1 or the first synchronization output signal SS1. For example, the first processing signal PS1 may be provided to the event control device 100 of the next stage for subsequent event connection operations. For example, the first synchronization output signal SS1 may be provided to the target peripheral device to instruct the target device to perform a corresponding operation.

FIG. 3 is a schematic diagram of an event control device according to another embodiment of the present invention. Please refer to FIG. 3 , the event control device 300 may include a first selection module 310_1 , a second selection module 310_2 , a third selection module 310_3 , a first processing module 320 , a channel connection module 330 and an output module 340 .

The first selection module 310_1 can receive a plurality of event signals S0 , S1 , S2 and a selection signal SEL1_1 , and output a first event signal S0 from the event signals S0 , S1 , and S2 according to the selection signal SEL1_1 . In this embodiment, the first selection module 110_1 may be a multiplexer. In addition, the above-mentioned event signals S0 , S1 , and S2 are generated by, for example, peripheral devices, and the peripheral devices are, for example, analog-to-digital converters, timers, etc., but the embodiments of the present invention are not limited thereto.

The second selection module 310_2 can receive the event signals S0, S1, S2 and the selection signal SEL1_2, and output the second event signal S1 from the event signals S0, S1, and S2 according to the selection signal SEL1_2. In this embodiment, the second selection module 310_2 may be a multiplexer. The third selection module 310_3 can receive the event signals S0 , S1 , S2 and the selection signal SEL1_3 , and output the third event signal S2 from the event signals S0 , S1 , and S2 according to the selection signal SEL1_3 . In this embodiment, the third selection module 310_3 may be a multiplexer.

The first processing module 320 is coupled to the first selection module 310_1, the second selection module 310_2 and the third selection module 310_3. The first processing module 320 can receive the first event signal S0, the second event signal S1 and the third event signal S2. The first processing module 320 can perform first logic processing on the first event signal S0 or the first inverted event signal S0' and the second event signal S1 or the second inverted event signal S1' to generate the first processing signal PS1 . For the manner in which the first processing module 320 generates the first processing signal PS1, reference may be made to the description of the embodiment of the first processing module 120 in FIG.

The first processing module 320 may perform second logic processing on the third event signal S2 or the third inverted event signal S2' to generate the second processing signal PS2. In this embodiment, the second logical processing is, for example, no processing. That is to say, the first processing module 320 can use the third event signal S2 or the third inverted event signal S2' as the second processing signal PS2, and output the second processing signal PS2. In this embodiment, the third inverted event signal S2' is an inverted signal of the third event signal S2.

The channel connection module 330 can receive the first processing signal PS1 and the second processing signal PS2, and designate the first output channel (eg CH0) of the output channels CH0, CH1 and CH2 to output the first processing signal PS1, and designate the output channels CH0, The second output channel (eg CH1) of CH1 and CH2 outputs the second processing signal PS2.

The output module 340 can receive the first processing signal PS1 and the second processing signal PS2, generate a first output signal or a first synchronization output signal according to the first processing signal PS1, and generate a second output according to the second processing signal PS2 signal or a second sync output signal.

Further, the first processing module 320 may include a first inverter 321_1, a second inverter 321_2, a third inverter 321_3, a first selection unit 322_1, a second selection unit 322_2, and a third selection unit 322_3 , the first logical processing unit 323_1 and the second logical processing unit 323_2. In this embodiment, the first inverter 321_1, the second inverter 321_2, the first selection unit 322_1, the second selection unit 322_2 and the first logic processing unit 323_1 are the same as the first inverter 121_1, The second inverter 121_2 , the first selection unit 122_1 , the second selection unit 122_2 and the first logic processing unit 123_1 are the same or similar, and the description of the embodiment in FIG. 1 can be referred to, so they are not repeated here.

The third inverter 321_3 has an input terminal and an output terminal, the input terminal of the third inverter 321_3 receives the third event signal S2, and the output terminal of the third inverter 321_3 generates the third inversion event signal S2'. That is, the third inverter 321_3 receives the third event signal S2 and inverts the third event signal S2 to generate the third inverted event signal S2'.

The third selection unit 322_1 may receive the third event signal S2, the third inversion event signal S2' and the selection signal SEL2_3, and select and output the third event signal S2 or the third inversion event signal S2' according to the selection signal SEL2_3.

The second logic processing unit 323_2 may receive the third event signal S2 or the third inverted event signal S2', and perform second logic processing on the third event signal S2 or the third inverted event signal S2' to generate the second processing Signal PS2.

The output module 340 may include a synchronization unit 341_1, a synchronization unit 341_2, a synchronization unit 341_3, an output selection unit 341_1, an output selection unit 342_2, and an output selection unit 342_3. The synchronization unit 341_1 is coupled to the first output channel CH0 of the channel connection module 330, receives a signal (eg, the first processing signal PS1) and the clock signal CLK1 output by the first output channel CH0, and uses the clock signal CLK1 to synchronize the first output channel CH0. The signal output by the output channel CH0 (eg, the first processing number PS1 ) is subjected to synchronization processing to generate a synchronization output signal (eg, the first synchronization output signal SS1 ).

The synchronization unit 341_2 is coupled to the second output channel CH2 of the channel connection module 330, receives the signal (eg, the second processing signal PS2) and the clock signal CLK2 output by the second output channel CH1, and uses the clock signal CLK2 to synchronize the second output channel CH1. The signal output by the output channel CH1 (eg, the second processing signal PS2 ) is subjected to synchronization processing to generate a synchronization output signal (eg, the second synchronization output signal SS2 ). The synchronization unit 341_3 is coupled to the third output channel CH2 of the channel connection module 330 , receives the signal output by the third output channel CH2 and the clock signal CLK3 , and uses the clock signal CLK3 to perform the signal output from the third output channel CH2 . Synchronous processing to generate a synchronized output signal.

The output selection unit 342_1 is coupled to the first output channel CH0 of the channel connection module 330 and the synchronization unit 341_1, and receives the signal output by the first output channel CH0 (eg, the first processing signal PS1) and the synchronization output signal generated by the synchronization unit 341_1 (for example, the first synchronization output signal SS1 ), and output the signal (for example, the first processing signal PS1 ) output by the first output channel CH0 as the first output signal or output the synchronization output signal (for example, the first processing signal PS1 ) generated by the synchronization unit 341_1 synchronous output signal SS1).

The output selection unit 342_2 is coupled to the second output channel CH1 of the channel connection module 330 and the synchronization unit 341_2, and receives the signal output by the second output channel CH1 (eg, the second processing signal PS2) and the synchronization output signal generated by the synchronization unit 341_2 (for example, the second synchronization output signal SS2 ), and output the signal (for example, the second processing signal PS2 ) output by the second output channel CH1 as the first output signal or output the synchronization output signal (for example, the second processing signal PS2 ) generated by the synchronization unit 341_2 synchronous output signal SS2). The output selection unit 342_3 is coupled to the third output channel CH2 of the channel connection module 130 and the synchronization unit 341_3, receives the signal output by the third output channel CH2 and the synchronization output signal generated by the synchronization unit 341_3, and connects the third output channel CH2 The output signal is output as the first output signal or the synchronization output signal generated by the synchronization unit 341_3.

FIG. 4 is a schematic diagram of an event control device according to another embodiment of the present invention. Referring to FIG. 4 , the event control device 400 may include a first selection module 310_1 , a second selection module 310_2 , a third selection module 310_3 , a first processing module 320 , a channel connection module 330 and an output module 410 .

In this embodiment, the first selection module 310_1, the second selection module 310_2, the third selection module 310_3, the first processing module 320 and the channel connection module 330 are the same as the first selection module 310_1, The second selection module 310_2 , the third selection module 310_3 , the first processing module 320 and the channel connection module 330 are the same or similar, so they are not repeated here.

In addition, the first processing module 320 may include a first inverter 321_1, a second inverter 321_2, a third inverter 321_3, a first selection unit 322_1, a second selection unit 322_2, a third selection unit 322_3, a A logic processing unit 323_1 and a second logic processing unit 323_2. In this embodiment, the first inverter 321_1, the second inverter 321_2, the third inverter 321_3, the first selection unit 322_1, the second selection unit 322_2, the third selection unit 322_3, the first logic processing unit 323_1 and the second logic processing unit 323_2 and the first inverter 321_1, the second inverter 321_2, the third inverter 321_3, the first selection unit 322_1, the second selection unit 322_2, the third selection unit in FIG. 1 322_3 , the first logical processing unit 323_1 and the second logical processing unit 323_2 are the same or similar, and reference may be made to the description of the embodiment in FIG. 3 , and thus will not be repeated here.

The output module 410 is coupled to the channel connection module 330, and can receive the first processing signal PS1 provided by the first output channel CH0 and the second processing signal PS2 provided by the second output channel CH1, and according to the first processing signal PS1 and the second processing signal PS2. The second processing signal PS2 generates a first output signal or a first synchronization output signal SS1.

Further, the output module 410 may include a second processing module 420, a synchronization unit 430_1, a synchronization unit 430_2, a synchronization unit 430_3, an output selection unit 440_3, an output selection unit 440_2, and an output selection unit 440_3.

The second processing module 420 is coupled to the channel connection module 330 . The second processing module 420 can at least receive the first processing signal PS1 and the second processing signal PS2 output by the channel connection module 330, and perform third logic processing on the first processing signal PS1 and the second processing signal PS2 to generate The third processed signal PS3 or the third inverted processed signal PS3'. In this embodiment, in this embodiment, the third logical processing may include AND processing, OR processing, inverse AND processing, mutually exclusive OR processing, and the like.

The synchronization unit 430_1 is coupled to the second processing module 420, receives the third processing signal PS3 or the third inversion processing signal PS3' and the clock signal CLK1, and uses the clock signal CLK1 to invert the third processing signal PS3 or the third inversion The processing signal PS3' is synchronized to generate the first synchronization output signal SS1. The synchronization unit 430_2 is coupled to the second processing module 420, receives the third processing signal or the third inversion processing signal and the clock signal CLK2 generated by the second processing module 420, and uses the clock signal CLK2 to process the third signal. Or the third inversion processing signal is synchronized to generate the second synchronized output signal. The synchronization unit 430_3 is coupled to the second processing module 420, receives the third processing signal or the third inverted processing signal and the clock signal CLK3 generated by the second processing module 420, and uses the clock signal CLK3 to process the third signal. Or the third inversion processing signal is subjected to synchronization processing to generate a third synchronization output signal.

The output selection unit 440_1 is coupled to the second processing module 420 and the synchronization unit 430_1, receives the third processing signal PS3 or the third inverted processing signal PS3' and the first synchronization output signal SS1, and converts the third processing signal PS3 or the third The inverted processing signal PS3' is output as the first output signal or outputs the first synchronization output signal SS1. The output selection unit 440_2 is coupled to the second processing module 420 and the synchronization unit 430_2, receives the third processing signal or the third inversion processing signal and the second synchronization output signal, and uses the third processing signal or the third inversion processing signal as the The second output signal outputs or outputs the second synchronization output signal. The output selection unit 430_3 is coupled to the second processing module 420 and the synchronization unit 430_3, receives the third processing signal or the third inversion processing signal and the third synchronization output signal, and uses the third processing signal or the third inversion processing signal as The third output signal outputs or outputs a third synchronization output signal.

In this embodiment, the second processing module 420 may include a plurality of second processing units 421_1, 421_2, and 421_3. The second processing unit 421_1 may include a first and gate 422_1, a second and gate 423_1, a third and gate 424_1, a third logical processing unit 425_1 and an exclusive OR gate 426_1.

The first and gate 422_1 has a first terminal, a second terminal and an output terminal. The first end of the first and gate 422_1 receives the first enable signal ES1_1, and the second end of the first and gate 422_1 is coupled to the first output channel CH0 and receives a signal (eg, a first processing signal) output by the first output channel CH0 PS1), the first terminal of the first sum gate 422_1 outputs the first sum signal. The second gate 423_1 has a first terminal, a second terminal and an output terminal. The first end of the second gate 422_2 receives the second enable signal ES2_1, and the second end of the second gate 423_1 is coupled to the second output channel CH1 and receives the signal (eg, the second processing signal) output by the second output channel CH1 PS2), the first terminal of the second sum gate 423_1 outputs the second sum signal. The third gate 424_1 has a first terminal, a second terminal and an output terminal. The first end of the third and gate 424_1 receives the fourth enable signal ES4_1, the second end of the third and gate 424_1 is coupled to the third output channel CH2 and receives the signal output by the third output channel CH2, and the third and gate 424_1 The first terminal outputs the third sum signal.

The third logic processing unit 425_1 is coupled to the output end of the first sum gate 422_1, the output end of the second sum gate 423_1 and the output end of the third sum gate 424_1, and receives the first sum signal, the second sum signal and the third sum signal , and perform third logic processing on the first sum signal, the second sum signal, and the third sum signal to generate a third processing signal PS3. The exclusive OR gate 426_1 has a first terminal, a second terminal and an output terminal. The first terminal of the exclusive OR gate 426_1 receives the third processing signal PS3, the second terminal of the mutual exclusive OR gate 426_1 receives the third enable signal ES3_1, and the output terminal of the exclusive OR gate 426_1 generates the third processing signal PS3 or the third processing signal ES3_1. Invert the processed signal PS3'.

The second processing unit 421_2 may include a first AND gate 422_2, a second AND gate 423_2, a third AND gate 424_2, a third logical processing unit 425_2, and an exclusive OR gate 426_2.

The first and gate 422_2 has a first terminal, a second terminal and an output terminal. The first end of the first and gate 422_2 receives the first enable signal ES1_2, the second end of the first and gate 422_2 is coupled to the first output channel CH0 and receives the signal output by the first output channel CH0, the first and the gate 422_2 The first terminal outputs the first sum signal. The second gate 423_2 has a first terminal, a second terminal and an output terminal. The first end of the second sum gate 423_2 receives the second enable signal ES2_2, the second end of the second sum gate 423_2 is coupled to the second output channel CH1 and receives the signal output by the second output channel CH1, the second sum gate 423_2 The first terminal outputs the second sum signal. The third gate 424_2 has a first terminal, a second terminal and an output terminal. The first end of the third and gate 424_2 receives the fourth enable signal ES4_2, the second end of the third and gate 424_2 is coupled to the third output channel CH2 and receives the signal output by the third output channel CH2, and the third and gate 424_2 The first terminal outputs the third sum signal.

The third logic processing unit 425_2 is coupled to the output end of the first sum gate 422_2, the output end of the second sum gate 423_2 and the output end of the third sum gate 424_2, and receives the first sum signal, the second sum signal and the third sum signal , and perform third logic processing on the first sum signal, the second sum signal and the third sum signal to generate a third processed signal. The exclusive OR gate 426_2 has a first terminal, a second terminal and an output terminal. The first end of the mutually exclusive OR gate 426_2 receives the third processing signal PS3, the second end of the mutually exclusive OR gate 426_2 receives the third enable signal ES3_2, and the output end of the mutually exclusive OR gate 426_2 generates the third processing signal or the third reverse signal. Phase processing signal.

The second processing unit 421_3 may include a first AND gate 422_3, a second AND gate 423_3, a third AND gate 424_3, a third logical processing unit 425_3, and an exclusive OR gate 426_3.

The first and gate 422_3 has a first terminal, a second terminal and an output terminal. The first end of the first and gate 422_3 receives the first enable signal ES1_3, the second end of the first and gate 422_3 is coupled to the first output channel CH0 and receives the signal output by the first output channel CH0, the first and the gate 422_3 The first terminal outputs the first sum signal. The second gate 423_3 has a first terminal, a second terminal and an output terminal. The first end of the second sum gate 423_3 receives the second enable signal ES2_3, the second end of the second sum gate 423_3 is coupled to the second output channel CH1 and receives the signal output by the second output channel CH1, the second sum gate 423_3 The first terminal outputs the second sum signal. The third gate 424_3 has a first terminal, a second terminal and an output terminal. The first end of the third and gate 424_3 receives the fourth enable signal ES4_3, the second end of the third and gate 424_3 is coupled to the third output channel CH2 and receives the signal output by the third output channel CH2, and the third and gate 424_3 The first terminal outputs the third sum signal.

The third logic processing unit 425_3 is coupled to the output end of the first sum gate 422_3, the output end of the second sum gate 423_3 and the output end of the third sum gate 424_3, and receives the first sum signal, the second sum signal and the third sum signal , and perform third logic processing on the first sum signal, the second sum signal and the third sum signal to generate a third processed signal.

The exclusive OR gate 426_3 has a first terminal, a second terminal and an output terminal. The first end of the mutually exclusive OR gate 426_3 receives the third processing signal, the second end of the mutually exclusive OR gate 426_3 receives the third enable signal ES3_3, and the output end of the mutually exclusive OR gate 426_3 generates the third processing signal or the third inversion Process the signal.

In this embodiment, the number of the first and gates 422_1 to 422_3, the second and gates 423_1 to 423_3, and the third and gates 424_1 to 424_3 corresponds to the number of the output channels CH0, CH1 and CH2 of the channel connection module 330 .

In addition, in the foregoing embodiment, the first processing signal PS1 and the second processing signal PS2 are provided to the third logic processing unit 425_1, and the third logic processing unit 425_1 performs the third processing on the first processing signal PS1 and the second processing signal PS2. Logical processing (for example, sum processing, or processing, anti-sum processing, mutual exclusion or processing, etc.), but the embodiment of the present invention is not limited thereto. In some embodiments, the first processing signal PS1 and the second processing signal PS2 may be provided to the third logic processing units 425_1 and 425_2, respectively, and the third logic processing units 425_1 and 425_2 may process the first processing signal PS1 and the second processing signal Signal PS2 undergoes third logic processing. In this embodiment, the third logic processing of the third logic processing units 425_1 and 425_2 is, for example, no processing. That is, the third logic processing unit 425_1 may take the first processing signal PS1 as the third processing signal PS3 output by the third logic processing unit 425_1, and the third logic processing unit 425_2 may take the second processing signal PS2 as the third processing signal PS2 The third processing signal PS3 output by the logic processing unit 425_2.

FIG. 5 is a schematic diagram of the correspondence between the first event signal, the second event signal, the first processing signal, the third event signal, the second processing signal, the third processing signal and the first synchronization output signal according to an embodiment of the present invention. . FIG. 5 may correspond to the event control device 400 of FIG. 4 . In Fig. 5, S0 represents the first event signal, S1 represents the second event signal, PS1 represents the first processing signal, S2 represents the third event signal, PS2 represents the second processing signal, PS3 represents the third processing signal, and SS1 represents the The first synchronization output signal. Please refer to FIG. 4 and FIG. 5, the first selection module 310_1 outputs the first event signal S0, the second selection module 310_2 outputs the second event signal S1, and the third selection module 310_3 outputs the third event signal S2. The selection unit 322_1 outputs the first event signal S0, the selection unit 322_2 outputs the second event signal S1, and the selection unit 322_3 outputs the third event signal S2.

The first logic processing unit 323_1 performs first logic processing (eg, OR logic processing) on the first event signal S0 and the second event signal S1 to generate a first processing signal PS1. The second logic unit 323_2 performs second logic processing (eg, "no processing") on the second event signal S2, so as to use the second event signal S2 as the second processing signal PS2.

The channel connection module 330 designates the first output channel CH0 to output the first processed signal PS1 and designates the second output channel CH1 to output the second processed signal PS2. The first enable signal ES1_1 and the second enable signal ES2_1 are enabled, and the first enable signals ES1_2 to ES1_3, the second enable signals ES2_2 to ES2_3, the fourth enable signals ES4_1 to ES4_3, the third The enable signals ES3_1 to ES3_3 are disabled.

The first sum signal output by the first sum gate 422_1 is the first processing signal PS1, and the second sum signal output by the second sum gate 423_1 is the second processing signal PS2. The third logic unit 425_1 performs third logic processing (eg, OR logic processing) on the first processing signal PS1 and the second processing signal PS2 to generate a third processing signal PS3. The synchronization unit 430_1 uses the clock signal CLK1 to perform synchronization processing (eg, negative edge triggering) on the third processing signal PS3 to generate the first synchronization output signal SS1. However, this embodiment is not limited to this. In other embodiments, the synchronization unit 430_1 may also use the clock signal CLK1 to perform synchronization processing on the third processing signal PS3 through, for example, a positive edge trigger, so as to generate the first synchronization output signal SS1. The selection unit 440_1 can select to output the third processing signal PS1 or the first synchronization output signal SS1. For example, the third processing signal PS3 may be provided to the event control device 400 of the next stage, so as to perform subsequent event connection operations. For example, the first synchronization output signal SS1 may be provided to the target peripheral device to instruct the target device to perform a corresponding operation.

FIG. 6 is a schematic diagram of an event control device according to another embodiment of the present invention. Referring to FIG. 6 , the event control device 600 includes a first selection module 610_1 , a second selection module 610_2 , a channel connection module 630 and an output module 640 . In this embodiment, the first selection module 610_1 and the second selection module 610_2 are the same as or similar to the first selection module 110_1 and the second selection module 110_2 in FIG. description, so it is not repeated here.

The channel connection module 630 is coupled to at least the first selection module 610_1 and the second selection module 610_2. The channel connection module 630 can at least receive the first event signal S0 and the second event signal S1, and designate the first output channel (eg CH0) of the output channels CH0, CH1 and CH2 to output the first event signal S0, and designate the output channel CH0 The second output channel (eg CH1) of , CH1 and CH2 outputs the second event signal S1.

The output module 640 is coupled to the channel connection module 630, receives the first event signal S0 and the second event signal S1, and performs a fourth logic operation on the first event signal S0 and the second event signal S1 to generate a fourth processing signal or the fourth inversely processed signal, and according to the fourth processed signal or the fourth inversely processed signal, a fourth output signal or a fourth synchronous output signal is generated.

Further, the output module 640 may include a second processing module 420, a synchronization unit 430_1, a synchronization unit 430_2, a synchronization unit 430_3, an output selection unit 440_3, an output selection unit 440_2, and an output selection unit 440_3. In this embodiment, the second processing module 420, the synchronization unit 430_1, the synchronization unit 430_2, the synchronization unit 430_3, the output selection unit 440_3, the output selection unit 440_2 and the output selection unit 440_3 and the second processing module 420 in FIG. 5 , synchronizing unit 430_1, synchronizing unit 430_2, synchronizing unit 430_3, output selecting unit 440_3, output selecting unit 440_2 and output selecting unit 440_3 are the same or similar, please refer to the description of the embodiment in FIG.

In addition, the second processing module 420 in FIG. 6 may also include second processing units 421_1, 421_2, and 421_3. The second processing units 421_1, 421_2, 421_3 and their internal components in FIG. 6 are the same as or similar to the second processing units 421_1, 421_2, 421_3 and their internal components in FIG. 5. Please refer to the description of the embodiment in FIG. 5. Therefore, it will not be repeated here.

In addition, the event control device 600 can also receive the event signal S2, and includes a third selection module 610_3. The first selection module 610_1 , the second selection module 610_2 and the third selection module 610_3 may be the same as the first selection module 310_1 , the second selection module 310_2 and the third selection module 310_3 in FIG. 3 or FIG. 4 . For the same or similar, reference may be made to the description of the embodiment in FIG. 3 or FIG. 4 , and thus will not be repeated here. In this way, the event control device 600 can also increase the flexibility of the event connection and the usage context, so as to increase the convenience of use.

FIG. 7 is a schematic diagram of an event control system according to an embodiment of the present invention. Please refer to FIG. 7 , the event control system 700 includes a plurality of event control devices 710_1 to 710_N, wherein N is a positive integer greater than 1. The event control devices 710_1 to 710_N are connected in series in sequence, and the event control devices 710_1 to 710_N may be implemented by the event control devices 100 , 300 , 400 , 500 and 600 , respectively. In this way, the event control system 700 can also achieve increased flexibility of event connection and usage scenarios, so as to increase the convenience of use.

With the description of the above embodiments, the embodiments of the present invention provide an operation method of an event control device. FIG. 8 is a flowchart of an operation method of an event control apparatus according to an embodiment of the present invention. In step S802, a plurality of event signals are received through the first selection module, and a first event signal is output. In step S804, the event signal is received through the second selection module, and the second event signal is output.

In step S806, a first logic processing is performed on the first event signal or the first inverted event signal and the second event signal or the second inverted event signal through the first processing module to generate a first processing signal. In step S808, the first processing signal is received through the channel connecting module, and the first output channel of the plurality of output channels of the channel connecting module is designated to output the first processing signal. In step S810, the output module receives the first processing signal, and generates the first output signal or the first synchronization output signal according to the first processing signal. In this embodiment, the first logical processing includes, for example, AND processing, OR processing, inverse AND processing, and mutually exclusive OR processing.

FIG. 9 is a detailed flowchart of step S806 in FIG. 8 . In step S902, the first event signal is inverted through the first inverter of the first processing module to generate a first inverted event signal. In step S904, the second event signal is inverted through the second inverter of the first processing module to generate a second inverted event signal. In step S906, the first event signal or the first inversion event signal is selected to be output through the first selection unit of the first processing module. In step S908, the second event signal or the second inversion event signal is selected to be output through the second selection unit of the first processing module. In step S910, the first logic processing unit of the first processing module performs first logic processing on the first event signal or the first inversion event signal and the second event signal or the second inversion event signal to generate The first process signal.

FIG. 10 is a detailed flowchart of step S810 in FIG. 8 . In step S1002, the synchronization unit of the output module performs synchronization processing on the first processing signal to generate a first synchronization output signal. In step S1004, the first processing signal is output as the first output signal or the first synchronization output signal is output through the output selection unit of the output module.

FIG. 11 is a flowchart of an operation method of an event control device according to another embodiment of the present invention. In this embodiment, steps S802 to S808 are the same as or similar to steps S802 to S808 in FIG. 8 . Reference can be made to the description of the embodiment in FIG. 8 , and details are not repeated here.

In step S1102, through the third selection module, the event signal is received, and the third event signal is output. In step S1104, through the first processing module, second logic processing is performed on the third event signal or the third inverted event signal to generate a second processing signal. In step S1106, the second processing signal is received through the channel connecting module, and the second output channel of the output channel of the channel connecting module is designated to output the second processing signal. In step S1108, the first processing signal and the second processing signal are received through the output module, and the first output signal or the first synchronization output signal is generated according to the first processing signal and the second processing signal.

FIG. 12 is a detailed flowchart of step S1104 in FIG. 11 . In step S1202, the third event signal is inverted through the third inverter of the first processing module to generate a third inverted event signal. In step S1204, the third event signal or the third inversion event signal is selected to be output through the third selection unit of the first processing module. In step S1206, second logic processing is performed on the third event signal or the third inverted event signal through the second logic processing unit of the first processing module to generate a second processing signal. In this embodiment, the second logical processing is, for example, no processing.

FIG. 13 is a detailed flowchart of step S1108 in FIG. 11 . In step S1302, through the second processing module of the output module, a third logic processing is performed on the first processing signal and the second processing signal to generate a third processing signal or a third inversion processing signal. In step S1304, the synchronization unit of the output module performs synchronization processing on the third processing signal or the third inversion processing signal to generate a first synchronization output signal. In step S1306, the third processing signal or the third inversion processing signal is output as the first output signal or the first synchronization output signal is output through the output selection unit of the output module.

FIG. 14 is a detailed flowchart of step S1302 in FIG. 13 . In step S1402, the first enabling signal and the first processing signal are received through the first gate of the second processing module, and the first sum signal is output. In step S1404, the second enable signal and the second processing signal are received through the second gate of the second processing module, and the second sum signal is output. In step S1406, the third logic processing unit of the second processing module receives the first sum signal and the second sum signal, and performs third logic processing on the first sum signal and the second sum signal to generate a third sum signal. Process the signal. In step S1408, the third processing signal and the third enabling signal are received through the mutual exclusion or gate of the second processing module, and the third processing signal or the third inversion processing signal is generated. In this embodiment, the third logical processing includes, for example, AND processing, OR processing, anti-AND processing, and mutual exclusion or processing.

It should be noted that the sequence of the steps in Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 and Fig. 14 are only for illustrative purposes and are not intended to limit the implementation of the present invention The order of the steps is illustrated, and the order of the above-mentioned steps can be changed by users according to their needs. Also, additional steps may be added or fewer steps may be used without departing from the spirit and scope of the present invention.

To sum up, in the event control device and the operation method thereof disclosed in the present invention, at least the first event signal or the first inverted event signal and the second event signal or the second inverted event signal are processed by the first processing module. The first logical processing is to generate the first processing signal, the first output channel of the designated output channel of the channel connection module outputs the first processing signal, and the output module generates the first output signal or the first synchronization output according to the first processing signal Signal. In this way, the flexibility of the event connection and the usage context can be effectively increased, so as to increase the convenience of use.

In addition, the first processing module of this embodiment may further perform second logic processing on the third event signal or the third inverted event signal to generate a second processing signal, and the channel connection module specifies the second output of the output channel The channel outputs the first processing signal, and the output module generates the second output signal or the second synchronous output signal according to the second processing signal. In addition, the output module of this embodiment may further perform third logic processing on the first processing signal and the second processing signal to generate the first output signal or the first synchronous output signal. In this way, the flexibility and usage context of event connection can be increased.

Although the present invention is disclosed above by the embodiments, it is not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

100,300,400,500,600,710_1~710_N: Event control device 110_1, 310_1, 610_1: first choice module 110_2, 310_2, 610_2: Second choice module 120,320: The first processing module 121_1, 321_1: first inverter 121_2, 321_2: Second inverter 122_1, 322_1: The first selection unit 122_2, 322_2: Second selection unit 123_1, 323_1: the first logical processing unit 130, 330, 630: Channel Link Module 140,340,410,640: Output module 141_1~141_3, 341_1~341_3, 430_1~430_3: synchronization unit 142_1~142_3, 342_1~342_3, 440_1~440_3: output selection unit 310_3, 610_3: The third option module 321_3: Third inverter 322_3: Third selection unit 323_2: Second logical processing unit 420: Second processing module 421_1~421_3: The second processing unit 422_1~422_3: The first gate 423_1~423_3: The second gate 424_1~424_3: The third gate 425_1~425_3: The third logical processing unit 426_1~426_3: Mutually exclusive or gate 700: Event Control System CH0, CH1, CH2: output channel S0, S1, S2: event signal SEL1_1~SEL1_3,SEL2_1~SEL2_3,SEL3_1~SEL3_3: Selection signal S0': The first inversion event signal S1': The second inversion event signal PS1: The first processing signal PS2: Second Processing Signal PS3: The third processing signal PS3': The third inverted processed signal SS1: The first synchronization output signal CLK1~CLK3: Clock signal ES1_1~ES1_3: The first enable signal ES2_1~ES2_3: The second enable signal ES3_1~ES3_3: The third enable signal ES4_1~ES4_3: Fourth enable signal S802~S810, S902~S910, S1002~S1004, S1102~S1108, S1202~S1206, S1302~S1306, S1402~S1408: Steps

FIG. 1 is a schematic diagram of an event control apparatus according to an embodiment of the present invention. FIG. 2 is a schematic diagram of the correspondence between the first event signal, the second event signal, the first processing signal, and the first synchronization output signal according to an embodiment of the present invention. FIG. 3 is a schematic diagram of an event control device according to another embodiment of the present invention. FIG. 4 is a schematic diagram of an event control device according to another embodiment of the present invention. FIG. 5 is a schematic diagram of the correspondence between the first event signal, the second event signal, the first processing signal, the third event signal, the second processing signal, the third processing signal and the first synchronization output signal according to an embodiment of the present invention. . FIG. 6 is a schematic diagram of an event control device according to another embodiment of the present invention. FIG. 7 is a schematic diagram of an event control system according to an embodiment of the present invention. FIG. 8 is a flowchart of an operation method of an event control apparatus according to an embodiment of the present invention. FIG. 9 is a detailed flowchart of step S806 in FIG. 8 . FIG. 10 is a detailed flowchart of step S810 in FIG. 8 . FIG. 11 is a flowchart of an operation method of an event control device according to another embodiment of the present invention. FIG. 12 is a detailed flowchart of step S1104 in FIG. 11 . FIG. 13 is a detailed flowchart of step S1108 in FIG. 11 . FIG. 14 is a detailed flowchart of step S1302 in FIG. 13 .

100: Event Control Device

110_1: First choice module

110_2: Second choice module

120: The first processing module

121_1: first inverter

121_2: Second inverter

122_1: First selection unit

122_2: Second selection unit

123_1: The first logical processing unit

130: Channel Link Module

140: Output module

141_1~141_3: Synchronization unit

142_1~142_3: Output selection unit

CH0, CH1, CH2: output channel

S0, S1: event signal

SEL1_1~SEL1_2,SEL2_1~SEL2_2,SEL3_1~SEL3_3: Selection signal

S0': The first inversion event signal

S1': The second inversion event signal

PS1: The first processing signal

SS1: The first synchronization output signal

CLK1~CLK3: Clock signal

Claims (10)

An event control device, comprising: a first selection module, receiving a plurality of event signals and outputting a first event signal; a second selection module, receiving the event signals and outputting a second event signal; a A first processing module, coupled to the first selection module and the second selection module, receives the first event signal and the second event signal, the first processing module for the first event signal or a first event signal An inversion event signal and the second event signal or a second inversion event signal are subjected to a first logic processing to generate a first processing signal; a channel connection module is coupled to the first processing module and has a plurality of output channels, the channel connection module receives the first processing signal, and designates a first output channel of the output channels to output the first processing signal; and an output module, coupled to the channel connection module, The first processing signal is received, and according to the first processing signal, a first output signal or a first synchronization output signal is generated. The event control device of claim 1, wherein the first processing module comprises: a first inverter for receiving the first event signal and inverting the first event signal to generate the first inversion event signal; a second inverter receives the second event signal and inverts the second event signal to generate the second inverted event signal; a first selection unit receives the first event signal and the a first inversion event signal, and selects to output the first event signal or the first inversion event signal; a second selection unit, receives the second event signal and the second inversion event signal, and selects to output the first event signal The second event signal or the second inverted event signal; and a first logic processing unit, receiving the first event signal or the first inversion event signal and the second event signal or the second inversion event signal, and processing the first event signal or the first inversion event The first logic processing is performed on the signal and the second event signal or the second inverted event signal to generate the first processing signal. If the event control device of claim 1 or 2, it also includes: a third selection module, coupled to the first processing module, receives the event signals, and outputs a third event signal; The first processing module further receives the third event signal, and the first processing module performs a second logic processing on the third event signal or a third inverted event signal to generate a second processing signal ; Wherein, the channel connection module further receives the second processing signal, and designates a second output channel of the output channels to output the second processing signal; The output module further receives the second processing signal, and generates a first output signal or a first synchronization output signal according to the first processing signal and the second processing signal. The event control device of claim 3, wherein the first processing module further comprises: a third inverter receiving the third event signal and inverting the third event signal to generate a third inverting event signal; a third selection unit, receiving the third event signal and the third inversion event signal, and selecting and outputting the third event signal or the third inversion event signal; and a second logic processing unit, receiving the third event signal or the third inversion event signal, and performing the second logic processing on the third event signal or the third inversion event signal to generate the second processing Signal. The event control device of claim 3, wherein the output module comprises: A second processing module, coupled to the channel connection module, receives the first processing signal and the second processing signal, and performs a third logic processing on the first processing signal and the second processing signal to generate a the third processed signal or a third inverted processed signal; a synchronization unit, coupled to the second processing module, receives the third processing signal or the third inversion processing signal, and performs synchronization processing on the third processing signal or the third inversion processing signal to generate the a first synchronization output signal; and an output selection unit, coupled to the second processing module and the synchronization unit, receives the third processing signal or the third inversion processing signal and the first synchronization output signal, and converts the third processing signal or the first The three-phase inversion processing signal is output as the first output signal or the first synchronous output signal is output. The event control device of claim 5, wherein the second processing module comprises: a first and gate, having a first end, a second end and an output end, the first end of the first and gate receives a first enable signal, and the second end of the first and gate receives the first processing signal, the first end of the first sum gate outputs a first sum signal; A second and gate has a first end, a second end and an output end, the first end of the second and gate receives a second enable signal, and the second end of the second and gate receives the second processing signal, the first end of the second sum gate outputs a second sum signal; a third logic processing unit, coupled to the output end of the first sum gate and the output end of the second sum gate, receives the first sum signal and the second sum signal, and combines the first sum signal and the second sum signal The second sum signal is subjected to the third logic processing to generate the third processed signal; and A mutex OR gate has a first end, a second end and an output end, the first end of the mutex OR gate receives the third processing signal, and the second end of the mutex OR gate receives a For a third enable signal, the output terminal of the mutually exclusive OR gate generates the third processing signal or the third inversion processing signal. The event control device of claim 6, wherein the third logical processing includes an AND process, an OR process, an inverse-AND process, and an exclusive OR process. The event control device of claim 1, wherein the output module comprises: a synchronization unit, coupled to the channel connection module, receives the first processing signal, and performs synchronization processing on the first processing signal to generate the first synchronization output signal; and an output selection unit, coupled to the channel connection module and the synchronization unit, receives the first processing signal and the first synchronization output signal, and outputs the first processing signal as the first output signal or outputs the first Sync output signal. An operation method of an event control device, comprising: receiving a plurality of event signals through a first selection module, and outputting a first event signal; receiving the event signals through a second selection module and outputting a second event signal; Through a first processing module, a first logic processing is performed on the first event signal or a first inversion event signal and the second event signal or a second inversion event signal to generate a first processing signal ; receiving the first processing signal through a channel linking module, and assigning a first output channel of a plurality of output channels of the channel linking module to output the first processing signal; and The first processing signal is received through an output module, and a first output signal or a first synchronization output signal is generated according to the first processing signal. The operation method of the event control device as claimed in claim 9, wherein receiving the first processing signal through the output module, and generating the first output signal or the first synchronization output signal according to the first processing signal comprises: performing synchronization processing on the first processing signal through a synchronization unit of the output module to generate the first synchronization output signal; and Through an output selection unit of the output module, the first processing signal is output as the first output signal or the first synchronization output signal is output.

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