JPH01319341A - Pn code acquisition circuit - Google Patents

Abstract

PURPOSE:To surely acquire a PN code regardless of using a clock equal to a chip frequency by giving two clocks whose chip frequency is equal to the chip frequency and whose phase is deviated by 180 deg. alternately to each correlation device so as to acquire the PN code. CONSTITUTION:A clock with a frequency equal to the chip frequency generated by a clock generator 12 is subjected to change in phase by 180 deg. by an inversion circuit 13. Then either of the two clocks with different phase is selected by a selection circuit 14 and given to correlation devices A, B. The selection circuit 14 is switched by a timer 15 every prescribed time, and the two clocks with a different phase are inputted alternately to the correlation devices A, B every prescribed time. Thus, even if the PN code is not acquired in one clock state. the acquisition of the PN code is surely finished in the other clock state.

Description

Detailed Description of the Invention [Field of Application in Industry A] The present invention relates to a PN code acquisition circuit for detecting the phase of a bit string consisting of a fixed pattern, and particularly to a PN code acquisition circuit used as an initial acquisition circuit in direct sequence spread spectrum communication. - [Prior art] Fig. 3 shows, for example, 'The Application
of Char, ge-Coupled Device
s to 5pread-SpectrumSyst
ems”, IEEE, Trans Coma+un
, C0M-28No., 9° 1980. In the figure, (1) is a received signal input terminal, and (2) is a terminal for converting this received signal into a baseband signal. Baseband conversion circuit, (A), (B)
are two sets of correlators with the same configuration, (3) is a sample hold circuit that samples the baseband signal from the baseband conversion circuit (2), and (4) is a shift register 1 that stores the sampled signal. (5) samples the baseband signal at twice the frequency and samples the above shift register 1 (4).
), (6) is a shift register 2 that stores a PN code (internal PN code) prepared in advance to correlate with the received PN code, (7) is A multiplier that multiplies the received signal and internal PN code by the number of stages of shift registers 1.2 (4) and (6), (8) is only the output of the odd stage among the outputs of the multiplier (7). (9) is an adder 2 that adds only the outputs of even-numbered stages among the outputs of the multiplier (7), and (10) is an adder 2 (10) that adds together the outputs of each of the adders 1.2 (
8), (9) and each adder (
(11) is a PN code acquisition circuit output terminal that outputs the output of this determination circuit (10) to the outside.

The conventional PN code acquisition circuit is configured as described above, and the received signal input to the received signal input terminal (1) is converted to a baseband signal by the baseband conversion circuit (2), and then the received signal is converted to a baseband signal by the clock generator ( It is sampled by the sample-and-hold circuit (3) using a clock with twice the frequency of the baseband signal generated in step 5), and is transferred to shift register 1 (4).
is stored in

Here, if one bit of the baseband signal is called a chip, it will be sampled twice for one chip.

Next, this signal is multiplied by the internal PN code stored in advance in the shift register 2 (6) by a multiplier (7) for each stage of the shift register 1.2 (4), (6). Then, the multiplication results of odd-numbered stages are added by adder 1 (8), and the multiplication results of even-numbered stages are added by adder 2 (9).
is added by

A similar operation is performed in the other correlator (B), and the summed outputs are inputted to a determination circuit (10), which determines whether or not the phases of the PN codes match. The determination result is outputted to the outside from the PN code acquisition circuit output terminal (11).

[Problems to be Solved by the Invention] In the conventional PN code acquisition circuit as described above, for example, P
If the N code length is M chips, the correlator (A), (
B) requires 2M stages. And the correlator is (A
) and (B) are used, so the total number of correlation stages is 4M stages.

From the perspective of hardware, the proportion of the correlator in the PN code acquisition circuit is very large, and especially when the PN code length M is large, it is still difficult to realize a correlator with such a large number of stages with recent LSI technology. is difficult. This is because, in the spread spectrum communication method, the signal-to-noise ratio of the received signal is very small compared to the conventional narrowband communication method, and it is not possible to obtain a clock synchronized with the chip. As shown in Figure 4, I sampled the chip transient (turning point), and P
Since it may become impossible to capture the N code, there is a problem in that it is necessary to sample at a frequency twice the chip frequency and to adopt a configuration that prevents such a situation from occurring.

The present invention has been made to solve this problem, and an object of the present invention is to obtain a PN code acquisition circuit that can be miniaturized by halving the number of correlation stages of the correlator compared to the conventional one.

[Means for Solving the Problems] A PN code acquisition circuit according to the present invention includes a baseband conversion circuit that converts a received signal to a baseband signal, a sample hold circuit that samples the baseband signal, and a sample hold circuit that stores the sampled signal. Two sets of shift registers each having a shift register, a shift register that stores a PN code prepared in advance, a multiplier that multiplies the received PN code and the PN code prepared in advance, and an adder that adds the results of all the multipliers. A correlator, a determination circuit that determines whether or not PN codes match based on the addition outputs of these correlators and outputs the result, a clock generator that generates a clock with a frequency equal to the chip frequency, and a clock generator. an inversion circuit that inverts the phase of the clock; a selection circuit that selects either the clock from the clock generator or the clock from the inversion circuit and supplies it to each of the correlators; The system is equipped with a timer for switching to.

[Operation] In the present invention, the phase of a clock having a frequency equal to the chip frequency generated by the clock generator is changed by 180 degrees by the inverting circuit. Then, one of these two clocks with different phases is selected by a selection circuit and inputted to each correlator.The 0 selection circuit is switched by a timer at regular intervals, so that each correlator Two clocks with different phases are input alternately at regular intervals. Therefore, even if the PN code cannot be captured in one clock state, the PN code capture can be reliably completed in the other clock state. Furthermore, since a clock equal to the chip frequency is always input to each correlator, the PN code acquisition circuit can be constructed using correlators with half the number of conventional correlation stages.

[Example] Figure 1 shows an example of the present invention.
The same reference numerals as in the figures indicate the same or corresponding parts. (12) is a clock generator 2 that generates a clock with a frequency equal to the chip frequency, and (13) is this clock generator 2 (1
2), an inverting circuit (14) for inverting the phase of the clock generated by the above clock generator 2 (12) is inputted with a clock from the above clock generator 2 (12) and a clock whose phase is shifted by 180 degrees from the above inverting circuit (13). , a selection circuit that selects one of them and applies it to each correlator (^), (B), (15) is a timer that switches this selection circuit (14) at regular intervals, and (16) is the number of correlator stages. This is an adder 3 that adds all the multiplication results.

In the PN code acquisition circuit configured as above,
The clock equal to the chip frequency generated by the clock generator 2 (12) has its phase inverted by the inverting circuit (13), and the clock generated by the clock generator 2 (12) and the inverting circuit (13) is inverted in phase.
3), two clocks with a phase shift of 1° and 80 degrees are generated. Both of these clocks are input to a selection circuit (14), which selects one of the clocks and inputs it to each correlator (A), (B).

For example, if we consider a case where a clock with phase (a) shown in FIG. 2 is input to each correlator (A) and (B),
In this clock state, no correlation can be established and the PN remains constant.
Code acquisition is not complete.

Therefore, if the acquisition is not completed within a certain period of time set by the timer (15) so that the selection circuit (14) is switched at an appropriate certain period of time, the phase of (b) shown in Fig. 2 will be shifted by 180 degrees. The selected clock is selected and each correlator (^),
(B) is given.

Thus, acquisition of the PN code is guaranteed to be completed in any clock state. Furthermore, since the clock input to each correlator (A) and (B) is always equal to the chip frequency, it is possible to reduce the number of correlators (A) and (B) to half the number of conventional correlation stages. This makes it possible to downsize the PN code acquisition circuit.

[Effects of the Invention] As explained above, the present invention captures the PN code by alternately applying two clocks equal to the chip frequency and having a phase difference of 180 degrees to each correlator. This has the effect that the PN code can be reliably captured even though a clock equal to the chip frequency is used. Furthermore, since a clock equal to the chip frequency is used, the number of correlation stages in the correlator can be halved compared to the conventional one, and the PN code acquisition circuit can be miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PN code capture circuit showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between the chip and the clock in the circuit of the present invention, and FIG. 3 is a conventional PN code capture circuit. FIG. 4 is an explanatory diagram showing the relationship between a chip and a clock in a conventional circuit. (2)... Baseband conversion circuit, (3)... Sample hold circuit, (4)... Shift register 1, (6)... Shift register 2, (7)... Multiplier, (10)...determination circuit, (12
)...Clock generator 2, (13)...Inversion circuit,
(14)...Selection circuit, (15)...Timer, (1
6)... Adder 3, (A), (B)... Correlator. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A baseband conversion circuit that converts a received signal to a baseband signal, a sample hold circuit that samples the baseband signal, a shift register that stores the sampled signal, a shift register that stores a PN code prepared in advance, and a received PN code. and a PN code prepared in advance, and two sets of correlators each having an adder that adds the results of all the multipliers. A determination circuit that determines the presence or absence and outputs the result, a clock generator that generates a clock with a frequency equal to the chip frequency, an inversion circuit that inverts the phase of the clock from the clock generator, and a clock from the clock generator. A PN code capture circuit comprising: a selection circuit that selects one of the clocks from the inversion circuit and applies it to each of the correlators; and a timer that switches the selection circuit at regular intervals.