JPH01161934A - Pn code acquisition circuit - Google Patents

Abstract

PURPOSE:To acquire the PN code at a high speed even when the accuracy of an AFC circuit is not enough by constituting an adder means by plural adders with different addition number. CONSTITUTION:An adder 14 with different addition stage number from that of an adder 11 constitutes an addition means together with the adder 11. Since the number of addition stages of both the adders 11, 14 constituting the adder means differs from each other, even if a frequency deviation component is included in the reception code inputted to a shift register 8, the result of correlation with less effect of the frequency deviation is outputted. Thus, the PN code is acquired at a higher speed than that of a conventional circuit using only the output of the adder 11 by using the output of the adder 14.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a PN code capture circuit that captures a bit string consisting of a fixed pattern, and particularly to a PN code capture circuit for initial capture used in a spread spectrum communication device. .

[Conventional technology]

Figure 2 shows, for example, the document ``Transactions of the Institute of Electronics and Communication Engineers'''86.
/11. Vo1j69B, No, 11.1540~1
This shows the conventional PN code acquisition circuit shown on page 547, in which (1) is the input terminal for the received signal, (2)
is an AFC circuit, and (3) is a PN code acquisition circuit.

Fig. 3 is a circuit diagram of the correlator incorporated in the PN code acquisition circuit (3) in Fig. 2, where (5) is the input terminal of the received signal, and (6) is the reference carrier wave oscillator. , (
7) is a mixer, (8) is a shift register into which the received PN code is input, (9) is an input terminal for a PN code prepared in advance (hereinafter referred to as reference code), (1)
G) is a multiplier that multiplies the received PN code and the reference code, (11) is an adder, and (12) is the received PN code.
A determination circuit (13) is a capture circuit output terminal for determining whether the code and the reference code match.

The conventional PN code acquisition circuit is configured as described above, and the received signal input to the input terminal (1) is sent to the AFC circuit (2).
is converted to a frequency equal to the oscillation frequency of the reference carrier oscillator (6). Next, it is converted into a baseband signal by a mixer (7) and sent to a shift register (8).
) is entered. P input to shift register (8)
The N code is multiplied by the reference PN code by a multiplier (10), and the multiplied results over the number of stages of each shift register (8) are added by an adder (11) and determined by a judgment circuit (12). After the determination is made, the output is output from the output terminal (13).

Here, if r (t) is the received signal output from the AFC circuit (2) and input to the PN code acquisition circuit (3), then the received signal r (t) is expressed by equation (1).

r (t)=A −d (t)4' N (t)・co
s(Wet 10') ・(1) However, A is the amplitude, d
(t) is data ±1, PN(1) is PN code ±1, Wc
is the carrier wave angular frequency, and θ is the phase difference from the reference carrier wave.

Therefore, if the baseband component of the output of mixer (7) is W (t), then this baseband component W
(t) is expressed by equation (2) (assuming the reference carrier angular frequency is W).

w(t)=pN(t)・cos(Ωt)
...(2) However, the existence of data d(t) and θ only complicates the explanation, so each d(t)=1
, θ=0. Further, the amplitude A is set to 1 for simplicity. Also, Ω is Ω=lie-1゜...
(3) is the frequency deviation between the input carrier wave and the reference carrier wave, and is determined by the accuracy of the AFC circuit (2). If the accuracy of AFC circuit (2) is poor, the value of Ω will become large, and conversely, if the accuracy is good, Ω will approach O.

If the received PN signal in the first stage of shift register (8) is W (t), this No. 43 W (t) is
Based on equation (2), it is expressed by equation (4). However, the number of stages of the shift register (8) is M, and the chip width of the PN code is Te.

W (t) = P N (t-iTe)・C05(
Ω(t-iTc)) −(4) Therefore, the adder (
If the output of 11) is X (t), then the output X (t
) is -cos(Ω(t-iTc)) -(
5). Here, ζte represents the initial phase difference between the received PN code and the reference PN code. The output X (t) is −ζTc+nLTc (n is an integer,
L is the code length of the PN code) and takes the maximum correlation value.

Now, if we later set Ω=O, then equation (6) becomes M.

(Problems to be Solved by the Invention) In the conventional PN code acquisition circuit as described above, if the signal manually input to the PN code acquisition circuit (3) contains a frequency deviation component, the correlation output becomes (6 ) deteriorates as shown in the formula,
In the worst case, the output may become O. One possible way to avoid this is, for example, to improve the accuracy of the AFC circuit (2), but this poses a problem in that the AFC search takes more time and as a result, the acquisition time becomes longer. Another possible method is to separately prepare a short PN code for acquisition and attach it to the beginning of the signal as a preamble, but this poses the problem of complicating the circuits in other parts.

The present invention was made to solve this problem, and an object of the present invention is to provide a PN code capture circuit that can capture a PN code at high speed even if the AFC circuit has poor accuracy.

[Means for solving problems]

A PN code acquisition circuit according to the present invention includes a shift register that stores a received PN code, a multiplier that multiplies the received PN code stored in the shift register by a PN code prepared in advance, and a result of the multiplier. , and the adding means is provided with a plurality of adders having different numbers of addition stages.

[Operation] In this invention, the received PN code stored in the shift register and the PN code prepared in advance are multiplied by the multiplier, and the results are added by the adding means. By the way, since the addition means has a plurality of adders with different numbers of addition stages, a correlation result with less influence of frequency deviation is output, and even if the accuracy of the AFC circuit is poor, PN can be achieved at high speed.
It becomes possible to capture the code.

[Example] Figure 1 shows an example of this invention.
The same reference numerals as those in the figures and FIG. 3 indicate the same or corresponding parts.

(14) is a new adder having a different number of addition stages from adder (11), and constitutes addition means together with adder (11).

In the PN code acquisition circuit configured as above,
Since the number of addition stages of both adders (11) and (14) that constitute the addition means is different, even if the received PN code manually entered into the shift register (8) contains a frequency deviation component, the influence of the frequency deviation will be reduced. A small correlation result is output. Therefore, by using the output of the adder (14), the PN code can be captured faster than in the conventional case where only the output of the adder (11) is used. In addition, in the conventional PN code acquisition circuit, an adder (11)
Even in the worst case, where the output of the adder (14) becomes 0 and it becomes impossible to capture the PN code, the PN code can be captured because the correlation pulse is obtained from the adder (14).

Note that in the above embodiment, two adders (11) and (1
Although the case where 4) is provided is shown, three or more may be provided. It is also possible to provide a large number of adders and calculate frequency deviation components from their outputs and apply AFC.

(Effects of the Invention) As explained above, in this invention, since the addition means is constituted by a plurality of adders having different numbers of addition stages, it is possible to capture the PN code at high speed even when the accuracy of the AFC circuit is poor. There are other effects.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a PN code acquisition circuit showing an embodiment of the present invention, Fig. 2 is a block diagram showing a conventional PN code acquisition circuit, and Fig. 3 is equivalent to Fig. 1 showing a conventional PN code acquisition circuit. It is a diagram. (2)...AFC circuit, (3)...PN code capture circuit, (8)...shift register, (9)...reference PN code input terminal, (lO
)...multiplier, (t+), (14)...adder. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] The above-mentioned system comprises a shift register for storing a received PN code, a multiplier for multiplying the received PN code stored in the shift register by a PN code prepared in advance, and an addition means for adding the results of the multiplier. A PN code acquisition circuit characterized in that the addition means has a plurality of adders having different numbers of addition stages.