TWI760014B - Display panel - Google Patents

Abstract

A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, wherein the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.

Description

display panel

The present invention relates to an optoelectronic device, and in particular, to a display panel.

With the development of display technology, people's demand for display panels is no longer satisfied with optical characteristics such as high resolution, high contrast, and wide viewing angle. People also expect display panels to have an elegant appearance. For example, people expect display panels with narrow bezels or even no bezels.

Generally speaking, a display panel includes a pixel array substrate, an opposite substrate, a display medium disposed therebetween, and a plurality of conductive particles, wherein the pixel array substrate has a common pad disposed in a peripheral area, and the opposite substrate has In the common electrode, a plurality of conductive particles are disposed between the pixel array substrate and the opposite substrate, and the common pad of the pixel array substrate and the common electrode of the opposite substrate are electrically connected to each other through the plurality of conductive particles. However, when the frame of the display panel is to be narrowed, the arrangement of the common pads limits the narrowing of the frame; in addition, the conductive particles are less likely to be good with the common pads of the pixel array substrate and the common electrodes of the opposite substrate. ground electrical connection.

An embodiment of the present invention provides a display panel with good performance.

A display panel according to an embodiment of the present invention includes a first substrate, a plurality of pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and at least one conductive particle. The first substrate has an active area and a peripheral area outside the active area. A plurality of pixel structures are disposed on the active region of the first substrate, wherein each pixel structure includes an active element, a pixel electrode electrically connected to the active element, and a first common electrode. The first common pads are disposed on the peripheral region of the first substrate and are electrically connected to the plurality of first common electrodes of the plurality of pixel structures. The second substrate is disposed opposite to the first substrate. The second common electrode is disposed on the second substrate. The display medium is arranged between the first substrate and the second substrate. At least one conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. At least one conductive particle includes a core and a conductive film disposed on the surface of the core, wherein the conductive film has a main portion and a plurality of raised portions, and the film thickness of each raised portion is larger than that of the main portion.

A display panel according to an embodiment of the present invention includes a first substrate, a plurality of pixel structures, a plurality of data lines, a plurality of scan lines, a plurality of transition lines, a first common pad, a second substrate, and a second common electrode , a display medium, at least one conductive particle and a first insulating layer. The first substrate has an active area and a peripheral area outside the active area. A plurality of pixel structures are disposed on the active region of the first substrate, wherein each pixel structure includes an active element, a pixel electrode electrically connected to the active element, and a first common electrode. A plurality of data lines are disposed on the first substrate and are electrically connected to a plurality of active elements of a plurality of pixel structures, wherein the plurality of data lines are arranged in a first direction. The plurality of scan lines are disposed on the first substrate and are electrically connected to the plurality of active elements of the plurality of pixel structures, wherein the plurality of scan lines are arranged in the second direction, and the first direction and the second direction are staggered. The plurality of patch cords are disposed on the first substrate, wherein the multiple patch cables are electrically connected to the multiple scan lines and are arranged in the first direction. The first common pads are disposed on the peripheral region of the first substrate and are electrically connected to the plurality of first common electrodes of the plurality of pixel structures. The second substrate is disposed opposite to the first substrate. The second common electrode is disposed on the second substrate. The display medium is arranged between the first substrate and the second substrate. At least one conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The first insulating layer is disposed on the first substrate, wherein the first common pad includes a first conductive pattern, and at least a part of the first conductive pattern is disposed in the through hole of the first insulating layer. In the top view of the display panel, the through hole of the first insulating layer has a first width in the first direction, the through hole of the first insulating layer has a second width in the second direction, and the first width is different from the second width .

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specific amount of measurement-related error (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

FIG. 1 is a schematic top view of a display panel 10 according to an embodiment of the present invention.

FIG. 2 is a partially enlarged schematic view of the display panel 10 according to an embodiment of the present invention. FIG. 2 corresponds to the part R1 of FIG. 1 .

For the sake of clarity, FIG. 1 omits the first common pad CP and the plurality of contact windows 151 of the second insulating layer 150 on the first substrate 110 , and the first common pad CP and the plurality of contact windows 151 Pictured in enlarged Figure 2.

FIG. 3 is a schematic cross-sectional view of the display panel 10 according to an embodiment of the present invention. Fig. 3 corresponds to the section line I-I' of Fig. 2 .

For the sake of clarity, FIG. 2 omits the conductive particles 400 , the display medium 300 and the plurality of contact windows 131 of the third insulating layer 130 in FIG. 3 .

FIG. 4 is a partial enlarged schematic view of the display panel 10 according to an embodiment of the present invention. FIG. 4 corresponds to the part R2 of FIG. 1 .

Referring to FIGS. 1 , 2 and 3 , the display panel 10 includes a first substrate 110 having an active area 110 a and a peripheral area 110 b outside the active area 110 a. In this embodiment, the material of the first substrate 110 can be glass, quartz, organic polymer, or opaque/reflective material (eg, wafer, ceramic, or other applicable materials), or other suitable materials. applicable material.

Referring to FIG. 1 , the display panel 10 further includes a plurality of pixel structures SPX disposed on the active region 110 a of the first substrate 110 . Each pixel structure SPX includes an active element T, a pixel electrode PE electrically connected to the active element T, and a first common electrode CL. Specifically, in this embodiment, the active element T may include a thin film transistor having a first end Ta, a second end Tb and a control end Tc; the pixel electrode PE is electrically connected to the thin film transistor The second end Tb; the first common electrode CL and the pixel electrode PE partially overlap to form a storage capacitor.

In this embodiment, the display panel 10 further includes a plurality of data lines DL and a plurality of scan lines SL. The plurality of data lines DL and the plurality of scan lines SL are disposed on the first substrate 110 and are electrically connected to the plurality of active elements T of the plurality of pixel structures SPX. Specifically, in this embodiment, the first end Ta of the thin film transistor of each pixel structure SPX is electrically connected to a corresponding data line DL, and the thin film transistor control end Tc of each pixel structure SPX It is electrically connected to a corresponding scan line SL. A plurality of data lines DL are arranged in a first direction x, a plurality of scan lines SL are arranged in a second direction y, and the first direction x and the second direction y are staggered. For example, in this embodiment, the first direction x and the second direction y may be perpendicular, but the invention is not limited to this.

In this embodiment, in order to make the frame width W1 of the display panel 10 smaller, the display panel 10 may selectively include a plurality of switching wires s1. The plurality of switching lines s1 are disposed on the first substrate 110, are electrically connected to the plurality of scan lines SL, and are arranged in the first direction x. In the top view of the display panel 10, a plurality of patch wires s1 are interspersed in an array formed by a plurality of pixel structures SPX.

Referring to FIGS. 1 , 2 , 3 and 4 , the display panel 10 further includes at least one first common pad CP disposed on the peripheral region 110 b of the first substrate 110 and electrically connected to a plurality of pixel structures SPX the plurality of first common electrodes CL.

Referring to FIGS. 2 , 3 and 4 , in this embodiment, each first common pad CP may include a first conductive pattern 180 , and the display panel 10 further includes a first insulating layer disposed on the first substrate 110 160 (drawn in FIG. 3 ), at least a portion of the first conductive pattern 180 may be disposed on the first insulating layer 160 , and the first insulating layer 160 is located between at least a portion of the first conductive pattern 180 and the first substrate 110 .

Please refer to FIG. 1 , FIG. 2 , FIG. 3 and FIG. 4 , for example, in this embodiment, the first conductive pattern 180 of the first common pad CP can be selectively connected to the pixel electrode PE of the pixel structure SPX It is formed in the same transparent conductive layer, but the present invention is not limited to this. In this embodiment, the transparent conductive layer may optionally include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, and other suitable oxide, or a stacked layer of at least the above two, but the present invention is not limited to this.

Referring to FIG. 2 , FIG. 3 and FIG. 4 , in this embodiment, each first common pad CP may optionally further include a second conductive pattern 140 , and the display panel 10 further includes a second conductive pattern 140 disposed on the first substrate 110 . The second insulating layer 150 (shown in FIG. 3 ) is disposed between the first conductive pattern 180 and the first substrate 110 , and the second conductive pattern 140 is disposed between the second insulating layer 150 and the first substrate 110 During this time, the first conductive pattern 180 is electrically connected to the second conductive pattern 140 through at least one contact window 151 of the second insulating layer 150 .

In this embodiment, a plurality of regions of the first conductive pattern 180 can be electrically connected to a plurality of regions of the second conductive pattern 140 through the plurality of contact windows 151 of the second insulating layer 150 respectively; that is, in this embodiment In an example, the first conductive pattern 180 and the second conductive pattern 140 of the first common pad CP can be selectively connected in parallel, but the invention is not limited thereto. Please refer to FIG. 1 , FIG. 2 , FIG. 3 and FIG. 4 , in addition, in this embodiment, the second conductive pattern 140 of the first common pad CP can be selectively formed on the same second metal layer as the data line DL, However, the present invention is not limited to this.

Referring to FIG. 2 , FIG. 3 and FIG. 4 , in this embodiment, each of the first common pads CP can optionally include a third conductive pattern 120 , and the display panel 10 further includes a third conductive pattern 120 disposed on the first substrate 110 . The third insulating layer 130 (drawn in FIG. 3 ), the second conductive pattern 140 is disposed between the second insulating layer 150 and the third insulating layer 130 , and the third conductive pattern 120 is disposed between the third insulating layer 130 and the first substrate Between 110 , the third insulating layer 130 has at least one contact window 131 disposed in the peripheral region 110 b , and the second conductive pattern 140 is electrically connected to the third conductive pattern 120 through the at least one contact window 131 of the third insulating layer 130 .

In this embodiment, the plurality of regions of the second conductive pattern 140 can be electrically connected to the plurality of regions of the third conductive pattern 120 through the plurality of contact windows 131 of the third insulating layer 130 respectively; that is, in this embodiment In an example, the second conductive pattern 140 and the third conductive pattern 120 of the first common pad CP can be selectively connected in parallel, but the invention is not limited thereto. Please refer to FIG. 1 , FIG. 2 , FIG. 3 and FIG. 4 , in addition, in this embodiment, the third conductive pattern 120 of the first common pad CP can be selectively formed on the same first metal layer as the scan line SL, However, the present invention is not limited to this.

Referring to FIG. 2 , FIG. 3 and FIG. 4 , in this embodiment, the first common pad CP can be selectively composed of the first conductive pattern 180 , the second conductive pattern 140 and the third conductive pattern 120 . However, the present invention is not limited to this. In other embodiments, the first common pad CP can also be any one or both of the first conductive pattern 180 , the second conductive pattern 140 and the third conductive pattern 120 . The present invention is not limited.

Please refer to FIG. 2 and FIG. 4 , in addition, in this embodiment, the first conductive pattern 180 can be selectively elongated (for example, but not limited to: a long capsule shape), and the second conductive pattern 140 can be selectively In a grid shape, the third conductive pattern 120 may selectively have another grid shape corresponding to the second conductive pattern 140 . However, the present invention is not limited to this. In other embodiments, the shape of the first conductive pattern 180 , the shape of the second conductive pattern 140 and/or the shape of the third conductive pattern 120 may be designed according to actual needs.

Referring to FIGS. 2 , 3 and 4 , in this embodiment, the display panel 10 further includes a first alignment film PI1 (drawn in FIG. 3 ), disposed on the first substrate 110 and covering the first common pad at least a portion of the CP. Specifically, in this embodiment, the first alignment film PI1 is the first conductive pattern 180 disposed on the plurality of pixel electrodes PE of the plurality of pixel structures SPX, the first insulating layer 160 and the first common pad CP superior.

Referring to FIGS. 1 , 2 , 3 and 4 , the display panel 10 further includes a second substrate 210 disposed opposite to the first substrate 110 . For example, in this embodiment, the material of the second substrate 210 may be glass, quartz, organic polymer, or other applicable materials. The display panel 10 further includes a display medium 300 (shown in FIG. 3 ) disposed between the first substrate 110 and the second substrate 210 . For example, in this embodiment, the display medium 300 may be a liquid crystal layer; but the present invention is not limited to this. In other embodiments, the display medium 300 may also be a plurality of organic electroluminescence patterns, a plurality of microscopic Light Emitting Diode Elements (μLEDs) or other applicable materials.

The display panel 10 further includes a second common electrode 220 disposed on the second substrate 210 . The second common electrode 220 is located between the second substrate 210 and the display medium 300 . For example, in this embodiment, the second common electrode 220 can be a transparent conductive layer, and its material can include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide , indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least the above two, but the present invention is not limited thereto.

In this embodiment, the display panel 10 further includes a second alignment film PI2 (shown in FIG. 3 ) disposed on the second substrate 210 and covering the second common electrode 220 . The second common electrode 220 is located between the second substrate 210 and the second alignment film PI2.

Referring to FIGS. 2 , 3 and 4 , the display panel 10 further includes at least one conductive particle 400 located between the peripheral region 110 b of the first substrate 110 and the second substrate 210 . At least one conductive particle 400 is disposed on the first common pad CP, and is electrically connected to the first common pad CP on the first substrate 110 and the second common electrode 220 on the second substrate 210 .

FIG. 5 shows a plurality of conductive particles 400 according to an embodiment of the present invention. FIG. 6 shows a portion of a cross-section of a conductive particle 400 according to an embodiment of the present invention.

Referring to FIGS. 3 , 5 and 6 , each conductive particle 400 includes a core 410 and a conductive film 420 disposed on a surface 410 a of the core 410 . In particular, the conductive film 420 has a main portion 421 and a plurality of raised portions 422, and a film thickness T2 (shown in FIG. 6 ) of each raised portion 422 is greater than a film thickness T1 (shown in FIG. 6 ) of the main portion 421 ).

A main portion 421 of the conductive film 420 and a plurality of protruding portions 422 dispersed from each other form rough outer surfaces of the conductive particles 400 . In this embodiment, the cores 410 of the conductive particles 400 can be deformed due to pressure, and the conductive films 420 of the conductive particles 400 have high conductivity. For example, in this embodiment, the material of the core 410 of the conductive particle 400 is nickel, and the material of the conductive film 420 of the conductive particle 400 is gold, but the invention is not limited thereto.

It should be noted that the protrusions 422 of the conductive film 420 of the conductive particles 400 help the conductive particles 400 to be electrically connected to the first common pad CP and the second common electrode 220 .

Please refer to FIG. 1 , FIG. 2 , FIG. 3 and FIG. 4 . Specifically, in this embodiment, since the frame widths W1 and W2 (marked in FIG. 1 ) of the display panel 10 are extremely small, the first alignment film is formed before the first alignment film is formed. During PI1, the first alignment film PI1 not only covers the plurality of pixel electrodes PE on the active region 110a, but also covers at least a part of the first common pad CP on the peripheral region 110b; after forming the second alignment film PI2 At this time, the second alignment film PI2 not only covers a part of the second common electrode 220 directly above the active region 110a, but also covers another part of the second common electrode 220 directly above the peripheral region 110b. The protrusions 422 of the conductive particles 400 can separate the first alignment film PI1 and/or the second alignment film PI2, and at least one first protrusion 422-1 of the plurality of protrusions 422 of the conductive particles 400 will pass through The first alignment film PI1 contacts the first common pad CP, and/or at least one second protrusion 422-2 of the plurality of protrusions 422 of the conductive particles 400 passes through the second alignment film PI2 and contacts with The second common electrode 220 is located directly above the peripheral region 110b. Therefore, even when the frame widths W1 and W2 are very small and the first common pad CP is located very close to the active region 110a and is covered by the first alignment film PI1, the conductive particles 400 can still be well connected to the first common pad CP. The common pad CP is electrically connected to serve as a signal transmission path between the first common pad CP and the second common electrode 220 .

In addition, in this embodiment, the conductive particles 400 are sandwiched between the first substrate 110 and the second substrate 210 , and the cores 410 of the conductive particles 400 can be deformed due to pressure. Thereby, the contact area between the conductive film 420 disposed on the surface 410a of the core 410 of the conductive particle 400 and the first common pad CP and/or the second common electrode 220 can be increased, so that the first common pad CP and the second common electrode 220 can be increased in contact area. The electrical connection of the common electrode 220 is better.

Referring to FIGS. 2 , 3 and 4 , in this embodiment, the first insulating layer 160 may have through holes 161 located in the peripheral region 110 b , and at least one conductive particle 400 is located in the through holes 161 of the first insulating layer 160 . Specifically, in this embodiment, at least a part of the first conductive pattern 180 of the first common pad CP can be disposed in a corresponding one of the through holes 161 to form a recessed surface 180s of the first conductive pattern 180 (marked with 3), a part of the first alignment film PI1 may be located on the recessed surface 180s of the first conductive pattern 180 of the first common pad CP and in the through hole 161 of the first insulating layer 160; at least one conductive particle 400 is located on the first common pad CP. The recessed surface 180s of a conductive pattern 180 passes through the first alignment film PI1 to be in contact with the first conductive pattern 180 of the first common pad CP.

Referring to FIG. 3 , in this embodiment, the contact window 151 of the second insulating layer 150 for electrically connecting the first conductive pattern 180 and the second conductive pattern 140 of the first common pad CP can be disposed in the first Below the through hole 161 of an insulating layer 160 , the through hole 161 of the first insulating layer 160 and the contact window 151 of the second insulating layer 150 may overlap, but the invention is not limited thereto.

In this embodiment, the contact window 131 of the third insulating layer 130 for electrically connecting the second conductive pattern 140 and the third conductive pattern 120 of the first common pad CP can be disposed on the first insulating layer 160 . Below the through hole 161 , the through hole 161 of the first insulating layer 160 and the contact window 131 of the third insulating layer 130 may overlap, but the invention is not limited thereto.

Referring to FIG. 1 , FIG. 2 and FIG. 3 , in this embodiment, the plurality of through holes 161 of the first insulating layer 160 may include a through hole 161 - 1 . In the top view of the display panel 10, the plurality of data lines DL and the through holes 161-1 of the first insulating layer 160 are arranged in the first direction x, and the through holes 161-1 of the first insulating layer 160 are arranged in the first direction x Having a first width L1, the through hole 161-1 of the first insulating layer 160 has a second width L2 in the second direction y, and the second width L2 is greater than the first width L1. Therefore, the first conductive pattern 180 of the first common pad CP disposed in the through hole 161-1 can be designed to be elongated accordingly, which is helpful for increasing the frame width W1 of the display panel 10 in the first direction x. reduce.

In addition, in this embodiment, the first conductive pattern 180 of the first common pad CP is elongated and extends in the second direction y. In this way, the area of the first common pad CP can be expanded without affecting the frame width W1 of the display panel 10 , and the first conductive pattern 180 with the large-area first common pad CP can be connected with a sufficient number of conductive particles. 400 is in electrical contact, so that the first common electrode CL of the pixel structure SPX on the first substrate 110 is well electrically connected to the second common electrode 220 on the second substrate 210 .

Referring to FIG. 1 , FIG. 3 and FIG. 4 , in this embodiment, the plurality of through holes 161 of the first insulating layer 160 further include a through hole 161 - 2 . In the top view of the display panel 10, the plurality of scan lines SL and the through holes 161-2 of the first insulating layer 160 are arranged in the second direction y, and the through holes 161-2 of the first insulating layer 160 are arranged in the first direction x Having a first width L3, the through hole 161-2 of the first insulating layer 160 has a second width L4 in the second direction y, and the first width L3 is greater than the second width L4. Thereby, the first conductive pattern 180 of the first common pad CP disposed in the through hole 161-2 can be correspondingly elongated, which is helpful for increasing the frame width W2 of the display panel 10 in the second direction y. reduce.

In addition, in this embodiment, the first conductive pattern 180 of the first common pad CP is elongated and extends in the first direction x. In this way, the area of the first common pad CP can be expanded without affecting the frame width W2 of the display panel 10 , and the first conductive pattern 180 with the large-area first common pad CP can be connected to a sufficient number of conductive pads. The particles 400 are in electrical contact, so that the first common electrode CL of the pixel structure SPX on the first substrate 110 is well electrically connected to the second common electrode 220 on the second substrate 210 .

Referring to FIGS. 1 , 2 , 3 and 4 , in this embodiment, the display panel 10 further includes a retaining wall structure 170 . The retaining wall structure 170 is disposed between the peripheral region 110 b of the first substrate 110 and the second substrate 210 . The retaining wall structure 170 defines a predetermined coating range r (marked in FIG. 1 ). The display panel 10 further includes a sealant 500 disposed on the predetermined coating range r and located between the peripheral region 110 b of the first substrate 110 and the second substrate 210 . The conductive particles 400 are located in a predetermined coating range r. The retaining wall structure 170 can prevent the thin sealant 500 disposed therein from being easily penetrated by the display medium 300 (eg, the liquid crystal layer), and/or help the conductive particles 400 to be fixed on the first common pad CP.

In this embodiment, the retaining wall structure 170 may include an inner retaining wall 171 and an outer retaining wall 172 , and the inner retaining wall 171 is disposed on the active region 110 a of the first substrate 110 and the edge 110 e of the first substrate 110 (marked in FIG. 1 ) The outer retaining wall 172 is disposed between the inner retaining wall 171 and the edge 110e of the first substrate 110, the predetermined coating range r is an area between the inner retaining wall 171 and the outer retaining wall 172, and the first common connection The pad CP overlaps the predetermined coating range r.

In this embodiment, at least one of the inner retaining wall 171 and the outer retaining wall 172 is a continuous structure. For example, in this embodiment, both the inner retaining wall 171 and the outer retaining wall 172 may be continuous structures. However, the present invention is not limited thereto, and in another embodiment, the inner retaining wall 171 may be a continuous structure, and the outer retaining wall 172 may be a discontinuous structure (ie, including a plurality of microstructures separated from each other); or , the inner retaining wall 171 may be a discontinuous structure, and the outer retaining wall 172 may be a continuous structure.

In addition, in this embodiment, the blocking wall structure 170 may be selectively formed on the first substrate 110 and abut against the second substrate 210 . However, the present invention is not limited thereto, and in other embodiments, the retaining wall structure 170 may also be selectively formed on the second substrate 210 and abut against the first substrate 110 .

It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

FIG. 7 is a schematic top view of a display panel 10A according to an embodiment of the present invention.

The display panel 10A of FIG. 7 is similar to the display panel 10 of FIG. 1 , and the difference between the two is that the retaining wall structure 170 of the display panel 10 of FIG. 7 is different from the retaining wall structure 170 of the display panel 10 of FIG. 1 .

Referring to FIG. 7 , specifically, in this embodiment, at least one of the inner retaining wall 171 and the outer retaining wall 172 of the retaining wall structure 170 includes a plurality of microstructures 171 a and 172 a separated from each other. For example, in this embodiment, the inner retaining wall 171 may include a plurality of microstructures 171a separated from each other, and the outer retaining wall 172 may include a plurality of microstructures 172a separated from each other; that is, in this embodiment , the inner retaining wall 171 and the outer retaining wall 172 may both be discontinuous structures, but the present invention is not limited thereto.

8 is a schematic cross-sectional view of a display panel 10B according to an embodiment of the present invention. The display panel 10B of FIG. 8 is similar to the display panel 10 of FIG. 3 , with the difference that the display panel 10B of FIG. 8 may not have the second alignment film PI2 of the display panel 10 of FIG. 3 . Specifically, in this embodiment, the second substrate 210 of the display panel 10B of FIG. 8 may not be provided with a conventional alignment film requiring transfer coating or printing and spraying, and the second substrate 210 of the display panel 10B may be provided with The polymer stabilized alignment layer is very tiny/thin and not shown. During the manufacturing process of the display panel 10B, the display medium 300 includes a liquid crystal composition, a monomer material and a polymerization initiator, and the polymer stable alignment layer disposed on the second substrate 210 may be polymerized from the monomer material made. In this embodiment, the polymer-stabilized alignment layer may be an optically polymerized material or a thermally polymerized material, which is not limited in the present invention.

FIG. 9 is a schematic cross-sectional view of a display panel 10C according to an embodiment of the present invention. The display panel 10C of FIG. 9 is similar to the display panel 10 of FIG. 3 , with the difference that the display panel 10C of FIG. 9 may not have the first alignment film PI1 of the display panel 10 of FIG. 3 . Specifically, in this embodiment, the first substrate 110 of the display panel 10C of FIG. 10 may not be provided with a conventional alignment film that requires transfer coating or printing and spraying, and the first substrate 110 of the display panel 10C may be provided with The polymer stabilized alignment layer is very tiny/thin and not shown. During the manufacturing process of the display panel 10C, the display medium 300 includes a liquid crystal composition, a monomer material and a polymerization initiator, and the polymer stable alignment layer disposed on the first substrate 110 may be made of the monomer material aggregated. In this embodiment, the polymer-stabilized alignment layer may be an optically polymerized material or a thermally polymerized material, which is not limited in the present invention.

10, 10A, 10B, 10C: Display panel 110: The first substrate 110a: Active Zone 110b: Surrounding area 110e: Edge 120: the third conductive pattern 130: The third insulating layer 131, 151: Contact window 140: the second conductive pattern 150: Second insulating layer 160: first insulating layer 161, 161-1, 161-2: Through hole 170: Retaining Wall Structure 171: Inner retaining wall 171a, 172a: Microstructure 172: External retaining wall 180: The first conductive pattern 180s: sunken surface 210: Second substrate 220: The second common electrode CP: First Common Pad 300: Display medium 400: Conductive Particles 410: Core 410a: Surface 420: Conductive film 421: Main Department 422: Raised part 422-1: The first protrusion 422-2: Second boss 500: Frame glue CL: first common electrode DL: data line L1, L3: the first width L2, L4: Second width PI1: first alignment film PI2: Second alignment film PE: pixel electrode R1, R2: local r: Predetermined coating range SPX: pixel structure SL: scan line sl: transfer cable T: Active element T1, T2: film thickness Ta: the first end Tb: second end Tc: control terminal W1, W2: border width x: first direction y: the second direction I-I': Section Line

FIG. 1 is a schematic top view of a display panel 10 according to an embodiment of the present invention. FIG. 2 is a partially enlarged schematic view of the display panel 10 according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of the display panel 10 according to an embodiment of the present invention. FIG. 4 is a partial enlarged schematic view of the display panel 10 according to an embodiment of the present invention. FIG. 5 shows a plurality of conductive particles 400 according to an embodiment of the present invention. FIG. 6 shows a portion of a cross-section of a conductive particle 400 according to an embodiment of the present invention. FIG. 7 is a schematic top view of a display panel 10A according to an embodiment of the present invention. 8 is a schematic cross-sectional view of a display panel 10B according to an embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a display panel 10C according to an embodiment of the present invention.

10: Display panel

110: The first substrate

110a: Active Zone

110b: Surrounding area

120: the third conductive pattern

130: The third insulating layer

131, 151: Contact window

140: the second conductive pattern

150: Second insulating layer

160: first insulating layer

161: Through hole

170: Retaining Wall Structure

171: Inner retaining wall

172: External retaining wall

180: The first conductive pattern

180s: sunken surface

210: Second substrate

220: The second common electrode

CP: First Common Pad

300: Display medium

400: Conductive Particles

410: Core

410a: Surface

420: Conductive film

421: Main Department

422: Raised part

422-1: The first protrusion

422-2: Second boss

500: Frame glue

PI1: first alignment film

PI2: Second alignment film

I-I': Section Line

Claims (18)

A display panel, comprising: a first substrate having an active area and a peripheral area outside the active area; a plurality of pixel structures disposed on the active area of the first substrate, wherein each of the pixel structures includes an active element, a pixel electrode electrically connected to the active element, and a first common electrode; a first common pad disposed on the peripheral region of the first substrate and electrically connected to the images A plurality of first common electrodes of a pixel structure; a second substrate, disposed opposite to the first substrate; a second common electrode, disposed on the second substrate; a display medium, disposed between the first substrate and the between the second substrates; at least one conductive particle disposed on the first common pad and electrically connecting the first common pad and the second common electrode, wherein the at least one conductive particle includes: a core; and a conductive film disposed on a surface of the core, wherein the conductive film has a main portion and a plurality of raised portions, and a film thickness of each raised portion is greater than a film thickness of the main portion; and a a first alignment film disposed on the first substrate and covering at least a part of the first common pad, wherein at least one of the raised portions of the at least one conductive particle passes through the first alignment film to contact on the first common pad. A display panel, comprising: a first substrate having an active area and a peripheral area outside the active area; a plurality of pixel structures disposed on the active region of the first substrate, wherein each of the pixel structures includes an active element, a pixel electrode electrically connected to the active element, and a first common electrode; a a first common pad, disposed on the peripheral region of the first substrate, and electrically connected to a plurality of first common electrodes of the pixel structures, wherein the first common pad includes a first conductive pattern; A second substrate disposed opposite to the first substrate; a second common electrode disposed on the second substrate; a display medium disposed between the first substrate and the second substrate; at least one conductive particles, disposed on the first common pad, and electrically connected to the first common pad and the second common electrode, wherein the at least one conductive particle includes: a core; and a conductive film disposed on one of the cores On the surface, the conductive film has a main portion and a plurality of raised portions, and a film thickness of each raised portion is greater than a film thickness of the main portion; a first alignment film is disposed on the first substrate and covering at least a portion of the first common pad; and a first insulating layer, wherein at least a portion of the first conductive pattern is disposed in the through hole of the first insulating layer, and a portion of the first alignment film on the first conductive pattern and in the through hole of the first insulating layer. The display panel of claim 2, wherein the at least one conductive particle is located in the through hole of the first insulating layer. The display panel of claim 1, further comprising: a second alignment film disposed on the second substrate and covering the second common electrode. The display panel of claim 4, wherein at least one of the raised portions of the at least one conductive particle passes through the second alignment film and contacts the second common electrode. The display panel of claim 1, further comprising: a plurality of data lines disposed on the first substrate and electrically connected to a plurality of active elements of the pixel structures, wherein the data lines are on a first are arranged in one direction; a plurality of scan lines are arranged on the first substrate and are electrically connected to the active elements of the pixel structures, wherein the scan lines are arranged in a second direction, and the first A direction alternates with the second direction; and a plurality of patch cords are disposed on the first substrate, wherein the patch cables are electrically connected to the scan lines and are arranged in the first direction. A display panel, comprising: a first substrate having an active area and a peripheral area outside the active area; a plurality of pixel structures disposed on the active area of the first substrate, wherein each of the pixel structures includes an active element, a pixel electrode electrically connected to the active element, and a first common electrode; A first common pad is disposed on the peripheral region of the first substrate and is electrically connected to a plurality of first common electrodes of the pixel structures, wherein the first common pad includes a first conductive pattern ; a second substrate disposed opposite to the first substrate; a second common electrode disposed on the second substrate; a display medium disposed between the first substrate and the second substrate; and at least A conductive particle is disposed on the first common pad and electrically connected to the first common pad and the second common electrode, wherein the at least one conductive particle includes: a core; and a conductive film disposed on the core on a surface of the conductive film, wherein the conductive film has a main portion and a plurality of raised portions, and a film thickness of each raised portion is greater than a film thickness of the main portion; a plurality of data lines are arranged on the first on the substrate and electrically connected to a plurality of active elements of the pixel structures, wherein the data lines are arranged in a first direction; a plurality of scan lines are disposed on the first substrate and electrically connected to For the active elements of the pixel structures, the scan lines are arranged in a second direction, and the first direction and the second direction are staggered; a plurality of patch lines are disposed on the first substrate, wherein the patch lines are electrically connected to the scan lines and arranged in the first direction; and a first insulating layer, wherein at least a part of the first conductive pattern is disposed in the through hole of the first insulating layer middle; In the top view of the display panel, the data lines and the through holes of the first insulating layer are arranged in the first direction, and the through holes of the first insulating layer have a first width in the first direction , the through hole of the first insulating layer has a second width in the second direction, and the second width is greater than the first width. A display panel, comprising: a first substrate having an active area and a peripheral area outside the active area; a plurality of pixel structures disposed on the active area of the first substrate, wherein each of the pixel structures includes an active element, a pixel electrode electrically connected to the active element, and a first common electrode; a first common pad disposed on the peripheral region of the first substrate and electrically connected to the images A plurality of first common electrodes of a pixel structure, wherein the first common pad includes a first conductive pattern; a second substrate is disposed opposite to the first substrate; a second common electrode is disposed in the second on the substrate; a display medium disposed between the first substrate and the second substrate; and at least one conductive particle disposed on the first common pad and electrically connected to the first common pad and the second A common electrode, wherein the at least one conductive particle includes: a core; and a conductive film disposed on a surface of the core, wherein the conductive film has a main portion and a plurality of raised portions, and each raised portion A film thickness of the main portion is greater than a film thickness of the main portion; a plurality of data lines disposed on the first substrate and electrically connected to a plurality of active elements of the pixel structures, wherein the data lines are arranged in a first direction; a plurality of scan lines are disposed on the on the first substrate and electrically connected to the active elements of the pixel structures, wherein the scan lines are arranged in a second direction, and the first direction and the second direction are staggered; a plurality of transitions lines, disposed on the first substrate, wherein the patch lines are electrically connected to the scan lines and arranged in the first direction; and a first insulating layer, wherein at least a part of the first conductive pattern are arranged in the through holes of the first insulating layer; in the top view of the display panel, the scan lines and the through holes of the first insulating layer are arranged in the second direction, and the through holes of the first insulating layer are arranged in the second direction. The hole has a first width in the first direction, the through hole of the first insulating layer has a second width in the second direction, and the first width is greater than the second width. The display panel of claim 8, wherein the display panel further comprises a second insulating layer disposed on the first substrate, and the first common pad comprises: a first conductive pattern, wherein the second insulating layer A layer is disposed between the first conductive pattern and the first substrate; and a second conductive pattern is disposed between the second insulating layer and the first substrate, wherein the first conductive pattern penetrates the second insulating layer The at least one contact window is electrically connected to the second conductive pattern. The display panel of claim 9, wherein the first conductive pattern is connected in parallel with the second conductive pattern. A display panel, comprising: a first substrate having an active area and a peripheral area outside the active area; a plurality of pixel structures disposed on the active area of the first substrate, wherein each of the pixel structures includes an active element, a pixel electrode electrically connected to the active element, and a first common electrode; a first common pad disposed on the peripheral region of the first substrate and electrically connected to the images A plurality of first common electrodes of a pixel structure; a second substrate, disposed opposite to the first substrate; a second common electrode, disposed on the second substrate; a display medium, disposed between the first substrate and the between the second substrates; at least one conductive particle disposed on the first common pad and electrically connecting the first common pad and the second common electrode, wherein the at least one conductive particle includes: a core; and A conductive film is disposed on a surface of the core, wherein the conductive film has a main portion and a plurality of raised portions, and a film thickness of each raised portion is greater than a film thickness of the main portion; a stop a wall structure disposed between the peripheral region of the first substrate and the second substrate, wherein the retaining wall structure defines a predetermined coating area; and a sealant disposed on the predetermined coating area and located in the Between the peripheral region of the first substrate and the second substrate, the at least one conductive particle is located in the predetermined coating range. The display panel of claim 11, wherein the retaining wall structure comprises: an inner retaining wall disposed between the active region of the first substrate and an edge of the first substrate; and an outer retaining wall disposed between the inner retaining wall and the edge of the first substrate, wherein the predetermined coating range is an area between the inner retaining wall and the outer retaining wall, and the first common pad and the predetermined coating The ranges overlap. The display panel of claim 12, wherein at least one of the inner retaining wall and the outer retaining wall is a continuous structure; or, at least one of the inner retaining wall and the outer retaining wall comprises a plurality of structure. A display panel, comprising: a first substrate having an active area and a peripheral area outside the active area; a plurality of pixel structures disposed on the active area of the first substrate, wherein each of the pixel structures includes an active element, a pixel electrode electrically connected to the active element and a first common electrode; a plurality of data lines disposed on the first substrate and electrically connected to a plurality of active elements of the pixel structures an element, wherein the data lines are arranged in a first direction; a plurality of scan lines are disposed on the first substrate and are electrically connected to the active elements of the pixel structures, wherein the scan lines are in a second direction is arranged, and the first direction and the second direction are staggered; a plurality of patch cords are disposed on the first substrate, wherein the patch cords are electrically connected to the scan lines, and are arranged in the first direction; a first common pad disposed on the peripheral region of the first substrate and electrically connected to the plurality of first common electrodes of the pixel structures; a second substrate disposed on a pair of the first substrate a second common electrode disposed on the second substrate; a display medium disposed between the first substrate and the second substrate; at least one conductive particle disposed on the first common pad and electrically connecting the first common pad and the second common electrode; and a first insulating layer disposed on the first substrate, wherein the first common pad includes a first conductive pattern, the first conductive pattern At least a part is disposed in the through hole of the first insulating layer; in the top view of the display panel, the through hole of the first insulating layer has a first width in the first direction, and the through hole of the first insulating layer has a first width in the first direction. The through hole has a second width in the second direction, and the first width is different from the second width. The display panel of claim 14, wherein in a plan view of the display panel, the patch cords and the through holes of the first insulating layer are arranged in the first direction, and the second width is greater than the first width a width. The display panel of claim 14, further comprising: a first alignment film disposed on the first substrate and covering at least a part of the first common pad and the at least one conductive particle passing through the first alignment The film is in contact with the first common pad. The display panel of claim 14, wherein the display panel further comprises a second insulating layer disposed on the first substrate, and the second insulating layer is disposed between the first conductive pattern and the first substrate, The first common pad further includes: a second conductive pattern disposed between the second insulating layer and the first substrate, wherein the first conductive pattern is electrically connected through at least one contact window of the second insulating layer to the second conductive pattern. The display panel of claim 14, further comprising: a retaining wall structure disposed between the peripheral region of the first substrate and the second substrate, wherein the retaining wall structure defines a predetermined coating range; and a The sealant is disposed on the predetermined coating range and located between the peripheral region of the first substrate and the second substrate, wherein the at least one conductive particle is located in the predetermined coating range.

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