TWI759383B - Solid-state imaging device and method for producing the same, and electronic device - Google Patents

Abstract

There is provided an imaging device with a semiconductor substrate having a first side and a second side opposite the first side. A photoelectric conversion unit is on the first side of the semiconductor substrate. A multilayer wiring layer is on the second side of the semiconductor substrate. A through electrode extends between the photoelectric conversion unit and the multilayer wiring layer. The multilayer wiring layer includes a local wiring layer. A second end of the through electrode is in direct contact with the local wiring layer.

Description

Solid-state imaging device and method for producing the same, and electronic device

The present invention relates to a solid-state imaging device, a production method thereof, and an electronic device, and in particular, the present invention relates to a solid-state imaging device, a production method thereof, and an electronic device that can make a through electrode finer.

In recent years, charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors have seen a reduction in pixel size. However, this results in lower sensitivity and lower S/N due to the reduction of photons entering a unit pixel.

Meanwhile, as a pixel array in which red (R), green (G), and blue (B) pixels are arranged on a plane, it is currently known to use a Bayer arrangement such as a primary color filter of. However, in the Bayer configuration, the G light and B light cannot pass through the filter and cannot be used for photoelectric conversion in the R pixel; therefore, a loss of sensitivity occurs and false colors are caused by the interpolation process between pixels.

In this regard, a technique for stacking three photoelectric conversion layers in the vertical direction and obtaining color signals of three colors in one pixel is known. For example, a structure in which a photoelectric conversion film disposed on a Si substrate detects G light and two photodiodes (PDs) stacked in the Si substrate detects R light and B light has been proposed.

In this structure, it is necessary to transfer the charges generated in the photoelectric conversion film to a floating diffusion (FD) formed on the opposite surface of the Si substrate. In this regard, for example, JP 2015-38931A discloses a structure in which a through electrode is provided for each pixel between a front surface and a rear surface of a semiconductor substrate and charges generated in a photoelectric conversion film are transferred to an FD.

However, the structure disclosed in PTL 1 cannot make the through electrodes finer. Specifically, there is a limit to making a Si through electrode finer in the production steps. In addition, a metal through electrode may be misaligned with a contact connected at the front surface or the back surface of the semiconductor substrate, which may increase the contact resistance.

The present invention can reliably make a through electrode finer.

According to an embodiment of the present invention, an imaging device is provided, which includes: a semiconductor substrate having a first side and a second side opposite to the first side; a photoelectric conversion unit located on the semiconductor substrate on the first side; a multi-layer wiring layer on the second side of the semiconductor substrate; a through electrode extending between the photoelectric conversion unit and the multi-layer wiring layer, wherein the multi-layer wiring layer includes A local wiring layer, wherein a second end of the through electrode is in direct contact with the local wiring layer.

According to an embodiment of the present invention, there is provided an electronic device including a plurality of pixels, wherein each of the pixels includes: a photoelectric conversion unit located on a first side of a semiconductor substrate; at least one first photodiode , which is formed in the semiconductor substrate; a multi-layer wiring layer, which is located on the second side of the semiconductor substrate; a through electrode, which extends between the photoelectric conversion unit and the multi-layer wiring layer, wherein the multi-layer wiring layer Including a local wiring layer, and wherein the through A second end of the electrode is in direct contact with the local wiring layer.

According to an embodiment of the present invention, a through electrode can be reliably made finer. It should be noted that the effects described herein are not necessarily limiting, and any effects described in this disclosure may be exhibited.

10: Solid-state imaging device

20: Pixels

21: Pixel area

22: Vertical drive circuit

23: Line signal processing circuit

24: Horizontal drive circuit

25: Output circuit

26: Control circuit

27: Vertical signal line

28: Horizontal signal line

29: Input/output terminal

31: Peripheral circuit unit

50: Semiconductor substrate

50A: Front surface

50B: Back Surface

50i: area

51: Inorganic photoelectric conversion unit

52: Inorganic photoelectric conversion unit

53: Floating Diffusion (FD)

54: Transfer transistor

55: Amplifying transistor

55G: Gate electrode

55s: Component isolation part

56: reset transistor

56G: Gate electrode

56s: Component isolation section

57: Etch stop layer

58: Through Electrodes

58t: end

60: Multilayer wiring layer

61: Local wiring layer

62: wiring layer

63: wiring layer

65: Contacts

70: insulating film

70a: insulating film

80: Organic photoelectric conversion unit

81: Lower electrode

82: Upper electrode

83: Organic Photoelectric Conversion Layer

91: Passivation film

91a: Passivation film

92: On-wafer lens

101a: Interlayer insulating film

101b: Insulating film

111: photoresist layer

112: Through hole

112t: end

151: Transistor

151G: Gate electrode

152: Element isolation film

153: Through Electrode

153a: Lead out wiring layer/metal structure

153b: Contacts/Metallic Components

153c: Contacts/Metallic Components

153d: Wiring Layers/Metallic Components

161: Local wiring layer

163: wiring layer

165: Contacts

171: Fixed Charge Films

172: insulating film

181: Through hole

181e: groove

191: Light Blocking Structures

252: Component isolation part

253: Through Electrode

261: wiring layer

262: wiring layer

265: Contacts

270: insulating film

281: p-type diffusion layer

282: Fixed Charge Film

283: Metal Electrode

291: photoresist layer

292: Through hole

300: Electronics

301: Optical lens

302: Shutter device

303: Solid State Imaging Devices

304: Drive circuit

305: Signal processing circuit

CH1: Contact hole

CH2: Contact hole

TR1: groove

FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to an embodiment of the present invention.

2 is a cross-sectional view of a configuration example of a solid-state imaging device according to a first embodiment.

3 is a cross-sectional view illustrating a production step of a pixel.

4 is a cross-sectional view illustrating a production step of a pixel.

5 is a cross-sectional view illustrating a production step of a pixel.

6 is a cross-sectional view illustrating a production step of a pixel.

7 is a cross-sectional view showing a production step of a pixel.

FIG. 8 is a cross-sectional view showing a production step of a pixel.

9 is a cross-sectional view illustrating a production step of a pixel.

10 is a cross-sectional view showing a production step of a pixel.

11 is a cross-sectional view showing a production step of a pixel.

Figure 12 is a cross-sectional view showing a production step of a pixel.

Figure 13 is a cross-sectional view showing a production step of a pixel.

Figure 14 is a cross-sectional view showing a production step of a pixel.

Figure 15 is a cross-sectional view showing a production step of a pixel.

Figure 16 is a cross-sectional view showing a production step of a pixel.

Figure 17 is a cross-sectional view showing a production step of a pixel.

18 is a cross-sectional view of a configuration example of a solid-state imaging device according to a second embodiment.

19 is a cross-sectional view illustrating a production step in a configuration in which a voltage is applied to an upper electrode.

20 is a cross-sectional view illustrating a production step in a configuration in which a voltage is applied to an upper electrode.

21 is a cross-sectional view of a production step in a configuration in which a voltage is applied to an upper electrode.

22 is a cross-sectional view illustrating a production step in a configuration in which a voltage is applied to an upper electrode.

23 is a cross-sectional view illustrating a production step in a configuration in which a voltage is applied to an upper electrode.

FIG. 24 is a view for describing the dielectric strength of a fixed charge film.

FIG. 25 is a view for describing the programmed resistance of a fixed charge film.

26 is a cross-sectional view of a configuration example of a solid-state imaging device according to a third embodiment.

27 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

28 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

Figure 29 shows a configuration in which a through electrode and a fixed charge film are not in contact with each other A cross-sectional view of a production step.

30 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

31 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

32 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

33 is a cross-sectional view showing a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

34 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

35 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

36 is a cross-sectional view showing a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

37 is a cross-sectional view showing a production step of a configuration in which a through electrode and a fixed charge film are not in contact with each other.

38 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

39 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

40 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

41 is a cross-sectional view showing a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

42 is a cross-sectional view showing a production step of a configuration in which a through electrode and a fixed charge film are not in contact with each other.

43 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

44 is a cross-sectional view showing a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

45 is a cross-sectional view illustrating a production step in a configuration in which a through electrode and a fixed charge film are not in contact with each other.

46 is a cross-sectional view of an example of a configuration in which a through electrode and a wiring layer are not in contact with each other.

FIG. 47 shows an example of a pattern of a conductive film.

FIG. 48 shows an example of a pattern of a conductive film.

49 is a cross-sectional view of a configuration example of a solid-state imaging device according to a fourth embodiment.

50 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

51 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

52 is a cross-sectional view showing a production step of forming a through electrode from the front surface of a substrate.

Figure 53 is a cross-section showing a production step of forming a through electrode from the front surface of a substrate face map.

54 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

55 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

56 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

57 is a cross-sectional view showing a production step of forming a through electrode from the front surface of a substrate.

58 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

59 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

60 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

61 is a cross-sectional view illustrating a production step of forming a through electrode from the front surface of a substrate.

FIG. 62 is a block diagram illustrating a configuration example of an electronic device according to an embodiment of the present invention.

FIG. 63 shows a usage example of an image sensor.

Cross-references to related applications

This application claims Japanese Priority Patent Application JP 2016- filed on December 14, 2016 242144 and Japanese Priority Patent Application JP 2017-217217 filed on November 10, 2017, the entire contents of which are each incorporated herein by reference.

Modes for carrying out the present invention (hereinafter referred to as embodiments) will hereinafter be described. The description will be given in the following order.

1. Configuration example of solid-state imaging device

2. First Embodiment

3. Pixel production steps

4. Second Embodiment

5. Production steps of the configuration in which a voltage is applied to the upper electrode

6. Third Embodiment

7. Production steps of a configuration in which the penetrating electrode and the fixed charge film are not in contact with each other

8. Fourth Embodiment

9. Production steps for forming through electrodes from the front surface of the substrate

10. Configuration example of electronic device

11. Examples of use of image sensors

<1. Configuration example of solid-state imaging device>

FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to an embodiment of the present invention.

A solid-state imaging device 10 is configured as a CMOS image sensor. The solid-state imaging device 10 includes: a pixel region (pixel array) 21, wherein a plurality of pixels 20 are regularly arranged in a semiconductor substrate (eg, a Si substrate) (not shown in the figure) in a two-dimensional array; and a peripheral circuit unit.

The pixel 20 includes a photoelectric conversion unit (eg, a photodiode) and a plurality of pixel transistors (MOS transistor). The plurality of pixel transistors may include, for example, three transistors: a transfer transistor, a reset transistor, and an amplification transistor. Alternatively, the plurality of pixel transistors may include four transistors that additionally include a select transistor. It should be noted that an equivalent circuit of a unit pixel is similar to a general circuit, and thus a detailed description thereof is omitted.

Pixel 20 may be configured as a unit pixel or may be located in a pixel sharing structure. The pixel sharing structure is a structure in which a plurality of photodiodes share a floating diffusion region and transistors other than a transfer transistor.

Although a detailed description will be given later, the pixel 20 is constituted by stacking photoelectric conversion units.

The peripheral circuit unit includes a vertical driving circuit 22 , a row signal processing circuit 23 , a horizontal driving circuit 24 , an output circuit 25 and a control circuit 26 .

The control circuit 26 receives an input clock and data commanding an operation mode or the like, and outputs data such as internal information of the solid-state imaging device 10 . In addition, based on a vertical synchronization signal, a horizontal synchronization signal, and a main clock, the control circuit 26 generates a clock signal and a control signal, which act as the vertical driving circuit 22, the horizontal signal processing circuit 23, the horizontal driving circuit 24 and the like. A reference to the operations of similar ones. Then, the control circuit 26 inputs these signals to the vertical driving circuit 22, the row signal processing circuit 23, the horizontal driving circuit 24, and the like.

The vertical driving circuit 22 is constituted by, for example, a shift register. The vertical driving circuit 22 selects a pixel driving line and supplies a pulse for driving the pixels to the selected pixel driving line to drive the pixels in units of columns. That is, the vertical driving circuit 22 sequentially selectively scans the pixels 20 of the pixel region 21 in units of columns along the vertical direction. Next, the vertical driving circuit 22 supplies the pixel signal based on the signal charge generated according to the amount of received light in the photoelectric conversion unit of the respective pixel 20 to the row signal processing circuit 23 through the vertical signal line 27 .

One row of signal processing circuits 23 is disposed for, for example, each row of pixels 20 . The row signal processing circuit 23 performs signal processing such as noise cancellation on the signals output from the pixels 20 of a column in units of pixel rows. Specifically, the line signal processing circuit 23 performs signal processing such as correlated double sampling (CDS), which is used to remove fixed image noise specific to pixels 20, signal amplification, and analog/digital (A/D) conversion. In the output stage of the row signal processing circuit 23, a horizontal selection switch (not shown) connected to a horizontal signal line 28 is provided.

The horizontal driving circuit 24 is constituted by, for example, a shift register. The horizontal driving circuit 24 sequentially outputs a horizontal scan pulse to sequentially select the row signal processing circuit 23 and causes the row signal processing circuit 23 to output pixel signals to the horizontal signal line 28 .

The output circuit 25 performs signal processing on the signals sequentially supplied from the signal processing circuit 23 through the horizontal signal line 28 and outputs the resulting signal. For example, the output circuit 25 performs only buffering in some cases, and black level adjustment, line variation correction, various digital signal processing, and the like in some cases.

The input/output terminal 29 exchanges signals with the outside.

<2. First Embodiment>

FIG. 2 is a cross-sectional view of a solid-state imaging device 10 according to a first embodiment of the present invention.

FIG. 2 shows a cross section of the pixel region 21 and a peripheral circuit unit 31 included in the solid-state imaging device 10 .

In the solid-state imaging device 10, a multilayer wiring layer 60 is formed on the front surface 50A (first surface) side of a semiconductor substrate 50 (which is made of Si or the like). In addition, an organic photoelectric conversion unit 80 serving as a photoelectric conversion element is formed on the rear surface 50B (second surface) side of the semiconductor substrate 50 with an insulating film 70 interposed between the organic photoelectric conversion unit 80 and the rear surface 50B, Surface 50B acts as a light receiving surface.

In the pixel area 21, each pixel 20 has one organic photoelectric conversion unit 80 and two inorganic photoelectric conversion units 51 and 52 (PD1 and PD2) stacked in the vertical direction, which selectively detect light of different wavelength ranges and perform photoelectric conversion) a stack structure. The inorganic photoelectric conversion units 51 and 52 are formed to be embedded in the semiconductor substrate 50 .

The organic photoelectric conversion unit 80 includes, for example, two or more types of organic semiconductor materials. The organic photoelectric conversion unit 80 is configured with an organic photoelectric conversion element that uses organic semiconductors to absorb light in a selective wavelength range (here, green light) to produce electron-hole pairs. The organic photoelectric conversion unit 80 has an organic photoelectric conversion layer (organic semiconductor layer) 83 sandwiched between a lower electrode 81 (which is provided to each pixel 20 and used to capture signal charges) and an upper electrode 82 (which is arranged to shared by the pixels 20) between a configuration.

The lower electrode 81 is disposed in an area facing the light-receiving surfaces of the inorganic photoelectric conversion units 51 and 52 formed in the semiconductor substrate 50 and covering these light-receiving surfaces. The lower electrode 81 is composed of a light-transmitting conductive film and, for example, indium tin oxide (ITO). In addition to indium tin oxide, a tin oxide (SnO ₂ ) based material can also be added to it using a dopant or one obtained by adding a dopant to aluminum zinc oxide (ZnO) based oxide The material of zinc is used as one of the constituent materials of the lower electrode 81 . Examples of zinc oxide based materials include aluminum zinc oxide (AZO) to which aluminum (Al) is added as a dopant, gallium zinc oxide (GZO) to which gallium (Ga) is added, and indium (In) Indium zinc oxide (IZO) was added thereto. Besides these, CuI, InSbO ₄ , ZnMgO, CuInO ₂ , MgIN ₂ O ₄ , CdO, ZnSnO ₃ or the like can also be used. It should be noted that the lower electrode 81 is provided to each pixel 20 individually because the signal charges (electrons) obtained in the organic photoelectric conversion layer 83 are extracted from the lower electrode 81 .

The organic photoelectric conversion layer 83 includes, for example, three types of organic semiconductor materials: a first organic semiconductor material, a second organic semiconductor material, and/or a third organic semiconductor material. this At least one of the three types of organic semiconductor materials is one or both of an organic p-type semiconductor and an organic n-type semiconductor, and photoelectrically converts light of a selective wavelength range, while enabling light of another wavelength range pass. Specifically, the organic photoelectric conversion layer 83 has a maximum absorption wavelength in a range of equal to or greater than 450 nm and equal to or less than 650 nm, such as the wavelength of green (G) light.

Another layer (not shown) may be disposed between the organic photoelectric conversion layer 83 and the lower electrode 81 and between the organic photoelectric conversion layer 83 and the upper electrode 82 . For example, a base film, a hole transport layer, an electron blocking film, an organic photoelectric conversion layer 83, a hole blocking film, a buffer film, an electron transport layer, and a work function can be sequentially stacked from the lower electrode 81 side Adjust the membrane.

Similar to the lower electrode 81, the upper electrode 82 is composed of a light-transmitting conductive film. The upper electrode 82 is formed as one electrode shared by the pixels 20, but may be used for each pixel 20 independently. The thickness of the upper electrode 82 is, for example, 10 nm to 200 nm.

The inorganic photoelectric conversion units 51 and 52 have a p-n junction photodiode (PD) and are sequentially formed on an optical path in the semiconductor substrate 50 from the rear surface 50B side. The inorganic photoelectric conversion unit 51 selectively detects blue light and accumulates signal charges corresponding to the blue light. The inorganic photoelectric conversion unit 51 is formed in a selective region, for example, along the rear surface 50B of the semiconductor substrate 50 . The inorganic photoelectric conversion unit 52 selectively detects red light and accumulates signal charges corresponding to the red light. The inorganic photoelectric conversion unit 52 is formed, for example, in a region below the inorganic photoelectric conversion unit 51 (on the front surface 50A side). It should be noted that blue (B) is a color corresponding to, for example, a wavelength range of 450 nm to 495 nm, and red (R) is a color corresponding to a wavelength range of, for example, 620 nm to 750 nm; inorganic photoelectric conversion Units 51 and 52 are fully capable of detecting light in part or all of their respective wavelength ranges.

As described above, the pixel 20 has the organic photoelectric conversion unit in which the organic photoelectric conversion units are stacked in the vertical direction 80 and one of the two inorganic photoelectric conversion units 51 and 52 are stacked, and the organic photoelectric conversion unit 80, the inorganic photoelectric conversion unit 51, and the inorganic photoelectric conversion unit 52 absorb (detect) green light, blue light, and red light, respectively, and perform photoelectric conversion. conversion; thus, vertical spectral diffraction in the vertical direction (stacking direction) can be performed in one pixel, and red, green, and blue color signals can be acquired.

A floating diffusion (FD) 53 , a transfer transistor 54 , an amplification transistor 55 and a reset transistor 56 are disposed, for example, on the front surface 50A of the semiconductor substrate 50 . Among them, the FD 53 and a gate electrode 55G of the amplifier transistor 55 are connected to a local wiring layer 61 formed so as to be closest to the front surface of the semiconductor substrate 50 among the wiring layers 61 to 63 constituting the multilayer wiring layer 60 50A. The local wiring layer 61 is provided to each pixel 20 . In addition, a gate electrode 56G of the reset transistor 56 is connected to the wiring layer 63 via a contact 65 . It should be noted that the amplification transistor 55 is separated from the other regions by a device isolation portion 55s having a shallow trench isolation (STI) structure, and the reset transistor 56 is separated from the other regions by a device isolation portion 56s.

Furthermore, an etch stop layer 57 made of a SiN film or the like is formed on the front surface 50A of the semiconductor substrate 50 .

In each pixel 20 , a through electrode 58 is formed in the semiconductor substrate 50 in such a way that its lower end penetrates the front surface 50A of the semiconductor substrate 50 to be directly connected to the local wiring layer 61 and its upper end is connected to the lower electrode 81 . Specifically, the through electrode 58 is formed on the front surface 50A side of the semiconductor substrate 50 to penetrate between the element isolation portion 55s of the amplification transistor 55 and the element isolation portion 56s of the reset transistor 56 . The through electrode 58 is composed of a metal material such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), cobalt (Co), hafnium (Hf), or tantalum (Ta).

Therefore, in each pixel 20 , the charges generated in the organic photoelectric conversion unit 80 on the rear surface 50B side of the semiconductor substrate 50 are transferred to the FD 53 and the amplifying transistor 55 on the front surface 50A side of the semiconductor substrate 50 via the through electrodes 58 .

In addition, in each pixel 20 , a passivation film 91 is formed on the upper electrode 82 and an on-wafer lens 92 is formed on the passivation film 91 .

<3. Pixel production steps>

Next, the production steps of the pixel 20 will be described with reference to FIGS. 3 to 15 .

First, FIG. 3 shows a state in which transistors 54 to 56 are formed by ion implantation or the like on the front surface 50A side of the semiconductor substrate 50 in which the inorganic photoelectric conversion units 51 and 52 and the FD 53 are formed, And the etching stopper layer 57 and the interlayer insulating film 101a are formed. The etch stop layer 57 is formed by forming a SiN film or the like by a technique such as, for example, low pressure chemical vapor deposition (LP-CVD). The interlayer insulating film 101a is formed by forming an oxide film or the like by a technique such as plasma CVD and planarizing the surface by a technique such as chemical mechanical polishing (CMP). It should be noted that a high-concentration impurity region (P++ region) may be formed in a region 50i of the semiconductor substrate 50 in which the through electrode 58 is to be formed. Accordingly, damage caused when the through electrodes 58 are formed can be reduced and dark current can thus be reduced.

Next, as shown in FIG. 4 , a contact hole CH1 for connecting the local wiring layer 61 to the semiconductor substrate 50 (FD 53 and amplifying transistor 55 ) is formed by patterning and dry etching. In addition, a trench TR1 of the local wiring layer 61 is formed by patterning and dry etching.

Thereafter, as shown in FIG. 5 , metal is embedded in the contact hole CH1 and the trench TR1 to form a contact and local wiring layer 61 . For example, a Ti film or the like for work function adjustment is formed by a technique such as physical vapor deposition (PVD), and barrier metals TiN, W, etc. are embedded by a technique such as CVD. In addition, an unnecessary metal film on the surface is removed by a technique such as CMP.

In this way, the local wiring layer 61 connected to one end of the through electrode 58 is formed of a metal such as W or Ti that is less likely to cause contamination.

Subsequently, as shown in FIG. 6, an insulating film 101b is formed on the local wiring layer 61 by forming an oxide film or the like by a technique such as plasma CVD.

Next, as shown in FIG. 7 , a wiring layer 63 (not shown, which will be formed in the next step) over the local wiring layer 61 is formed by patterning and dry etching to connect the semiconductor substrate 50 A contact hole is formed, and metal is embedded to form a contact 65 . For example, a Ti film or the like for work function adjustment is formed by a technique such as PVD, and barrier metal TiN, W, etc. are embedded by a technique such as CVD. In addition, an unnecessary metal film on the surface is removed by a technique such as CMP.

Thereafter, as shown in FIG. 8, the wiring layer 63 is formed; thus, the multilayer wiring layer 60 is formed.

Next, a support substrate (not shown), another semiconductor substrate or the like is bonded to the front surface 50A side of the semiconductor substrate 50 (multilayer wiring layer 60 ), and the resulting structure is turned upside down.

First, as shown in FIG. 9 , on the rear surface 50B side of the semiconductor substrate 50 , a photoresist layer 111 is patterned according to a position where the through electrode 58 will be formed. Thereafter, as shown in FIG. 10, Si (semiconductor substrate 50) is processed by a technique such as dry etching; thus, a through hole 112 is formed. Here, the etching is stopped at the etch stop layer 57 formed on the front surface 50A side of the semiconductor substrate 50 . In addition, the element isolation portions 55s and 56s formed on the side of the front surface 50A of the semiconductor substrate 50 serve as etching stoppers even in the case where misalignment occurs in the patterning of the photoresist layer 111 .

After removing the photoresist layer 111, as shown in FIG. 11, an oxide film or the like is formed in the via hole 112 by a technique such as atomic layer deposition (ALD); thus, an insulating film is embedded 70a.

Thereafter, as shown in FIG. 12, the insulating film 70a, the etching stopper layer 57, and one of the multilayer wiring layers 60 formed at the bottom of the through hole 112 are etched by a technique such as dry etching insulating film; thus, the through holes 112 reach the local wiring layer 61 . Here, the etching stops at the local wiring layer 61 .

Subsequently, as shown in FIG. 13, a barrier metal or the like is embedded in the via hole 112 by a technique such as ALD to form a conductive film, and W or the like is embedded by a technique such as CVD By. Thus, through electrodes 58 are formed. Next, after patterning by photolithography, an unnecessary conductive film is removed by a technique such as dry etching to form a lead-out wiring layer on the upper end of the through electrode 58 .

Thereafter, as shown in FIG. 14, an insulating film 70 is formed, and then a lower electrode 81, an organic photoelectric conversion layer 83, and an upper electrode 82 are formed; thus, an organic photoelectric conversion unit 80 is formed.

Next, as shown in FIG. 15 , a passivation film 91 is formed on the upper electrode 82 and an on-wafer lens 92 is formed on the passivation film 91 .

The pixel 20 is formed through the above steps.

According to the above steps, the through electrode 58 is formed in such a way that one end of the through electrode 58 penetrates the front surface 50A of the semiconductor substrate 50 to be directly connected to the local wiring layer 61 serving as an etch stop. This can avoid occurrence of misalignment with a contact and increase in contact resistance; therefore, the through electrodes can be reliably made finer.

Additionally, for the configuration disclosed in PTL 1, making a through electrode finer results in an increase in parasitic capacitance and contact resistance that occurs in a path from an organic photoelectric conversion unit through the through electrode to an FD resulting in Longer RC delay and lower conversion efficiency.

In contrast, in the present embodiment, the local wiring layer 61 connected to the FD 53 of the through electrode and the amplifying transistor 55 is located in a layer separated from other wiring layers, which improves the flexibility of wiring layout and reduces parasitic capacitance . Therefore, the RC delay can be shortened and the conversion efficiency can be improved.

Additionally, a metal that is less likely to cause contamination, such as W or Ti, is used for the local wiring layer 61, and the Si substrate is processed without exposing the metal material; thus, the dark characteristics and white point characteristics due to metal contamination or the like can be kept favorable.

Furthermore, with existing through-silicon vias (TSVs), there is stress and a transistor cannot be placed near the TSVs, which constrains the layout.

In contrast, in this embodiment, the through-electrode can be made finer without inducing stress, which enables a layout in which a transistor is placed near the through-electrode.

It should be noted that in the step of making the vias 112 reach the local wiring layer 61 (described with reference to FIG. 12 ), an etching technique called a Bosch process may be used. The Bosch procedure is an etching technique in which etching and etching sidewall protection are repeatedly performed and achieve etching at a high aspect ratio.

Through the Bosch process, as shown in FIG. 16 , one end 112t of the through hole 112 is formed into a tapered shape. Therefore, as shown in FIG. 17, one end 58t of the penetration electrode 58 is formed into a tapered shape. Forming the tip 58t of the through electrode 58 into a tapered shape in this way reduces a contact area between the through electrode 58 and the local wiring layer 61 (which acts as a stopper), and this can suppress the through electrode 58 and the local wiring layer Misalignment between 61. In addition, forming the tip end 58t of the through electrode 58 into a tapered shape can reduce the parasitic capacitance between the through electrode 58 and the wiring layers constituting the multilayer wiring layer 60 .

<4. Second Embodiment>

18 is a cross-sectional view of a solid-state imaging device 10 according to a second embodiment of the present invention.

FIG. 18 shows a cross section of a portion of the peripheral circuit unit 31 included in the solid-state imaging device 10 .

Also in the example of FIG. 18 , the multilayer wiring layer 60 is formed on the side of the front surface 50A of the semiconductor substrate 50 , and the organic photoelectric conversion unit 80 is formed on the side of the rear surface 50B of the semiconductor substrate 50 . above, wherein the insulating film 70 is interposed between the organic photoelectric conversion unit 80 and the rear surface 50B, and the rear surface 50B serves as a light-receiving surface.

A transistor 151 is disposed, for example, on the front surface 50A of the semiconductor substrate 50 . A gate electrode 151G of the transistor 151 is connected to a local wiring layer 161 formed closest to the front surface 50A of the semiconductor substrate 50 among the wiring layers 161 and 163 constituting the multilayer wiring layer 60 . The gate electrode 151G of the transistor 151 is formed on an element isolation film 152 . In addition, the gate electrode 151G of the transistor 151 is connected to the wiring layer 163 via a contact 165 . The wiring layer 163 serves as a power supply line connected to a predetermined power source. Accordingly, the local wiring layer 161 is connected to the power supply line via the gate electrode 151G of the transistor 151 .

In addition, a through electrode 153 is formed in the semiconductor substrate 50 in such a way that its lower end penetrates the front surface 50A of the semiconductor substrate 50 to be directly connected to the local wiring layer 161 and its upper end is connected to the upper electrode 82 via the metal members 153a to 153d. The metal member 153a is formed to penetrate one of the lead-out wiring layers of the electrodes 153 and the metal members 153b and 153c are formed as contacts. The metal member 153d is formed as a wiring layer connecting the metal members 153b and 153c. The penetration electrode 153 and the metal members 153a to 153d are composed of a metal material such as W, Cu, Al, Ti, Co, Hf, or Ta. It should be noted that in the example of FIG. 18 , one end of the through electrode 153 may be formed with a tapered shape, like the through electrode 58 in FIG. 17 .

With this configuration, a predetermined voltage is applied to the upper electrode 82 that is arranged to be shared by the pixels 20 .

Although a voltage is continuously applied to the upper electrode 82 , reliability such as withstand voltage can be maintained by forming the gate electrode 151G on the element isolation film 152 . In addition, in the process, the gate electrode 151G may be in a floating state and undergo charging damage when the through electrode 153 and the metal members 153a to 153d are formed, but this may also be formed by forming the gate electrode 151G on the element isolation film 152 came up to ease.

<5. Production steps of the configuration in which a voltage is applied to the upper electrode>

Next, the production steps of a configuration in which a voltage is applied to the upper electrode 82 will be described with reference to FIGS. 19 to 23 .

It should be noted that the steps until the multilayer wiring layer 60 is formed on the front surface 50A side of the semiconductor substrate 50 and the through electrodes 153 are formed are substantially similar to the steps for forming the pixels 20 , and thus the description thereof is omitted.

After forming the through electrodes 153, as shown in FIG. 19, after patterning by photolithography, an unnecessary conductive film is removed by a technique such as dry etching to form the upper ends of the through electrodes 153. The wiring layer 153a is drawn out.

Subsequently, as shown in FIG. 20 , an insulating film 70 is formed, and then a lower electrode 81 , an organic photoelectric conversion layer 83 , and an upper electrode 82 are formed, and a passivation film 91 a is formed on the upper electrode 82 .

Next, as shown in FIG. 21 , a contact hole CH2 for connecting the local wiring layer 161 to the upper electrode 82 is formed by patterning and dry etching.

Thereafter, as shown in FIG. 22, metal is embedded in the contact hole CH2 to form contacts 153b and 153c. For example, a Ti film or the like for work function adjustment is formed by a technique such as PVD, and barrier metal TiN, W, etc. are embedded by a technique such as CVD or PVD. Thereafter, after patterning by photolithography, an unnecessary conductive film is removed by a technique such as dry etching to form the wiring layer 153d.

Next, as shown in FIG. 23, the passivation film 91 is formed on the wiring layer 153d.

Through the above steps, a configuration in which a voltage is applied to the upper electrode 82 is formed.

According to the above steps, the through electrode 153 is formed in such a way that one end of the through electrode 153 penetrates the front surface 50A of the semiconductor substrate 50 to be directly connected to the local wiring layer 161 serving as an etch stopper. Through electrode 153 . This avoids misalignment with a contact and increases in contact resistance; thus, even in configurations in which a voltage is applied to the upper electrode, the penetrating electrode can be reliably made finer.

Although description is omitted in the configurations of FIG. 2 and the like, as shown in FIG. 24, a fixed charge film 171 having a negative fixed charge is formed between a through hole in which the penetrating electrode 58 is formed and the embedded through hole between the insulating films 70 (70a). This can reduce dark current.

In this configuration, when the bottom of the through hole is punched by etching, the fixed charge film 171 is exposed at one side surface of the opening portion. In the case where the through electrode 58 is formed by embedding a conductive film, for example, in this state, the through electrode 58 and the fixed charge film 171 come into contact with each other.

The fixed charge film 171 has lower dielectric strength and program resistance than the insulating film 70 . Therefore, insufficient dielectric strength of the fixed charge film 171 can cause a short circuit failure between the through electrode 58 and the fixed charge film 171, as indicated by a double-headed arrow #1 in FIG. 24 .

Furthermore, the insufficient programming resistance of the fixed charge film 171 causes a contact portion between the fixed charge film 171 and the through electrode 58 to retract, and a conductive film enters, as shown in FIG. 25 . This causes a short circuit failure between the semiconductor substrate 50 and the through electrodes 58, as indicated by a double-headed arrow #2 in FIG. 25 .

Therefore, a configuration in which the penetration electrode 58 and the fixed charge film 171 are not in contact with each other will be described below.

<6. Third Embodiment>

26 is a cross-sectional view of a solid-state imaging device 10 according to a third embodiment of the present invention.

FIG. 26 shows a cross-sectional configuration around the through electrode 58 described above.

As shown in FIG. 26 , a fixed charge film 171 is formed in which through holes penetrating the electrodes 58 are formed Among them, the insulating film 70 is formed on the fixed charge film 171 , and an insulating film 172 is formed on the insulating film 70 . The insulating film 172 is formed to prevent the through electrode 58 and the fixed charge film 171 from contacting each other at a side surface of an opening portion obtained by punching through a portion of the bottom of the through hole on the front surface 50A side of the semiconductor substrate 50 . The insulating film 172 has insulating properties superior to those of the fixed charge film 171 .

In the example of FIG. 26, the insulating film 172 is embedded in the through hole together with the through electrode 58 to start contact with the local wiring layer 61 (hereinafter simply referred to as the wiring layer 61).

<7. Production steps of the configuration in which the through electrode and the fixed charge film do not contact each other>

(Example 1)

Next, an example of the production steps of a configuration in which the through electrode 58 and the fixed charge film 171 are not in contact with each other will be described with reference to FIGS. 27 to 33 .

Figure 27 shows a state similar to that of Figure 10 described above. In the step of FIG. 27, in a state in which the multilayer wiring layer 60 is formed on the front surface 50A side (lower side in the drawing) of the semiconductor substrate 50, from the rear surface 50B side (the lower side in the drawing) of the semiconductor substrate 50 upper side) a through hole 181 is formed.

The multilayer wiring layer 60 is formed by disposing the wiring layers 61 and 62 between layers of an insulating film made of SiO ₂ , SiN, SiOC, SiON or the like. The wiring layers 61 and 62 are formed of Cu, W, Al or the like, and Ti, TiN, Ta, TaN, Ru, Co, Zr or the like is used as the barrier metal thereof.

The through holes 181 are formed by processing Si (semiconductor substrate 50 ) by lithography and plasma etching. Here, etching is performed so as to stop in the insulating film of the multilayer wiring layer 60 . In this embodiment, a thickness of the semiconductor substrate 50 is, for example, 1 μm to 50 μm, and a diameter of the through hole 181 is, for example, 100 nm to 1 μm. In addition, one of the aspect ratios of the etching exceeds 5, for example.

After formation of vias 181, as shown in FIG. 28, by a technique such as, for example, ALD The fixed charge film 171 is formed in the through hole 181 by a technique. The fixed charge film 171 is formed to have a film thickness of less than, for example, 50 nm.

Examples of a material of the fixed charge film 171 include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, titanium oxide, lanthanum oxide, tantalum oxide, cerium oxide, neodymium oxide, titanium oxide, samarium oxide, europium oxide, tantalum oxide, oxide Ytterbium, Dysprosium oxide, Ytterbium oxide, Chlorine oxide, Ytterbium oxide, Ruthenium oxide and Yttrium oxide. An aluminum nitride film, a hafnium oxide film, or an aluminum nitride oxide film may be formed as the fixed charge film 171 .

After that, as shown in FIG. 29 , the insulating film 70 is formed in the through hole 181 in which the fixed charge film 171 is formed. The insulating film 70 is formed by forming a film of one of SiO ₂ , SiN, SiOC or the like by one of ALD or CVD. An inner diameter of the through hole 181 after the insulating film 70 is formed is about, for example, 30 nm to 500 nm.

After the insulating film 70 is formed, the insulating film 70, the fixed charge film 171, and the insulating film of the multilayer wiring layer 60 at the bottom of the through hole 181 (the front surface 50A side of the semiconductor substrate 50) are processed by plasma etching; therefore, as As shown in FIG. 30 , the vias 181 are made to reach the wiring layer 61 .

Examples of an etching gas used in plasma _etching include, for example, _CF4 , _CHF3 , _CH2F2 , _CH3F , _{C4F8 , C4F6 , C5HF7} , _{CH4 , C2H 4.} He, Ar, O ₂ , CO and N ₂ gases.

After the via 181 reaches the wiring layer 61, the etching residues and polymer are removed by ashing or wet etching. In, for example, ashing, a gas such as _O2 , _H2 or _N2 can be made into a plasma to be used.

After that, as shown in FIG. 31 , the insulating film 172 is formed in the through hole 181 that has reached the wiring layer 61 . The insulating film 172 is formed by forming a film of one of SiO ₂ , SiN, SiOC, or the like by a technique of ALD. The insulating film 172 is formed to have, for example, a film thickness of 5 nm or more.

After the insulating film 172 is formed, as shown in FIG. 32, the insulating film 172 at the bottom of the through hole 181 (the front surface 50A side of the semiconductor substrate 50) is processed by plasma etching; thus, the through hole 181 reaches the wiring again Layer 61. An etching gas similar to the etching gas in the step of FIG. 29 is also used here.

After the via 181 reaches the wiring layer 61, the etching residues and polymer are removed by ashing or wet etching.

Thereafter, in the through hole 181, a barrier metal is formed by a technique such as CVD, PVD or ALD, and then a conductive film is formed. Ti, TiN, Ta, TaN, Ru, Co, Zr or the like is used as a barrier metal, and a conductive film is formed by Cu electroplating. A film of W or Al can be formed as a conductive film by a technique such as CVD, PVD or ALD. In this way, as shown in FIG. 33 , the through electrodes 58 are formed in the through holes 181 .

Through the above steps, the insulating film 172 is formed to prevent contact between the through electrode 58 and the fixed charge film 171; therefore, the dielectric strength (withstand voltage) of the fixed charge film 171 can be increased, which can suppress the through electrode 58 and the fixed charge One of the films 171 has a short circuit failure.

In addition, since the fixed charge film 171 can be selected without considering the dielectric strength of the fixed charge film 171, a high noise reduction effect can be obtained.

In addition, the formation of an insulating film can be performed twice to make the inner diameter of the through hole 181 less than 1 μm, and thus the through electrode 58 can be made finer.

(Example 2)

In the step of FIG. 30 described above, when the vias 181 are made to reach the wiring layer 61, performing etching using, for example, a dilute hydrofluoric acid cleaning causes the fixed charge film 171 to retract due to being etched in a lateral direction , and a groove 181e is formed, as shown in FIG. 34 .

Thereafter, as shown in FIG. 35, an insulating film 172 is formed on the reaching the through hole 181 of the wiring layer 61; therefore, the insulating film 172 is also formed in the groove 181e.

After the insulating film 172 is formed, as shown in FIG. 36 , the insulating film 172 at the bottom of the via hole 181 is processed by plasma etching; thus, the via hole 181 reaches the wiring layer 61 .

Thereafter, barrier metal is formed in the through hole 181 and then a conductive film is formed; therefore, as shown in FIG. 37 , the through electrode 58 is formed in the through hole 181 .

Through the above steps, even in the case where an insufficient program resistance of the fixed charge film 171 causes a contact portion between the fixed charge film 171 and the through electrode 58 to retract, the insulating film 172 is formed to fill the space from which the contact portion has retracted. part. This can suppress a short-circuit failure between the semiconductor substrate 50 and the through electrodes 58 due to insufficient program resistance of the fixed charge film 171 .

In addition, since the fixed charge film 171 can be selected without considering the program resistance of the fixed charge film 171, a high noise reduction effect can be obtained.

(Example 3)

In the step of FIG. 30 described above, the vias 181 are made to reach the wiring layer 61 by plasma etching, but as shown in FIG. 38 , processing can be stopped before reaching the wiring layer 61 .

After that, as shown in FIG. 39 , the insulating film 172 is formed in the through hole 181 pierced midway to the multilayer wiring layer 60 .

After the insulating film 172 is formed, as shown in FIG. 40 , the insulating film 172 at the bottom of the via hole 181 is processed by plasma etching; thus, the via hole 181 reaches the wiring layer 61 .

Thereafter, barrier metal is formed in the through hole 181 and then a conductive film is formed; thus, as shown in FIG. 41 , the through electrode 58 is formed in the through hole 181 .

Through the above steps, charging damage when the wiring layer 61 is exposed by plasma etching can be reduced, and the possibility of wiring formation being inhibited by a metal-containing reaction product can be reduced.

(Example 4)

After the step of FIG. 28 described above, in the step of FIG. 29, the insulating film 70 is formed in the through hole 181 in which the fixed charge film 171 is formed. Without being limited thereto, after the fixed charge film 171 is formed in the through hole 181 (step of FIG. 28 ), the fixed charge film 171 at the bottom of the through hole 181 may be removed by plasma etching , as shown in Figure 42.

Thereafter, as shown in FIG. 43 , the insulating film 70 is formed in the through hole 181 of the fixed charge film 171 at the bottom from which the insulating film 70 has been removed.

After the insulating film 70 is formed, the insulating film 70 at the bottom of the via hole 181 and the insulating film of the multilayer wiring layer 60 are processed by plasma etching; therefore, as shown in FIG. 44 , the via hole 181 reaches the wiring layer 61 .

Thereafter, barrier metal is formed in the through hole 181 and then a conductive film is formed; thus, as shown in FIG. 45 , the through electrode 58 is formed in the through hole 181 .

That is, the insulating film 70 is formed to prevent the through electrode 58 and the fixed charge film 171 from contacting each other at a side surface where an opening portion is obtained by piercing the bottom of the through hole 181 on the front surface 50A side of the semiconductor substrate 50 .

Through the above steps, a configuration in which the through electrode 58 and the fixed charge film 171 do not contact each other can be achieved by reducing the steps without forming the insulating film 172, but this example is limited in which the fixed charge film 171 has a program A case of resistance.

(Example 5)

The above description is given based on a structure in which the through electrodes 58 are in contact with one of the multi-layer wiring layers 60, but as shown in FIG. The wiring layer contacts a structure.

In this case, in the step of FIG. 32 described above, the insulating film 172 at the bottom of the through hole 181 need not be processed.

In addition to being applied to a through electrode, the structure of this embodiment can also be applied in which a conductive film is embedded in Si (semiconductor substrate) to suppress noise occurring on a Si surface, and different voltages are applied to the conductive film and Si in each structure.

Furthermore, a pattern of a conductive film is not limited to a circular shape like, for example, the circular shape of the through electrode 58 in the top view of FIG. 47, but a trench may be formed. For example, as shown in FIG. 48 , a light blocking structure 191 that blocks light may be employed as a pattern of a conductive film between the pixels 20 .

Incidentally, the through electrodes are formed from the rear surface 50B side of the semiconductor structure 50 in the above embodiment, but may also be formed from the front surface 50A side of the semiconductor substrate 50 .

Therefore, a configuration in which a through electrode is formed from the front surface 50A side of the semiconductor substrate 50 will be described below.

<8. Fourth Embodiment>

49 is a cross-sectional view of a solid-state imaging device 10 according to a fourth embodiment of the present invention.

Figure 49 is a cross-sectional configuration around a through electrode.

Also in the example of FIG. 49, a multilayer wiring layer 60 having wiring layers 261 and 262 is formed on the front surface 50A side of the semiconductor substrate 50, and an organic photoelectric conversion unit (not shown in the figure) is formed on the rear surface of the semiconductor substrate 50. On the 50B side, the rear surface 50B serves as a light receiving surface.

An insulating film 270 is formed between the front surface 50A of the semiconductor substrate 50 and the multilayer wiring layer 60, and the insulating film 270 is also formed on the rear surface 50B side of the semiconductor substrate 50, wherein a fixed charge film 282 is interposed between the insulating film 270 and the rear surface between 50B.

A through electrode 253 is shaped in such a way that its lower end is connected to the wiring layer 261 via a contact 265 on the side of the front surface 50A of the semiconductor substrate 50 and its upper end is connected to a metal electrode 283 formed in the semiconductor substrate 50 . The metal electrode 283 is connected to the organic photoelectric conversion unit (not shown in the figure).

The insulating film 270 is also embedded in a through hole in which the through electrode 253 is formed. A p-type diffusion layer 281 is formed in a peripheral portion of the through hole in which the insulating film 270 is embedded.

In addition, an element isolation portion 252 having an STI structure is formed in a region on the side of the front surface 50A of the semiconductor substrate 50 in which the through hole is formed.

<9. Production steps for forming through electrodes from the front surface of the substrate>

Next, the production steps of forming the through electrodes 253 from the front surface 50A of the semiconductor substrate 50 will be described with reference to FIGS. 50 to 61 .

First, as shown in FIG. 50 , the element isolation portion 252 is formed on the front surface 50A side of the semiconductor substrate 50 .

Next, as shown in FIG. 51 , the photoresist layer 291 is patterned according to a location where the through electrode 253 will be formed. Thereafter, as shown in FIG. 52, the Si (semiconductor substrate 50) is processed by a technique such as dry etching; thus, a through hole 292 is formed.

After removing the photoresist layer 291, as shown in FIG. 53, an oxide film such as, for example, a BSG film is embedded in the through hole 292; thus, an insulating film 270 is formed.

In this state, annealing is performed on one side surface of the through hole 292; thus, as shown in FIG. 54, the p-type diffusion layer 281 is formed in one periphery (the semiconductor substrate 50 side) of the through hole 292.

Thereafter, in the through hole 292, an oxide film such as, for example, a TEOS film is embedded again, and a conductive film of polycrystalline Si, doped amorphous silicon, or the like is embedded by a technique such as ALD or CVD . In this manner, as shown in FIG. 55, through electrodes 253 are formed.

Next, as shown in FIG. 56, after patterning by photolithography, an unnecessary conductive film on the front surface 50A of the semiconductor substrate 50 is removed by a technique such as dry etching.

After that, as shown in FIG. 57 , the contacts 265 connected to the through electrodes 253 and the wiring layer 261 are formed on the front surface 50A side of the semiconductor substrate 50 . In addition, an insulating layer and a metal layer such as a wiring layer 262 are stacked on the front surface 50A side of the semiconductor substrate 50; thus, as shown in FIG. 58, a multilayer wiring layer 60 is formed.

Meanwhile, as shown in FIG. 59, on the rear surface 50B of the semiconductor substrate 50, Si (semiconductor substrate 50) is polished so that one end of the through electrode 253 is exposed.

Thereafter, as shown in FIG. 60, a fixed charge film 282 is formed on the rear surface 50B of the semiconductor substrate 50, and then an insulating film 270 such as an oxide film is formed.

Next, as shown in FIG. 61 , on the rear surface 50B side of the semiconductor substrate 50 , a metal electrode 283 is formed on the through electrode 253 .

The through electrodes 253 are formed in the manner described above.

Through the above steps, the through electrodes can be formed not from the rear surface side of the semiconductor substrate, but from the front surface side.

The above description has described an example in which one of the through electrodes of one embodiment of the present invention is applied to a solid-state imaging device that performs spectral diffraction in the vertical direction, but is not limited to this example, one of one embodiment of the present invention The through electrode can be applied to a configuration including a through electrode electrically connecting a first surface and a second surface of a semiconductor substrate. In addition, the above embodiments may be used in combination with each other.

The present invention is not limited to being applied to a solid-state imaging device, but can also be applied to an imaging device. Here, the imaging device refers to a camera system (eg, a digital still camera and a digital video camera) and an electronic device (eg, a mobile phone) having an imaging function. It should be noted that, in some cases, a module form (ie, a camera module) mounted on an electronic device is considered an imaging device.

<10. Configuration example of electronic device>

Therefore, a configuration example of an electronic device to which the present invention is applied will be described with reference to FIG. 62 .

An electronic device 300 shown in FIG. 62 includes an optical lens 301 , a shutter device 302 , a solid-state imaging device 303 , a driving circuit 304 and a signal processing circuit 305 . FIG. 62 illustrates an embodiment in which the solid-state imaging device 10 of one embodiment of the present invention described above is provided as a solid-state imaging device 303 in an electronic device (digital still camera).

Optical lens 301 causes image light (incident light) from an object to form an image on an imaging surface of solid-state imaging device 303 . Therefore, the signal charges are accumulated in the solid-state imaging device 303 for a certain period. The shutter device 302 controls a light radiation period and a light blocking period of the solid-state imaging device 303 .

The drive circuit 304 supplies drive signals to the shutter device 302 and the solid-state imaging device 303 . The driving signal supplied to the shutter device 302 is a signal for controlling the shutter operation of the shutter device 302 . The drive signal supplied to the solid-state imaging device 303 is one signal for controlling the signal transfer operation of the solid-state imaging device 303 . The solid-state imaging device 303 performs signal transfer according to the drive signal (timing signal) supplied from the drive circuit 304 . The signal processing circuit 305 performs various signal processing on the signal output from the solid-state imaging device 303 . The video signal that has undergone signal processing is stored in a storage medium such as a memory or output to a monitor.

<11. Example of use of image sensor>

Finally, a use example of an image sensor to which the present invention is applied will be described.

Figure 63 shows an example of the use of the image sensor described above.

The image sensors described above can be used, for example, in various situations where light such as visible light, infrared light, ultraviolet light, or X-rays are detected: - devices for capturing images for viewing, such as a digital video camera and a portable device with a camera function; - devices for transportation, such as capturing the front and back of cars, surroundings, car interiors and the like An on-board sensor for the image of the vehicle, a surveillance camera for monitoring the moving vehicle and the road, and a distance sensor for measuring the distance between the vehicle and the like (which is used for safe driving (such as automatic parking), the driver Status recognition and the like);- devices for household appliances such as a TV, a refrigerator, and an air conditioner, which are used to capture an image of a gesture of a user and perform electrical operations according to the gesture;- Devices for healthcare, such as an endoscope and a device for performing angiography by receiving infrared light; - Devices for security, such as a surveillance camera for crime prevention and a camera for personal authentication ;- devices for beauty, such as a skin measuring device for taking images of the skin and a microscope for taking images of the scalp;- devices for sports, such as an action camera and a wearable for sports and the like camera; - a device used in agriculture, such as one used to monitor the condition of fields and crops.

In addition, the embodiments of the present invention are not limited to the above-described embodiments, but various modifications can be made within the scope of the present invention.

In addition, the present invention can also be configured as follows.

(1)

A solid-state imaging device comprising: a wiring layer disposed on a first surface side of a semiconductor substrate; a photoelectric conversion element disposed on a second surface side of the semiconductor substrate; and a through electrode such that one end penetrates the first surface to be connected to the wiring layer and the other end is connected to the photoelectric conversion element One way setting.

(2)

The solid-state imaging device according to (1), wherein the through electrode is provided to each pixel, the other end of the through electrode is connected to an electrode provided to each pixel in the photoelectric conversion element, and the wiring layer is provided to each pixel and is connected to a floating diffusion region and an amplifying transistor.

(3)

The solid-state imaging device of (1) or (2), wherein the wiring layer is disposed closer to the second surface than another wiring layer.

(4)

The solid-state imaging device of any one of (1) to (3), wherein the wiring layer is formed of W or Ti.

(5)

The solid-state imaging device according to (2), wherein at least one photoelectric conversion element is provided to each pixel in the semiconductor substrate.

(6)

The solid-state imaging device of (1), wherein the other end of the through electrode is connected to an electrode provided to be shared by pixels in the photoelectric conversion element, and the wiring layer is connected to a power supply line.

(7)

The solid-state imaging device of (6), wherein the wiring layer is connected to the power supply line via a gate electrode.

(8)

The solid-state imaging device according to (7), wherein the gate electrode is provided on an element isolation film.

(9)

The solid-state imaging device according to (1), wherein the through electrode is formed of W, Cu, Al, Ti, Co, Hf, or Ta.

(10)

The solid-state imaging device of (1), wherein one end of the through electrode on the wiring layer side has a tapered shape.

(11)

The solid-state imaging device according to (1), wherein a fixed charge film is formed in a through hole in which the through electrode is provided, and an insulating film is formed on the fixed charge film, and the insulating film is formed to prevent the through electrode and The fixed charge films are in contact with each other at a side surface of an opening portion of the through hole on the first surface side.

(12)

The solid-state imaging device of (11), wherein in the through hole, a first insulating film is formed on the fixed charge film, and a second insulating film is formed on the through hole by punching through the first surface side On an opening portion obtained by a portion of a bottom portion of a hole, and the second insulating film is formed to prevent the through electrode and the fixed charge film from being in the opening portion contact with each other at one of the side surfaces.

(13)

The solid-state imaging device according to (12), wherein the second insulating film has insulating properties superior to those of the fixed charge film.

(14)

The solid-state imaging device of (11), wherein the fixed charge film is formed in the through hole, and the insulating film is formed in an opening portion obtained by punching through a bottom of the through hole on the first surface side superior.

(16)

The method for producing a solid-state imaging device as in (15), wherein the through electrode is provided in such a manner that one end penetrates the first surface to be connected to the wiring layer by using a Bosch procedure.

(17)

The method for producing a solid-state imaging device as in (15), wherein a high-concentration impurity region is provided in a region in which the through electrode is provided in the semiconductor substrate.

(18)

The method for producing a solid-state imaging device as in (15), wherein the through electrode is provided from the second surface side of the semiconductor substrate.

(19)

The method for producing a solid-state imaging device as in (15), wherein the through electrode is provided from the first surface side of the semiconductor substrate.

(20)

A method for producing a solid-state imaging device, the method comprising: Disposing a wiring layer on a first surface side of a semiconductor substrate; disposing a through electrode in such a way that one end penetrates the first surface to be connected to the wiring layer; and connecting the other end of the through electrode One way to a photoelectric conversion element is to dispose the photoelectric conversion element on a second surface side of the semiconductor substrate.

(twenty one)

An electronic device comprising a solid-state imaging device comprising a wiring layer disposed on a first surface side of a semiconductor substrate, a photoelectric conversion element disposed on a second surface side of the semiconductor substrate, and a through electrode, which is arranged in such a way that one end penetrates the first surface to be connected to the wiring layer and the other end is connected to the photoelectric conversion element.

(twenty two)

An imaging device comprising: a semiconductor substrate having a first side and a second side opposite to the first side; a photoelectric conversion unit located on the first side of the semiconductor substrate; a plurality of a multi-layer wiring layer on the second side of the semiconductor substrate; a through electrode extending between the photoelectric conversion unit and the multi-layer wiring layer, wherein the multi-layer wiring layer includes a local wiring layer, and wherein the penetrating electrode A second end of the electrode is in direct contact with the local wiring layer.

(twenty three)

The imaging device of (22), wherein the photoelectric conversion unit includes a lower electrode, and wherein a first end of the through electrode is in direct contact with the lower electrode.

(twenty four)

The imaging device of (23), wherein the semiconductor substrate includes a light incident surface at the first side of the semiconductor substrate.

(25)

The imaging device of (24), further comprising an interlayer insulating film between a front surface of the semiconductor substrate and the local wiring layer, wherein the front surface is located at the second side of the semiconductor substrate, and wherein The local wiring layer is separated from the front surface of the semiconductor substrate by the interlayer insulating film.

(26)

The imaging device of (24), further comprising an insulating film interposed between the lower electrode and the light incident surface of the semiconductor substrate.

(27)

The imaging device of (22), wherein the through electrode is formed of a metal.

(28)

The imaging device of (22), wherein the through electrode is formed of at least one of Al, Ti, Co, Hf, Ta, Cu, and W.

(29)

The imaging device of (23), wherein the first end of the through electrode has a width greater than a width of the second end of the through electrode.

(30)

The imaging device of (22), wherein the second end of the through electrode is tapered.

(31)

The imaging device of (22), further comprising a plurality of pixels, wherein each of the pixels It includes a first photodiode formed in the semiconductor substrate and a second photodiode formed in the semiconductor substrate.

(32)

An electronic device comprising: a plurality of pixels, wherein each of the pixels comprises: a photoelectric conversion unit located on the first side of the semiconductor substrate; at least one photodiode formed in the semiconductor substrate ; a multi-layer wiring layer on the second side of the semiconductor substrate; a through electrode extending between the photoelectric conversion unit and the multi-layer wiring layer, wherein the multi-layer wiring layer includes a local wiring layer, and A second end of the through electrode is in direct contact with the local wiring layer.

(33)

The electronic device according to (32), wherein the photoelectric conversion unit includes a lower electrode, and wherein a first end of the through electrode is in direct contact with the lower electrode.

(34)

The electronic device of (32), wherein the through electrode is formed of at least one of Al, Ti, Co, Hf, Ta, Cu, and W.

(35)

The electronic device of (33), wherein the first end of the through electrode has a width greater than a width of the second end of the through electrode.

(36)

The electronic device of (32), wherein the second end of the through electrode is tapered.

(37)

The electronic device of (32), wherein each of the pixels further includes a second photodiode formed in the semiconductor substrate.

10‧‧‧Solid-state imaging device

20‧‧‧pixels

21‧‧‧Pixel area

31‧‧‧Peripheral circuit unit

50‧‧‧Semiconductor substrate

50A‧‧‧Front surface

50B‧‧‧Back surface

51‧‧‧Inorganic photoelectric conversion unit

52‧‧‧Inorganic photoelectric conversion unit

53‧‧‧Floating Diffusion (FD)

54‧‧‧Transistor

55‧‧‧Amplifying transistor

55G‧‧‧Gate Electrode

55s‧‧‧Component isolation part

56‧‧‧Reset Transistor

56G‧‧‧Gate Electrode

56s‧‧‧Component isolation part

57‧‧‧Etch Stop Layer

58‧‧‧Through Electrodes

60‧‧‧Multilayer wiring layer

61‧‧‧Local wiring layer

62‧‧‧Wiring Layer

63‧‧‧Wiring Layer

65‧‧‧Contact

70‧‧‧Insulating film

80‧‧‧Organic photoelectric conversion unit

81‧‧‧Lower electrode

82‧‧‧Top electrode

83‧‧‧Organic Photoelectric Conversion Layer

91‧‧‧Passivation film

92‧‧‧On-Chip Lenses

Claims (16)

An imaging device comprising: a semiconductor substrate having a first side and a second side opposite to the first side; a photoelectric conversion unit located on the first side of the semiconductor substrate; a plurality of A wiring layer on the second side of the semiconductor substrate; a through electrode extending between the photoelectric conversion unit and the multilayer wiring layer, wherein the through electrode penetrates between an amplifying transistor and a reset The multilayer wiring layer between transistors. The imaging device of claim 1, wherein the photoelectric conversion unit comprises a lower electrode, and wherein a first end of the through electrode is in direct contact with the lower electrode. The imaging device of claim 2, wherein the semiconductor substrate includes a light incident surface at the first side of the semiconductor substrate. The imaging device of claim 3, further comprising an interlayer insulating film interposed between a front surface of the semiconductor substrate and a local wiring layer, wherein the front surface is located at the second side of the semiconductor substrate, and wherein The local wiring layer is separated from the front surface of the semiconductor substrate by the interlayer insulating film. The imaging device of claim 3, further comprising an insulating film interposed between the lower electrode and the light incident surface of the semiconductor substrate. The imaging device of claim 1, wherein the through electrode is formed of a metal. The imaging device of claim 1, wherein the through electrode is formed of at least one of Al, Ti, Co, Hf, Ta, Cu, and W. The imaging device of claim 2, wherein the first end of the through electrode has a width greater than a width of a second end of the through electrode. The imaging device of claim 1, wherein a second end of the through electrode is tapered. The imaging device of claim 1, further comprising a plurality of pixels, wherein each of the pixels includes a first photodiode formed in the semiconductor substrate and a second photodiode formed in the semiconductor substrate . An electronic device comprising: a plurality of pixels, wherein each of the pixels comprises: a photoelectric conversion unit located on a first side of a semiconductor substrate; at least one first photodiode formed on the semiconductor In the substrate; a multi-layer wiring layer located on a second side of the semiconductor substrate; a through electrode extending between the photoelectric conversion unit and the multi-layer wiring layer, wherein the through electrode penetrates between an amplification The multilayer wiring layer between the transistor and a reset transistor. The electronic device of claim 11, wherein the photoelectric conversion unit comprises a lower electrode, and wherein a first end of the through electrode is in direct contact with the lower electrode. The electronic device of claim 11, wherein the through electrode is formed of at least one of Al, Ti, Co, Hf, Ta, Cu, and W. The electronic device of claim 12, wherein the first end of the through electrode has a width greater than a width of a second end of the through electrode. The electronic device of claim 11, wherein a second end of the through electrode is tapered. The electronic device of claim 11, wherein each of the pixels further comprises a second photodiode formed in the semiconductor substrate.

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