KR102524146B1 - Solid-state imaging device, manufacturing method therefor, and electronic device - Google Patents

Abstract

An imaging device of the present invention includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photoelectric conversion section on the first surface of the semiconductor substrate; a multilayer wiring layer on the second side of the semiconductor substrate and including a local wiring layer; and a through electrode extending between the photoelectric conversion unit and the multi-layer wiring layer and having a second end directly contacting the local wiring layer.

Description

Solid-state imaging device, manufacturing method therefor, and electronic device

TECHNICAL FIELD The present technology relates to a solid-state imaging device, a method for manufacturing the same, and electronic devices, and more particularly, to a solid-state imaging device capable of miniaturizing through electrodes, a method for manufacturing the same, and electronic devices.

This application claims priority based on JP2016-242144 filed on December 14, 2016 and JP2017-217217 filed on November 10, 2017, the contents of which are incorporated herein by reference.

In recent years, in CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors, reduction in pixel size has been attempted. However, accompanying this, a decrease in sensitivity and a decrease in S/N occur due to a decrease in the number of photons incident on the unit pixel.

On the other hand, as a pixel array in which red (R), green (G), and blue (B) pixels are arranged on a plane, for example, a Bayer array using a primary color filter is widely known. However, in the Bayer array, since the G and B lights in the R pixel do not pass through the color filter and are not used for photoelectric conversion, sensitivity loss occurs or false color (false color) is caused by interpolation processing between pixels. ) occurs and is discarded.

In contrast to these, a method is known in which three photoelectric conversion layers are stacked in the vertical direction to obtain color signals for three colors with one pixel. For example, a structure has been proposed in which G light is detected by a photoelectric conversion film provided on a Si substrate, and R and B lights are detected by two photodiodes PD stacked on the Si substrate.

In such a structure, it is necessary to transfer the electric charge generated in the photoelectric conversion film to the floating diffusion (FD) formed on the opposite surface of the Si substrate. In contrast, for example, Patent Literature 1 discloses a structure in which through electrodes are provided for each pixel between the front and back surfaces of a semiconductor substrate to transfer the electric charge generated in the photoelectric conversion film to the FD.

Patent Document 1: Japanese Unexamined Publication No. 2015-38931

However, with the structure disclosed in Patent Literature 1, it was not possible to miniaturize the through electrode. Specifically, in the through electrode made of Si, there is a limit to miniaturization in terms of the manufacturing process. Further, in the through electrode made of metal, misalignment with the contact connected to the front or rear surface of the semiconductor substrate may occur, resulting in an increase in contact resistance.

The present technology was made in view of such a situation, and was made possible to reliably miniaturize the through electrode.

An imaging device of the present invention includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photoelectric conversion section on the first surface of the semiconductor substrate; a multilayer wiring layer on the second side of the semiconductor substrate and including a local wiring layer; and a through electrode extending between the photoelectric conversion unit and the multi-layer wiring layer and having a second end directly contacting the local wiring layer.

An electronic device of the present invention includes a photoelectric conversion unit on a first surface of a semiconductor substrate; at least a first photodiode formed on the semiconductor substrate; a multilayer wiring layer on the second side of the semiconductor substrate and including a local wiring layer; and a plurality of pixels each including through electrodes extending between the photoelectric conversion unit and the multi-layer wiring layer and having second ends directly contacting the local wiring layer.

According to the present technology, it is possible to reliably miniaturize the through electrode. In addition, the effects described here are not necessarily limited, and any one of the effects described in the present disclosure may be used.

1 is a block diagram showing a configuration example of a solid-state imaging device of the present technology.
Fig. 2 is a cross-sectional view showing a configuration example of a solid-state imaging device according to the first embodiment.
Fig. 3 is a sectional view showing a manufacturing process of a pixel;
Fig. 4 is a sectional view showing a manufacturing process of a pixel;
Fig. 5 is a cross-sectional view showing a manufacturing process of a pixel.
Fig. 6 is a sectional view showing a manufacturing process of a pixel;
Fig. 7 is a sectional view showing a manufacturing process of a pixel;
Fig. 8 is a cross-sectional view showing a manufacturing process of a pixel.
Fig. 9 is a sectional view showing a manufacturing process of a pixel.
Fig. 10 is a sectional view showing a manufacturing process of a pixel.
Fig. 11 is a sectional view showing a manufacturing process of a pixel.
Fig. 12 is a cross-sectional view showing a manufacturing process of a pixel.
Fig. 13 is a sectional view showing a manufacturing process of a pixel.
Fig. 14 is a sectional view showing a manufacturing process of a pixel.
Fig. 15 is a sectional view showing a manufacturing process of a pixel.
Fig. 16 is a sectional view showing a manufacturing process of a pixel.
Fig. 17 is a sectional view showing a manufacturing process of a pixel.
Fig. 18 is a cross-sectional view showing a configuration example of a solid-state imaging device according to a second embodiment.
Fig. 19 is a cross-sectional view showing a manufacturing process of a configuration in which a voltage is applied to an upper electrode.
Fig. 20 is a cross-sectional view showing a manufacturing process of a configuration in which a voltage is applied to an upper electrode.
Fig. 21 is a cross-sectional view showing a manufacturing process of a configuration in which a voltage is applied to an upper electrode.
22 is a cross-sectional view showing a manufacturing process of a configuration in which a voltage is applied to an upper electrode.
Fig. 23 is a cross-sectional view showing a manufacturing process of a configuration in which a voltage is applied to an upper electrode.
Fig. 24 is a diagram explaining the insulation resistance of a fixed charge film.
Fig. 25 is a diagram explaining process resistance of a fixed charge film;
Fig. 26 is a cross-sectional view showing a configuration example of a solid-state imaging device according to a third embodiment.
Fig. 27 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 28 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 29 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 30 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 31 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 32 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 33 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 34 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 35 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 36 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 37 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 38 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 39 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 40 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 41 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 42 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 43 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 44 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 45 is a cross-sectional view showing a manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact each other.
Fig. 46 is a cross-sectional view showing a configuration example in which a through electrode and a wiring layer do not contact each other;
47 is a diagram showing an example of a pattern of a conductive film;
48 is a diagram showing an example of a pattern of a conductive film;
49 is a cross-sectional view showing a configuration example of a solid-state imaging device according to a fourth embodiment.
Fig. 50 is a cross-sectional view showing a manufacturing process of forming through electrodes from the substrate surface.
Fig. 51 is a cross-sectional view showing a manufacturing process of forming through electrodes from the substrate surface.
Fig. 52 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 53 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 54 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 55 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 56 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 57 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 58 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 59 is a sectional view showing a manufacturing process of forming a through electrode from the substrate surface;
Fig. 60 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 61 is a cross-sectional view showing a manufacturing process of forming a through electrode from the substrate surface.
Fig. 62 is a block diagram showing a configuration example of an electronic device according to the present technology.
63 is a diagram showing a use case using an image sensor;

Hereinafter, a mode for implementing the present disclosure (hereinafter, referred to as an embodiment) will be described. In addition, description is performed in the following order.

1. Configuration example of solid-state imaging device

2. First Embodiment

3. Pixel Manufacturing Process

4. Second Embodiment

5. Manufacturing process of a configuration in which voltage is applied to the upper electrode

6. Third Embodiment

7. Manufacturing process for a configuration in which the through electrode and the fixed charge film do not contact each other

8. Fourth Embodiment

9. Manufacturing process of forming a through electrode from the substrate surface

10. Examples of configuration of electronic devices

11. Use cases of image sensors

<1. Configuration example of solid-state imaging device>

1 is a block diagram showing a configuration example of a solid-state imaging device of the present technology.

The solid-state imaging device 10 is configured as a CMOS image sensor. The solid-state imaging device 10 includes a pixel region (pixel array) 21 in which a plurality of pixels 20 are regularly arranged in a two-dimensional array on a semiconductor substrate (eg, Si substrate), not shown, and a peripheral circuit section. have

The pixel 20 has a photoelectric conversion unit (for example, a photodiode) and a plurality of pixel transistors (MOS transistors). The plurality of pixel transistors can be composed of, for example, three transistors: a transfer transistor, a reset transistor, and an amplification transistor. Further, the plurality of pixel transistors may be configured with four transistors by adding a selection transistor. In addition, since the equivalent circuit of a unit pixel is the same as that of a general one, detailed description is abbreviate|omitted.

Further, the pixel 20 may be configured as one unit pixel or may have a shared pixel structure. This pixel sharing structure is a structure in which a plurality of photodiodes share a floating diffusion and transistors other than transfer transistors.

Incidentally, although a detailed description will be given later, the pixel 20 is formed by stacking photoelectric conversion units.

The peripheral circuit section has a vertical driving circuit 22 , a column signal processing circuit 23 , a horizontal driving circuit 24 , an output circuit 25 , and a control circuit 26 .

The control circuit 26 receives an input clock and data instructing an operation mode and the like, and also outputs data such as internal information of the solid-state imaging device 10 . In addition, the control circuit 26 determines the operation of the vertical driving circuit 22, the column signal processing circuit 23, the horizontal driving circuit 24, etc., based on the vertical synchronizing signal, the horizontal synchronizing signal, and the master clock. Generates a reference clock signal or control signal. Then, the control circuit 26 inputs these signals to the vertical driving circuit 22, the column signal processing circuit 23, the horizontal driving circuit 24, and the like.

The vertical drive circuit 22 is constituted by a shift register, for example. The vertical driving circuit 22 selects a pixel driving wiring, supplies pulses for driving pixels to the selected pixel driving wiring, and drives the pixels row by row. That is, the vertical driving circuit 22 sequentially selectively scans each pixel 20 in the pixel region 21 in the vertical direction in units of rows. Then, the vertical drive circuit 22 supplies a pixel signal based on the signal charge generated in response to the amount of light received by the photoelectric conversion unit of each pixel 20 to the column signal processing circuit 23 through the vertical signal line 27 do.

Column signal processing circuits 23 are arranged for each column of pixels 20, for example. The column signal processing circuit 23 performs signal processing such as noise removal for each pixel column on signals output from the pixels 20 for one row. Specifically, the column signal processing circuit 23 performs signal processing such as Correlated Double Sampling (CDS) to remove fixed pattern noise inherent in the pixels 20, signal amplification, and A/D (Analog/Digital) conversion. do At the output end of the column signal processing circuit 23, a horizontal selection switch (not shown) is connected between the horizontal signal line 28 and provided.

The horizontal driving circuit 24 is constituted by a shift register, for example. The horizontal driving circuit 24 selects each of the column signal processing circuits 23 in order by sequentially outputting horizontal scanning pulses, and transmits pixel signals from each of the column signal processing circuits 23 to the horizontal signal line 28. output to

The output circuit 25 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 23 through the horizontal signal lines 28 and outputs them. The output circuit 25 may perform, for example, only buffering, or may perform black level adjustment, column deviation correction, various digital signal processing, and the like, for example.

The input/output terminal 29 exchanges signals with the outside.

<2. First Embodiment>

2 is a cross-sectional view of the solid-state imaging device 10 according to the first embodiment of the present technology.

In FIG. 2 , cross-sections of the pixel region 21 and the peripheral circuit portion 31 constituting the solid-state imaging device 10 are shown.

In the solid-state imaging device 10, a multilayer wiring layer 60 is formed on the surface 50A (first surface) side of the semiconductor substrate 50 made of Si or the like. Further, on the side of the back surface 50B (second surface) serving as the light-receiving surface of the semiconductor substrate 50, an organic photoelectric conversion unit 80 as a photoelectric conversion element is formed via the insulating film 70.

In the pixel region 21, each pixel 20 includes one organic photoelectric conversion unit 80 and two inorganic photoelectric conversion units 51 and 52 that selectively detect light in different wavelength ranges and perform photoelectric conversion. ) (PD(1), PD(2)) have a laminated structure in which they are stacked in the longitudinal direction. The inorganic photoelectric conversion units 51 and 52 are formed in a form embedded in the semiconductor substrate 50 .

The organic photoelectric conversion unit 80 is constituted by, for example, two or more types of organic semiconductor materials. The organic photoelectric conversion unit 80 is composed of an organic photoelectric conversion element using an organic semiconductor to absorb light in a selective wavelength range, that is, green light here, and generate electron-hole pairs. The organic photoelectric conversion unit 80 is an organic photoelectric conversion layer between a lower electrode 81 provided for each pixel 20 for extracting signal charge and an upper electrode 82 provided in common to each pixel 20. It has a structure in which (organic semiconductor layer 83) is interposed.

The lower electrode 81 opposes the light-receiving surfaces of the inorganic photoelectric conversion units 51 and 52 formed in the semiconductor substrate 50 and is provided in a region covering these light-receiving surfaces. The lower electrode 81 is made of a light-transmitting conductive film, for example, made of indium tin oxide (ITO). In addition to indium tin oxide, as a constituent material of the lower electrode 81, a tin oxide (SnO2)-based material to which a dopant is added or a zinc oxide-based material obtained by adding a dopant to aluminum zinc oxide (ZnO) may be used. Examples of the zinc oxide-based material include aluminum zinc oxide (AZO) to which aluminum (Al) is added as a dopant, gallium zinc oxide (GZO) to which gallium (Ga) is added, and indium zinc oxide (IZO) to which indium (In) is added. ) can be heard. In addition, CuI, InSbO4, ZnMgO, CuInO2, MgIN2O4, CdO, ZnSnO3 or the like may be used. Further, since signal charge (electrons) obtained in the organic photoelectric conversion layer 83 is taken out from the lower electrode 81, the lower electrode 81 is formed separately for each pixel 20.

The organic photoelectric conversion layer 83 is comprised including three types of a 1st organic-semiconductor material, a 2nd organic-semiconductor material, and/or a 3rd organic-semiconductor material, for example. Any one of these three types of organic semiconductor materials is one or both of an organic p-type semiconductor and an organic n-type semiconductor, photoelectrically converts light in a selective wavelength range, and transmits light in a different wavelength range. Specifically, the organic photoelectric conversion layer 83 has a maximum absorption wavelength in the range of 450 nm or more and 650 nm or less as the wavelength of green (G), for example.

Other layers not shown may be provided between the organic photoelectric conversion layer 83 and the lower electrode 81 and between the organic photoelectric conversion layer 83 and the upper electrode 82 . For example, in order from the lower electrode 81 side, a lower film, a hole transport layer, an electron blocking film, an organic photoelectric conversion layer 83, a hole blocking film, a buffer film, an electron transport layer, and work function adjustment Films may be laminated.

The upper electrode 82 is made of a conductive film having the same light-transmitting properties as the lower electrode 81 . The upper electrode 82 is formed as an electrode common to each pixel 20, but may be separated for each pixel 20. The upper electrode 82 has a thickness of 10 nm to 200 nm, for example.

The inorganic photoelectric conversion units 51 and 52 are PDs (photodiodes) each having a pn junction, and the order of the inorganic photoelectric conversion units 51 and 52 from the back surface 50B side on the optical path in the semiconductor substrate 50 is formed with The inorganic photoelectric converter 51 selectively detects blue light and accumulates signal charges corresponding to blue. The inorganic photoelectric converter 51 is formed in a selective region along the back surface 50B of the semiconductor substrate 50, for example. The inorganic photoelectric converter 52 selectively detects red light and accumulates signal charges corresponding to red. The inorganic photoelectric conversion section 52 is formed in a region lower than the inorganic photoelectric conversion section 51 (on the surface 50A side), for example. In addition, blue (B) is a color corresponding to, for example, a wavelength range of 450 nm to 495 nm, red (R) is a color corresponding to a wavelength range of, for example, 620 nm to 750 nm, respectively, and the inorganic photoelectric conversion unit (51, 52) should be capable of detecting light in some or all of the wavelength ranges, respectively.

As described above, the pixel 20 has a laminated structure in which an organic photoelectric conversion unit 80 and two inorganic photoelectric conversion units 51 and 52 are stacked in the vertical direction, and the organic photoelectric conversion unit 80 emits green light. Since the inorganic photoelectric conversion unit 51 absorbs (detects) and photoelectrically converts blue light and the inorganic photoelectric conversion unit 52 red light, respectively, longitudinal polarization in the vertical direction (layer direction) is performed in one pixel, Each color signal of red, green, and blue can be acquired.

On the surface 50A of the semiconductor substrate 50, for example, a floating diffusion (FD) 53, a transfer transistor 54, an amplification transistor 55, and a reset transistor 56 are provided. Among them, the gate electrode 55G of the FD 53 and the amplifying transistor 55 is closest to the surface 50A of the semiconductor substrate 50 among the wiring layers 61 to 63 forming the multilayer wiring layer 60. It is connected to the local wiring layer 61 formed on the side. The local wiring layer 61 is formed for each pixel 20 . Also, the gate electrode 56G of the reset transistor 56 is connected to the wiring layer 63 via a contact 65 . Further, the amplification transistor 55 is isolated from other regions by an element isolation section 55s having an STI (Shallow Trench Isolation) structure, and the reset transistor 56 is separated from other regions by an element isolation section 56s. is separated from

Further, an etch stop layer 57 made of a SiN film or the like is formed on the surface 50A of the semiconductor substrate 50 .

In addition, in each pixel 20, the semiconductor substrate 50 has a through electrode 58, the lower end of which penetrates the surface 50A of the semiconductor substrate 50 and is directly connected to the local wiring layer 61, and the upper end It is formed so as to be connected to this lower electrode 81. In particular, on the surface 50A side of the semiconductor substrate 50, the through electrode 58 penetrates between the element isolation portion 55s of the amplifier transistor 55 and the device isolation portion 56s of the reset transistor 56. is formed The through electrode 58 is formed of a metal material such as W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Co (cobalt), Hf (hafnium), or Ta (tantalum). .

As a result, in each pixel 20, electric charge generated in the organic photoelectric conversion unit 80 on the back surface 50B side of the semiconductor substrate 50 passes through the through electrode 58 to the front surface 50A of the semiconductor substrate 50. ) side FD 53 or amplifying transistor 55.

Further, in each pixel 20 , a passivation film 91 is formed on the upper electrode 82 , and an on-chip lens 92 is formed on the passivation film 91 .

<3. Pixel Manufacturing Process>

Next, with reference to FIGS. 3 to 15 , the manufacturing process of the pixel 20 will be described.

First, in FIG. 3 , each transistor 54 to 56 is formed by ion implantation or the like on the surface 50A side of the semiconductor substrate 50 on which the inorganic photoelectric conversion units 51 and 52 and the FD 53 are formed, The state in which the etch stop layer 57 and the interlayer insulating film 101a are formed is shown. The etch stop layer 57 is formed by, for example, forming a SiN film or the like by a method such as LP-CVD (Low Pressure-Chemical Vapor Deposition). Further, the interlayer insulating film 101a is formed by forming an oxide film or the like by a method such as plasma CVD, and planarizing the surface by a method such as CMP (Chemical Mechanical Polishing). Further, a high-concentration impurity region (P++ region) may be formed in the region 50i of the semiconductor substrate 50 where the through electrode 58 is to be formed. Accordingly, damage caused during formation of the through electrode 58 can be reduced, and as a result, dark current can be reduced.

Next, as shown in FIG. 4, a contact hole CH1 for connecting the local wiring layer 61 and the semiconductor substrate 50 (FD 53 and amplification transistor 55) is formed by patterning and dry etching. is formed by Further, a groove TR1 for the local wiring layer 61 is formed by patterning and dry etching.

Then, as shown in Fig. 5, a contact and local wiring layer 61 is formed by filling the contact hole CH1 and the groove TR1 with metal. For example, a Ti film for work function adjustment or the like is formed by a method such as PVD (Physical Vapor Deposition), and a barrier metal such as TiN or W is embedded by a method such as CVD. In addition, an unnecessary metal film on the surface is removed by a method such as CMP.

In this way, the local wiring layer 61 connected to one end of the through electrode 58 is made of a metal that is unlikely to cause contamination, such as W or Ti.

Subsequently, as shown in FIG. 6, an insulating film 101b is formed by forming an oxide film or the like on the local wiring layer 61 by a method such as plasma CVD.

Subsequently, as shown in FIG. 7, a contact hole for connecting the wiring layer 63 above the local wiring layer 61 and the semiconductor substrate 50 is formed by patterning and dry etching, and a metal is filled in, A contact 65 is formed. For example, a Ti film for work function adjustment or the like is formed by a method such as PVD, and a barrier metal such as TiN or W is embedded by a method such as CVD. In addition, an unnecessary metal film on the surface is removed by a method such as CMP.

After that, as shown in FIG. 8, by forming the wiring layer 63, the multilayer wiring layer 60 is formed.

Then, a support substrate (not shown) or another semiconductor substrate is bonded to the front surface 50A side (multilayer wiring layer 60) of the semiconductor substrate 50, and is inverted vertically.

On the back surface 50B side of the semiconductor substrate 50, first, as shown in FIG. 9, the resist 111 is patterned according to the position where the through electrode 58 is formed. After that, as shown in Fig. 10, through-holes 112 are formed by processing Si (semiconductor substrate 50) by a method such as dry etching. Etching here is stopped at the etch stop layer 57 formed on the surface 50A side of the semiconductor substrate 50 . In addition, even when misalignment occurs in the patterning of the resist 111, the element isolation portions 55s and 56s formed on the surface 50A side of the semiconductor substrate 50 function as an etching stopper.

After the resist 111 is removed, as shown in FIG. 11 , an oxide film or the like is formed in the through hole 112 by, for example, ALD (Atomic Layer Deposition), so that the insulating film 70a is buried. do.

Thereafter, as shown in FIG. 12, the insulating film 70a formed on the bottom of the through hole 112, the etch stop layer 57, and the interlayer insulating film of the multilayer wiring layer 60 are removed by a method such as dry etching. By etching, the through hole 112 opens up to the local wiring layer 61 . Etching here stops at the local wiring layer 61.

Subsequently, as shown in FIG. 13, a conductive film is formed by embedding a barrier metal or the like into the through hole 112 by a method such as ALD, and then embedding W or the like by a method such as CVD. In this way, the through electrode 58 is formed. Then, in order to form the lead-out wiring layer on the top of the through electrode 58, after patterning by photolithography, an unnecessary conductive film is removed by a method such as dry etching.

Then, as shown in FIG. 14 , after the insulating film 70 is formed, the organic photoelectric conversion unit 80 is formed by forming the lower electrode 81, the organic photoelectric conversion layer 83, and the upper electrode 82. is formed

Then, as shown in FIG. 15 , a passivation film 91 is formed on the upper electrode 82 , and an on-chip lens 92 is formed on the passivation film 91 .

Through the above steps, the pixel 20 is formed.

According to the above steps, the through electrode 58 is formed so that one end of the through electrode 58 penetrates the surface 50A of the semiconductor substrate 50 and is directly connected to the local wiring layer 61 as an etching stopper. As a result, it is possible to avoid misalignment of the contact and an increase in contact resistance, and it is possible to reliably miniaturize the through electrode.

Further, in the configuration disclosed in Patent Literature 1, parasitic capacitance and contact resistance generated in the path from the organic photoelectric conversion unit to the FD through the through electrode increase with the through electrode being miniaturized, resulting in deterioration of RC delay and conversion A decrease in efficiency is a concern.

On the other hand, in this embodiment, the local wiring layer 61 connected to the FD 53 of the through electrode and the amplifying transistor 55 is hierarchically separated from other wiring layers, so that the degree of freedom in wiring layout is increased. , the parasitic capacitance can be reduced. As a result, it becomes possible to realize improvement of RC delay and improvement of conversion efficiency.

In addition, since a metal such as W or Ti that does not cause contamination is used for the local wiring layer 61, and the Si substrate is processed without exposing the metal material, dark time characteristics and white point characteristics due to metal contamination or the like can be reduced. You can keep it good.

In addition, in existing TSVs (Through Silicon Vias), stress due to stress occurs, and transistors cannot be disposed near the TSV, resulting in layout restrictions.

On the other hand, in the present embodiment, since the through electrode can be miniaturized without generating stress due to stress, a layout in which transistors are disposed near the through electrode can be realized.

Further, in the step of opening the through hole 112 to the local wiring layer 61 described with reference to FIG. 12, an etching technique called a Bosch process may be used. The Bosch process is an etching method in which etching and etching sidewall protection are repeated, and etching with a high aspect ratio is possible.

According to the Bosch process, as shown in FIG. 16, the tip 112t of the through hole 112 is formed in a tapered shape. As a result, as shown in FIG. 17, the tip 58t of the through electrode 58 is formed in a tapered shape. In this way, since the tip 58t of the through electrode 58 is formed in a tapered shape, the contact area of the through electrode 58 to the local wiring layer 61 serving as a stopper is reduced, so that the through electrode 58 and the local wiring layer It is possible to suppress misalignment with (61). In addition, by forming the tip 58t of the through electrode 58 into a tapered shape, parasitic capacitance between the through electrode 58 and each wiring layer forming the multilayer wiring layer 60 can be reduced.

<4. Second Embodiment>

18 is a cross-sectional view of a solid-state imaging device 10 according to a second embodiment of the present technology.

18, a cross section of a part of the peripheral circuit part 31 constituting the solid-state imaging device 10 is shown.

18, the multi-layer wiring layer 60 is formed on the front surface 50A side of the semiconductor substrate 50, and the back surface 50B side serving as the light-receiving surface of the semiconductor substrate 50 passes through the insulating film 70, An organic photoelectric conversion unit 80 is formed.

A transistor 151 is provided on the surface 50A of the semiconductor substrate 50, for example. The gate electrode 151G of the transistor 151 is the local wiring layer 161 formed on the side closest to the surface 50A of the semiconductor substrate 50 among the wiring layers 161 and 163 forming the multilayer wiring layer 60. ) is connected. A gate electrode 151G of the transistor 151 is formed on the element isolation film 152 . In addition, the gate electrode 151G of the transistor 151 is connected to the wiring layer 163 via a contact 165 . The wiring layer 163 functions as a power supply wiring connected to a predetermined power supply. Therefore, the local wiring layer 161 is connected to the power supply wiring via the gate electrode 151G of the transistor 151 .

Further, in the semiconductor substrate 50, a through electrode 153 has a lower end penetrating the surface 50A of the semiconductor substrate 50 and is directly connected to the local wiring layer 161, and an upper end thereof having metal members 153a to 153d. ) through which it is formed to be connected to the upper electrode 82. The metal member 153a is formed as an outgoing wiring layer of the through electrode 153, and the metal members 153b and 153c are formed as contacts. In addition, the metal member 153d is formed as a wiring layer connecting the metal members 153b and 153c, respectively. The through electrode 153 and the metal members 153a to 153d are formed of a metal material such as W, Cu, Al, Ti, Co, Hf, or Ta. Further, in the example of FIG. 18 , similar to the through electrode 58 of FIG. 17 , the tip of the through electrode 153 may be formed in a tapered shape.

As a result, a predetermined voltage is applied to the upper electrode 82 provided in common to each pixel 20 .

In addition, voltage is always applied to the upper electrode 82, and reliability such as withstand voltage can be maintained by forming the gate electrode 151G on the isolation layer 152. In addition, during the process, the gate electrode 151G is in a floating state and there is a risk of receiving charge-up damage during formation of the through electrode 153 and the metal members 153a to 153d. By forming on (152), this can also be alleviated.

<5. Manufacturing process of a configuration in which voltage is applied to the upper electrode>

Next, with reference to FIGS. 19 to 23 , a manufacturing process of a configuration in which a voltage is applied to the upper electrode 82 will be described.

Steps from forming the multilayer wiring layer 60 to forming the through electrode 153 on the surface 50A side of the semiconductor substrate 50 are basically the same as the step of forming the pixel 20. Because of this, their descriptions are omitted.

After the through electrode 58 is formed, as shown in FIG. 19 , in order to form the lead wiring layer 153a on the top of the through electrode 153, after patterning by photolithography, dry etching or the like is unnecessary. The conductive film is removed.

Subsequently, as shown in FIG. 20, after the insulating film 70 is formed, the lower electrode 81, the organic photoelectric conversion layer 83, and the upper electrode 82 are formed, and on the upper electrode 82, A passivation film 91a is formed.

Next, as shown in Fig. 21, a contact hole CH2 for connecting the local wiring layer 61 and the upper electrode 82 is formed by patterning and dry etching.

Then, as shown in FIG. 22, contacts 153b and 153c are formed by filling the contact hole CH2 with metal. For example, a Ti film for work function adjustment or the like is formed by a method such as PVD, and a barrier metal such as TiN or W is embedded by a method such as CVD or PVD. Then, in order to form the wiring layer 153d, after patterning by photolithography, an unnecessary conductive film is removed by a method such as dry etching.

Then, as shown in Fig. 23, a passivation film 91 is formed on the wiring layer 153d.

Through the above steps, a configuration for applying a voltage to the upper electrode 82 is formed.

According to the above steps, the through electrode 153 is formed so that one end of the through electrode 153 penetrates the surface 50A of the semiconductor substrate 50 and is directly connected to the local wiring layer 161 as an etching stopper. In this way, it is possible to avoid misalignment with the contact and an increase in contact resistance, and even in a configuration in which a voltage is applied to the upper electrode, it is possible to reliably miniaturize the through electrode.

Although description is omitted in the configuration of FIG. 2 and the like, as shown in FIG. 24, there is a negative gap between the through hole in which the through electrode 58 is formed and the insulating film 70 (70a) embedded in the through hole. A fixed charge film 171 having a fixed charge is formed. Thereby, dark current can be reduced.

In this configuration, when the bottom of the through hole is opened by etching, the fixed charge film 171 is exposed on the side surface of the opening. In this state, when the through electrode 58 is formed by embedding a conductive film or the like, the through electrode 58 and the fixed charge film 171 come into contact.

Compared with the insulating film 70, the fixed charge film 171 has lower insulation resistance and lower process resistance. Therefore, due to insufficient insulation resistance of the fixed charge film 171, a short circuit failure may occur between the through electrode 58 and the fixed charge film 171, as indicated by the positive arrow #1 in FIG. 24 . There is a possibility.

Further, due to the lack of process resistance of the fixed charge film 171, as shown in FIG. 25, the contact portion of the fixed charge film 171 with the through electrode 58 recedes, and the conductive film enters and is discarded. This may cause a short circuit defect between the semiconductor substrate 50 and the through electrode 58, as shown by the positive arrow #2 in FIG. 25 .

Therefore, a configuration in which the through electrode 58 and the fixed charge film 171 do not contact each other will be described below.

<6. Third Embodiment>

26 is a cross-sectional view of a solid-state imaging device 10 according to a third embodiment of the present technology.

26 shows a cross-sectional configuration around the through electrode 58 described above.

26, in the through hole where the through electrode 58 is formed, an insulating film 70 is formed over the fixed charge film 171, and an insulating film 172 is formed over the insulating film 70. it is encapsulated The insulating film 172 is formed so that the through-electrode 58 and the fixed charge film 171 do not come into contact with each other on the side surface of the opening where a part of the bottom part of the through-hole on the surface 50A side of the semiconductor substrate 50 is opened. has been The insulating film 172 has higher insulating properties than the fixed charge film 171 .

In the example of FIG. 26 , the insulating film 172 is embedded in the through hole so as to contact the local wiring layer 61 (hereinafter simply referred to as the wiring layer 61) together with the through electrode 58.

<7. Manufacturing process of a configuration in which the through electrode and the fixed charge film do not contact>

(Example 1)

Next, with reference to FIGS. 27 to 33, an example of a manufacturing process in which the through electrode 58 and the fixed charge film 171 do not contact each other will be described.

Fig. 27 shows the same state as Fig. 10 described above. In the step of FIG. 27 , in the state where the multilayer wiring layer 60 is formed on the front surface 50A side (lower side in the figure) of the semiconductor substrate 50, from the back surface 50B side (upper side in the figure) of the semiconductor substrate 50 , a through hole 181 is formed.

The multilayer wiring layer 60 is formed by providing wiring layers 61 and 62 between layers of an insulating film made of SiO2, SiN, SiOC, SiON, or the like. The wiring layers 61 and 62 are formed of Cu, W, Al, or the like, and Ti, TiN, Ta, TaN, Ru, Co, Zr, or the like is used as the barrier metal.

The through hole 181 is formed by processing Si (semiconductor substrate 50) by lithography and plasma etching. Etching here is performed so as to stop in the insulating film of the multilayer wiring layer 60 . In this embodiment, the thickness of the semiconductor substrate 50 is, for example, 1 to 50 μm, and the diameter of the through hole 181 is, for example, 100 nm to 1 μm. In addition, the aspect ratio of etching shall exceed 5, for example.

After the through hole 181 is formed, as shown in FIG. 28 , a fixed charge film 171 is formed in the through hole 181 by a method such as ALD. The fixed charge film 171 is formed such that the film thickness is smaller than 50 nm, for example.

As the material of the fixed charge film 171, hafnium oxide, aluminum oxide, zirconium oxide,

Tantalum oxide, titanium oxide, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide etc. are used. Alternatively, as the fixed charge film 171, an aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film may be formed.

Then, as shown in FIG. 29, an insulating film 70 is formed in the through hole 181 where the fixed charge film 171 is formed. The insulating film 70 is formed by forming a film of SiO2, SiN, SiOC, or the like by ALD or CVD. The inner diameter of the through hole 181 after the insulating film 70 is formed is about 30 to 500 nm, for example.

After the insulating film 70 is formed, the insulating film 70 at the bottom of the through hole 181 (on the front surface 50A side of the semiconductor substrate 50), the fixed charge film 171, and the multilayer are formed by plasma etching. By processing the insulating film of the wiring layer 60, the through hole 181 is opened extending to the wiring layer 61 as shown in FIG. 30 .

Examples of etching gases used in plasma etching include gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5HF7, CH4, C2H4, He, Ar, O2, CO, and N2.

After the through hole 181 is opened to the wiring layer 61, etching residues and polymers are removed by ashing or wet etching. In ashing, for example, gases such as O2, H2, and N2 are converted into plasma and used.

After that, as shown in FIG. 31 , an insulating film 172 is formed in the through hole 181 opened up to the wiring layer 61 . The insulating film 172 is formed by forming a film of SiO2, SiN, SiOC, or the like by an ALD technique. The insulating film 172 is formed such that the film thickness is, for example, 5 nm or more.

After the insulating film 172 is formed, the insulating film 172 at the bottom of the through hole 181 (on the front surface 50A side of the semiconductor substrate 50) is processed by plasma etching, as shown in FIG. 32 . , the through hole 181 reaches the wiring layer 61 again. Here too, the same etching gas as in the process of FIG. 29 is used.

After the through hole 181 reaches the wiring layer 61, etching residues and polymers are removed by ashing or wet etching.

Thereafter, a barrier metal is formed in the through hole 181 by a method such as CVD, PVD, or ALD, and then a conductive film is formed. As the barrier metal, Ti, TiN, Ta, TaN, Ru, Co, Zr or the like is used, and the conductive film is formed by Cu plating. As the conductive film, W or Al may be formed by a method such as CVD, PVD, or ALD. As a result, as shown in FIG. 33 , a through electrode 58 is formed in the through hole 181 .

According to the above process, since the insulating film 172 is formed so that the through electrode 58 and the fixed charge film 171 do not come into contact, the insulation resistance (breakdown voltage) of the through electrode 58 can be increased, and the through electrode Short circuit defects between (58) and the fixed charge film 171 can be suppressed.

In addition, since the fixed charge film 171 can be selected without considering the insulation resistance of the fixed charge film 171, a high noise reduction effect can be obtained.

In addition, since the inner diameter of the through hole 181 can be made smaller than 1 μm by performing the film formation of the insulating film twice, as a result, the through electrode 58 can be miniaturized.

(Example 2)

In the step of FIG. 30 described above, when opening the through hole 181 to the wiring layer 61, etching using, for example, dilute hydrofluoric acid cleaning is performed, as shown in FIG. The charge film 171 retreats by being etched in the lateral direction, and a groove 181e is formed.

Then, as shown in FIG. 35, an insulating film 172 is formed by an ALD method in the through hole 181 that opens up to the wiring layer 61, so that the insulating film 172 is also formed in the groove 181e. .

After the insulating film 172 is formed, as shown in FIG. 36 , the through hole 181 reaches the wiring layer 61 by processing the insulating film 172 at the bottom of the through hole 181 by plasma etching. .

Thereafter, a barrier metal is formed in the through hole 181, and then a conductive film is formed, so that the through electrode 58 is formed in the through hole 181 as shown in FIG. 37 .

According to the above steps, even when the contact portion of the fixed charge film 171 with the through electrode 58 recedes due to insufficient process resistance of the fixed charge film 171, the insulating film 172 retains the retracted portion. It is formed to fill. Accordingly, a short circuit defect between the semiconductor substrate 50 and the through electrode 58 due to insufficient process resistance of the fixed charge film 171 can be suppressed.

In addition, since the fixed charge film 171 can be selected without considering the process resistance of the fixed charge film 171, a high noise reduction effect can be obtained.

(Example 3)

In the step of FIG. 30 described above, the through hole 181 is opened to reach the wiring layer 61 by plasma etching, but as shown in FIG. 38 , the process is stopped before reaching the wiring layer 61. You can do it.

After that, as shown in FIG. 39 , an insulating film 172 is formed in the through hole 181 opened to the middle of the multilayer wiring layer 60 .

After the insulating film 172 is formed, as shown in FIG. 40 , the through hole 181 reaches the wiring layer 61 by processing the insulating film 172 at the bottom of the through hole 181 by plasma etching. .

Thereafter, a barrier metal is formed in the through hole 181, and then a conductive film is formed, so that a through electrode 58 is formed in the through hole 181 as shown in FIG. 41 .

According to the above process, charging damage at the time of exposure of the wiring layer 61 by plasma etching can be reduced, and the possibility that wiring formation is hindered by a metal-containing reaction product can be reduced.

(Example 4)

After the process of FIG. 28 described above, in the process of FIG. 29 , an insulating film 70 was formed in the through hole 181 where the fixed charge film 171 was formed. Without being limited to this, after the fixed charge film 171 is formed in the through hole 181 (step in FIG. 28 ), as shown in FIG. 42 , the bottom of the through hole 181 is formed by plasma etching. The fixed charge film 171 may be removed.

After that, as shown in FIG. 43, an insulating film 70 is formed in the through hole 181 from which the fixed charge film 171 at the bottom is removed.

After the insulating film 70 is formed, the insulating film 70 at the bottom of the through hole 181 and the insulating film of the multilayer wiring layer 60 are processed by plasma etching, so that the through hole 181 is formed as shown in FIG. ) is opened up to the wiring layer 61.

Thereafter, a barrier metal is formed in the through hole 181, and then a conductive film is formed, so that a through electrode 58 is formed in the through hole 181 as shown in FIG. 45 .

That is, in the insulating film 70, the through electrode 58 and the fixed charge film 171 do not contact at the side surface of the opening portion of the through hole 181 at the bottom surface 50A side of the semiconductor substrate 50 is opened. It is shielded to prevent

Although the above process is limited to the case where the charge-fixed film 171 has process resistance, the process is shortened without forming the insulating film 172 so that the through electrode 58 and the fixed charge film 171 come into contact. It is possible to realize a configuration that does not

(Example 5)

In the above, the structure in which the through electrode 58 contacts the wiring layer in the multilayer wiring layer 60 has been described, but as shown in FIG. 46 , the through electrode 58 contacts the wiring layer in the multilayer wiring layer 60. You may make it take the structure which does not do it.

In this case, it is not necessary to process the insulating film 172 at the bottom of the through hole 181 in the process of FIG. 32 described above.

In addition, the structure of this embodiment is not limited to the through electrode, but the overall structure in which a conductive film is embedded in Si (semiconductor substrate), noise generated on the surface of Si is suppressed, and different voltages are applied between the conductive film and Si. can be applied to

Further, the pattern of the conductive film is not limited to a circular shape like the through electrode 58 shown in the top view of FIG. 47, for example, and a trench may be formed. For example, as shown in FIG. 48 , the pattern of the conductive film may have a light-shielding structure 191 that blocks light between pixels 20 each other.

By the way, in the embodiment described above, the through electrode is formed on the back surface 50B side of the semiconductor substrate 50, but it is also possible to form it on the front surface 50A side of the semiconductor substrate 50.

Therefore, below, a configuration in which the through electrode is formed from the front surface 50A side of the semiconductor substrate 50 will be described.

<8. Fourth Embodiment>

49 is a cross-sectional view of a solid-state imaging device 10 according to a fourth embodiment of the present technology.

49 shows a cross-sectional configuration around the through electrode.

Also in the example of FIG. 49 , the multilayer wiring layer 60 provided with the wiring layers 261 and 262 is formed on the front surface 50A side of the semiconductor substrate 50, and on the back surface 50B side serving as the light-receiving surface of the semiconductor substrate 50, , an organic photoelectric conversion unit not shown is formed.

An insulating film 270 is formed between the front surface 50A of the semiconductor substrate 50 and the multilayer wiring layer 60, and the insulating film 270 is also provided on the back surface 50B side of the semiconductor substrate 50 via a fixed charge film 282. ) is formed.

In the semiconductor substrate 50, a through electrode 253 is connected to the wiring layer 261 via a contact 265 on the surface 50A of the semiconductor substrate 50 at its lower end, and the metal electrode 283 at its upper end. ) is formed to be connected to. The metal electrode 283 is connected to an organic photoelectric conversion unit (not shown).

The insulating film 270 is also embedded in the through hole where the through electrode 253 is formed. A P-type diffusion layer 281 is formed on the outer periphery of the through hole in which the insulating film 270 is embedded.

Further, an element isolation portion 252 having an STI structure is formed in a region where the through hole is formed on the surface 50A side of the semiconductor substrate 50 .

<9. Manufacturing process of forming a through electrode from the substrate surface>

Next, with reference to FIGS. 50 to 61 , a manufacturing process of forming the through electrode 253 from the surface 50A of the semiconductor substrate 50 will be described.

First, as shown in FIG. 50 , an element isolation portion 252 is formed on the surface 50A side of the semiconductor substrate 50 .

Next, as shown in FIG. 51, the resist 291 is patterned according to the position where the through electrode 253 is formed. After that, as shown in FIG. 52, through-holes 292 are formed by processing Si (semiconductor substrate 50) by a method such as dry etching.

After the resist 291 is removed, an insulating film 270 is formed by filling the through hole 292 with an oxide film such as a BSG film, for example, as shown in FIG. 53 .

In this state, by annealing the side surface of the through hole 292, as shown in FIG. 54, a P-type diffusion layer 281 is formed around the through hole 292 (on the side of the semiconductor substrate 50). is formed

Thereafter, an oxide film such as a TEOS film is again embedded in the through hole 292, and a conductive film such as Poly Si or Doped Amorphous Silicon is embedded by a method such as ALD or CVD. As a result, as shown in FIG. 55, through electrodes 253 are formed.

Then, after patterning by photolithography, an unnecessary conductive film on the surface 50A of the semiconductor substrate 50 is removed by a method such as dry etching, as shown in FIG. 56 .

Thereafter, as shown in FIG. 57 , a contact 265 connected to the through electrode 253 and a wiring layer 261 are formed on the surface 50A side of the semiconductor substrate 50 . Further, on the surface 50A side of the semiconductor substrate 50, an insulating layer and a metal layer such as the wiring layer 262 are laminated, thereby forming a multilayer wiring layer 60 as shown in FIG. 58 .

On the other hand, on the back surface 50B side of the semiconductor substrate 50, as shown in FIG. 59, Si (semiconductor substrate 50) is polished so that one end of the through electrode 253 is exposed.

60, after a fixed charge film 282 is formed on the back surface 50B of the semiconductor substrate 50, an insulating film 270 such as an oxide film is formed.

Then, as shown in FIG. 61 , a metal electrode 283 is formed on the through electrode 253 on the back surface 50B side of the semiconductor substrate 50 .

In the above manner, the through electrode 253 is formed.

According to the above steps, it becomes possible to form the through electrode not from the back side of the semiconductor substrate but from the front side.

In the above, an example in which the through-electrode of the present technology is applied to a solid-state imaging device that performs light spectroscopy in the vertical direction has been described, but the first and second surfaces of the semiconductor substrate are not limited thereto. It can be applied to a configuration provided with a through electrode. Further, the embodiments described above may be employed in combination with each other.

In addition, this technology is not limited to application to a solid-state imaging device, and is applicable also to an imaging device. Here, the imaging device refers to a camera system such as a digital still camera or a digital video camera, or an electronic device having an imaging function such as a mobile phone. Further, in some cases, a modular form mounted on an electronic device, that is, a camera module is used as an imaging device.

<10. Configuration example of electronic device>

Then, referring to Fig. 62, a configuration example of an electronic device to which the present technology is applied will be described.

An electronic device 300 shown in FIG. 62 includes an optical lens 301, a shutter device 302, a solid-state imaging device 303, a drive circuit 304, and a signal processing circuit 305. 62 shows an embodiment in the case where the above-described solid-state imaging device 10 of the present technology is provided in an electronic device (digital still camera) as the solid-state imaging device 303 .

The optical lens 301 forms an image of image light (incident light) from a subject on the imaging surface of the solid-state imaging device 303 . As a result, signal charge is accumulated in the solid-state imaging device 303 for a certain period of time. The shutter device 302 controls the light irradiation period and light blocking period for the solid-state imaging device 303 .

The drive circuit 304 supplies drive signals to the shutter device 302 and the solid-state imaging device 303 . The drive signal supplied to the shutter device 302 is a signal for controlling the shutter operation of the shutter device 302 . The driving signal supplied to the solid-state imaging device 303 is a signal for controlling the signal transmission operation of the solid-state imaging device 303 . The solid-state imaging device 303 performs signal transmission by means of a driving signal (timing signal) supplied from the driving circuit 304 . The signal processing circuit 305 performs various signal processing on the signal output from the solid-state imaging device 303 . A video signal subjected to signal processing is stored in a storage medium such as a memory or output to a monitor.

<11. Example of image sensor use>

Finally, a use case of an image sensor to which the present technology is applied will be described.

63 is a diagram showing a usage example of the image sensor described above.

The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.

Devices that capture images provided for viewing, such as digital cameras and mobile devices with camera functions

In-vehicle sensors that take pictures of the front, back, surroundings, and inside of the car, surveillance cameras that monitor driving vehicles and roads, and distances between vehicles for safe driving such as automatic stop and recognition of the driver's condition. Devices provided for traffic, such as distance measuring sensors that make measurements

Devices provided to home appliances such as TVs, refrigerators, air conditioners, etc., in order to photograph a user's gesture and operate the device according to the gesture

Devices provided for medical or healthcare purposes, such as an endoscope or a device for imaging blood vessels by receiving infrared light

・Devices provided for security purposes, such as surveillance cameras for crime prevention purposes and cameras for person authentication purposes

Devices provided for beauty purposes, such as a skin measuring device that takes pictures of the skin or a microscope that takes pictures of the scalp

Devices provided for sports, such as action cameras and wearable cameras for sports use, etc.

Devices provided for agricultural use, such as cameras for monitoring the conditions of fields or crops

In addition, the embodiment of the present technology is not limited to the above-described embodiment, and various changes are possible within a range not departing from the gist of the present technology.

In addition, the present technology can take the following configuration.

(One)

a wiring layer formed on the first surface side of the semiconductor substrate;

a photoelectric conversion element formed on the second surface side of the semiconductor substrate;

A solid-state imaging device comprising a through-electrode formed so that one end penetrates the first surface and is connected to the wiring layer, and the other end is connected to the photoelectric conversion element.

(2)

the through electrode is formed for each pixel, and the other end of the through electrode is connected to an electrode provided for each pixel in the photoelectric conversion element;

The solid-state imaging device according to (1), wherein the wiring layer is formed for each pixel and is connected to a floating diffusion and an amplifying transistor.

(3)

The solid-state imaging device according to (1) or (2), wherein the wiring layer is formed closer to the second surface than the other wiring layers.

(4)

The solid-state imaging device according to any one of (1) to (3), wherein the wiring layer is formed of W or Ti.

(5)

The solid-state imaging device according to (2), wherein at least one photoelectric conversion unit is formed for each pixel in the semiconductor substrate.

(6)

The other end of the through electrode is connected to an electrode provided in common to each pixel in the photoelectric conversion element;

The solid-state imaging device according to (1), wherein the wiring layer is connected to a power supply wiring.

(7)

The solid-state imaging device according to (6), wherein the wiring layer is connected to the power supply wiring through a gate electrode.

(8)

The solid-state imaging device according to (7), wherein the gate electrode is formed on an element isolation film.

(9)

The solid-state imaging device according to (1), wherein the through electrode is formed of W, Cu, Al, Ti, Co, Hf, or Ta.

(10)

The solid-state imaging device according to (1), wherein a tip of the through electrode on the wiring layer side is formed in a tapered shape.

(11)

In the through hole where the through electrode is formed, an insulating film is formed over the fixed charge film,

The solid-state imaging device according to (1), wherein the insulating film is formed on the side surface of the opening portion on the first surface side of the through hole so that the through electrode and the fixed charge film do not contact each other.

(12)

In the through hole, a first insulating film is formed on the fixed charge film, and a second insulating film is formed over the opening of a part of the bottom portion of the through hole on the first surface side;

The solid-state imaging device according to (11), wherein the second insulating film is formed on the side surface of the opening so that the through electrode and the fixed charge film do not come into contact.

(13)

The solid-state imaging device according to (12), wherein the second insulating film has a higher insulating property than that of the fixed charge film.

(14)

The solid-state imaging device according to (11), wherein the fixed charge film is formed in the through hole, and the insulating film is formed on an open bottom of the through hole on the first surface side.

(16)

The method of manufacturing the solid-state imaging device according to (15), wherein the through-electrode is formed by using a Bosch process so that one end penetrates the first surface and is connected to the wiring layer.

(17)

The method of manufacturing a solid-state imaging device according to (15), wherein a high-concentration impurity region is formed in a region where the through electrode is to be formed in the semiconductor substrate.

(18)

The method of manufacturing a solid-state imaging device according to (15), wherein the through electrode is formed from the side of the second surface of the semiconductor substrate.

(19)

The method of manufacturing a solid-state imaging device according to (15), wherein the through electrode is formed from the side of the first surface of the semiconductor substrate.

(20)

forming a wiring layer on the first surface side of the semiconductor substrate;

forming a through electrode so that one end penetrates the first surface and is connected to the wiring layer;

and forming a photoelectric conversion element on the second surface side of the semiconductor substrate so that the other end of the through electrode is connected.

(21)

a wiring layer formed on the first surface side of the semiconductor substrate;

a photoelectric conversion element formed on the second surface side of the semiconductor substrate;

An electronic device comprising a solid-state imaging device having a through-electrode formed so that one end penetrates the first surface and is connected to the wiring layer, and the other end is connected to the photoelectric conversion element.

(22)

a semiconductor substrate having a first surface and a second surface opposite to the first surface;

a photoelectric conversion section on the first surface of the semiconductor substrate;

a multilayer wiring layer on the second side of the semiconductor substrate and including a local wiring layer;

and a through electrode extending between the photoelectric conversion unit and the multilayer wiring layer, and a second end thereof directly contacting the local wiring layer.

(23)

The imaging device according to (22), wherein the photoelectric converter includes a lower electrode, and a first end of the through electrode directly contacts the lower electrode.

(24)

The imaging device according to (23), wherein the semiconductor substrate includes a light incident surface on the first surface of the semiconductor substrate.

(25)

The image pickup described in (24) further comprising an interlayer insulating film between the local wiring layer separated from the front side of the semiconductor substrate by the interlayer insulating film and the front surface on the second surface of the semiconductor substrate. Device.

(26)

The imaging device according to (24), further including an insulating film between the lower electrode and the light incident surface of the semiconductor substrate.

(27)

The imaging device according to (22), wherein the through electrode is formed of metal.

(28)

The imaging device according to (22), wherein the through electrode is formed from at least one of Al, Ti, Co, Hf, Ta, Cu, and W.

(29)

The imaging device according to (23), wherein a width of the first end of the through electrode is larger than a width of the second end of the through electrode.

(30)

The imaging device according to (22), wherein the second end of the through electrode is tapered.

(31)

The imaging device according to (22), further comprising a plurality of pixels each including a first photodiode formed on the semiconductor substrate and a second photodiode formed on the semiconductor substrate.

(32)

a photoelectric conversion unit on the first side of the semiconductor substrate;

at least a first photodiode formed on the semiconductor substrate;

a multilayer wiring layer on the second side of the semiconductor substrate and including a local wiring layer;

An electronic device comprising a plurality of pixels, each including a through electrode extending between the photoelectric conversion unit and the multi-layer wiring layer, the second end of which directly contacts the local wiring layer.

(33)

The electronic device according to (32), wherein the photoelectric conversion unit includes a lower electrode, and a first end of the through electrode directly contacts the lower electrode.

(34)

The electronic device according to (32), wherein the through electrode is formed from at least one of Al, Ti, Co, Hf, Ta, Cu, and W.

(35)

The electronic device according to (33), wherein a width of the first end of the through electrode is larger than a width of the second end of the through electrode.

(36)

The electronic device according to (32), wherein the second end of the through electrode is tapered.

(37)

The electronic device according to (32), wherein each of the plurality of pixels further includes a second photodiode formed on the semiconductor substrate.

10: solid-state imaging device
20: pixels
50: semiconductor substrate
51, 52: inorganic photoelectric conversion unit
53: F.D.
54: transfer transistor
55: amplification transistor
55G: gate electrode
55s: element separation unit
56: reset transistor
56G: gate electrode
56s: element separation unit
57: etch stop layer
58: through electrode
60: multilayer wiring layer
61: local wiring layer
62, 63: wiring layer
70: insulating film
80: organic photoelectric conversion unit
81: lower electrode
82: upper electrode
83: organic photoelectric conversion layer
91: passivation film
92: on-chip lens
151: transistor
151G: gate electrode
152: element isolation film
153: through electrode,
153a: outgoing wiring layer
153b, 153c: contact
153d: wiring layer
161: local wiring layer
163: wiring layer
171: charge fixing film
172: insulating film
181: through hole
300: electronic devices
303 solid-state imaging device

Claims (16)

a semiconductor substrate having a first surface and a second surface opposite to the first surface;
a photoelectric conversion section on the first surface of the semiconductor substrate;
a multilayer wiring layer on the second side of the semiconductor substrate;
A penetration electrode extending between the photoelectric conversion unit and the multilayer wiring layer;
The through electrode is directly connected to wiring in the multilayer wiring layer between an amplifying transistor and a reset transistor;
In the through hole in which the through electrode is formed, a first insulating film is formed on the side surface of the through hole and the bottom on the side of the second surface, on which a fixed charge film is formed, and a part of the bottom part is opened. The insulating film of 2 is formed,
The imaging device according to claim 1, wherein the second insulating film is formed such that the fixed charge film exposed from the side surface of the opening of the bottom portion and the through electrode do not contact each other. According to claim 1,
The imaging device according to claim 1 , wherein the photoelectric converter includes a lower electrode, and a first end of the through electrode directly contacts the lower electrode. According to claim 2,
The imaging device according to claim 1, wherein the semiconductor substrate includes a light incident surface on the first surface of the semiconductor substrate. According to claim 3,
and an interlayer insulating film between a local wiring layer separated from a front side of the semiconductor substrate by an interlayer insulating film, and the front side on the second surface of the semiconductor substrate. According to claim 3,
and an insulating film between the lower electrode and the light incident surface of the semiconductor substrate. According to claim 1,
The imaging device according to claim 1, wherein the through electrode is formed of metal. According to claim 1,
The through electrode is formed from at least one of Al, Ti, Co, Hf, Ta, Cu and W. According to claim 2,
The imaging device according to claim 1 , wherein a width of the first end of the through electrode is larger than a width of a second end of the through electrode. According to claim 1,
The imaging device according to claim 1 , wherein the second end of the through electrode has a tapered shape. According to claim 1,
and a plurality of pixels each including a first photodiode formed on the semiconductor substrate and a second photodiode formed on the semiconductor substrate. contains a plurality of pixels,
Each of the plurality of pixels,
a photoelectric conversion unit on the first surface of the semiconductor substrate;
at least a first photodiode formed on the semiconductor substrate;
a multilayer wiring layer on the second side of the semiconductor substrate;
A penetration electrode extending between the photoelectric conversion unit and the multilayer wiring layer;
The through electrode is directly connected to wiring in the multilayer wiring layer between an amplifying transistor and a reset transistor;
In the through hole in which the through electrode is formed, a first insulating film is formed on the side surface of the through hole and the bottom on the side of the second surface, on which a fixed charge film is formed, and a part of the bottom part is opened. The insulating film of 2 is formed,
The electronic device according to claim 1, wherein the second insulating film is formed so that the fixed charge film exposed from the side surface of the opening of the bottom portion and the through electrode do not contact each other. According to claim 11,
The electronic device according to claim 1, wherein the photoelectric converter includes a lower electrode, and a first end of the through electrode directly contacts the lower electrode. According to claim 11,
The through electrode is formed of at least one of Al, Ti, Co, Hf, Ta, Cu and W. According to claim 12,
The electronic device according to claim 1, wherein a width of the first end of the through electrode is larger than a width of a second end of the through electrode. According to claim 11,
The electronic device characterized in that the second end of the through electrode has a tapered shape. According to claim 11,
Each of the plurality of pixels further includes a second photodiode formed on the semiconductor substrate.

Images