JP2018098495A - Solid-state imaging device, manufacturing method of the same, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely enable refinement of a through electrode.SOLUTION: A solid-state imaging device includes: a wiring layer formed on a first surface side of a semiconductor substrate; a photoelectric conversion element formed on a second surface side of the semiconductor substrate; and a through electrode having one end directly connected to wiring in a wiring layer and having the other end connected to the photoelectric conversion element. The present technology is applicable to, for example, a CMOS image sensor.SELECTED DRAWING: Figure 2

Description

  The present technology relates to a solid-state imaging device, a manufacturing method thereof, and an electronic device, and more particularly, to a solid-state imaging device capable of miniaturizing a through electrode, a manufacturing method thereof, and an electronic device.

  In recent years, pixel size reduction has been achieved in charge coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. However, in accordance with this, a decrease in sensitivity due to a decrease in photons incident on the unit pixel and a decrease in S / N occur.

  On the other hand, for example, a Bayer array using primary color filters is widely known as a pixel array in which red (R), green (G), and blue (B) pixels are arranged on a plane. However, in the Bayer array, G and B light does not pass through the color filter and are not used for photoelectric conversion in the R pixel, so that loss in sensitivity occurs or false color occurs due to interpolation processing between pixels. End up.

  On the other hand, a method is known in which three photoelectric conversion layers are stacked in the vertical direction to obtain color signals for three colors with one pixel. For example, a structure has been proposed in which G light is detected by a photoelectric conversion film provided on a Si substrate, and R and B light are detected by two photodiodes (PD) stacked in the Si substrate.

  In such a structure, it is necessary to transfer the charge generated in the photoelectric conversion film to a floating diffusion (FD) formed on the opposite surface of the Si substrate. On the other hand, for example, Patent Document 1 discloses a structure in which a through electrode is provided for each pixel between a front surface and a back surface of a semiconductor substrate and charges generated in the photoelectric conversion film are transferred to the FD.

JP 2015-38931 A

  However, in the structure disclosed in Patent Document 1, the through electrode cannot be miniaturized. Specifically, in the through electrode composed of Si, there is a limit to miniaturization in the manufacturing process. In addition, in the through electrode made of metal, misalignment with the contact connected on the front surface or the back surface of the semiconductor substrate may occur, and the contact resistance may increase.

  The present technology has been made in view of such a situation, and surely enables miniaturization of the through electrode.

  A solid-state imaging device according to an embodiment of the present technology includes a wiring layer formed on a first surface side of a semiconductor substrate, a photoelectric conversion element formed on a second surface side of the semiconductor substrate, and one end extending from the first surface. A through-electrode formed so as to penetrate through and connect to the wiring layer, and to connect the other end to the photoelectric conversion element.

  The through electrode is formed for each pixel, the other end of the through electrode is connected to an electrode provided for each pixel in the photoelectric conversion element, and the wiring layer is formed for each pixel, and the floating diffusion and amplification It can be connected to a transistor.

  The wiring layer may be formed closer to the second surface than the other wiring layers.

  The other end of the through electrode may be connected to an electrode provided in common for each pixel in the photoelectric conversion element, and the wiring layer may be connected to a power supply wiring.

  In the method for manufacturing a solid-state imaging device according to the present technology, a wiring layer is formed on a first surface side of a semiconductor substrate, and a through electrode is provided so that one end penetrates the first surface and is connected to the wiring layer. And forming a photoelectric conversion element so that the other end of the through electrode is connected to the second surface side of the semiconductor substrate.

  An electronic device of the present technology includes a wiring layer formed on a first surface side of a semiconductor substrate, a photoelectric conversion element formed on a second surface side of the semiconductor substrate, and one end penetrating the first surface. A solid-state imaging device having a through electrode connected to the wiring layer and having the other end connected to the photoelectric conversion element.

  In the present technology, the wiring layer is formed on the first surface side of the semiconductor substrate, the through electrode is formed so that one end penetrates the first surface and is connected to the wiring layer, and photoelectric conversion is performed. The element is formed so that the other end of the through electrode is connected to the second surface side of the semiconductor substrate.

  According to the present technology, the through electrode can be surely miniaturized. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a block diagram showing an example of composition of a solid imaging device of this art. It is sectional drawing which shows the structural example of the solid-state imaging device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the manufacturing process of a pixel. It is sectional drawing which shows the structural example of the solid-state imaging device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing process of the structure which applies a voltage to an upper electrode. It is sectional drawing which shows the manufacturing process of the structure which applies a voltage to an upper electrode. It is sectional drawing which shows the manufacturing process of the structure which applies a voltage to an upper electrode. It is sectional drawing which shows the manufacturing process of the structure which applies a voltage to an upper electrode. It is sectional drawing which shows the manufacturing process of the structure which applies a voltage to an upper electrode. It is a figure explaining the insulation tolerance of a fixed charge film. It is a figure explaining the process tolerance of a fixed charge film. It is sectional drawing which shows the structural example of the solid-state imaging device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the manufacturing process of the structure where a penetration electrode and a fixed charge film | membrane do not contact. It is sectional drawing which shows the structural example which a penetration electrode and a wiring layer do not contact. It is a figure which shows the example of the pattern of an electrically conductive film. It is a figure which shows the example of the pattern of an electrically conductive film. It is sectional drawing which shows the structural example of the solid-state imaging device which concerns on 4th Embodiment. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is sectional drawing which shows the manufacturing process which forms a penetration electrode from the board | substrate surface. It is a block diagram showing an example of composition of electronic equipment of this art. It is a figure which shows the usage example which uses an image sensor.

  Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The description will be given in the following order.

1. 1. Configuration example of solid-state imaging device 1. First embodiment 3. Pixel manufacturing process Second Embodiment 5. 5. Manufacturing process with a configuration in which a voltage is applied to the upper electrode. Third embodiment 7. Manufacturing process in which the through electrode and the fixed charge film are not in contact with each other. Fourth embodiment 9. 9. Manufacturing process for forming through electrode from substrate surface Configuration example of electronic device 11. Examples of using image sensors

<1. Configuration Example of Solid-State Imaging Device>
FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to the present technology.

  The solid-state imaging device 10 is configured as a CMOS image sensor. The solid-state imaging device 10 includes a pixel region (pixel array) 21 in which a plurality of pixels 20 are regularly arranged in a two-dimensional array on a semiconductor substrate (for example, Si substrate) (not shown), and a peripheral circuit unit.

  The pixel 20 includes a photoelectric conversion unit (for example, a photodiode) and a plurality of pixel transistors (MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, the plurality of pixel transistors can be configured by four transistors by adding selection transistors. Since the equivalent circuit of the unit pixel is the same as a general one, detailed description is omitted.

  In addition, the pixel 20 can be configured as one unit pixel or a shared pixel structure. This pixel sharing structure is a structure in which a plurality of photodiodes share transistors other than the floating diffusion and the transfer transistor.

  Although detailed description will be given later, the pixel 20 is configured by stacking photoelectric conversion units.

  The peripheral circuit unit includes a vertical drive circuit 22, a column signal processing circuit 23, a horizontal drive circuit 24, an output circuit 25, and a control circuit 26.

  The control circuit 26 receives an input clock and data for instructing an operation mode and outputs data such as internal information of the solid-state imaging device 10. In addition, the control circuit 26 is a clock signal or control signal that serves as a reference for operations of the vertical drive circuit 22, the column signal processing circuit 23, the horizontal drive circuit 24, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. Is generated. The control circuit 26 inputs these signals to the vertical drive circuit 22, the column signal processing circuit 23, the horizontal drive circuit 24, and the like.

  The vertical drive circuit 22 is configured by a shift register, for example. The vertical drive circuit 22 selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixels in units of rows. That is, the vertical drive circuit 22 selectively scans each pixel 20 in the pixel region 21 in the vertical direction sequentially in units of rows. Then, the vertical drive circuit 22 supplies the column signal processing circuit 23 with a pixel signal based on the signal charge generated according to the amount of received light in the photoelectric conversion unit of each pixel 20 through the vertical signal line 27.

  The column signal processing circuit 23 is disposed, for example, for each column of the pixels 20. The column signal processing circuit 23 performs signal processing such as noise removal for each pixel column on the signal output from the pixels 20 for one row. Specifically, the column signal processing circuit 23 performs signal processing such as CDS (Correlated Double Sampling), signal amplification, and A / D (Analog / Digital) conversion for removing fixed pattern noise unique to the pixel 20. . At the output stage of the column signal processing circuit 23, a horizontal selection switch (not shown) is connected between the horizontal signal line 28 and provided.

  The horizontal drive circuit 24 is configured by a shift register, for example. The horizontal driving circuit 24 sequentially selects the column signal processing circuits 23 by sequentially outputting horizontal scanning pulses, and outputs the pixel signals from the respective column signal processing circuits 23 to the horizontal signal line 28.

  The output circuit 25 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 23 through the horizontal signal line 28. For example, the output circuit 25 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.

  The input / output terminal 29 exchanges signals with the outside.

<2. First Embodiment>
FIG. 2 is a cross-sectional view of the solid-state imaging device 10 according to the first embodiment of the present technology.

  FIG. 2 shows a cross section of the pixel region 21 and the peripheral circuit unit 31 constituting the solid-state imaging device 10.

  In the solid-state imaging device 10, a multilayer wiring layer 60 is formed on the surface 50A (first surface) side of the semiconductor substrate 50 made of Si or the like. In addition, an organic photoelectric conversion unit 80 as a photoelectric conversion element is formed on the back surface 50B (second surface) side, which is a light receiving surface of the semiconductor substrate 50, via an insulating film 70.

  In the pixel region 21, each pixel 20 includes one organic photoelectric conversion unit 80 that selectively detects light in different wavelength ranges and performs photoelectric conversion, and two inorganic photoelectric conversion units 51 and 52 (PD1, PD2). And have a stacked structure in which they are stacked vertically. The inorganic photoelectric conversion portions 51 and 52 are formed so as to be embedded in the semiconductor substrate 50.

  The organic photoelectric conversion unit 80 includes, for example, two or more types of organic semiconductor materials. The organic photoelectric conversion unit 80 is composed of an organic photoelectric conversion element that generates an electron-hole pair by absorbing light in a selective wavelength range, that is, green light here, using an organic semiconductor. The organic photoelectric conversion unit 80 includes an organic photoelectric conversion layer (organic) between a lower electrode 81 provided for each pixel 20 for extracting signal charges and an upper electrode 82 provided in common for each pixel 20. (Semiconductor layer) 83 is sandwiched.

  The lower electrode 81 is provided in a region that faces the light receiving surfaces of the inorganic photoelectric conversion portions 51 and 52 formed in the semiconductor substrate 50 and covers these light receiving surfaces. The lower electrode 81 is made of a light-transmitting conductive film, for example, indium tin oxide (ITO). In addition to indium tin oxide, as a constituent material of the lower electrode 81, a tin oxide (SnO2) material added with a dopant or a zinc oxide material obtained by adding a dopant to aluminum zinc oxide (ZnO) is used. Also good. Examples of zinc oxide-based materials include aluminum zinc oxide (AZO) added with aluminum (Al) as a dopant, gallium zinc oxide (GZO) added with gallium (Ga), and indium zinc oxide added with indium (In). (IZO). In addition, CuI, InSbO4, ZnMgO, CuInO2, MgIN2O4, CdO, ZnSnO3, etc. may be used. Since signal charges (electrons) obtained from the organic photoelectric conversion layer 83 are extracted from the lower electrode 81, the lower electrode 81 is formed separately for each pixel 20.

  The organic photoelectric conversion layer 83 includes, for example, three types of first organic semiconductor material, second organic semiconductor material, and / or third organic semiconductor material. Any one of these three types of organic semiconductor materials is one or both of an organic p-type semiconductor and an organic n-type semiconductor, and photoelectrically converts light in a selective wavelength range, while light in other wavelength ranges. Permeate. Specifically, the organic photoelectric conversion layer 83 has a maximum absorption wavelength in a range of 450 nm to 650 nm as a wavelength of green (G), for example.

  Other layers (not shown) may be provided between the organic photoelectric conversion layer 83 and the lower electrode 81 and between the organic photoelectric conversion layer 83 and the upper electrode 82. For example, an undercoat film, a hole transport layer, an electron blocking film, an organic photoelectric conversion layer 83, a hole blocking film, a buffer film, an electron transport layer, and a work function adjusting film are laminated in order from the lower electrode 81 side. Also good.

  The upper electrode 82 is composed of a conductive film having light transmission similar to that of the lower electrode 81. The upper electrode 82 is formed as a common electrode for each pixel 20, but may be separated for each pixel 20. The thickness of the upper electrode 82 is, for example, 10 nm to 200 nm.

  The inorganic photoelectric conversion units 51 and 52 are PDs (photodiodes) each having a pn junction, and are formed in the order of the inorganic photoelectric conversion units 51 and 52 from the back surface 50 </ b> B side on the optical path in the semiconductor substrate 50. The inorganic photoelectric conversion unit 51 selectively detects blue light and accumulates signal charges corresponding to blue. For example, the inorganic photoelectric conversion unit 51 is formed in a selective region along the back surface 50 </ b> B of the semiconductor substrate 50. The inorganic photoelectric conversion unit 52 selectively detects red light and accumulates signal charges corresponding to red. The inorganic photoelectric conversion part 52 is formed in the area | region (lower surface 50A side) lower than the inorganic photoelectric conversion part 51, for example. For example, blue (B) is a color corresponding to a wavelength range of 450 nm to 495 nm, red (R) is a color corresponding to a wavelength range of 620 nm to 750 nm, for example, and the inorganic photoelectric conversion units 51 and 52 are respectively It is only necessary that light in a part or all of the wavelength range can be detected.

  As described above, the pixel 20 has a stacked structure in which the organic photoelectric conversion unit 80 and the two inorganic photoelectric conversion units 51 and 52 are stacked in the vertical direction, and the organic photoelectric conversion unit 80 transmits green light and inorganic light. The photoelectric conversion unit 51 absorbs (detects) blue light and the inorganic photoelectric conversion unit 52 absorbs (detects) red light and performs photoelectric conversion. Therefore, vertical spectroscopy (layer direction) is performed on one pixel, and red, green, Each color signal of blue can be acquired.

  For example, a floating diffusion (FD) 53, a transfer transistor 54, an amplification transistor 55, and a reset transistor 56 are provided on the surface 50A of the semiconductor substrate 50. Among these, the FD 53 and the gate electrode 55G of the amplification transistor 55 are connected to the local wiring layer 61 formed on the side closest to the surface 50A of the semiconductor substrate 50 among the wiring layers 61 to 63 forming the multilayer wiring layer 60. It is connected. The local wiring layer 61 is formed for each pixel 20. The gate electrode 56G of the reset transistor 56 is connected to the wiring layer 63 via the contact 65. The amplification transistor 55 is separated from other regions by an element isolation portion 55s having an STI (Shallow Trench Isolation) structure, and the reset transistor 56 is isolated from other regions by the element isolation portion 56s.

  Further, an etch stop layer 57 made of a SiN film or the like is formed on the surface 50A of the semiconductor substrate 50.

  In each pixel 20, the through electrode 58 is formed in the semiconductor substrate 50 so that the lower end thereof is directly connected to the local wiring layer 61 through the surface 50 </ b> A of the semiconductor substrate 50 and the upper end is connected to the lower electrode 81. Is formed. In particular, on the surface 50 </ b> A side of the semiconductor substrate 50, the through electrode 58 is formed so as to penetrate between the element isolation part 55 s of the amplification transistor 55 and the element isolation part 56 s of the reset transistor 56. The through electrode 58 is formed of a metal material such as W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Co (cobalt), Hf (hafnium), or Ta (tantalum).

  As a result, in each pixel 20, charges generated in the organic photoelectric conversion unit 80 on the back surface 50 </ b> B side of the semiconductor substrate 50 are transferred to the FD 53 and the amplification transistor 55 on the front surface 50 </ b> A side of the semiconductor substrate 50 through the through electrode 58. Become so.

  In each pixel 20, a passivation film 91 is formed on the upper electrode 82, and an on-chip lens 92 is formed on the passivation film 91.

<3. Pixel manufacturing process>
Next, a manufacturing process of the pixel 20 will be described with reference to FIGS.

  First, FIG. 3 shows that each of the transistors 54 to 56 is formed by ion implantation or the like on the surface 50A side of the semiconductor substrate 50 on which the inorganic photoelectric conversion portions 51 and 52 and the FD 53 are formed, an etch stop layer 57, and an interlayer insulating film 101a is formed. The etch stop layer 57 is formed by forming a SiN film or the like by a technique such as LP-CVD (Low Pressure-Chemical Vapor Deposition). The interlayer insulating film 101a is formed by depositing an oxide film or the like by a method such as plasma CVD and planarizing the surface by a method such as CMP (Chemical Mechanical Polishing). A high concentration impurity region (P ++ region) may be formed in the formation region 50 i of the through electrode 58 in the semiconductor substrate 50. Thereby, the damage which arises in the case of formation of the penetration electrode 58 can be reduced, and as a result, a dark current can be reduced.

  Next, as shown in FIG. 4, a contact hole CH1 for connecting the local wiring layer 61 and the semiconductor substrate 50 (FD 53 and amplification transistor 55) is formed by patterning and dry etching. Further, a trench TR1 for the local wiring layer 61 is formed by patterning and dry etching.

  After that, as shown in FIG. 5, the contact and local wiring layer 61 are formed by burying metal in the contact hole CH1 and the trench TR1. For example, a work function adjusting Ti film or the like is formed by a method such as PVD (Physical Vapor Deposition), and a barrier metal TiN or W is embedded by a method such as CVD. Further, the unnecessary metal film on the surface is removed by a technique such as CMP.

  As described above, the local wiring layer 61 connected to one end of the through electrode 58 is formed of a metal that hardly causes contamination, such as W or Ti.

  Subsequently, as shown in FIG. 6, an insulating film 101b is formed by forming an oxide film or the like on the local wiring layer 61 by a method such as plasma CVD.

  Next, as shown in FIG. 7, a contact hole for connecting the wiring layer 63 above the local wiring layer 61 and the semiconductor substrate 50 is formed by patterning and dry etching, and a metal is embedded to form the contact 65. Is formed. For example, a work function adjusting Ti film or the like is formed by a method such as PVD, and a barrier metal TiN or W is embedded by a method such as CVD. Further, the unnecessary metal film on the surface is removed by a technique such as CMP.

  Thereafter, as shown in FIG. 8, the multilayer wiring layer 60 is formed by forming the wiring layer 63.

  Then, a support substrate (not shown) or another semiconductor substrate is bonded to the surface 50A side (multilayer wiring layer 60) of the semiconductor substrate 50, and is turned upside down.

  On the back surface 50B side of the semiconductor substrate 50, first, as shown in FIG. 9, the resist 111 is patterned in accordance with the position where the through electrode 58 is formed. Thereafter, as shown in FIG. 10, through holes 112 are formed by processing Si (semiconductor substrate 50) by a technique such as dry etching. The etching here stops at the etch stop layer 57 formed on the surface 50A side of the semiconductor substrate 50. Further, even when a positional shift occurs in the patterning of the resist 111, the element isolation portions 55s and 56s formed on the surface 50A side of the semiconductor substrate 50 function as an etching stopper.

  After the resist 111 is removed, as shown in FIG. 11, the insulating film 70a is embedded by forming an oxide film or the like in the through hole 112 by a technique such as ALD (Atomic Layer Deposition).

  Thereafter, as shown in FIG. 12, the insulating film 70a, the etch stop layer 57, and the interlayer insulating film of the multilayer wiring layer 60 formed at the bottom of the through hole 112 are etched by a technique such as dry etching, The through hole 112 is opened to the local wiring layer 61. The etching here stops at the local wiring layer 61.

  Subsequently, as shown in FIG. 13, a conductive film is formed in the through hole 112 by embedding a barrier metal or the like by a technique such as ALD, and W or the like is buried by a technique such as CVD. Thereby, the through electrode 58 is formed. Then, in order to form an extraction wiring layer at the upper end of the through electrode 58, an unnecessary conductive film is removed by a technique such as dry etching after patterning by photolithography.

  Thereafter, as shown in FIG. 14, after the insulating film 70 is formed, the organic photoelectric conversion unit 80 is formed by forming the lower electrode 81, the organic photoelectric conversion layer 83, and the upper electrode 82.

  Then, as shown in FIG. 15, a passivation film 91 is formed on the upper electrode 82, and an on-chip lens 92 is formed on the passivation film 91.

  Through the above steps, the pixel 20 is formed.

  According to the above steps, the through electrode 58 is formed so that one end of the through electrode 58 penetrates the surface 50A of the semiconductor substrate 50 and is directly connected to the local wiring layer 61 as an etching stopper. Thereby, the occurrence of misalignment with the contact and the increase in contact resistance can be avoided, and the through electrode can be miniaturized with certainty.

  Further, in the configuration disclosed in Patent Document 1, with the miniaturization of the through electrode, the parasitic capacitance and contact resistance generated in the path from the organic photoelectric conversion unit to the FD through the through electrode increase, and the RC delay is reduced. There were concerns about deterioration and reduction in conversion efficiency.

  On the other hand, in the present embodiment, the local wiring layer 61 connected to the FD 53 of the through electrode and the amplification transistor 55 is separated from other wiring layers, so that the degree of freedom of wiring layout is increased and the parasitic capacitance is reduced. Can be reduced. As a result, it is possible to improve RC delay and conversion efficiency.

  Further, the local wiring layer 61 is made of a metal such as W or Ti that hardly causes contamination, and the Si substrate is processed without exposing the metal material. The white spot characteristic can be kept good.

  In addition, in existing TSVs (Through Silicon Vias), stress due to stress occurs, and transistors cannot be disposed in the vicinity of the TSVs, which is subject to layout restrictions.

  On the other hand, in this embodiment, since the through electrode can be miniaturized without generating stress due to stress, a layout in which transistors are arranged in the vicinity of the through electrode can be realized.

  Note that an etching technique called a Bosch process may be used in the step of opening the through hole 112 to the local wiring layer 61 described with reference to FIG. The Bosch process is an etching technique that repeats etching and etching sidewall protection, and enables etching with a high aspect ratio.

  According to the Bosch process, as shown in FIG. 16, the tip 112t of the through hole 112 is formed in a tapered shape. As a result, as shown in FIG. 17, the tip 58t of the through electrode 58 is formed in a tapered shape. As described above, since the tip 58t of the through electrode 58 is formed in a tapered shape, a contact area with the local wiring layer 61 serving as a stopper of the through electrode 58 is reduced. Misalignment can be suppressed. Further, by forming the tip 58t of the through electrode 58 in a tapered shape, it is possible to reduce the parasitic capacitance between the through electrode 58 and each wiring layer forming the multilayer wiring layer 60.

<4. Second Embodiment>
FIG. 18 is a cross-sectional view of the solid-state imaging device 10 according to the second embodiment of the present technology.

  FIG. 18 shows a partial cross section of the peripheral circuit unit 31 constituting the solid-state imaging device 10.

  Also in the example of FIG. 18, the multilayer wiring layer 60 is formed on the front surface 50 </ b> A side of the semiconductor substrate 50, and the organic photoelectric conversion unit is interposed on the back surface 50 </ b> B side serving as the light receiving surface of the semiconductor substrate 50 via the insulating film 70. 80 is formed.

  For example, a transistor 151 is provided on the surface 50 </ b> A of the semiconductor substrate 50. The gate electrode 151 </ b> G of the transistor 151 is connected to the local wiring layer 161 formed on the side closest to the surface 50 </ b> A of the semiconductor substrate 50 among the wiring layers 161 and 163 that form the multilayer wiring layer 60. A gate electrode 151 </ b> G of the transistor 151 is formed on the element isolation film 152. The gate electrode 151 </ b> G of the transistor 151 is connected to the wiring layer 163 through the contact 165. The wiring layer 163 functions as a power supply wiring connected to a predetermined power supply. Therefore, the local wiring layer 161 is connected to the power supply wiring through the gate electrode 151G of the transistor 151.

  The semiconductor substrate 50 has a through electrode 153 having a lower end penetrating the surface 50A of the semiconductor substrate 50 and directly connected to the local wiring layer 161, and an upper end connected to the upper electrode 82 through the metal members 153a to 153d. It is formed to be. The metal member 153a is formed as a lead-out wiring layer of the through electrode 153, and the metal members 153b and 153c are formed as contacts. The metal member 153d is formed as a wiring layer that connects the metal members 153b and 153c. The through electrode 153 and the metal members 153a to 153d are formed of a metal material such as W, Cu, Al, Ti, Co, Hf, or Ta. In the example of FIG. 18, the tip of the through electrode 153 may be formed in a tapered shape, similar to the through electrode 58 of FIG.

  As a result, a predetermined voltage is applied to the upper electrode 82 provided in common for each pixel 20.

  Note that a voltage is constantly applied to the upper electrode 82, but by forming the gate electrode 151G on the element isolation film 152, reliability such as withstand voltage can be maintained. Further, during the process, the gate electrode 151G is in a floating state, and there is a risk of charge-up damage when the through electrode 153 and the metal members 153a to 153d are formed. However, by forming the gate electrode 151G on the element isolation film 152, This can be mitigated.

<5. Manufacturing process for applying voltage to upper electrode>
Next, with reference to FIGS. 19 to 23, a manufacturing process of a configuration in which a voltage is applied to the upper electrode 82 will be described.

  Note that the process from the formation of the multilayer wiring layer 60 to the formation of the through electrode 153 on the surface 50A side of the semiconductor substrate 50 is basically the same as the process of forming the pixel 20, and therefore description thereof is omitted. To do.

  After the through electrode 58 is formed, an unnecessary conductive film is removed by a method such as dry etching after patterning by photolithography in order to form a lead wiring layer 153a at the upper end of the through electrode 153 as shown in FIG. Is done.

  Subsequently, as shown in FIG. 20, after the insulating film 70 is formed, the lower electrode 81, the organic photoelectric conversion layer 83, and the upper electrode 82 are formed, and the passivation film 91 a is formed on the upper electrode 82. The

  Next, as shown in FIG. 21, a contact hole CH2 for connecting the local wiring layer 61 and the upper electrode 82 is formed by patterning and dry etching.

  Thereafter, as shown in FIG. 22, contacts 153b and 153c are formed by burying metal in the contact hole CH2. For example, a work function adjusting Ti film or the like is formed by a method such as PVD, and a barrier metal TiN or W is embedded by a method such as CVD or PVD. Thereafter, in order to form the wiring layer 153d, an unnecessary conductive film is removed by a technique such as dry etching after patterning by photolithography.

  Then, as shown in FIG. 23, a passivation film 91 is formed on the wiring layer 153d.

  Through the above steps, a configuration for applying a voltage to the upper electrode 82 is formed.

  According to the above process, the through electrode 153 is formed so that one end of the through electrode 153 penetrates the surface 50A of the semiconductor substrate 50 and is directly connected to the local wiring layer 161 as an etching stopper. As a result, the occurrence of misalignment with the contact and the increase in contact resistance can be avoided, and the through electrode can be reliably miniaturized even in the configuration in which a voltage is applied to the upper electrode.

  Although not described in the configuration of FIG. 2 and the like, as shown in FIG. 24, between the through hole in which the through electrode 58 is formed and the insulating film 70 (70a) embedded in the through hole, A fixed charge film 171 having a negative fixed charge is formed. Thereby, dark current can be reduced.

  In such a configuration, when the bottom of the through hole is opened by etching, the fixed charge film 171 is exposed on the side surface of the opening. In this state, when the through electrode 58 is formed by embedding the conductive film, the through electrode 58 and the fixed charge film 171 come into contact with each other.

  The fixed charge film 171 has lower insulation resistance and process resistance than the insulating film 70. Therefore, due to insufficient insulation resistance of the fixed charge film 171, there is a possibility of causing a short circuit failure between the through electrode 58 and the fixed charge film 171 as indicated by a double arrow # 1 in FIG.

  Further, due to insufficient process resistance of the fixed charge film 171, as shown in FIG. 25, the contact portion of the fixed charge film 171 with the through electrode 58 recedes and the conductive film enters. This may cause a short circuit failure between the semiconductor substrate 50 and the through electrode 58 as indicated by a double-headed arrow # 2 in FIG.

  Therefore, hereinafter, a configuration in which the through electrode 58 and the fixed charge film 171 are not in contact with each other will be described.

<6. Third Embodiment>
FIG. 26 is a cross-sectional view of the solid-state imaging device 10 according to the third embodiment of the present technology.

  FIG. 26 shows a cross-sectional configuration around the through electrode 58 described above.

  As shown in FIG. 26, the fixed charge film 171 is formed on the through hole in which the through electrode 58 is formed, and the insulating film 70 is formed thereon. The insulating film 172 is formed on the insulating film 70. A film is formed. The insulating film 172 is formed so that the through electrode 58 and the fixed charge film 171 are not in contact with each other on the side surface of the opening portion where a part of the bottom of the through hole on the surface 50A side of the semiconductor substrate 50 is opened. The insulating film 172 has a higher insulating property than the fixed charge film 171.

  In the example of FIG. 26, the insulating film 172 is embedded in the through hole so as to be in contact with the local wiring layer 61 (hereinafter simply referred to as the wiring layer 61) together with the through electrode 58.

<7. Manufacturing process in which the through electrode and the fixed charge film are not in contact>
(Example 1)
Next, an example of a manufacturing process having a configuration in which the through electrode 58 and the fixed charge film 171 are not in contact with each other will be described with reference to FIGS.

  FIG. 27 shows a state similar to FIG. 10 described above. In the process of FIG. 27, the through-hole 181 is formed from the back surface 50B side (upper side in the figure) of the semiconductor substrate 50 with the multilayer wiring layer 60 formed on the front surface 50A side (lower side in the figure) of the semiconductor substrate 50. It is formed.

  The multilayer wiring layer 60 is formed by providing wiring layers 61 and 62 between layers of insulating films made of SiO2, SiN, SiOC, SiON or the like. The wiring layers 61 and 62 are made of Cu, W, Al or the like, and Ti, TiN, Ta, TaN, Ru, Co, Zr or the like is used as the barrier metal.

  The through hole 181 is formed by processing Si (semiconductor substrate 50) by lithography and plasma etching. The etching here is performed so as to stop in the insulating film of the multilayer wiring layer 60. In the present embodiment, the thickness of the semiconductor substrate 50 is, for example, 1 to 50 μm, and the diameter of the through hole 181 is, for example, 100 nm to 1 μm. In addition, the aspect ratio of etching exceeds 5, for example.

  After the through hole 181 is formed, as shown in FIG. 28, a fixed charge film 171 is formed in the through hole 181 by a technique such as ALD. The fixed charge film 171 is formed so that the film thickness becomes smaller than, for example, 50 nm.

  Materials for the fixed charge film 171 include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, titanium oxide, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, and terbium oxide. Dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, and the like are used. Further, as the fixed charge film 171, an aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film may be formed.

  Thereafter, as shown in FIG. 29, the insulating film 70 is formed in the through hole 181 in which the fixed charge film 171 is formed. The insulating film 70 is formed by depositing SiO2, SiN, SiOC or the like by an ALD or CVD method. The inner diameter of the through hole 181 after the insulating film 70 is formed is, for example, about 30 to 500 nm.

  After the insulating film 70 is formed, the insulating film 70 at the bottom of the through hole 181 (on the surface 50A side of the semiconductor substrate 50), the fixed charge film 171, and the insulating film of the multilayer wiring layer 60 are processed by plasma etching. Thus, as shown in FIG. 30, the through hole 181 is opened so as to reach the wiring layer 61.

  As an etching gas used for plasma etching, gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5HF7, CH4, C2H4, He, Ar, O2, CO, and N2 are used.

  After the through-hole 181 is opened to the wiring layer 61, the etching residue and polymer are removed by ashing or wet etching. In ashing, for example, a gas such as O2, H2, and N2 is used after being converted into plasma.

  Thereafter, as shown in FIG. 31, an insulating film 172 is formed in the through hole 181 opened to the wiring layer 61. The insulating film 172 is formed by depositing SiO2, SiN, SiOC or the like by the ALD technique. The insulating film 172 is formed so as to have a film thickness of, for example, 5 nm or more.

  After the insulating film 172 is formed, the through-hole 181 is formed by processing the insulating film 172 at the bottom of the through-hole 181 (on the surface 50A side of the semiconductor substrate 50) by plasma etching, as shown in FIG. The wiring layer 61 is reached again. Again, the same etching gas as in the step of FIG. 29 is used.

  After the through-hole 181 reaches the wiring layer 61, etching residues and polymers are removed by ashing or wet etching.

  Thereafter, a barrier metal is formed in the through hole 181 by a method such as CVD, PVD, or ALD, and then a conductive film is formed. Ti, TiN, Ta, TaN, Ru, Co, Zr, etc. are used for the barrier metal, and the conductive film is formed by Cu plating. As the conductive film, W or Al may be formed by a method such as CVD, PVD, or ALD. Thereby, as shown in FIG. 33, the through electrode 58 is formed in the through hole 181.

  According to the above process, since the insulating film 172 is formed so that the through electrode 58 and the fixed charge film 171 do not come into contact with each other, the insulation resistance (breakdown voltage) of the fixed charge film 171 can be increased. And a short circuit defect between the fixed charge film 171 and the fixed charge film 171 can be suppressed.

  Further, since the fixed charge film 171 can be selected without considering the insulation resistance of the fixed charge film 171, a high noise reduction effect can be obtained.

  Furthermore, since the insulating film is formed twice, the inner diameter of the through hole 181 can be made smaller than 1 μm, and as a result, the through electrode 58 can be miniaturized.

(Example 2)
When the through hole 181 is opened to the wiring layer 61 in the above-described step of FIG. The groove 181e is formed by retreating by etching.

  Thereafter, as shown in FIG. 35, the insulating film 172 is formed in the through hole 181 opened to the wiring layer 61 by the ALD technique, so that the insulating film 172 is also formed in the groove 181e.

  After the insulating film 172 is formed, the through hole 181 reaches the wiring layer 61 by processing the insulating film 172 at the bottom of the through hole 181 by plasma etching as shown in FIG.

  Thereafter, a barrier metal is formed in the through hole 181 and then a conductive film is formed, whereby the through electrode 58 is formed in the through hole 181 as shown in FIG.

  According to the above steps, even if the contact portion of the fixed charge film 171 with the through electrode 58 is retracted due to insufficient process resistance of the fixed charge film 171, the insulating film 172 fills the retracted portion. A film is formed. Thereby, short-circuit failure between the semiconductor substrate 50 and the through electrode 58 due to insufficient process resistance of the fixed charge film 171 can be suppressed.

  In addition, since the fixed charge film 171 can be selected without considering the process resistance of the fixed charge film 171, a high noise reduction effect can be obtained.

(Example 3)
In the process of FIG. 30 described above, the through hole 181 is opened by plasma etching so as to reach the wiring layer 61. However, the processing is stopped before reaching the wiring layer 61 as shown in FIG. You may do it.

  Thereafter, as shown in FIG. 39, an insulating film 172 is formed in the through hole 181 opened to the middle of the multilayer wiring layer 60.

  After the insulating film 172 is formed, the through hole 181 reaches the wiring layer 61 by processing the insulating film 172 at the bottom of the through hole 181 by plasma etching as shown in FIG.

  Thereafter, a barrier metal is formed in the through hole 181 and then a conductive film is formed, whereby the through electrode 58 is formed in the through hole 181 as shown in FIG.

  According to the above steps, charging damage when the wiring layer 61 is exposed due to plasma etching can be reduced, and the possibility that wiring formation is hindered by the metal-containing reaction product can be reduced.

(Example 4)
After the process of FIG. 28 described above, in the process of FIG. 29, the insulating film 70 is formed in the through hole 181 in which the fixed charge film 171 is formed. Not limited to this, after the fixed charge film 171 is formed in the through hole 181 (step of FIG. 28), the fixed charge film 171 at the bottom of the through hole 181 is formed by plasma etching as shown in FIG. It may be removed.

  Thereafter, as shown in FIG. 43, the insulating film 70 is formed in the through hole 181 from which the bottom fixed charge film 171 has been removed.

  After the insulating film 70 is formed, the insulating film 70 at the bottom of the through hole 181 and the insulating film of the multilayer wiring layer 60 are processed by plasma etching, so that the through hole 181 is wired as shown in FIG. Open up to layer 61.

  Thereafter, a barrier metal is formed in the through hole 181 and then a conductive film is formed, whereby the through electrode 58 is formed in the through hole 181 as shown in FIG.

  That is, the insulating film 70 is formed so that the through electrode 58 and the fixed charge film 171 are not in contact with each other on the side surface of the opening where the bottom of the through hole 181 on the surface 50A side of the semiconductor substrate 50 is opened.

  According to the above process, the charge fixing film 171 is limited to the case where it has process resistance. However, the process is shortened without forming the insulating film 172, and the through electrode 58 and the fixed charge film 171 are not in contact with each other. Can be realized.

(Example 5)
In the above description, the structure in which the through electrode 58 contacts the wiring layer in the multilayer wiring layer 60 has been described. However, as shown in FIG. 46, the through electrode 58 does not contact the wiring layer in the multilayer wiring layer 60. You may make it take a structure.

  In this case, it is not necessary to process the insulating film 172 at the bottom of the through hole 181 in the above-described step of FIG.

  In addition, the structure of the present embodiment is not limited to a through electrode, and a conductive film embedded in Si (semiconductor substrate) suppresses noise generated on the Si surface, and a different voltage is applied between the conductive film and Si. It can be applied to all structures.

  Furthermore, the pattern of the conductive film is not limited to a circle like the through electrode 58 shown in the top view of FIG. 47, and a trench may be formed. For example, as shown in FIG. 48, the pattern of the conductive film may adopt a light shielding structure 191 that shields light between the pixels 20.

  In the above-described embodiment, the through electrode is formed from the back surface 50B side of the semiconductor substrate 50, but may be formed from the front surface 50A side of the semiconductor substrate 50.

  Therefore, in the following, a configuration in which the through electrode is formed from the surface 50A side of the semiconductor substrate 50 will be described.

<8. Fourth Embodiment>
FIG. 49 is a cross-sectional view of the solid-state imaging device 10 according to the fourth embodiment of the present technology.

  FIG. 49 shows a cross-sectional configuration around the through electrode.

  Also in the example of FIG. 49, the multilayer wiring layer 60 provided with the wiring layers 261 and 262 is formed on the front surface 50 </ b> A side of the semiconductor substrate 50, and is not shown on the back surface 50 </ b> B side that becomes the light receiving surface of the semiconductor substrate 50. An organic photoelectric conversion part is formed.

  An insulating film 270 is formed between the front surface 50A of the semiconductor substrate 50 and the multilayer wiring layer 60, and the insulating film 270 is also formed on the back surface 50B side of the semiconductor substrate 50 via the fixed charge film 282.

  A through electrode 253 is formed in the semiconductor substrate 50 such that its lower end is connected to the wiring layer 261 via the contact 265 on the surface 50A of the semiconductor substrate 50 and its upper end is connected to the metal electrode 283. . The metal electrode 283 is connected to an organic photoelectric conversion unit (not shown).

  An insulating film 270 is also embedded in the through hole in which the through electrode 253 is formed. A P-type diffusion layer 281 is formed on the outer peripheral portion of the through hole in which the insulating film 270 is embedded.

  An element isolation portion 252 having an STI structure is formed in a region where a through hole on the surface 50A side of the semiconductor substrate 50 is formed.

<9. Manufacturing process for forming through electrode from substrate surface>
Next, a manufacturing process for forming the through electrode 253 from the surface 50A of the semiconductor substrate 50 will be described with reference to FIGS.

  First, as illustrated in FIG. 50, the element isolation part 252 is formed on the surface 50 </ b> A side of the semiconductor substrate 50.

  Next, as shown in FIG. 51, the resist 291 is patterned in accordance with the position where the through electrode 253 is formed. Thereafter, as shown in FIG. 52, through holes 292 are formed by processing Si (semiconductor substrate 50) by a technique such as dry etching.

  After the resist 291 is removed, an insulating film 270 is formed by embedding an oxide film such as a BSG film in the through hole 292 as shown in FIG.

  In this state, by performing an annealing process on the side surface of the through hole 292, as shown in FIG. 54, a P-type diffusion layer 281 is formed in the peripheral portion of the through hole 292 (on the semiconductor substrate 50 side).

  Thereafter, an oxide film such as a TEOS film is embedded again in the through hole 292, and a conductive film such as Poly Si or Doped Amorphous Silicon is embedded by a technique such as ALD or CVD. Thereby, as shown in FIG. 55, the through electrode 253 is formed.

  Then, after patterning by photolithography, an unnecessary conductive film on the surface 50A of the semiconductor substrate 50 is removed by a technique such as dry etching, as shown in FIG.

  Thereafter, as shown in FIG. 57, a contact 265 and a wiring layer 261 connected to the through electrode 253 are formed on the surface 50 </ b> A side of the semiconductor substrate 50. Further, a multilayer wiring layer 60 is formed as shown in FIG. 58 by laminating an insulating layer and a metal layer such as a wiring layer 262 on the surface 50A side of the semiconductor substrate 50.

  On the other hand, on the back surface 50B side of the semiconductor substrate 50, Si (semiconductor substrate 50) is polished so that one end of the through electrode 253 is exposed, as shown in FIG.

  Thereafter, as shown in FIG. 60, after the fixed charge film 282 is formed on the back surface 50B of the semiconductor substrate 50, an insulating film 270 such as an oxide film is formed.

  61, a metal electrode 283 is formed on the through electrode 253 on the back surface 50B side of the semiconductor substrate 50.

  As described above, the through electrode 253 is formed.

  According to the above steps, the through electrode can be formed not from the back surface side of the semiconductor substrate but from the front surface side.

  In the above, an example in which the through electrode of the present technology is applied to a solid-state imaging device that performs spectral in the vertical direction is described. It can apply to the structure provided with the penetration electrode to connect. Further, the above-described embodiments may be employed in combination with each other.

  In addition, this technique is not restricted to application to a solid-state imaging device, It can apply also to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a digital video camera, or an electronic apparatus having an imaging function such as a mobile phone. In some cases, a module-like form mounted on an electronic device, that is, a camera module is used as an imaging device.

<10. Configuration example of electronic device>
Then, with reference to FIG. 62, the structural example of the electronic device to which this technique is applied is demonstrated.

  An electronic apparatus 300 illustrated in FIG. 62 includes an optical lens 301, a shutter device 302, a solid-state imaging device 303, a drive circuit 304, and a signal processing circuit 305. In FIG. 62, an embodiment in which the solid-state imaging device 10 of the present technology described above is provided in an electronic apparatus (digital still camera) as the solid-state imaging device 303 is shown.

  The optical lens 301 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 303. Thereby, the signal charge is accumulated in the solid-state imaging device 303 for a certain period. The shutter device 302 controls the light irradiation period and the light shielding period for the solid-state imaging device 303.

  The drive circuit 304 supplies drive signals to the shutter device 302 and the solid-state imaging device 303. The drive signal supplied to the shutter device 302 is a signal for controlling the shutter operation of the shutter device 302. The drive signal supplied to the solid-state imaging device 303 is a signal for controlling the signal transfer operation of the solid-state imaging device 303. The solid-state imaging device 303 performs signal transfer using a drive signal (timing signal) supplied from the drive circuit 304. The signal processing circuit 305 performs various types of signal processing on the signal output from the solid-state imaging device 303. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

<11. Examples of using image sensors>
Finally, a usage example of an image sensor to which the present technology is applied will be described.

  FIG. 63 is a diagram illustrating a usage example of the image sensor described above.

  The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray, as described below.

・ Devices for taking images for viewing, such as digital cameras and mobile devices with camera functions ・ For safe driving such as automatic stop and recognition of the driver's condition, etc. Devices used for traffic, such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc. Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ・ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc. Equipment used for medical and health care ・ Security equipment such as security surveillance cameras and personal authentication cameras ・ Skin measuring instrument for photographing skin and scalp photography Beauty, such as a microscope Equipment used for sports-Equipment used for sports such as action cameras and wearable cameras for sports applications-Used for agriculture such as cameras for monitoring the condition of fields and crops apparatus

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

Furthermore, this technique can take the following structures.
(1)
A wiring layer formed on the first surface side of the semiconductor substrate;
A photoelectric conversion element formed on the second surface side of the semiconductor substrate;
A solid-state imaging device comprising: a penetrating electrode formed so that one end penetrates the first surface and is connected to the wiring layer, and the other end is connected to the photoelectric conversion element.
(2)
The through electrode is formed for each pixel, and the other end of the through electrode is connected to an electrode provided for each pixel in the photoelectric conversion element,
The solid-state imaging device according to (1), wherein the wiring layer is formed for each pixel and is connected to a floating diffusion and an amplification transistor.
(3)
The solid-state imaging device according to (1) or (2), wherein the wiring layer is formed on a side closer to the second surface than other wiring layers.
(4)
The solid-state imaging device according to any one of (1) to (3), wherein the wiring layer is formed of W or Ti.
(5)
The solid-state imaging device according to (2), wherein at least one photoelectric conversion unit is formed for each pixel in the semiconductor substrate.
(6)
The other end of the through electrode is connected to an electrode provided in common for each pixel in the photoelectric conversion element,
The solid-state imaging device according to (1), wherein the wiring layer is connected to a power supply wiring.
(7)
The solid-state imaging device according to (6), wherein the wiring layer is connected to the power supply wiring through a gate electrode.
(8)
The solid-state imaging device according to (7), wherein the gate electrode is formed on an element isolation film.
(9)
The solid-state imaging device according to any one of (1) to (8), wherein the through electrode is formed of W, Cu, Al, Ti, Co, Hf, or Ta.
(10)
The solid-state imaging device according to any one of (1) to (9), wherein a tip of the through electrode on the wiring layer side is formed in a tapered shape.
(11)
In the through hole in which the through electrode is formed, an insulating film is formed on the fixed charge film,
The solid-state imaging device according to (1), wherein the insulating film is formed on a side surface of the opening portion on the first surface side of the through hole so that the through electrode and the fixed charge film do not contact each other.
(12)
In the through hole, a first insulating film is formed on the fixed charge film, and a second insulating film is formed on a part of the bottom of the through hole on the first surface side. Membrane
The solid-state imaging device according to (11), wherein the second insulating film is formed on the side surface of the opening portion so that the through electrode and the fixed charge film do not contact each other.
(13)
The solid-state imaging device according to (12), wherein the second insulating film has higher insulating properties than the fixed charge film.
(14)
The solid-state imaging device according to (11), wherein the fixed charge film is formed in the through-hole, and the insulating film is formed on the bottom of the through-hole on the first surface side being opened. .
(15)
Forming a wiring layer on the first surface side of the semiconductor substrate;
Forming a through electrode so that one end penetrates the first surface and is connected to the wiring layer;
A method for manufacturing a solid-state imaging device, comprising: forming a photoelectric conversion element so that the other end of the through electrode is connected to the second surface side of the semiconductor substrate.
(16)
The manufacturing method of the solid-state imaging device according to (15), wherein the through electrode is formed using a Bosch process so that one end penetrates the first surface and is connected to the wiring layer.
(17)
The method for manufacturing a solid-state imaging device according to (15) or (16), wherein a high concentration impurity region is formed in a region where the through electrode is to be formed in the semiconductor substrate.
(18)
The method of manufacturing a solid-state imaging device according to (15), wherein the through electrode is formed from the second surface side of the semiconductor substrate.
(19)
The method of manufacturing a solid-state imaging device according to (15), wherein the through electrode is formed from the first surface side of the semiconductor substrate.
(20)
A wiring layer formed on the first surface side of the semiconductor substrate;
A photoelectric conversion element formed on the second surface side of the semiconductor substrate;
An electronic apparatus comprising: a solid-state imaging device having one end passing through the first surface and connected to the wiring layer, and the other end connected to the photoelectric conversion element.

  10 solid-state imaging device, 20 pixels, 50 semiconductor substrate, 51, 52 inorganic photoelectric conversion unit, 53 FD, 54 transfer transistor, 55 amplification transistor, 55G gate electrode, 55s element isolation unit, 56 reset transistor, 56G gate electrode, 56s element Separation part, 57 etch stop layer, 58 through electrode, 60 multilayer wiring layer, 61 local wiring layer, 62, 63 wiring layer, 70 insulating film, 80 organic photoelectric conversion part, 81 lower electrode, 82 upper electrode, 83 organic photoelectric conversion Layer, 91 passivation film, 92 on-chip lens, 151 transistor, 151G gate electrode, 152 element isolation film, 153 through electrode, 153a lead wiring layer, 153b, 153c contact, 153d wiring layer, 1 61 Local Wiring Layer, 163 Wiring Layer, 171 Charge Fixing Film, 172 Insulating Film, 181 Through Hole, 300 Electronic Device, 303 Solid-State Imaging Device

Claims (20)

A wiring layer formed on the first surface side of the semiconductor substrate;
A photoelectric conversion element formed on the second surface side of the semiconductor substrate;
A solid-state imaging device comprising: a penetrating electrode formed so that one end penetrates the first surface and is connected to the wiring layer, and the other end is connected to the photoelectric conversion element. The through electrode is formed for each pixel, and the other end of the through electrode is connected to an electrode provided for each pixel in the photoelectric conversion element,
The solid-state imaging device according to claim 1, wherein the wiring layer is formed for each pixel and is connected to a floating diffusion and an amplification transistor. The solid-state imaging device according to claim 2, wherein the wiring layer is formed closer to the second surface than other wiring layers. The solid-state imaging device according to claim 3, wherein the wiring layer is formed of W or Ti. The solid-state imaging device according to claim 2, wherein at least one photoelectric conversion unit is formed for each pixel in the semiconductor substrate. The other end of the through electrode is connected to an electrode provided in common for each pixel in the photoelectric conversion element,
The solid-state imaging device according to claim 1, wherein the wiring layer is connected to a power supply wiring. The solid-state imaging device according to claim 6, wherein the wiring layer is connected to the power supply wiring through a gate electrode. The solid-state imaging device according to claim 7, wherein the gate electrode is formed on an element isolation film. The solid-state imaging device according to claim 1, wherein the through electrode is formed of W, Cu, Al, Ti, Co, Hf, or Ta. The solid-state imaging device according to claim 1, wherein a tip of the through electrode on the wiring layer side is formed in a tapered shape. In the through hole in which the through electrode is formed, an insulating film is formed on the fixed charge film,
The solid-state imaging device according to claim 1, wherein the insulating film is formed so that the through electrode and the fixed charge film are not in contact with each other on a side surface of the opening portion on the first surface side of the through hole. In the through hole, a first insulating film is formed on the fixed charge film, and a second insulating film is formed on a part of the bottom of the through hole on the first surface side. Membrane
The solid-state imaging device according to claim 11, wherein the second insulating film is formed on a side surface of the opening portion so that the through electrode and the fixed charge film do not contact each other. The solid-state imaging device according to claim 12, wherein the second insulating film has a higher insulating property than the fixed charge film. The solid-state imaging device according to claim 11, wherein the fixed charge film is formed in the through hole, and the insulating film is formed on an opening of a bottom portion of the first surface side of the through hole. . Forming a wiring layer on the first surface side of the semiconductor substrate;
Forming a through electrode so that one end penetrates the first surface and is connected to the wiring layer;
A method for manufacturing a solid-state imaging device, wherein a photoelectric conversion element is formed so that the other end of the through electrode is connected to the second surface side of the semiconductor substrate. The method of manufacturing a solid-state imaging device according to claim 15, wherein the through electrode is formed using a Bosch process so that one end penetrates the first surface and is connected to the wiring layer. The method for manufacturing a solid-state imaging device according to claim 15, wherein a high concentration impurity region is formed in a region where the through electrode is to be formed in the semiconductor substrate. The method of manufacturing a solid-state imaging device according to claim 15, wherein the through electrode is formed from the second surface side of the semiconductor substrate. The method of manufacturing a solid-state imaging device according to claim 15, wherein the through electrode is formed from the first surface side of the semiconductor substrate. A wiring layer formed on the first surface side of the semiconductor substrate;
A photoelectric conversion element formed on the second surface side of the semiconductor substrate;
An electronic apparatus comprising: a solid-state imaging device having one end passing through the first surface and connected to the wiring layer, and the other end connected to the photoelectric conversion element.

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