TWI752569B - memory system - Google Patents

memory system Download PDF

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TWI752569B
TWI752569B TW109125506A TW109125506A TWI752569B TW I752569 B TWI752569 B TW I752569B TW 109125506 A TW109125506 A TW 109125506A TW 109125506 A TW109125506 A TW 109125506A TW I752569 B TWI752569 B TW I752569B
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data
programming
memory
bit
threshold value
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TW202121426A (en
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原徳正
柴田昇
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日商鎧俠股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements

Abstract

實施形態，係提供一種能夠避免胞之間之相互干涉而削減寫入緩衝之容量並且對於位元錯誤率之偏頗作抑制的記憶體系統。 在實施形態之記憶體系統中，記憶體系統內之記憶體控制器，係構成為以使在記憶體胞中之臨限值區域會因應於第1位元、第2位元、第4位元之資料而成為代表資料為被作了刪除的刪除狀態之第17臨限值區域和電壓準位為較第17臨限值區域而更高並代表資料被作了寫入的寫入狀態之第18～第24臨限值區域之其中一者之臨限值區域的方式，來使非揮發性記憶體進行第1程式化，並以使在記憶體胞中之臨限值區域會因應於第3位元之資料而從第17～第24臨限值區域中之任一者之臨限值區域來成為第1～第16臨限值區域中之2個的臨限值區域內之任一者之臨限值區域的方式，來使非揮發性記憶體進行第2程式化，在使非揮發性記憶體進行第2程式化的情況時，係將第2位元之資料和第3位元之資料對於非揮發性記憶體作輸入。An embodiment provides a memory system capable of reducing the capacity of the write buffer and suppressing the bias of the bit error rate by avoiding the mutual interference between cells. In the memory system of the embodiment, the memory controller in the memory system is configured so that the threshold region in the memory cell corresponds to the 1st bit, the 2nd bit, the 4th bit The 17th threshold value area and the voltage level are higher than the 17th threshold value area and represent the write state where the data has been written. One of the 18th to 24th threshold value areas is the threshold value area of the non-volatile memory to perform the first programming, so that the threshold value area in the memory cell corresponds to the For the data of the third bit, the threshold value area of any one of the 17th to 24th threshold value areas becomes any of the threshold value areas of two of the 1st to 16th threshold value areas. In the case of the second programming of the non-volatile memory, the second programming of the non-volatile memory is performed by the method of the threshold value area of the first, and the data of the second bit and the third Bit data is input to non-volatile memory.

Description

記憶體系統memory system

本揭示之實施形態，係有關於記憶體系統。 [關連申請案] 本申請案，係享受以日本專利申請2019-210823號(申請日：2019年11月21日)以及日本專利申請2020-113206號(申請日：2020年6月30日)作為基礎申請之優先權。本申請案，係藉由參照此些基礎申請案，而包含基礎申請案之所有的內容。Embodiments of the present disclosure relate to memory systems. [Connected Application] This application enjoys the priority of Japanese Patent Application No. 2019-210823 (filing date: November 21, 2019) and Japanese Patent Application No. 2020-113206 (application date: June 30, 2020) as basic applications . This application includes all the contents of the basic application by referring to these basic applications.

在NAND型快閃記憶體中，一般而言係對於記憶體胞而寫入由複數位元所成之多值資料，對於記憶體胞而寫入由3位元所成之多值資料的TLC(Triple Level Cell)技術係被實用化。今後，可以預期到，寫入由4位元所成之多值資料之QLC(Quadruple Level Cell)技術係會成為主流。 在QLC中，為了避免胞間之相互干涉，係檢討有「在將4位元資料同時寫入至第1記憶體胞中之後，對於鄰接之胞而亦同樣地將4位元資料同時寫入，之後，再度對於第1記憶體胞而將4位元資料同時地再寫入」之手法。然而，在此手法中，係有必要將4位元資料預先保持在記憶體控制器內之寫入緩衝中，直到再寫入結束為止。 近年之NAND記憶體係被3維化，所必要的寫入緩衝之記憶體容量係增大，而有著將寫入緩衝作了內藏的記憶體控制器之成本變高的問題。因此，在3維之非揮發性記憶體中，係同樣的，係需要對於將記憶體控制器之寫入緩衝量降低的對策有所檢討。 作為避免胞間之相互干涉並同時對於記憶體控制器之寫入緩衝量作削減的對策，係周知有：在對於記憶體胞而將各位元之資料作寫入時，藉由分成2個的階段來作寫入，而成為不需要進行全部位元資料之再寫入的手法。 然而，在此手法中，係有著在對於記憶體胞而將各位元資料作寫入時的位元錯誤率之偏頗為大的問題。 為了將QLC技術之信賴性提升，係需要避免胞之間之相互干涉並且削減記憶體控制器內之寫入緩衝之容量並且亦對於在將各位元資料作寫入時的位元錯誤率之偏頗作抑制的記憶體系統。In the NAND type flash memory, generally speaking, multi-valued data composed of multiple bits is written to the memory cell, and multi-valued data composed of 3 bits is written to the memory cell. (Triple Level Cell) technology system is put into practical use. In the future, it can be expected that the QLC (Quadruple Level Cell) technology for writing multi-value data composed of 4 bits will become mainstream. In QLC, in order to avoid mutual interference between cells, it is reviewed that "after writing 4-bit data to the first memory cell at the same time, the adjacent cells are also written to the 4-bit data at the same time. , and then rewrite the 4-bit data to the first memory cell again at the same time" method. However, in this method, it is necessary to keep the 4-bit data in the write buffer in the memory controller in advance until the rewriting is completed. In recent years, the NAND memory system has been three-dimensionalized, and the necessary memory capacity of the write buffer has increased, and there has been a problem that the cost of a memory controller with a built-in write buffer increases. Therefore, in a three-dimensional non-volatile memory, similarly, it is necessary to review the countermeasures for reducing the write buffer amount of the memory controller. As a countermeasure to avoid mutual interference between cells and reduce the write buffer amount of the memory controller at the same time, it is well known that when writing the data of each cell to the memory cell, dividing the data into two It is a method that does not require rewriting of all bit data. However, in this method, there is a problem that the bit error rate when writing each bit of metadata to a memory cell is large. In order to improve the reliability of QLC technology, it is necessary to avoid mutual interference between cells and reduce the capacity of the write buffer in the memory controller and also bias the bit error rate when writing bits of metadata. as an inhibited memory system.

在本揭示之其中一個態樣中，係提供一種能夠避免胞之間之相互干涉並且削減記憶體控制器內之寫入緩衝之容量並且亦對於在將各位元資料作寫入時的位元錯誤率之偏頗作抑制的記憶體系統。 若依據本實施形態，則係提供一種記憶體系統，其係具備有：非揮發性記憶體，係具有複數之記憶體胞，該複數之記憶體胞，係各別藉由16個臨限值區域，而能夠記憶藉由第1～第4位元來作表現的4位元之資料，該16個的臨限值區域，係包含有代表資料被作了刪除的刪除狀態之第1臨限值區域、和電壓準位為較前述第1臨限值區域而更高並代表資料被作了寫入的寫入狀態之第2～第16臨限值區域；和 記憶體控制器，係在使前述非揮發性記憶體進行了將前述第1位元、前述第2位元、前述第4位元之資料作寫入的第1程式化之後，使前述非揮發性記憶體進行將前述第3位元之資料作寫入的第2程式化， 在存在於前述第1～第16臨限值區域中之相鄰接之臨限值區域間之15個的邊界中，被使用在前述第1位元之資料之值的判定中之第1邊界之數量、被使用在前述第2位元之資料之值的判定中之第2邊界之數量、被使用在前述第3位元之資料之值的判定中之第3邊界之數量、被使用在前述第4位元之資料之值的判定中之第4邊界之數量，此些之數量中之最大之值係為5，第2大之值係為4， 前述記憶體控制器，係構成為以使在前述記憶體胞中之臨限值區域會因應於前述第1位元、前述第2位元、前述第4位元之資料而成為代表資料為被作了刪除的刪除狀態之第17臨限值區域和電壓準位為較前述第17臨限值區域而更高並代表資料被作了寫入的寫入狀態之第18～第24臨限值區域之其中一者之臨限值區域的方式，來使前述非揮發性記憶體進行前述第1程式化， 前述記憶體控制器，係構成為以使在前述記憶體胞中之臨限值區域會因應於前述第3位元之資料而從前述第17～第24臨限值區域中之任一者之臨限值區域來成為前述第1～第16臨限值區域中之2個的臨限值區域內之任一者之臨限值區域的方式，來使前述非揮發性記憶體進行前述第2程式化， 位置於前述2個的臨限值區域中之電壓準位為最低之臨限值區域和電壓準位為最高之臨限值區域之間的臨限值區域之個數，係為2個以內， 前述記憶體控制器，在使前述非揮發性記憶體進行前述第2程式化的情況時，係構成為將前述第2位元之資料和前述第3位元之資料對於前述非揮發性記憶體作輸入。In one aspect of the present disclosure, a method is provided that can avoid mutual interference between cells and reduce the capacity of the write buffer in the memory controller and is also resistant to bit errors when writing bits of metadata. Rate bias is suppressed by the memory system. According to the present embodiment, a memory system is provided, which is provided with: a non-volatile memory, a plurality of memory cells, and the plurality of memory cells are respectively controlled by 16 threshold values The 4-bit data represented by the 1st to 4th bits can be memorized, and the 16 threshold value areas include the first threshold representing the deletion state of the deleted data. The value area and the voltage level are higher than the aforementioned first threshold value area and represent the 2nd to 16th threshold value areas in which the data has been written; and The memory controller makes the non-volatile memory perform the first programming of writing the data of the first bit, the second bit, and the fourth bit, so as to make the non-volatile memory The second programming that writes the data of the aforementioned third bit into the memory is performed, Among the 15 boundaries existing between adjacent threshold value areas among the first to 16th threshold value areas, the first boundary used for the determination of the value of the data of the first bit number, the number of the second boundary used in the determination of the value of the data of the second bit, the number of the third boundary used in the determination of the value of the data of the third bit, The number of the fourth boundary in the determination of the value of the data of the fourth bit above, the largest value of these numbers is 5, the second largest value is 4, The memory controller is configured so that the threshold value area in the memory cell becomes representative data in response to the data of the first bit, the second bit, and the fourth bit. The 17th threshold value region and the voltage level of the deletion state in which the deletion has been performed are higher than the aforementioned 17th threshold value region and represent the 18th to 24th threshold values of the write state in which data has been written. The non-volatile memory is subjected to the first programming by means of the threshold value region of one of the regions, The memory controller is configured such that the threshold value region in the memory cell is changed from any one of the 17th to 24th threshold value regions in response to the data of the third bit. The non-volatile memory is made to perform the above-mentioned 2 stylized, The number of threshold value areas between the threshold value area where the voltage level is the lowest and the threshold value area where the voltage level is the highest in the aforementioned two threshold value areas is within 2, The memory controller, in the case of performing the second programming on the non-volatile memory, is configured to assign the data of the second bit and the data of the third bit to the non-volatile memory as input.

圖1，係為對於由第1實施形態所致的記憶體系統1之概略構成作展示之區塊圖。圖1之記憶體系統1，係具備有記憶體控制器2和非揮發性記憶體3。圖1之記憶體系統1，係能夠與主機處理器(以下，係單純稱作主機)4作連接。主機4，例如，係為個人電腦、攜帶終端等之電子機器。 非揮發性記憶體3，係為將資料非揮發性地作記憶之記憶體，例如，係具備有NAND快閃記憶體(以下，係亦有稱作NAND記憶體的情形)5。在本實施形態中，係針對非揮發性記憶體3乃身為具備有在每一記憶體胞處能夠記憶4位元之資料的記憶體胞之4bit/Cell(QLC：Quad Level Cell)之NAND記憶體5的例子，來進行說明。由本實施形態所致之非揮發性記憶體3，係具備有使記憶體胞被立體性地作了層積的3維構造。非揮發性記憶體3，係具有複數之記憶體胞，該複數之記憶體胞，係各別藉由16個臨限值區域，而能夠記憶藉由第1～第4位元來作表現的4位元之資料，該16個的臨限值區域，係包含有代表資料被作了刪除的刪除狀態之第1臨限值區域、和電壓準位為較第1臨限值區域而更高並代表資料被作了寫入的寫入狀態之第2～第16臨限值區域。例如，第1位元，係身為最下位之Lower位元，前述第2位元，係身為第2小之Middle位元，前述第3位元，係身為第2大之Upper位元，前述第4位元，係身為最上位之Top位元。 記憶體控制器2，係依循於從主機4而來的寫入指令而對於對非揮發性記憶體3之資料的寫入作控制。又，記憶體控制器2，係依循於從主機4而來的讀出指令而對於從非揮發性記憶體3之資料的讀出作控制。記憶體控制器2，係具備有RAM(Random Access Memory)6、ROM(Read Only Memory)7、處理器8、主機介面9、ECC(Error Check and Correct)電路10以及記憶體介面11。RAM6、處理器8、主機介面9、ECC電路10以及記憶體介面11，係藉由共通之內部匯流排12而被作連接。 如同後述一般，本實施形態之記憶體控制器2，係在使非揮發性記憶體3進行了將第1位元、第2位元、第4位元之資料作寫入的第1程式化之後，使非揮發性記憶體3進行將第3位元之資料作寫入的第2程式化。在存在於第1～第16臨限值區域中之相鄰接之臨限值區域間之15個的邊界中，被使用在第1位元之資料之值的判定中之第1邊界之數量、被使用在第2位元之資料之值的判定中之第2邊界之數量、被使用在第3位元之資料之值的判定中之第3邊界之數量、被使用在第4位元之資料之值的判定中之第4邊界之數量，此些之數量中之最大之值係為5，第2大之值係為4。記憶體控制器2，係構成為以使在記憶體胞中之臨限值區域會因應於第1位元、第2位元、第4位元之資料而成為代表資料為被作了刪除的刪除狀態之第17臨限值區域和電壓準位為較第17臨限值區域而更高並代表資料被作了寫入的寫入狀態之第18～第24臨限值區域之其中一者之臨限值區域的方式，來使非揮發性記憶體3進行第1程式化。記憶體控制器2，係構成為以使在記憶體胞中之臨限值區域會因應於第3位元之資料而從第17～第24臨限值區域中之任一者之臨限值區域來成為第1～第16臨限值區域中之2個的臨限值區域內之任一者之臨限值區域的方式，來使非揮發性記憶體3進行第2程式化。位置於2個的臨限值區域中之電壓準位為最低之臨限值區域和電壓準位為最高之臨限值區域之間的臨限值區域之個數，係為2個以內。記憶體控制器2，在使非揮發性記憶體3進行第2程式化的情況時，係構成為將第2位元之資料和第3位元之資料對於非揮發性記憶體3作輸入。 更詳細而言，記憶體控制器2，係以會使在16個的臨限值區域(第1～第16臨限值區域)間之15個的邊界中的相鄰接之臨限值區域之間，第1位元之值為相異的邊界之數量、第2位元之值為相異的邊界之數量、第3位元之值為相異的邊界之數量、以及第4位元之值為相異的邊界之數量，依序成為(1、4、5、5)、(1、5、4、5)或者是(3、3、4、5)的方式，來使非揮發性記憶體進行第1程式化以及第2程式化。 或者是，本實施形態之記憶體控制器2，係在使非揮發性記憶體3進行了將第1位元、第2位元、第4位元之資料作寫入的第1程式化之後，使非揮發性記憶體3進行將第3位元之資料作寫入的第2程式化。在存在於第1～第16臨限值區域中之相鄰接之臨限值區域間之15個的邊界中，被使用在第1位元之資料之值的判定中之第1邊界之數量、被使用在第2位元之資料之值的判定中之第2邊界之數量、被使用在第3位元之資料之值的判定中之第3邊界之數量、被使用在第4位元之資料之值的判定中之第4邊界之數量，係依序為(3、5、2、5)。記憶體控制器2，係構成為以使在記憶體胞中之臨限值區域會因應於第1位元、第2位元、第4位元之資料而成為代表資料為被作了刪除的刪除狀態之第17臨限值區域和電壓準位為較第17臨限值區域而更高並代表資料被作了寫入的寫入狀態之第18～第24臨限值區域之其中一者之臨限值區域的方式，來使非揮發性記憶體3進行第1程式化。記憶體控制器2，係構成為以使在記憶體胞中之臨限值區域會因應於第3位元之資料而從第17～第24臨限值區域中之任一者之臨限值區域來成為第1～第16臨限值區域中之2個的臨限值區域內之任一者之臨限值區域的方式，來使非揮發性記憶體3進行第2程式化。位置於2個的臨限值區域中之電壓準位為最低之臨限值區域和電壓準位為最高之臨限值區域之間的臨限值區域之個數，係為2個以內。記憶體控制器2，在使非揮發性記憶體3進行第2程式化的情況時，係構成為將第2位元之資料和第3位元之資料對於非揮發性記憶體3作輸入。 記憶體控制器2，係亦能夠以會使第17～第24臨限值區域中之第2位元之資料之值為相異的2個的臨限值區域之間之電壓準位之差成為較第1位元之資料之值為相異的2個的臨限值區域之間之電壓準位之差而更小並且成為較第4位元之資料之值為相異的2個的臨限值區域之間之電壓準位之差而更小的方式，來使非揮發性記憶體進行第1程式化。 或者是，記憶體控制器2，係亦能夠以會相較於第2位元之資料之值為相異的第1程式化時之2個的臨限值區域之間之間隔，而使對於2個的臨限值區域而藉由第3位元之資料來進行第2程式化所得到的4個的臨限值區域中之相鄰接之臨限值區域之間隔變得更廣的方式，來使非揮發性記憶體進行第2程式化。 主機介面9，係將從主機4所受訊了的指令、使用者資料(寫入資料)等輸出至內部匯流排12處。又，主機介面9，係將從非揮發性記憶體3所讀出了的使用者資料或從處理器8而來之回應等，對於主機4作送訊。 記憶體介面11，係基於處理器8之指示，而對於將使用者資料等對於非揮發性記憶體3作寫入之處理和從非揮發性記憶體3而將使用者資料讀出之處理作控制。 處理器8，係對於記憶體控制器2作統籌性的控制。處理器8，例如係為CPU(Central Processing Unit)、MPU(Micro Processing Unit)等。處理器8，當從主機4經由主機介面9而接收了指令的情況時，係進行依循於該指令之控制。例如，處理器8，係依循於從主機4而來之指令，而對於記憶體介面11下達對於非揮發性記憶體3之使用者資料以及同位檢查碼的寫入之指示。又，處理器8，係依循於從主機4而來之指令，而對於記憶體介面11下達從非揮發性記憶體3而來之使用者資料以及同位檢查碼的讀出之指示。 使用者資料，係經由內部匯流排12而被儲存於RAM6中。處理器8，係對於被儲存在RAM6中之使用者資料，而決定在非揮發性記憶體3上之儲存區域(記憶體區域)。處理器8，係對於身為寫入單位之頁面單位的資料(頁面資料)，而決定在非揮發性記憶體3上之記憶體區域。在本說明書中，係將被儲存在非揮發性記憶體3之1個頁面中的使用者資料，定義為單位資料。單位資料，一般而言係被編碼並作為碼字而被儲存在非揮發性記憶體3中，但是，編碼係並非為必須。記憶體控制器2，係亦可並不進行編碼地而將單位資料儲存在非揮發性記憶體3中，但是，在圖1中，作為其中一構成例，係對於進行編碼之構成作展示。當記憶體控制器2並不進行編碼的情況時，頁面資料係與單位資料相互一致。又，係可基於1個的單位資料來產生1個的碼字，亦可基於使單位資料被作了分割後的分割資料，來產生1個的碼字。又，係亦可使用複數之單位資料，來產生1個的碼字。 處理器8，係針對各單位資料之每一者，而分別決定寫入目標之非揮發性記憶體3之記憶體區域。在非揮發性記憶體3之記憶體區域處，係被分配有物理位址。處理器8，係使用物理位址來對於單位資料之寫入目標之記憶體區域作管理。處理器8，係以指定所決定了的記憶體區域(物理位址)並將使用者資料對於非揮發性記憶體3作寫入的方式，來對於記憶體介面11下達指示。另一方面，主機4係藉由邏輯位址來對於資料作管理。因此，處理器8，係對於使用者資料之邏輯位址與物理位址之間之對應關係作管理。處理器8，當受訊了從主機4而來之包含有邏輯位址之讀出指令的情況時，係特定出與邏輯位址相對應之物理位址，並對於物理位址作指定而對於記憶體介面11下達使用者資料的讀出之指示。 在本說明書中，係將被與1個的字元線共通地作了連接的複數之記憶體胞，定義為記憶體胞群MG。1個的記憶體胞群MG，係成為寫入(程式化)之單位。在本實施形態中，非揮發性記憶體3，係身為4bit/Cell之NAND記憶體5，1個的記憶體胞群MG係具備有4位元×位元數之量的資料量。被寫入至各記憶體胞中之各位元，係對應於互為相異之頁面。在本實施形態中，係將1個的記憶體胞群MG之4頁面，稱作Lower頁面(第1頁面)、Middle頁面(第2頁面)、Upper頁面(第3頁面)、Top頁面(第4頁面)。 ECC電路10，係將被儲存在RAM6中之使用者資料作編碼，並產生碼字。又，ECC電路10，係將從非揮發性記憶體3所讀出了的碼字作解碼。ECC電路10，係將在從非揮發性記憶體3所讀出了的碼字中所包含之位元錯誤作了訂正之後，解碼為使用者資料。 RAM6，係將從主機4所受訊了的使用者資料暫時性地作儲存，直到將其記憶至非揮發性記憶體3中為止，或者是將從非揮發性記憶體3所讀出了的資料暫時性地作儲存，直到對於主機4作送訊為止。RAM6，例如係身為SRAM(Static Random Access Memory)或DRAM(Dynamic Random Access Memory)等之泛用記憶體。 在圖1中，係對於記憶體控制器2為分別具備有ECC電路10和記憶體介面11的構成例作展示。但是，ECC電路10係亦可被內藏於記憶體介面11中。又，ECC電路10係亦可被內藏於非揮發性記憶體3中。 當從主機4而受訊了寫入要求的情況時，記憶體系統1係如同下述一般地而動作。處理器8，係將寫入資料暫時性地儲存於RAM6中。處理器8，係讀取被儲存於RAM6中之資料，並輸入至ECC電路10處。ECC電路10，係將被輸入了的資料作編碼，並將碼字輸入至記憶體介面11處。記憶體介面11，係將被輸入了的碼字對於非揮發性記憶體3作寫入。 當從主機4而受訊了讀取要求的情況時，記憶體系統1係如同下述一般地而動作。記憶體介面11，係將從非揮發性記憶體3所讀出了的碼字輸入至ECC電路10處。ECC電路10，係將被輸入了的碼字解碼，並將被作了解碼後之資料暫時性地儲存於RAM6中。處理器8，係將被儲存在RAM6中之資料，經由主機介面9來送訊至主機4處。另外，非揮發性記憶體3，係亦會有藉由複數之晶片而被構成的情況，非揮發性記憶體3和記憶體介面11，係亦可經由貫通通孔(TSV：Through Silicon Via)來作連接。 另外，圖1中所示之記憶體控制器2之構成，係僅為其中一例，而亦可採用使內部匯流排12成為分割構造或階層構造、或者是被連接有附加性之功能區塊等的其他之各式各樣的衍生性之形態。 圖2，係為對於本實施形態的非揮發性記憶體3之內部構成之其中一例作展示之區塊圖。非揮發性記憶體3，係具備有NAND I/O介面21、控制部22、NAND記憶體胞陣列(記憶體胞部)23、以及頁面緩衝(第2記憶部)24。非揮發性記憶體3，例如係被形成於半導體基板(例如矽基板)上並被晶片化。 控制部22，係基於經由NAND I/O介面21而從記憶體控制器2而來之指令等，而對於非揮發性記憶體3之動作作控制。具體而言，控制部22，在被輸入有寫入要求的情況時，係以將被要求了寫入的資料對於NAND記憶體胞陣列23上之被指定了的位址來作寫入的方式而進行控制。又，控制部22，在被輸入有讀出要求的情況時，係以將被要求了讀出的資料從NAND記憶體胞陣列23而讀出並經由NAND I/O介面21來對於記憶體控制器2作輸出的方式來進行控制。頁面緩衝24，係身為在NAND記憶體胞陣列23之寫入時將從記憶體控制器2所輸入了的資料暫時性地作儲存並將從NAND記憶體胞陣列23所讀出了的資料暫時性地作儲存之緩衝。 如同後述一般，控制部22，係基於將藉由1st階段之程式化而被作了程式化的資料讀出所得到之資料、和在1st階段以及2nd階段之程式化時被重複作輸入的位元之資料、以及藉由2nd階段之程式化而被作了程式化的位元之輸入資料，來決定藉由2nd階段之程式化而被作程式化的位元之資料之臨限值電壓。 控制部22，係具備有震盪器31、和序列器32、和指令使用者介面33、和電壓供給部34、和列計數器35、以及序列存取控制器36。又，NAND記憶體胞陣列23，係具備有行解碼器37和感測放大器38。 NAND I/O介面21，係為用以與記憶體控制器2之間而將IO訊號以及控制訊號作送受訊的電路。指令使用者介面33，係將從記憶體控制器2而經由IO訊號線所受訊了的指令、位址以及資料中之指令以及位址，基於控制訊號來取得之。指令使用者介面33，係將所取得了的指令以及位址交付給序列器32。 震盪器31，係為產生時脈之電路。藉由震盪器31所產生了的時脈，係被供給至包含序列器32之各構成要素處。序列器32，係身為藉由從震盪器31所供給的時脈而被作驅動之狀態機(State Machine)。序列器32，係實行對於NAND記憶體胞陣列23之存取等的控制。例如，序列器32，係因應於從指令使用者介面33所受訊了的指令，來下達各種之用以對於內部電壓或動作時序等作控制的指令。又，序列器32，係將在從指令使用者介面33所受訊了的位址中所包含之區塊位址以及頁面位址，供給至行解碼器37處。進而，序列器32，係將在從指令使用者介面33所受訊了的位址中所包含之列位址，供給至列計數器35處。 電壓供給部34，係產生被供給至字元線處之各種之內部電壓和被供給至位元線處之各種之內部電壓，並對於行解碼器37和感測放大器38作供給。列計數器35，在程式化動作或讀取動作時，係將從序列器32所供給了的列位址作為開頭，並依循於從序列存取控制器36所供給的控制訊號來使列位址依序前進。 頁面緩衝24，在程式化動作時，係將從序列存取控制器36所受訊了的資料依序儲存在上述列計數器35所指定了的列位址區域處。又，頁面緩衝24，在讀取動作時，係將被儲存的資料中之藉由上述列位址所指定了的列位址之資料依序送至序列存取控制器36處。 序列存取控制器36，在程式化動作時，係將從NAND I/O介面21而於IO訊號線之每位元寬幅處序列地受訊了的資料，儲存在頁面緩衝24中。又，序列存取控制器36，在讀取動作時，係從頁面緩衝24而於IO訊號線之每位元寬幅處序列地受訊了的資料，送至NAND I/O介面21處。 行解碼器37，在程式化動作以及讀取動作時，係將區塊位址以及頁面位址作解碼，並選擇與在存取目標之區塊BLK中所包含的成為存取對象之頁面相對應的字元線。之後，各行解碼器37，係對於選擇字元線以及非選擇字元線而施加適當之電壓。 感測放大器38，在程式化動作時，係將被儲存於頁面緩衝24中之相對應之資料傳輸至記憶體胞電晶體處。又，感測放大器38，在讀取動作時，係對於從選擇字元線而讀出至了位元線處之資料作感測，並將所得到的資料儲存於頁面緩衝24中。被儲存在頁面緩衝24中之資料，係經由序列存取控制器36以及NAND I/O介面21而被送至記憶體控制器2處。 圖3，係為對於3維構造的NAND記憶體胞陣列23之其中一例作展示之電路圖。圖3，係對於3維構造的NAND記憶體胞陣列23內的複數之區塊中之1個的區塊BLK之電路構成作展示。NAND記憶體胞陣列23之其他區塊，亦係具備有與圖3相同之電路構成。另外，本實施形態，係亦可對於2維構造之記憶體胞作適用。 如同圖3中所示一般，區塊BLK，例如係具備有4個的指(finger)FNG(FNG0～FNG3)。又，各個的指FNG，係包含複數之NAND字串NS。NAND字串NS之各者，例如係具備有被作了串接連接之8個的記憶體胞電晶體MT(MT0～MT7)、和選擇電晶體ST1、ST2。在本說明書中，係會有將各個的指FNG稱作字串St的情況。 另外，NAND字串NS內之記憶體胞電晶體MT的個數，係並不被限定於8個。記憶體胞電晶體MT，係於選擇電晶體ST1、ST2之間，以使其之電流路徑被作串聯連接的方式而被作配置。此串聯連接之其中一端側之記憶體胞電晶體MT7的電流路徑，係被與選擇電晶體ST1之電流路徑之其中一端作連接，另外一端側之記憶體胞電晶體MT0之電流路徑，係被與選擇電晶體ST2之電流路徑之其中一端作連接。 指FNG0～FNG3之各者之選擇電晶體ST1之閘極，係分別被與選擇閘極線SGD0～SGD3作共通連接。另一方面，選擇電晶體ST2之閘極，係在複數之指FNG間而被與同一之選擇閘極線SGS作共通連接。又，位於同一區塊BLK內的記憶體胞電晶體MT0～MT7之控制閘極，係分別被與字元線WL0～WL7作共通連接。亦即是，字元線WL0～WL7以及選擇閘極線SGS，係於同一區塊BLK內之複數之指FNG0～FNG3之間而被共通地作連接，相對於此，選擇閘極線SGD，係就算是於同一區塊BLK內亦係在指FNG0～FNG3之各者處而分別相互獨立。 在構成NAND字串NS之記憶體胞電晶體MT0～MT7的控制閘極電極處，係分別被連接有字元線WL0～WL7，又，同一之指FNG內之各NAND字串NS中之第i個的記憶體胞電晶體MTi(i＝0～n)，係藉由同一之字元線WLi(i＝0～n)而被作共通連接。亦即是，區塊BLK內的同一行之記憶體胞電晶體MTi之控制閘極電極，係被與同一之字元線WLi作連接。 各NAND字串NS，係被與字元線WLi作連接並且亦被與位元線作連接。各NAND字串NS內之各記憶體胞，係能夠藉由對於字元線WLi以及選擇閘極線SGD0～SGD3作辨識之位址和對於位元線作辨識之位址，來作辨識。如同上述一般，位於同一區塊BLK內的記憶體胞(記憶體胞電晶體MT)之資料，係整批地被刪除。另一方面，資料之讀出以及寫入，係以物理扇區MS之單位來進行。1個物理扇區MS，係被與1個的字元線WLi作連接，並且包含有隸屬於1個的指FNG之複數之記憶體胞。 記憶體控制器2，係將1個的指內之被與1根的字元線作連接之所有的NAND字串NS作為單位，而進行寫入(程式化)。因此，記憶體控制器2所進行程式化之資料量的單位，係成為4位元×位元線數量。 在讀取動作以及程式化動作時，因應於物理位址，1根的字元線WLi以及1根的選擇閘極線SGD係被作選擇，物理扇區MS係被選擇。另外，在本說明書中，係將對於記憶體胞而將資料作寫入一事，因應於需要而稱作程式化(program)。 圖4，係為3維構造的NAND記憶體5之NAND記憶體胞陣列23之一部分區域的剖面圖。如同圖4中所示一般，在半導體基板之p型井區域(P-well)41上，係於上下方向而被形成有複數之NAND字串NS。亦即是，在p型井區域41上，係於上下方向，而被形成有作為選擇閘極線SGS而起作用之複數之配線層42、作為字元線WLi而起作用之複數之配線層43、以及作為選擇閘極線SGD而起作用之複數之配線層44。 又，係被形成有貫通此些之配線層42、43、44並到達p型井區域41處的記憶體洞45。在記憶體洞45之側面處，係依序被形成有區塊絕緣膜46、電荷積蓄層47以及閘極絕緣膜48，進而，在記憶體洞45內係被埋入有導電膜49。導電膜49，係作為NAND字串NS之電流路徑而起作用，並身為在記憶體胞電晶體MT和選擇電晶體ST1以及ST2之動作時而被形成有通道的區域。 在各NAND字串NS處，係於p型井區域41上，依序被層積有選擇電晶體ST2、複數之記憶體胞電晶體MT、以及選擇電晶體ST1。在導電膜49之上端處，係被形成有作為位元線BL而起作用之配線層。 進而，在p型井區域41之表面內，係被形成有n＋型雜質擴散層以及p＋型雜質擴散層。在n＋型雜質擴散層上，係被形成有接觸插銷50，在接觸插銷50上，係被形成有作為源極線SL而起作用之配線層。又，在p＋型雜質擴散層上，係被形成有接觸插銷51，在接觸插銷51上，係被形成有作為井配線CPWELL而起作用之配線層。井配線CPWELL，係為了施加刪除電壓而被使用。 圖4中所示之NAND記憶體胞陣列23，係在圖4之紙面的深度方向上被作複數配列，藉由在深度方向上而並排為1列的複數之NAND字串NS之集合，1個的指FNG係被形成。其他之指FNG，例如係被形成於圖4之左右方向上。在圖3中，雖係圖示有4個的指FNG0～3，但是，在圖4中，係對於在接觸插銷50、51之間配置有3個的指的例子作展示。 圖5，係為對於第1實施形態之臨限值區域的其中一例作展示之圖。圖5，係對於4位元/Cell之非揮發性記憶體3的臨限值區域之分布之其中一例作展示。在非揮發性記憶體3處，係藉由被積蓄在記憶體胞之電荷積蓄層47中的電子之電荷量，來記憶資訊。各記憶體胞，係具備有與電子之電荷量相對應的臨限值電壓。又，係使記憶在記憶體胞中之複數之資料值，分別與臨限值電壓為相異的複數之區域(臨限值區域)相對應。 圖5之S0～S15，係對於16個的臨限值區域內之臨限值分布作展示。圖5之橫軸，係代表臨限值電壓，縱軸，係為記憶體胞數(胞數)。臨限值分布，係為臨限值所變動之範圍。如此這般，各記憶體胞，係具備有藉由15個的邊界所劃分出之16個的臨限值區域，各臨限值區域，係具備有固有之臨限值分布。 在本實施形態中，係將臨限值電壓乃成為Vr1以下之區域，稱作區域S0，並將臨限值電壓成為較Vr1更大並為Vr2以下之區域，稱作區域S1，並將臨限值電壓成為較Vr2更大並為Vr3以下之區域，稱作區域S2，並且將臨限值電壓成為較Vr3更大並為Vr4以下之區域，稱作區域S3。又，在本實施形態中，係將臨限值電壓成為較Vr4更大並為Vr5以下之區域，稱作區域S4，並將臨限值電壓成為較Vr5更大並為Vr6以下之區域，稱作區域S5，並將臨限值電壓成為較Vr6更大並為Vr7以下之區域，稱作區域S6，並且將臨限值電壓成為較Vr7更大並為Vr8以下之區域，稱作區域S7。又，在本實施形態中，係將臨限值電壓成為較Vr8更大並為Vr9以下之區域，稱作區域S8，並將臨限值電壓成為較Vr9更大並為Vr10以下之區域，稱作區域S9，並將臨限值電壓成為較Vr10更大並為Vr11以下之區域，稱作區域S10，並且將臨限值電壓成為較Vr11更大並為Vr12以下之區域，稱作區域S11。又，在本實施形態中，係將臨限值電壓成為較Vr12更大並為Vr13以下之區域，稱作區域S12，並將臨限值電壓成為較Vr13更大並為Vr14以下之區域，稱作區域S13，並將臨限值電壓成為較Vr14更大並為Vr15以下之區域，稱作區域S14，並且將臨限值電壓成為較Vr15更大之區域，稱作區域S15。 又，係將與區域S0～S15相對應之臨限值分布，稱作第1～第16分布。Vr1～Vr15，係身為成為各臨限值區域之邊界的臨限值電壓。 在非揮發性記憶體3中，係使複數之資料值分別與記憶體胞之複數之臨限值區域相對應。將此對應稱作資料編碼。預先對於此資料編碼作制定，在資料之寫入(程式化)時，係依循於資料編碼而以會成為與所記憶之資料值相對應之臨限值區域內的方式，來對於記憶體胞內之電荷積蓄層47注入電荷。而，在讀出時，係對於記憶體胞施加讀出電壓，並根據記憶體胞之臨限值為較讀出電壓而更低或更高一事，來決定資料邏輯。 在資料之讀出時，根據臨限值係為較讀出對象之邊界的讀出準位而更低或更高一事，資料之邏輯係被決定。當臨限值為最低的情況時，係身為「刪除」狀態，所有的位元之資料係被定義為“1”。當臨限值為較「刪除」狀態而更高的情況時，係身為「被作了程式化」之狀態，依循於編碼，資料係被定義為“1”或“0”。 圖6A，係為對於第1實施形態之資料編碼的其中一例作展示之圖，並對於1-4-5-5資料編碼之其中一例作展示。在本實施形態中，係使圖5中所示之16個的臨限值區域分別對應於4位元之16個的資料值。圖6A中之臨限值電壓與對應於Top、Upper、Middle、Lower頁面的位元之資料值之間之關係，係如下所示。 ・臨限值電壓為位於S0區域內之記憶體胞，係身為記憶有“1111”之狀態。 ・臨限值電壓為位於S1區域內之記憶體胞，係身為記憶有“0111”之狀態。 ・臨限值電壓為位於S2區域內之記憶體胞，係身為記憶有“0011”之狀態。 ・臨限值電壓為位於S3區域內之記憶體胞，係身為記憶有“1011”之狀態。 ・臨限值電壓為位於S4區域內之記憶體胞，係身為記憶有“1001”之狀態。 ・臨限值電壓為位於S5區域內之記憶體胞，係身為記憶有“0001”之狀態。 ・臨限值電壓為位於S6區域內之記憶體胞，係身為記憶有“0101”之狀態。 ・臨限值電壓為位於S7區域內之記憶體胞，係身為記憶有“1101”之狀態。 ・臨限值電壓為位於S8區域內之記憶體胞，係身為記憶有“1100”之狀態。 ・臨限值電壓為位於S9區域內之記憶體胞，係身為記憶有“1110”之狀態。 ・臨限值電壓為位於S10區域內之記憶體胞，係身為記憶有“1010”之狀態。 ・臨限值電壓為位於S11區域內之記憶體胞，係身為記憶有“1000”之狀態。 ・臨限值電壓為位於S12區域內之記憶體胞，係身為記憶有“0000”之狀態。 ・臨限值電壓為位於S13區域內之記憶體胞，係身為記憶有“0100”之狀態。 ・臨限值電壓為位於S14區域內之記憶體胞，係身為記憶有“0110”之狀態。 ・臨限值電壓為位於S15區域內之記憶體胞，係身為記憶有“0010”之狀態。 圖6B，係為對於第1實施形態之資料編碼的另外一例作展示之圖，並對於4-3-4-4資料編碼之其中一例作展示。圖6B中之臨限值電壓與對應於Top、Upper、Middle、Lower頁面的位元之資料值之間之關係，係如下所示。 ・臨限值電壓為位於S0區域內之記憶體胞，係身為記憶有“1111”之狀態。 ・臨限值電壓為位於S1區域內之記憶體胞，係身為記憶有“0111”之狀態。 ・臨限值電壓為位於S2區域內之記憶體胞，係身為記憶有“0011”之狀態。 ・臨限值電壓為位於S3區域內之記憶體胞，係身為記憶有“1011”之狀態。 ・臨限值電壓為位於S4區域內之記憶體胞，係身為記憶有“1010”之狀態。 ・臨限值電壓為位於S5區域內之記憶體胞，係身為記憶有“1110”之狀態。 ・臨限值電壓為位於S6區域內之記憶體胞，係身為記憶有“1100”之狀態。 ・臨限值電壓為位於S7區域內之記憶體胞，係身為記憶有“1000”之狀態。 ・臨限值電壓為位於S8區域內之記憶體胞，係身為記憶有“1001”之狀態。 ・臨限值電壓為位於S9區域內之記憶體胞，係身為記憶有“0001”之狀態。 ・臨限值電壓為位於S10區域內之記憶體胞，係身為記憶有“0000”之狀態。 ・臨限值電壓為位於S11區域內之記憶體胞，係身為記憶有“0010”之狀態。 ・臨限值電壓為位於S12區域內之記憶體胞，係身為記憶有“0110”之狀態。 ・臨限值電壓為位於S13區域內之記憶體胞，係身為記憶有“0100”之狀態。 ・臨限值電壓為位於S14區域內之記憶體胞，係身為記憶有“0101”之狀態。 ・臨限值電壓為位於S15區域內之記憶體胞，係身為記憶有“1101”之狀態。 如同圖6A以及圖6B中所示一般，係能夠在臨限值電壓之各區域處而分配各記憶體胞之4位元之資料的邏輯。另外，在記憶體胞為未寫入的狀態(「刪除」之狀態)下，記憶體胞之臨限值電壓係位於S0區域內。又，於在此所示之符號中，係如同「在S0(刪除)狀態下係記憶“1111”之資料，在S1狀態下係記憶“0111”之資料」一般地，而在任意之2個的鄰接之區域間僅使資料作1個位元的變化。如此這般，圖6A以及圖6B中所示之資料編碼，係身為在任意之2個的相鄰接之區域間僅使資料作1個位元的變化之格雷碼。 在圖6A所示之本實施形態之編碼中，成為用以判定各頁面之位元值的邊界之臨限值電壓，係如下所示。 ・成為用以判定Top頁面之位元值的邊界之臨限值電壓，係為Vr1、Vr3、Vr5、Vr7、Vr12。 ・成為用以判定Upper頁面之位元值的邊界之臨限值電壓，係為Vr2、Vr6、Vr10、Vr13、Vr15。 ・成為用以判定Middle頁面之位元值的邊界之臨限值電壓，係為Vr4、Vr9、Vr11、Vr14。 ・成為用以判定Lower頁面之位元值的邊界之臨限值電壓，係為Vr8。 如此這般，成為用以判定位元值的邊界之臨限值電壓之數量(以下，稱作邊界數量)，係於Lower頁面、Middle頁面、Upper頁面、Top頁面而分別為1、4、5、5。以下，將此種編碼，使用Lower頁面、Middle頁面、Upper頁面、Top頁面之各者的邊界數量而稱作1-4-5-5編碼。 本實施形態之第1特徵，係在於：各頁面之位元值所變化的邊界數量，最大係為5。在將16個的狀態以4位元來作表現的情況時，最大邊界數量之最小值係為4，圖6之編碼，係僅較此而更多出1，位元錯誤之偏頗係變少。如此這般，由本實施形態所致之記憶體系統1，係藉由具備有第1特徵，而能夠對位元錯誤率作抑制，又，係亦能夠針對各頁面而對於位元錯誤之偏頗作抑制。 本實施形態之第2特徵，係在於：Lower頁面之邊界數量係為1個，Middle頁面之邊界數量係為4個，而成為能夠以「將Lower頁面與Middle頁面統整為一的第1階段之程式化」和「將Upper頁面與Top頁面統整為一的第2階段之程式化」之2個的階段，來進行程式化。 本實施形態之第3特徵，係在於：從藉由第1階段之程式化所產生的臨限值區域起而至藉由第2階段之程式化所產生的臨限值區域之變化幅度係為少。亦即是，此係指臨限值區域之變化幅度係為小。若是臨限值區域之變化幅度為越小，則係成為越難以受到鄰接胞間干涉的影響。針對上述之第1～第3特徵，於後再作詳細敘述。 非揮發性記憶體3之控制部22，係基於圖6A或圖6B中所示之編碼，來對於對NAND記憶體胞陣列23之程式化以及從NAND記憶體胞陣列23之讀出作控制。 3維記憶體胞，其記憶體胞之微細化係並未如同2維記憶體胞一般地進展。因此，在3維記憶體胞中，若是身為相鄰接之記憶體胞彼此之間隔為廣的世代，則胞間之相互干涉係為小。於此情況，一般而言，係採用將各記憶體胞之所有位元同時地(例如，若是將各位元分配至相異之頁面處，則係將所有頁面同時地)作程式化之手法。 在將各記憶體胞之所有位元同時地作程式化的情況時，作為資料編碼，係並不特別對於組合作限定。只要基於所有位元之資料，而決定要位置在16個的臨限值區域之何者處，並以從身為刪除狀態之S0之區域起而成為所被決定了的臨限值區域的方式來進行程式化即可。於此情況，一般而言，係採用像是4-4-3-4資料編碼一般的會使最大邊界數量取最小值一般的資料編碼。在4-4-3-4資料編碼中，在將16個的臨限值區域間之15個的邊界分配至4個的頁面處時，係對於Lower頁面分配4個邊界，並對於Middle頁面分配4個邊界，並對於Upper頁面分配3個邊界，並且對於Top頁面分配4個邊界。於此資料編碼的情況時，由於頁面間之邊界數量之偏頗係為小，因此，其結果，頁面間之位元錯誤率之偏頗係變小。此係因為，位元錯誤之原因的絕大部分，係起因於臨限值偏移至相鄰接之臨限值區域處一事所引發者，而若是具有越多的邊界數量的頁面，則位元錯誤數量會變得越多之故。此事，由於係會導致「就算是作為記憶體胞之錯誤率為相同也必須要將對於對頁面資料之錯誤作訂正一事而言所必要的ECC電路10之訂正能力強化」，因此，在為了對於針對從主機4而來之寫入要求的記憶體系統1之回應性能、成本以及消耗電力之惡化作抑制一事上，亦為有效。又，起因於邊界數量之偏頗所引發的讀出速度之偏頗亦係變小。 又，在4位元/Cell之NAND記憶體5中，由於相鄰接之臨限值區域之間隔係為狹窄，因此，起因於胞間相互干涉所導致的影響，相較於1位元/Cell或2位元/Cell之NAND記憶體5係變大。因此，在近年之微細化有所進展的世代之NAND記憶體5中，一般而言，係為了對於胞間相互干涉作抑制，而採用有使用複數之程式化階段、例如使用2個的程式化階段(以下，係亦會有單純稱作階段的情形)，來對於記憶體胞之電荷積蓄層47而逐次少量地注入電荷之程式化方法(Foggy-Fine程式化)。在此Foggy-Fine程式化中，於在第1個的階段(Foggy階段)中而進行了對於記憶體胞之寫入之後，係進行鄰接胞之寫入，之後，回到最初之記憶體胞處，並進行第2個的階段(Fine階段)之寫入。於此情況中之各階段，係身為程式化之實行單位，對應於1根的字元線WLi之記憶體胞的程式化，係藉由實行2個的程式化階段而結束。 不論是在第1個的階段之程式化中或者是在第2個的階段之程式化中，均係使用16個的臨限值區域而實行程式化。在第1個的階段之程式化結束時的臨限值區域之臨限值分布，係具備有較在最終的資料編碼中之臨限值區域之臨限值分布而更廣的寬幅。亦即是，在Foggy階段中，係進行Foggy(粗略)之寫入。在此Foggy階段之程式化中，輸入資料係4個頁面全部均為必要。Foggy階段之程式化後的臨限值分布，由於係身為相鄰接之分布為相互重疊的中間狀態，因此係並無法進行資料的讀出。在身為第2個的階段之Fine階段的程式化中，係使Foggy階段之程式化後之臨限值區域移動至在最終的資料編碼中之臨限值區域處。亦即是，在Fine階段中，係進行Fine之寫入。此Fine階段之程式化，亦同樣的，輸入資料係4個頁面全部均為必要。Fine階段之程式化後的臨限值分布，由於係身為相鄰接之分布為相互分離了的最終狀態，因此在Fine階段之程式化後，係能夠進行資料的讀出。 在4-4-3-4資料編碼的情況時，雖然邊界數量之偏頗係為少，但是，在Foggy-Fine程式化之資料輸入中，於各階段處係需要進行4個頁面之量的資料輸入。此係會導致在資料輸入中所耗費的時間之增大，並使相對於從主機4而來之寫入要求的記憶體系統1之回應性能惡化。又，在記憶體系統1內，會使用以將為了對於NAND記憶體5作輸入的資料預先作保持之寫入緩衝(第1記憶部)的緩衝量(寫入緩衝量)增大。此寫入緩衝，一般而言，係為被分配有記憶體系統1內之RAM6的一部分之區域者。 作為針對此些問題之對策，在本實施形態中，記憶體系統1，係對於具有3維構造之非揮發性記憶體3，而採用1-4-5-5資料編碼，並進而以2個的階段來實施頁面單位(page by page)之寫入。藉由此，在本實施形態中，就算是於具備有3維構造之非揮發性記憶體3中，亦能夠對於胞間相互干涉和各頁面間之位元錯誤率之偏頗作抑制，並同時將記憶體控制器2之寫入緩衝量降低。本實施形態之寫入緩衝，係將第1～第4位元(Lower頁面、Middle頁面、Upper頁面以及Top頁面之各資料)中的於第1程式化以及第2程式化時會被重複輸入的位元之資料，在開始了第2程式化之後設為能夠廢棄或無效化，並將其以外的位元之資料，在開始了第1程式化之後設為能夠廢棄或無效化。 於此，針對鄰接記憶體胞間干涉作說明。被積蓄在某1個的記憶體胞之電荷積蓄層47中的電荷，係會對於相鄰接之記憶體胞的電場造成擾亂，其結果，會賦予使在將相鄰接之記憶體胞讀出時的臨限值電壓產生變動之雜訊。起因於「在某一電場條件下而被實施有程式化(program)和驗證(verify)，並在程式化結束之後，相鄰接之記憶體胞被程式化為相異之電荷」一事，讀出精確度係會成為有所劣化。此鄰接記憶體胞間干涉，係隨著記憶體裝置之製造技術的微細化而記憶體胞之間隔縮小一事，而變得顯著。又，此鄰接記憶體胞間干涉，若是有所擴大，則會在被與同一字元線WLi上之相異之位元線作連接的鄰接記憶體胞彼此之間而產生。 鄰接記憶體胞間干涉，係能夠藉由將在「程式化以及驗證時」和「相鄰接之記憶體胞被作了程式化之後的讀出時」之間之記憶體胞之電場條件的差異縮小一事，而有所紓緩。作為將在被與同一字元線WLi上之相異之位元線作連接的鄰接記憶體胞彼此之鄰接記憶體胞間干涉作降低的其中一個方法，係存在有將程式化分割成複數之階段並以在各階段之間而不會於電荷積蓄層47內之電荷量處產生大幅度之變化的方式來實行程式化的方法。 在本實施形態之程式化序列中，1根的字元線WLi上之4位元，係藉由2個的程式化階段、亦即是藉由1st階段和2nd階段，而被程式化。各程式化階段，係身為程式化之實行單位，本實施形態之記憶體系統1，係將對於記憶體胞之4位元資料的寫入，藉由實行2個的程式化階段而結束。又，在本實施形態中，於2個的程式化階段之各者處，係使用有4位元之某些的頁面之資料。具體而言，在1st階段之程式化中，係使用有Lower頁面資料、Middle頁面以及Top頁面之資料，在2nd階段之程式化中，係使用有Middle頁面及Upper頁面以及Top頁面之資料。 圖7，係為對於第1實施形態中之程式化後的臨限值區域作展示之圖。在圖7中，係展示有在對於記憶體胞而進行了1st階段和2nd階段之程式化之後的臨限值區域。圖7之(T1)，係對於身為程式化前之初期狀態的刪除狀態之臨限值區域作展示。圖7之(T2)，係對於1st階段之程式化(第1程式化)後的臨限值區域作展示。圖7之(T3)，係對於2nd階段之程式化(第2程式化)後的臨限值區域作展示。 如同圖7之(T1)中所示一般，NAND記憶體胞陣列23之所有記憶體胞，在未寫入的狀態(「刪除」之狀態)下，係身為分布S0之狀態。非揮發性記憶體3之控制部22，係如同圖7之(T2)中所示一般，在1st階段之程式化中，係因應於寫入(記憶)至Lower頁面及Middle頁面以及Top頁面中之位元值，來針對各記憶體胞之每一者，而維持於分布S0之狀態，或者是注入電荷而使其移動至較分布S0而更上方之分布處。 具體而言，控制部22，係以「當寫入至Lower頁面及Middle頁面以及Top頁面中之位元值係均為“1”的情況時，係並不注入電荷，當寫入至Lower頁面及Middle頁面以及Top頁面處的位元值只要有任1個為“0”的情況時，則係注入電荷並使臨限值電壓移動至較高處」的方式，來進行程式化。 亦即是，當寫入至Lower頁面和Middle頁面以及Top頁面處之位元值係身為“011”的情況時，係使其移動至分布S1，又，當寫入至Lower頁面和Middle頁面以及Top頁面處之位元值係身為“101”的情況時，係使其移動至分布S4，又，當寫入至Lower頁面和Middle頁面以及Top頁面處之位元值係身為“001”的情況時，係使其移動至分布S5，又，當寫入至Lower頁面和Middle頁面以及Top頁面處之位元值係身為“100”的情況時，係使其移動至分布S8，又，當寫入至Lower頁面和Middle頁面以及Top頁面處之位元值係身為“110”的情況時，係使其移動至分布S9，又，當寫入至Lower頁面和Middle頁面以及Top頁面處之位元值係身為“000”的情況時，係使其移動至分布S12，又，當寫入至Lower頁面和Middle頁面以及Top頁面處之位元值係身為“010”的情況時，係使其移動至分布S14。 於此，較理想，分布S1、分布S4、分布S5、分布S8、分布S9、分布S12、分布S14，係以使臨限值電壓會多少有所降低的方式來將臨限值區域之寬幅擴廣並粗略地進行程式化。亦即是，係將後述之程式化電壓脈衝的上升幅度增大。藉由此，係能夠將在寫入中所需要的時間縮短。又，藉由以使臨限值電壓會多少有所降低的方式來進行程式化，係能夠以在2nd階段之程式化中而最終性地會成為特定之寬幅的方式來將臨限值分布區域之寬幅作寫入。 又，較理想，相鄰接之分布S8與分布S9、以及相鄰接之臨限值分布S12與分布S14，該些之各者之間隔，係設為較與其他之相鄰接之分布之間之間隔而更窄。此些之將間隔作了縮窄的鄰接臨限值分布彼此之寫入位元值，係Middle頁面之資料為相異。亦即是，1st階段之程式化後的資料，由於看起來係如同二元值(binary)一般，因此，係能夠進行Lower頁面與Middle頁面資料以及Top頁面之讀出，但是，係藉由將Middle頁面之資料為相異的臨限值分布之間隔縮窄，來將Lower頁面與Top頁面之資料為相異的臨限值分布之間隔確保為廣，並使Lower頁面與Top頁面之讀出時的餘裕(margin)增加。圖7之(T2)中所示的臨限值分布S0～S14，係對應於第17～第24臨限值區域。 接著，如同圖7之(T3)中所示一般，在2nd階段之程式化中，於資料之寫入中係需要Middle頁面與Upper頁面之2個頁面。又，非揮發性記憶體3之控制部22，係以在2nd階段之程式化後之臨限值分布會以使各鄰接之分布被作了分離的最終狀態而成為16值之準位的方式，來進行程式化。在2nd階段之程式化後，係能夠進行所有的頁面資料之讀出。 在2nd階段之程式化中，若是記憶體胞之臨限值的從1st階段之程式化結束時起的變化幅度越大，則鄰接胞間干涉係會變得越大。故而，較理想，係使記憶體胞之臨限值分布之變化量為最大的臨限值分布之變化量成為最小。若依據本實施例，則此最大的臨限值分布之變化量，係為3個的臨限值分布之量，而身為S0變化為S3的情況和S4變化為S7的情況以及S8變化為S11的情況。圖7之(T3)中所示的臨限值分布S0～S15，係對應於第1～第16臨限值區域。 另外，典型而言，程式化，係藉由施加1次或複數次之程式化電壓脈衝，而進行之。在複數次之程式化施加脈衝中，係使電壓值階段性地上升。在各程式化電壓脈衝之後，為了對於記憶體胞是否超越臨限值邊界準位地而作了移動一事作確認，係進行有被稱作驗證(verify)之讀出。藉由反覆進行此施加和讀出，係成為能夠使記憶體胞之臨限值移動至特定之臨限值分布的範圍之中。 另外，控制部22，雖然亦可對於1根的字元線WLi，來連續實施1st階段之程式化和2nd階段之程式化，但是，為了將鄰接記憶體胞間干涉之影響降低，係亦可橫跨複數之字元線WLi地，來以非連續性之順序而實施程式化。 圖8A，係為對於第1實施形態之程式化順序的第1例作展示之圖。圖8B，係為對於第1實施形態之程式化順序的第2例作展示之圖。圖8C，係為對於第1實施形態之程式化順序的第3例作展示之圖。在圖8A～圖8C中，為了將鄰接記憶體胞間干涉之影響縮小，係以2個的程式化階段來進行程式化。圖8A，係對於在各區塊內之各字元線處被連接有1個的字串St之NAND記憶體5中的程式化順序之其中一例作展示。又，圖8B以及圖8C，係對於在各區塊內之各字元線處被連接有4個的字串St之NAND記憶體5中的程式化順序之其中一例作展示。另外，在圖8B以及圖8C中，係將被與各字元線作了連接之4個的字串St，標記為String0～3。 若是開始進行寫入，則控制部22，係以特定之非連續性之順序來一面橫跨字元線WLi一面進行各程式化階段。亦即是，針對同一字元線之1st階段和2nd階段，係並不被連續性地實行，而是在身對某一字元線而進行了1st階段之程式化之後，針對相異之字元線而進行2nd階段之程式化。 若是在對於某一字元線而直到2nd階段為止地來結束了程式化之後，針對相鄰接之字元線而連續進行1st階段以及2nd階段之程式化，則臨限值電壓之變動量係會變大。而，若是鄰接字元線之臨限值電壓之變動量為大，則字元線間之鄰接記憶體胞間干涉係會變大。故而，為了將字元線間之鄰接記憶體胞間干涉縮小，在使字元線直到2nd階段為止地而結束了程式化之後，將鄰接字元線之臨限值電壓之變動量縮小一事係為有效。若是身為圖8A之序列，則在對於某一字元線而直到2nd階段為止地來結束了程式化之後的鄰接字元線之程式化階段，係成為僅有2nd階段。 在以圖8A之程式化順序來對於3維構造之NAND記憶體5進行程式化的情況時，若是開始進行寫入，則控制部22，係基於從處理器8而來之指示，而藉由以下之(1)～(9)所示之順序來實行程式化。控制部22，係基於從處理器8而來之指示，而進行對於NAND記憶體5之程式化，但是，以下，係將有關基於從處理器8而來之指示一事的內容之記載省略。 (1)首先，控制部22，係實施字元線WL0之1st階段的程式化ST11。 (2)接著，控制部22，係實施字元線WL1之1st階段的程式化ST12。 (3)接著，控制部22，係實施字元線WL0之2nd階段的程式化ST13。 (4)接著，控制部22，係實施字元線WL2之1st階段的程式化ST14。 (5)接著，控制部22，係實施字元線WL1之2nd階段的程式化ST15。 (6)接著，控制部22，係實施字元線WL3之1st階段的程式化ST16。 (7)接著，控制部22，係實施字元線WL2之2nd階段的程式化ST17。 (8)接著，控制部22，係實施字元線WL4之1st階段的程式化ST18。 (9)接著，控制部22，係實施字元線WL3之2nd階段的程式化ST19。 以下，同樣的，控制部22，係從圖8A之左下起朝向右上地而朝斜上方來使處理進行。如此這般，在圖8A中，非揮發性記憶體3內之複數之記憶體胞，係具備有被與第1字元線作連接的複數之第1記憶體胞、和被與和第1字元線相鄰接之第2字元線作連接的複數之第2記憶體胞，記憶體控制器2，係在對於複數之第1記憶體胞而使其進行了第1程式化之後，對於複數之第2記憶體胞而使其進行第1程式化，接著，在對於複數之第2記憶體胞而使其進行了第1程式化之後，對於複數之第1記憶體胞而使其進行第2程式化。 在以圖8B之程式化順序來對於3維構造之NAND記憶體5進行程式化的情況時，若是開始進行寫入，則控制部22，係藉由以下之(11)～(24)所示之順序來實行程式化。 (11)首先，控制部22，係實施字串St0＿字元線WL0之1st階段的程式化ST21。 (12)接著，控制部22，係實施字串St1＿字元線WL0之1st階段的程式化ST22。 (13)接著，控制部22，係實施字串St2＿字元線WL0之1st階段的程式化ST23。 (14)接著，控制部22，係實施字串St3＿字元線WL0之1st階段的程式化ST24。 (15)接著，控制部22，係實施字串St0＿字元線WL1之1st階段的程式化ST25。 (16)接著，控制部22，係實施字串St0＿字元線WL0之2nd階段的程式化ST26。 (17)接著，控制部22，係實施字串St1＿字元線WL1之1st階段的程式化ST27。 (18)接著，控制部22，係實施字串St1＿字元線WL0之2nd階段的程式化ST28。 (19)接著，控制部22，係實施字串St2＿字元線WL1之1st階段的程式化ST29。 (20)接著，控制部22，係實施字串St2＿字元線WL0之2nd階段的程式化ST210。 (21)接著，控制部22，係實施字串St3＿字元線WL1之1st階段的程式化ST211。 (22)接著，控制部22，係實施字串St3＿字元線WL0之2nd階段的程式化ST212。 (23)接著，控制部22，係實施字串St0＿字元線WL2之1st階段的程式化ST213。 (24)接著，控制部22，係實施字串St0＿字元線WL1之2nd階段的程式化ST214。 以下，同樣的，控制部22，係從圖8B之左下起朝向右上地而朝斜上方來使處理進行。另外，在圖8B中，雖係針對區塊內之字串St為4個的情況來作了說明，但是，區塊內之字串St，係亦可為3個以下，亦可為5個以上。 在以圖8C之程式化順序來對於3維構造之NAND記憶體5進行程式化的情況時，若是開始進行寫入，則控制部22，係藉由以下之(31)～(50)所示之順序來實行程式化。 (31)首先，控制部22，係實施字串St0＿字元線WL0之1st階段的程式化ST31。 (32)接著，控制部22，係實施字串St1＿字元線WL0之1st階段的程式化ST32。 (33)接著，控制部22，係實施字串St2＿字元線WL0之1st階段的程式化ST33。 (34)接著，控制部22，係實施字串St3＿字元線WL0之1st階段的程式化ST34。 (35)首先，控制部22，係實施字串St0＿字元線WL1之1st階段的程式化ST35。 (36)接著，控制部22，係實施字串St1＿字元線WL1之1st階段的程式化ST36。 (37)接著，控制部22，係實施字串St2＿字元線WL1之1st階段的程式化ST37。 (38)接著，控制部22，係實施字串St3＿字元線WL1之1st階段的程式化ST38。 (39)接著，控制部22，係實施字串St0＿字元線WL0之2nd階段的程式化ST39。 (40)接著，控制部22，係實施字串St1＿字元線WL0之2nd階段的程式化ST310。 (41)接著，控制部22，係實施字串St2＿字元線WL0之2nd階段的程式化ST311。 (42)接著，控制部22，係實施字串St3＿字元線WL0之2nd階段的程式化ST312。 (43)接著，控制部22，係實施字串St0＿字元線WL2之1st階段的程式化ST313。 (44)接著，控制部22，係實施字串St1＿字元線WL2之1st階段的程式化ST314。 (45)接著，控制部22，係實施字串St2＿字元線WL2之1st階段的程式化ST315。 (46)接著，控制部22，係實施字串St3＿字元線WL2之1st階段的程式化ST316。 (47)接著，控制部22，係實施字串St0＿字元線WL1之2nd階段的程式化ST317。 (48)接著，控制部22，係實施字串St1＿字元線WL1之2nd階段的程式化ST318。 (49)接著，控制部22，係實施字串St2＿字元線WL1之2nd階段的程式化ST319。 (50)接著，控制部22，係實施字串St3＿字元線WL1之2nd階段的程式化ST320。 另外，在圖8C中，雖係針對區塊內之字串St為4個的情況來作了說明，但是，區塊內之字串St，係亦可為3個以下，亦可為5個以上。 如此這般，就算是字串St成為複數，在1個的字串St內之字元線WLi的各程式化階段之程式化的順序，亦係與字串St為1個的情況時相同。於在區塊內存在有複數之字串St的3維構造之非揮發性記憶體3的情況時，字元線WLi與字串St之組合位置的程式化，一般而言，係先對於相異之字串St內之同一字元線編號進行程式化，之後前進至下一個的字元線編號處。在依循此種順序的情況時，若是將圖8A作字串St之數量之量的結合，則例如係會成為如同圖8B或圖8C一般的順序。 於此，針對依循於由第1實施形態所致的程式化順序之寫入程序的其中一例，使用圖9～圖11而作說明。在圖9～圖11中，係對於依循在圖8B或圖8C中所示之程式化順序的情況時之寫入程序作展示。如同前述一般，記憶體控制器2，由於係以非連續性之順序來一面橫跨字元線WLi一面使程式化階段前進，因此，係將某些字元線WLi之整批(於此，係為區塊)作為程式化序列的整體而實行程式化。 圖9，係為對於由第1實施形態所致的1個區塊之量之全體的寫入程序之第1例作展示之流程圖。於此之1個區塊，假設係具備有字元線WL0～WLn(n為自然數)之n＋1根的字元線WLi。圖10，係為對於由第1實施形態所致的1st階段中之寫入程序作展示之流程圖，圖11，係為對於由第1實施形態所致的2nd階段中之寫入程序作展示之流程圖。 如同圖9中所示一般，若是開始進行寫入，則控制部22，係實行字串St0＿字元線WL0之1st階段的程式化(步驟S10)。接著，控制部22，係實施字串St1＿字元線WL0之1st階段的程式化(步驟S20)。之後，控制部22，係對於各字串St而實行與步驟S10、S20相同的處理。接著，控制部22，係實施字串St3＿字元線WL0之1st階段的程式化(步驟S30)。 進而，控制部22，係實施字串St0＿字元線WL1之1st階段的程式化(步驟S40)。接著，控制部22，係實施字串St0＿字元線WL0之2nd階段的程式化(步驟S50)。接著，控制部22，係實施字串St1＿字元線WL1之1st階段的程式化(步驟S60)。之後，控制部22，係對於各字串St之各字元線WLi而反覆進行如同步驟S40、S50、S60一般的處理。 接著，控制部22，係實施字串St0＿字元線WLn之1st階段的程式化(步驟S70)。接著，控制部22，係實施字串St0＿字元線WLn-1之2nd階段的程式化(步驟S80)。之後，控制部22，係對於各字串St之各字元線WLi而反覆進行如同步驟S70、S80一般的處理。 接著，控制部22，係實施字串St3＿字元線WLn-1之2nd階段的程式化(步驟S90)。接著，控制部22，係實施字串St0＿字元線WLn之2nd階段的程式化(步驟S100)。接著，控制部22，係實施字串St1＿字元線WLn之2nd階段的程式化(步驟S110)。之後，控制部22，係對於各字串St而實行與步驟S100、S110相同的處理。接著，控制部22，係實施字串St3＿字元線WLn之2nd階段的程式化(步驟S120)。 圖10，係為對於1st階段之寫入程序之第1例作展示之流程圖。在1st階段之程式化中，首先，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Lower頁面資料的輸入開始指令(步驟S210)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Lower頁面資料(步驟S215)。接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Middle頁面資料的輸入開始指令(步驟S220)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Middle頁面資料(步驟S225)。接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Top頁面之資料的輸入開始指令(步驟S230)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Top頁面資料(步驟S235)。進而，係從記憶體控制器2對於非揮發性記憶體3而被輸入有1st階段之程式化實行指令(步驟S240)，並藉由此而成為chip_busy(步驟S245)。 在進行資料寫入時，係決定臨限值電壓Vth(步驟S250)，並被施加有1～複數次的程式化電壓脈衝(步驟S255)。之後，為了對於記憶體胞是否超越臨限值邊界準位地而作了移動一事作確認，係進行有資料讀出(驗證)(步驟S260)。 進而，係判定在Lower頁面及Middle頁面以及Top頁面中之資料的失敗位元(fail-bit)數量是否為較判定基準(criteria)而更小(步驟S265)。當資料的失敗位元數量係為判定基準以上的情況時，從程式化脈衝施加起而至criteria判定為止之處理(步驟S255～S265)係被反覆進行。而，若是資料的失敗位元數量成為較判定基準而更小，則係成為chip_ready(步驟S270)。如此這般，藉由反覆進行施加和讀出以及確認，係成為能夠使記憶體胞之臨限值移動至特定之臨限值分布的範圍之中。 另外，如同上述一般，在1st階段寫入時之程式化電壓脈衝施加後的讀出準位，係亦能夠與2nd階段寫入後之讀出準位有些許差異，較理想，係身為較2nd階段寫入後之讀出準位而更低的準位。亦即是，係身為Vr1’≦Vr1、Vr4’≦Vr4、Vr5’≦Vr5、Vr8’≦Vr8、Vr9’≦Vr9、Vr12’≦Vr12、Vr14’≦Vr14。 又，在1st階段寫入中之程式化電壓脈衝施加後的讀出中，係亦可將由Vr9’所致之讀出和由Vr14’所致之讀出省略，Vr9’，係在通過了Vr8’之讀出之後，於施加了某規定次數之程式化電壓脈衝之後，設為寫入結束，Vr14’，係在通過了Vr13’之讀出之後，於施加了某規定次數之程式化電壓脈衝之後，設為寫入結束。 此係因為，如同上述一般，藉由將在1st階段之程式化後的資料中之Middle頁面之資料為相異的臨限值區域之間隔縮窄，係能夠將在2nd階段寫入時而進行讀出的Lower頁面與Top頁面之資料為相異的臨限值區域之間隔，就算是僅藉由「施加某規定次數之程式化電壓脈衝」的簡單之控制也能夠充分確保為廣。 進而，係亦可將Vr8’和Vr9’和Vr12’以及Vr14’的程式化電壓脈衝施加後之讀出省略，並在通過了Vr5’之讀出之後，於施加了各別之某規定次數之程式化電壓脈衝之後，設為寫入結束。除此之外，進而，係亦可將Vr4’、Vr5’、Vr8’、Vr9’、Vr12’、Vr14’的程式化電壓脈衝施加後之讀出省略，並在通過了Vr1’之讀出之後，於施加了各別之某規定次數之程式化電壓脈衝之後，設為寫入結束。 圖11，係為對於2nd階段之寫入程序之第1例作展示之流程圖。在2nd階段之程式化中，首先，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Middle頁面之資料的輸入開始指令(步驟S310)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Middle頁面之資料(步驟S320)。 接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Upper頁面之資料的輸入開始指令(步驟S330)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Upper頁面之資料(步驟S340)。接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有2nd階段之程式化實行指令(步驟S350)，並藉由此而成為chip_busy(步驟S360)。 之後，控制部22，係進行身為IDL(Internal Data Load)之Lower頁面以及Top頁面資料的讀出(步驟S370)。之後，基於之前所輸入的Middle頁面資料和由IDL所致之Lower頁面以及Top頁面之資料，Upper頁面之程式化目標的Vth(臨限值電壓)係被決定(步驟S380)。之後，使用被決定了的Vth，對於Upper頁面之資料寫入係被進行。更具體而言，係以會成為所被決定了的臨限值電壓的方式，來將複數之程式化脈衝的電壓值逐次些許提高並進行寫入(步驟S390)。到達了目的之臨限值電壓的記憶體胞，係被從寫入對象而去除。 之後，係將寫入了的資料讀出(步驟S400)，並判定失敗位元數量是否為較判定基準(criteria)而更小(步驟S410)。當資料的失敗位元數量係為判定基準以上的情況時，從程式化脈衝施加起而至criteria判定為止之處理(步驟S390～S410)係被反覆進行。而，若是資料的失敗位元數量成為較判定基準而更小，則係成為chip_ready(步驟S420)。 於此，在本實施形態中，係具備有2個的特徵。第1特徵係在於，Middle頁面之資料，係在1st階段之程式化中而已被輸入，1st程式化後之臨限值區域，係身為亦包含有Middle頁面之資料的寫入狀態，但是，在2nd階段之程式化中，仍係再度輸入有Middle頁面之資料。第2特徵係在於，在1st階段之程式化中，該Middle頁面之資料所作切換的鄰接臨限值區域彼此，其間隔係變窄，相反的，Lower頁面之資料與Top頁面之資料所作切換的鄰接臨限值分布彼此，其間隔係變廣。藉由此，係能夠將藉由IDL所讀出的Lower頁面以及Top頁面資料之信賴性提高。另一方面，Middle頁面之資料，若是藉由IDL而將資料作了讀出，則係會有信賴性降低之虞，但是，在本實施形態中，由於係將在1st階段程式化中所使用了的Middle頁面之資料再度作輸入，因此係並不會有信賴性降低的問題。 進而，控制部22，係亦能夠為了將IDL之讀出資料的信賴性提升，而進行複數次數之讀出，並在晶片內之頁面緩衝處，採用此讀出結果之多數決，而作為接下來的寫入資料而作使用。當然的，控制部22，在通常之讀出動作時，亦能夠進行複數次數之讀出並在晶片內採用此讀出結果之多數決，而作為對於外部之讀出資料而作使用。 圖12，係為用以對於複數次數之讀出結果的多數決處理作說明的圖。在圖12中，係作為將特定之頁面之資料作了讀出後的結果，而將正確的位元以圈記號(○)來作標示，並將錯誤的位元以叉記號(×)來作標示。又，在圖12中，係對於進行了3次的讀出的情況時之多數決之結果作展示。 在各位元處，多數決之結果被判斷為錯誤的情形，係為(a)3次均為錯誤的情況、和(b)2次為錯誤的情況。若是將各位元為錯誤的機率設為p，則在p＝0.2的情況時，(a)3次錯誤的機率，係為p×p×p＝0.2×0.2×0.2，(b)2次錯誤的機率，係為(1-p)×p×p＝(1-0.2)×0.2×0.2。 故而，3次之多數決之結果被判斷為錯誤的機率，係為(p×p×p)＋3×(1-p)×p×p＝0.104。如此這般，控制部22，係藉由在晶片內之頁面緩衝24處進行複數次數之讀出結果之多數決處理，而成為能夠將讀出資料之信賴性提升。 進而，控制部22，係亦可為了將在字元線WLn之2nd階段寫入中的IDL之讀出資料之信賴性提升，而因應於在WLn＋1之1st階段寫入中而進行了寫入的資料或者是臨限值電壓，來改變在IDL處之字元線WLn之讀出電壓並進行讀出。 又，進而，控制部22，係亦可為了將在字元線WLn之2nd階段寫入中的IDL之讀出資料之信賴性提升，而因應於在字元線WLn＋1之1st階段寫入中而進行了寫入的資料或者是臨限值電壓，來改變在IDL處之字元線WLn＋1之非選擇電壓並進行讀出。此時，係亦可同時地改變字元線WLn之讀出電壓並進行讀出。 在進行對於Upper頁面之資料寫入時，係被施加有1～複數次的程式化電壓脈衝。之後，為了對於記憶體胞是否超越臨限值邊界準位地而作了移動一事作確認，係進行有Upper頁面之資料讀出(驗證)。此時之讀出準位，係身為特定之準位。 進而，係判定在Upper頁面中之資料的失敗位元數量是否為較判定基準而更小。當在Upper頁面中之資料的失敗位元數量係為判定基準以上的情況時，從程式化電壓脈衝施加起而至驗證為止之處理係被反覆進行。而，若是資料的失敗位元數量成為較判定基準而更小，則係成為chip_ready。 於此，針對在圖11中所示的寫入程序之變形例作說明。圖13，係為對於在第1實施形態的2nd階段中之寫入程序之變形例作展示之流程圖。另外，在圖13之流程圖中，係追加有「針對將在1st階段中所作了程式化的資料作了讀出之IDL資料，而進行錯誤訂正，並回送至非揮發性記憶體3處」之程序。具體而言，首先，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Lower頁面之讀出指令(步驟S510)。藉由此，係成為chip_ready(步驟S512)。接著，控制部22，係將Lower頁面資料之讀出藉由Vr8’之臨限值電壓來進行。之後，控制部22，係基於在Vr8’之臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S514)。之後，係成為chip_ready(步驟S516)。 若是將控制部22所讀出了的Lower頁面資料作輸出(步驟S518)，則此Lower頁面資料，係被送訊至ECC電路10處(步驟S520)。藉由此，ECC電路10係對於Lower頁面資料進行ECC訂正(步驟S522)。 接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Lower頁面之資料的輸入開始指令(步驟S524)。藉由此，ECC電路10係對於非揮發性記憶體3而輸入Lower頁面之資料(步驟S526)。 接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Top頁面之讀出指令(步驟S528)，並藉由此而成為chip_busy(步驟S530)。之後，控制部22，係將Top頁面資料之讀出藉由Vr2’和Vr10’之臨限值電壓來進行。之後，控制部22，係基於在Vr1’和Vr4’和Vr8’以及Vr12’之臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S532)。之後，係成為chip_ready(步驟S534)。 若是將控制部22所讀出了的Top頁面資料作輸出(步驟S536)，則此Top頁面資料，係被送訊至ECC電路10處(步驟S538)。藉由此，ECC電路10係對於Top頁面資料進行ECC訂正(步驟S540)。接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Top頁面之資料的輸入開始指令(步驟S542)。藉由此，ECC電路10係對於非揮發性記憶體3而輸入Top頁面之資料(步驟S544)。 之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有Middle頁面資料的輸入開始指令。(步驟S546)。後續之步驟，係與圖11之程序相同。程式化目標之臨限值電壓Vth，係基於從ECC電路10而來之Lower頁面資料以及Top頁面資料、和再度被作了輸入的Middle頁面之資料、以及新輸入了的Upper頁面之資料，來決定程式化目標的臨限值電壓Vth。 在上述之2nd階段之程式化中，對於非揮發性記憶體3之資料輸入，係僅為Middle頁面和Upper頁面之2個頁面。但是，在此2nd階段中，於身為記憶體胞之程式化之目的地的臨限值電壓Vth處，係需要亦包含有Lower頁面、Top頁面(在開始2nd階段之前的臨限值電壓Vth)之4個頁面之量的資料。因此，在此階段之程式化中，作為前置處理，控制部22，係進行「首先將Lower頁面資料和Top頁面資料讀出，並將該資料藉由更進而被作了輸入的Middle頁面與Upper頁面來作合成並決定程式化目標之臨限值電壓Vth」之動作。另外，在2nd階段之驗證時之讀出準位，係亦可為與2nd階段寫入後之讀出準位有些許的差異。 於此，針對採用了4-3-4-4資料編碼之Foggy-Fine程式化的處理程序和本實施形態的程式化處理程序之間之比較作說明。圖14A，係為用以對於在採用了4-3-4-4資料編碼之Foggy-Fine程式化中之寫入緩衝的資料量作說明之圖。圖14B，係為對於在本實施形態中之寫入緩衝的資料量作說明之圖。圖14B，係對於採用了1-4-5-5資料編碼之例作展示。 在圖14A以及圖14B中，於上段側處，係對於區塊寫入之資料輸入和程式化實行之時序表作展示，於下段側處，係對於為了將資料在寫入緩衝內作資料保持所需要的期間之時序表作展示。另外，在圖14A以及圖14B中，為了使說明簡單化，係針對1個區塊內的字串St之個數為1的情況作展示。當字串St為複數的情況時，係需要字串St之個數倍數的寫入緩衝之資料量。 在4-3-4-4資料編碼之Foggy-Fine程式化的情況時，在身為第1個的階段之Foggy階段中，係進行有4個頁面之量的資料輸入、和此4個頁面之量的程式化(Foggy階段之程式化)。又，在4-3-4-4資料編碼之Foggy-Fine程式化的情況時，在身為第2個的階段之Fine階段中，亦係進行有4個頁面之量的資料輸入、和此4個頁面之量的程式化(Fine階段之程式化)。 而，在各字元線WL0、WL1、WL2、…處，直到於Fine階段處而程式化被開始為止，係有必要將在Foggy階段中而被作了寫入的4個頁面之量之資料，預先儲存在寫入緩衝中。 在Foggy-Fine程式化中，亦同樣的，為了將鄰接記憶體胞間干涉降低，Lower/Middle/Upper/Top之4個頁面之量的資料係並不被連續地作寫入。例如，在對於字元線WL0之Foggy階段被作了實行之後，於對於字元線WL0之Fine階段被實行之前，對於與字元線WL0相鄰接之字元線WL1的Foggy階段係被實行。又，在對於字元線WL0之Foggy階段被作了實行之後，於對於字元線WL1之Fine階段被實行之前，對於與字元線WL1相鄰接之字元線WL2的Foggy階段係被實行。於此方法的情況時，直到最終之身為第2個的Fine階段之資料輸入結束為止，係有必要將Lower/Middle/Upper/Top之4個頁面之量之資料，預先保持在寫入緩衝內。又，為了將鄰接記憶體胞間干涉降低，係有必要將在複數之字元線WLi處的資料預先保持於寫入緩衝內。例如，在對於字元線WL2而Foggy階段被實行時，係有必要使針對字元線WL1之3個頁面之量的資料和針對字元線WL2之3個頁面之量的資料被保持於寫入緩衝內。如此這般，在4-3-4-4資料編碼之Foggy-Fine程式化的情況時，係有必要將最大8個頁面之量的資料保持在寫入緩衝內。 如同圖14B中所示一般，在本實施形態之程式化中，例如係以1-4-5-5資料編碼而使用有2階段的程式化。在本實施形態之程式化中，於1st階段中，係進行有3個頁面之量(Lower頁面和Middle頁面以及Top頁面)的資料輸入、和此3個頁面之量的程式化(1st程式化)。又，在本實施形態之程式化的情況時，於2nd階段中，係進行有2個頁面之量(Middle頁面以及Upper頁面)的資料輸入、和Upper頁面之1個頁面之量的程式化(2nd程式化)。 而，在各字元線WL0、WL1、WL2、…處，除了在雙方的階段中均被作輸入的Middle頁面以外，係只要在各階段之資料輸入時將資料預先儲存在寫入緩衝中即可，若是程式化被開始，則係亦可將資料從寫入緩衝內而刪除。例如，若是在1st階段處而資料被作輸入，則此資料係被儲存在寫入緩衝內。而，若是在1st階段處而程式化被開始，則係亦可將預先被儲存在寫入緩衝內之Lower頁面與Top頁面之資料刪除。同樣的，若是在2nd階段處而資料被作輸入，則此資料係被儲存在寫入緩衝內。而，若是在2nd階段處而程式化被開始，則係亦可將預先被儲存在寫入緩衝內之資料全部刪除。因此，在本實施形態之程式化的情況時，有必要預先保持在寫入緩衝內之資料，就算是最大亦係僅為4個頁面之量的資料。 在本實施形態之程式化中，亦同樣的，為了將鄰接記憶體胞間干涉降低，Lower/Middle/Upper/Top之4個頁面之量的資料係並不被連續地作寫入。例如，在對於字元線WL0之1st階段被作了實行之後，於對於字元線WL0之2nd階段被實行之前，對於與字元線WL0相鄰接之字元線WL1的1st階段係被實行。同樣的，在對於字元線WL1之1st階段被作了實行之後，於對於字元線WL1之2nd階段被實行之前，對於與字元線WL1相鄰接之字元線WL2的1st階段係被實行。 如此這般，在本實施形態中，由於除了Middle頁面以外的頁面資料，係僅在1次的階段之程式化中而為必要，因此，若是該資料輸入結束，則係成為能夠將寫入緩衝內之資料刪除。因此，在本實施形態中，有必要預先同時保持在寫入緩衝內之頁面數量係僅需要少量即可。 被對於非揮發性記憶體3而進行程式化的頁面資料，係先在RAM6內之寫入緩衝中暫時被作保持，之後在程式化時被資料輸入至非揮發性記憶體3中。在本實施形態中，由於係成為能夠將此RAM6之必要容量縮小，因此係能夠謀求成本之削減。 又，在使用Foggy-Fine程式化時，由於係必須要將所有的頁面資料之資料傳輸進行2次，因此係會耗費傳輸時間，並且亦成為需要更多的傳輸時之消耗電力。在本實施形態中，除了Middle頁面以外的頁面資料，由於各頁面係個別以1次的資料傳輸而結束，因此係成為能夠將傳輸時間以及電力消耗抑制為1/2程度。 於此，針對頁面讀出處理作說明。頁面讀出之方法，係基於針對包含有讀出對象頁面之字元線WLi的程式化乃身為2nd階段之寫入前還是寫入後一事而有所相異。 在2nd階段寫入前的情況時，所被作記錄之資料係僅有Lower頁面和Middle頁面以及Top頁面為有效。因此，控制部22，在讀出頁面係身為Lower頁面和Middle頁面以及Top頁面的情況時，係從記憶體胞而將資料讀出，但是，在其他之頁面(具體而言，Upper頁面)的情況時，係並不進行記憶體胞讀出動作，並進行作為讀出資料而強制性地全部輸出“1”之控制。 另一方面，在直到2nd階段為止而均結束了的字元線WLi的情況時，控制部22，係不論是讀出頁面為Top/Upper/Middle/Lower頁面之何者，均將記憶體胞讀出。於此情況，由於依存於讀出頁面乃身為何者之頁面一事，所需要的讀出電壓係為相異，因此，控制部22，係依循於被作了選擇的頁面而僅進行必要之讀出。 以下，針對頁面讀出之具體性的處理程序作說明。圖15，係為對於在由第1實施形態所致之記憶體系統1中之於直到1st階段為止之程式化為結束(2nd階段的程式化係尚未結束)的字元線處之頁面讀出的處理程序作展示之流程圖。若依據圖6中所示之1-4-5-5資料編碼，則由於Lower頁面資料所變化的臨限值狀態間之邊界係為1個，因此，控制部22，係根據臨限值為位置於藉由該邊界而被作了分離之2個的範圍之何者處一事，來決定資料。例如，當臨限值電壓為較Vr8’而更小的情況時，控制部22，係進行作為記憶體胞之資料而輸出“1”之控制。另一方面，當臨限值電壓為較Vr8’而更大的情況時，控制部22，係進行作為記憶體胞之資料而輸出“0”之控制。 又，由於Middle頁面資料所變化的臨限值狀態間之邊界係為3個，因此，控制部22，係根據臨限值為位置於藉由該些之邊界而被作了分離之4個的範圍之何者之中一事，來決定資料。又，由於Top頁面資料所變化的臨限值狀態間之邊界係為4個，因此，控制部22，係根據臨限值為位置於藉由該些之邊界而被作了分離之5個的範圍之何者之中一事，來決定資料。 如同圖15中所示一般，在2nd階段寫入前之字元線WLi的情況時，控制部22，係對讀出頁面作選擇(步驟S610)。當讀出頁面係為Lower頁面的情況時，控制部22，係藉由1個的讀出電壓而進行讀出(步驟S612)。此電壓，係為Vr8，但是，如同前述一般，在身為2nd階段寫入前之字元線的情況時，如同圖8(T2)中所示一般，係亦可具有讀出電壓與臨限值電壓之餘裕地，而例如為Vr8’。之後，控制部22，係基於在Vr8之臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S614)。 又，當讀出頁面係為Middle頁面的情況時，控制部22，係藉由3個的讀出電壓而進行讀出(步驟S616、S618、S620)。此電壓，係如同前述一般，而為Vr4和Vr9以及Vr14，但是，在身為2nd階段寫入前之字元線的情況時，如同圖8(T2)中所示一般，係亦可具有讀出電壓與臨限值電壓之餘裕地，而例如替代該些而分別設為Vr4’和Vr9’以及Vr14’。之後，控制部22，係基於在Vr4之臨限值電壓下的讀出結果和在Vr9之臨限值電壓下的讀出結果以及在Vr14之臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S622)。於此，如同前述一般，由於Middle頁面之資料為相異的臨限值分布的間隔係為窄，而Middle頁面之讀出餘裕係變窄，因此，讀出資料之值係會有信賴性顯著地惡化的可能性，而亦可將2nd階段寫入前之Middle頁面資料定義為無效。於此情況，當讀出頁面係為Middle頁面的情況時，控制部22，係亦可進行作為記憶體胞之輸出資料而強制性地全部輸出“1”之控制。 又，當讀出頁面係為Upper頁面的情況時，由於在1st程式化中係並未進行有Upper頁面之程式化，因此，控制部22，係作為輸出資料而強制性地全部輸出“1”(步驟S624)。 又，當讀出頁面係為Top頁面的情況時，控制部22，係藉由4個的讀出電壓而進行讀出(步驟S626、S628、S630、S632)。此電壓，係如同前述一般，而為Vr1和Vr4和Vr8以及Vr12，但是，在身為2nd階段寫入前之字元線的情況時，如同圖8(T2)中所示一般，係亦可具有讀出電壓與臨限值電壓之餘裕地，而例如替代該些而分別設為Vr1’和Vr4’和Vr8’以及Vr12’。之後，控制部22，係基於在Vr1之臨限值電壓下的讀出結果和在Vr4之臨限值電壓下的讀出結果和在Vr8之臨限值電壓下的讀出結果以及在Vr12之臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S634)。 圖16A，係為對於在第1實施形態之記憶體系統1中的於直到2nd階段為止之程式化為結束的字元線處之頁面讀出的處理程序作展示之流程圖。在直到2nd階段為止地而結束了程式化之字元線WLi的情況時，控制部22，係對讀出頁面作選擇(步驟S650)。當讀出頁面係為Lower頁面的情況時，控制部22，係藉由Vr8之1個的臨限值電壓而進行讀出(步驟S652)。之後，控制部22，係基於在Vr8之1個的臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S654)。 又，當讀出頁面係為Middle頁面的情況時，控制部22，係藉由Vr4、Vr9、Vr11以及Vr14之臨限值電壓而進行讀出(步驟S656、S658、S660、S662)。之後，控制部22，係基於在Vr4、Vr9、Vr11以及Vr14之臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S664)。 又，當讀出頁面係為Upper頁面的情況時，控制部22，係藉由Vr2、Vr6、Vr10、Vr13以及Vr15之臨限值電壓而進行讀出(步驟S666、S668、S670、S672、S674)。之後，控制部22，係基於在Vr2、Vr6、Vr10、Vr13以及Vr15之臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S676)。 又，當讀出頁面係為Top頁面的情況時，控制部22，係藉由Vr1、Vr3、Vr5、Vr7以及Vr12之臨限值電壓而進行讀出(步驟S678、S680、S682、S684、S686)。之後，控制部22，係基於在Vr1、Vr3、Vr5、Vr7以及Vr12之臨限值電壓下的讀出結果，來將所讀出了的資料之值決定為“0”或“1”(步驟S688)。 另外，關於對於字元線WLi的程式化乃身為2nd階段之寫入結束前還是後一事，係能夠以記憶體控制器2來進行管理以及辨識。在記憶體系統1中，由於記憶體控制器2係進行程式化之控制，因此，只要使記憶體控制器2將該進度狀況預先作記錄，則記憶體控制器2係能夠容易地對於非揮發性記憶體3之何者之位址乃是身為何種之程式化狀態一事作參照。於此情況，記憶體控制器2，在從非揮發性記憶體3而進行讀出時，係辨識出包含有對象頁面位址之字元線WLi乃身為何種之程式化狀態，並發行與所辨識出之狀態相對應的讀出指令。又，作為其他方法，係亦能夠在各字元線WLi之每一者處分別設置旗標胞，並在2nd階段寫入時，對旗標胞作寫入，而因應於旗標胞之資料，來藉由非揮發性記憶體3而對於是身為2nd階段寫入結束前還是後一事作管理、辨識。 FIG. 1 is a block diagram showing the schematic configuration of the memory system 1 according to the first embodiment. The memory system 1 of FIG. 1 includes a memory controller 2 and a non-volatile memory 3 . The memory system 1 of FIG. 1 can be connected to a host processor (hereinafter, simply referred to as a host) 4 . The host 4 is, for example, an electronic device such as a personal computer or a portable terminal. The non-volatile memory 3 is a memory that stores data in a non-volatile manner, and includes, for example, a NAND flash memory (hereinafter, also referred to as a NAND memory) 5 . In this embodiment, the non-volatile memory 3 is a NAND having 4bit/Cell (QLC: Quad Level Cell) having a memory cell capable of storing 4-bit data at each memory cell An example of the memory 5 will be described. The nonvolatile memory 3 according to the present embodiment has a three-dimensional structure in which memory cells are three-dimensionally stacked. The non-volatile memory 3 has a plurality of memory cells, and the plurality of memory cells respectively have 16 threshold value regions, and can store the memory expressed by the 1st to 4th bits. For 4-bit data, the 16 threshold value areas include the first threshold value area representing the deletion state of the data being deleted, and the voltage level is higher than the first threshold value area It also represents the 2nd to 16th threshold value areas of the write state in which data is written. For example, the first bit is the lowest bit, the second bit is the second smallest middle bit, the third bit is the second largest upper bit , the aforementioned fourth bit is the top bit. The memory controller 2 controls the writing of data in the non-volatile memory 3 according to the writing command from the host 4 . In addition, the memory controller 2 controls the readout of data from the non-volatile memory 3 in accordance with the readout command from the host computer 4 . The memory controller 2 includes a RAM (Random Access Memory) 6 , a ROM (Read Only Memory) 7 , a processor 8 , a host interface 9 , an ECC (Error Check and Correct) circuit 10 and a memory interface 11 . The RAM 6 , the processor 8 , the host interface 9 , the ECC circuit 10 and the memory interface 11 are connected by a common internal bus bar 12 . As will be described later, in the memory controller 2 of the present embodiment, the non-volatile memory 3 is subjected to the first programming for writing the data of the first bit, the second bit, and the fourth bit. After that, the non-volatile memory 3 is subjected to the second programming in which the data of the third bit is written. The number of the first boundaries used in the determination of the value of the data of the first bit among the 15 boundaries existing between the adjacent threshold value areas in the 1st to 16th threshold value areas , The number of 2nd boundaries used in the determination of the value of the 2nd bit data, The number of the 3rd boundaries used in the determination of the value of the 3rd bit data, The number of the 3rd boundaries used in the determination of the value of the 4th bit The number of the fourth boundary in the determination of the value of the data, the largest value of these numbers is 5, and the second largest value is 4. The memory controller 2 is configured so that the threshold value area in the memory cell becomes the representative data corresponding to the data of the 1st bit, the 2nd bit and the 4th bit as the deleted data The 17th threshold value area and the voltage level of the deletion state are higher than the 17th threshold value area and represent one of the 18th to 24th threshold value areas of the write state in which data is written. The first programming is performed on the nonvolatile memory 3 in the manner of the threshold value region. The memory controller 2 is configured so that the threshold value area in the memory cell is changed from the threshold value of any one of the 17th to 24th threshold value areas in response to the data of the third bit The second programming of the nonvolatile memory 3 is performed in such a manner that the area becomes the threshold value area of any one of the two threshold value areas of the first to sixteenth threshold value areas. The number of threshold value areas between the threshold value area where the voltage level is the lowest and the threshold value area where the voltage level is the highest in the two threshold value areas is within two. The memory controller 2 is configured to input the data of the second bit and the data of the third bit to the non-volatile memory 3 when the second programming is performed on the non-volatile memory 3 . More specifically, the memory controller 2 makes the threshold value regions adjacent to the 15 borders between the 16 threshold value regions (the first to the 16th threshold value regions). The value of the 1st bit is the number of different boundaries, the value of the 2nd bit is the number of different boundaries, the value of the 3rd bit is the number of different boundaries, and the value of the 4th bit The value is the number of different boundaries, in sequence (1, 4, 5, 5), (1, 5, 4, 5) or (3, 3, 4, 5), to make the non-volatile The first programming and the second programming are performed on the sexual memory. Alternatively, in the memory controller 2 of the present embodiment, the non-volatile memory 3 is subjected to the first programming for writing the data of the first bit, the second bit, and the fourth bit. , to make the non-volatile memory 3 perform the second programming of writing the data of the third bit. The number of the first boundaries used in the determination of the value of the data of the first bit among the 15 boundaries existing between the adjacent threshold value areas in the 1st to 16th threshold value areas , The number of 2nd boundaries used in the determination of the value of the 2nd bit data, The number of the 3rd boundaries used in the determination of the value of the 3rd bit data, The number of the 3rd boundaries used in the determination of the value of the 4th bit The number of the fourth boundary in the determination of the value of the data is (3, 5, 2, 5) in order. The memory controller 2 is configured so that the threshold value area in the memory cell becomes the representative data corresponding to the data of the 1st bit, the 2nd bit and the 4th bit as the deleted data The 17th threshold value area and the voltage level of the deletion state are higher than the 17th threshold value area and represent one of the 18th to 24th threshold value areas of the write state in which data is written. The first programming is performed on the nonvolatile memory 3 in the manner of the threshold value region. The memory controller 2 is configured so that the threshold value area in the memory cell is changed from the threshold value of any one of the 17th to 24th threshold value areas in response to the data of the third bit The second programming of the nonvolatile memory 3 is performed in such a manner that the area becomes the threshold value area of any one of the two threshold value areas of the first to sixteenth threshold value areas. The number of threshold value areas between the threshold value area where the voltage level is the lowest and the threshold value area where the voltage level is the highest in the two threshold value areas is within two. The memory controller 2 is configured to input the data of the second bit and the data of the third bit to the non-volatile memory 3 when the second programming is performed on the non-volatile memory 3 . The memory controller 2 can also set the voltage level difference between the two threshold value areas that make the data value of the second bit in the 17th to 24th threshold value areas different. It becomes smaller than the difference in voltage level between the two threshold value regions with the data value of the 1st bit different and becomes the value of the 4th bit data which is different from the two The first programming of the non-volatile memory is performed in such a way that the difference in voltage level between the threshold value regions is smaller. Alternatively, the memory controller 2 can also use the interval between the two threshold value regions in the first programming, which are different from the data value of the second bit, so that the A method in which the interval between adjacent threshold value areas becomes wider among the 4 threshold value areas obtained by performing the second programming with the data of the third bit. , for the second programming of the non-volatile memory. The host interface 9 outputs commands received from the host 4 , user data (writing data), and the like to the internal bus bar 12 . In addition, the host interface 9 transmits the user data read from the non-volatile memory 3 or the response from the processor 8 to the host 4 . The memory interface 11 is based on the instructions of the processor 8 , and performs the processing of writing user data to the non-volatile memory 3 and the processing of reading user data from the non-volatile memory 3 . control. The processor 8 performs overall control over the memory controller 2 . The processor 8 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When the processor 8 receives an instruction from the host computer 4 via the host interface 9, it performs control according to the instruction. For example, the processor 8 issues an instruction to the memory interface 11 to write the user data and the parity check code of the non-volatile memory 3 in accordance with the instruction from the host computer 4 . In addition, the processor 8 issues instructions to the memory interface 11 to read the user data and the parity check code from the non-volatile memory 3 in accordance with the instructions from the host computer 4 . User data is stored in the RAM 6 via the internal bus 12 . The processor 8 determines a storage area (memory area) on the non-volatile memory 3 for the user data stored in the RAM 6 . The processor 8 determines the memory area on the non-volatile memory 3 for the data of the page unit (page data) which is the writing unit. In this specification, the user data stored in one page of the non-volatile memory 3 is defined as unit data. The unit data is generally encoded and stored in the non-volatile memory 3 as a code word, but the encoding is not required. The memory controller 2 may also store the unit data in the non-volatile memory 3 without encoding, but in FIG. 1 , as an example of the configuration, the configuration for encoding is shown. When the memory controller 2 does not perform encoding, the page data and the unit data are consistent with each other. In addition, one codeword may be generated based on one unit data, or one codeword may be generated based on divided data obtained by dividing the unit data. In addition, it is also possible to use plural unit data to generate one codeword. The processor 8 determines the memory area of the non-volatile memory 3 to be written to for each unit of data, respectively. At the memory area of the non-volatile memory 3, physical addresses are allocated. The processor 8 uses the physical address to manage the memory area of the writing target of the unit data. The processor 8 issues an instruction to the memory interface 11 by specifying the determined memory area (physical address) and writing user data to the non-volatile memory 3 . On the other hand, the host 4 manages data by logical addresses. Therefore, the processor 8 manages the correspondence between the logical addresses and the physical addresses of the user data. The processor 8, when receiving a read command including a logical address from the host 4, specifies a physical address corresponding to the logical address, and specifies the physical address and specifies the physical address. The memory interface 11 issues an instruction to read out the user data. In this specification, a plurality of memory cells that are commonly connected to one word line are defined as a memory cell group MG. One memory cell group MG is a unit of writing (programming). In the present embodiment, the non-volatile memory 3 is a NAND memory 5 of 4bit/Cell, and one memory cell group MG has a data amount of 4 bits×the number of bits. The bits written into each memory cell correspond to different pages. In this embodiment, the four pages of one memory cell group MG are referred to as the Lower page (the first page), the Middle page (the second page), the Upper page (the third page), and the Top page (the first page). 4 pages). The ECC circuit 10 encodes the user data stored in the RAM 6 and generates code words. Also, the ECC circuit 10 decodes the codeword read from the non-volatile memory 3 . The ECC circuit 10 corrects the bit errors included in the codeword read from the non-volatile memory 3, and then decodes it into user data. The RAM 6 temporarily stores the user data received from the host computer 4 until it is stored in the non-volatile memory 3, or is read out from the non-volatile memory 3. The data is temporarily stored until it is sent to the host 4 . The RAM 6 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). In FIG. 1 , a configuration example in which the memory controller 2 is provided with the ECC circuit 10 and the memory interface 11 , respectively, is shown. However, the ECC circuit 10 can also be embedded in the memory interface 11 . In addition, the ECC circuit 10 can also be built in the non-volatile memory 3 . When a write request is received from the host computer 4, the memory system 1 operates as follows. The processor 8 temporarily stores the written data in the RAM 6 . The processor 8 reads the data stored in the RAM 6 and inputs it to the ECC circuit 10 . The ECC circuit 10 encodes the input data, and inputs the code word to the memory interface 11 . The memory interface 11 writes the input code word to the non-volatile memory 3 . When a read request is received from the host computer 4, the memory system 1 operates as follows. The memory interface 11 inputs the codewords read from the non-volatile memory 3 to the ECC circuit 10 . The ECC circuit 10 decodes the input code word, and temporarily stores the decoded data in the RAM 6 . The processor 8 sends the data stored in the RAM 6 to the host 4 via the host interface 9 . In addition, the non-volatile memory 3 may also be constituted by a plurality of chips, and the non-volatile memory 3 and the memory interface 11 may also be formed through through vias (TSV: Through Silicon Via). to connect. In addition, the structure of the memory controller 2 shown in FIG. 1 is only one example, and the internal bus bar 12 may be a divided structure or a hierarchical structure, or additional functional blocks may be connected. of various other derivative forms. FIG. 2 is a block diagram showing one example of the internal structure of the non-volatile memory 3 of the present embodiment. The non-volatile memory 3 includes a NAND I/O interface 21 , a control unit 22 , a NAND memory cell array (memory cell unit) 23 , and a page buffer (second memory unit) 24 . The non-volatile memory 3 is, for example, formed on a semiconductor substrate (eg, a silicon substrate) and chipped. The control unit 22 controls the operation of the non-volatile memory 3 based on commands or the like from the memory controller 2 via the NAND I/O interface 21 . Specifically, when a write request is input, the control unit 22 writes the data requested to be written to a designated address on the NAND memory cell array 23 . to control. In addition, when a read request is input, the control unit 22 reads the data requested to be read from the NAND memory cell array 23 and controls the memory via the NAND I/O interface 21 It is controlled by means of the output of the device 2. The page buffer 24 is for temporarily storing the data input from the memory controller 2 and reading the data from the NAND memory cell array 23 when the NAND memory cell array 23 is written. Temporary buffer for storage. As will be described later, the control unit 22 is based on data obtained by reading out the data programmed by the programming of the 1st stage, and bits repeatedly input in the programming of the 1st stage and the 2nd stage The data of the bits, and the input data of the bits programmed by the programming of the 2nd stage, determine the threshold voltage of the data of the bits programmed by the programming of the 2nd stage. The control unit 22 includes an oscillator 31 , a sequencer 32 , a command user interface 33 , a voltage supply unit 34 , a column counter 35 , and a sequence access controller 36 . Also, the NAND memory cell array 23 includes a row decoder 37 and a sense amplifier 38 . The NAND I/O interface 21 is a circuit for sending and receiving IO signals and control signals with the memory controller 2 . The command user interface 33 obtains the command, the address and the command and address in the data received from the memory controller 2 via the IO signal line based on the control signal. The command user interface 33 delivers the obtained command and address to the sequencer 32 . The oscillator 31 is a circuit for generating clock pulses. The clock generated by the oscillator 31 is supplied to each component including the sequencer 32 . The sequencer 32 is a state machine driven by the clock supplied from the oscillator 31 . The sequencer 32 controls access to the NAND memory cell array 23 and the like. For example, the sequencer 32 issues various commands for controlling the internal voltage, operation timing, etc. in response to commands received from the command user interface 33 . In addition, the sequencer 32 supplies the block address and page address included in the address received from the command user interface 33 to the row decoder 37 . Furthermore, the sequencer 32 supplies the column address included in the address received from the command user interface 33 to the column counter 35 . The voltage supply unit 34 generates various internal voltages supplied to the word lines and various internal voltages supplied to the bit lines, and supplies the row decoders 37 and the sense amplifiers 38 . The column counter 35 starts with the column address supplied from the sequencer 32 during programming operation or reading operation, and makes the column address according to the control signal supplied from the serial access controller 36 progress in order. The page buffer 24 sequentially stores the data received from the serial access controller 36 in the row address area designated by the row counter 35 during the programming operation. In addition, the page buffer 24 sequentially sends the data of the column address specified by the above column address among the stored data to the serial access controller 36 during the read operation. The serial access controller 36 stores the data sequentially received from the NAND I/O interface 21 at the bit width of the IO signal line in the page buffer 24 during the programming operation. In addition, the serial access controller 36 sends the data sequentially received from the page buffer 24 at the bit width of the IO signal line to the NAND I/O interface 21 during the read operation. The row decoder 37 decodes the block address and the page address during the programming operation and the reading operation, and selects a page corresponding to the access target contained in the access target block BLK. the corresponding character line. After that, each row decoder 37 applies an appropriate voltage to the selected word line and the unselected word line. The sense amplifier 38, during the programming operation, transmits the corresponding data stored in the page buffer 24 to the memory cell transistor. In addition, the sense amplifier 38 senses the data read from the selected word line to the bit line during the read operation, and stores the obtained data in the page buffer 24 . The data stored in the page buffer 24 is sent to the memory controller 2 via the serial access controller 36 and the NAND I/O interface 21 . FIG. 3 is a circuit diagram showing one example of the NAND memory cell array 23 having a three-dimensional structure. FIG. 3 shows the circuit configuration of one block BLK among the plurality of blocks in the NAND memory cell array 23 having a three-dimensional structure. The other blocks of the NAND memory cell array 23 also have the same circuit configuration as that shown in FIG. 3 . In addition, this embodiment can also be applied to a memory cell of a two-dimensional structure. As shown in FIG. 3 , the block BLK includes, for example, four fingers FNG ( FNG0 to FNG3 ). In addition, each finger FNG includes plural NAND strings NS. Each of the NAND strings NS includes, for example, eight memory cell transistors MT ( MT0 to MT7 ) connected in series, and selection transistors ST1 and ST2 . In this specification, each finger FNG may be referred to as a string St in some cases. In addition, the number of memory cell transistors MT in the NAND string NS is not limited to eight. The memory cell transistor MT is arranged between the selection transistors ST1 and ST2 so that the current paths thereof are connected in series. The current path of the memory cell transistor MT7 on one end side of the series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 on the other end side is connected by It is connected to one end of the current path of the selection transistor ST2. The gates of the selection transistors ST1 of FNG0 to FNG3 are respectively connected in common with the selection gate lines SGD0 to SGD3. On the other hand, the gate of the selection transistor ST2 is commonly connected to the same selection gate line SGS between the plurality of fingers FNG. In addition, the control gates of the memory cell transistors MT0-MT7 located in the same block BLK are respectively connected in common with the word lines WL0-WL7. That is, the word lines WL0-WL7 and the selection gate line SGS are connected in common between the plurality of fingers FNG0-FNG3 in the same block BLK. In contrast to this, the selection gate line SGD, Even if they are within the same block BLK, they are independent of each other at each of FNG0 to FNG3. The control gate electrodes of the memory cell transistors MT0-MT7 constituting the NAND string NS are respectively connected with the word lines WL0-WL7, and the same refers to the number one of the NAND strings NS in the FNG. The i memory cell transistors MTi (i=0-n) are commonly connected by the same word line WLi (i=0-n). That is, the control gate electrodes of the memory cell transistors MTi of the same row in the block BLK are connected to the same word line WLi. Each NAND string NS is connected to the word line WLi and is also connected to the bit line. Each memory cell in each NAND string NS can be identified by the address identified for the word line WLi and the selection gate lines SGD0-SGD3 and the address identified for the bit line. As described above, the data of the memory cells (memory cell transistors MT) located in the same block BLK are deleted in batches. On the other hand, data reading and writing are performed in units of physical sectors MS. One physical sector MS is connected to one word line WLi, and includes a plurality of memory cells belonging to one finger FNG. The memory controller 2 writes (programs) all the NAND word strings NS connected to one word line in one finger as a unit. Therefore, the unit of the amount of data programmed by the memory controller 2 is 4 bits×the number of bit lines. During the read operation and the programming operation, one word line WLi and one select gate line SGD are selected according to the physical address, and the physical sector MS is selected. In addition, in this specification, writing data to a memory cell is referred to as "programming" according to needs. FIG. 4 is a cross-sectional view of a partial region of the NAND memory cell array 23 of the NAND memory 5 having a three-dimensional structure. As shown in FIG. 4 , on the p-well region (P-well) 41 of the semiconductor substrate, a plurality of NAND strings NS are formed in the vertical direction. That is, on the p-type well region 41, a plurality of wiring layers 42 functioning as selection gate lines SGS and a plurality of wiring layers functioning as word lines WLi are formed in the vertical direction. 43, and a plurality of wiring layers 44 that function as selection gate lines SGD. Moreover, the memory hole 45 which penetrates these wiring layers 42, 43, and 44 and reaches the p-type well region 41 is formed. A block insulating film 46 , a charge storage layer 47 , and a gate insulating film 48 are sequentially formed on the side surfaces of the memory hole 45 , and a conductive film 49 is embedded in the memory hole 45 . The conductive film 49 functions as a current path for the NAND string NS, and is a region where channels are formed when the memory cell transistor MT and the selection transistors ST1 and ST2 operate. At each NAND string NS, on the p-type well region 41, a selection transistor ST2, a plurality of memory cell transistors MT, and a selection transistor ST1 are sequentially stacked. At the upper end of the conductive film 49, a wiring layer that functions as the bit line BL is formed. Furthermore, in the surface of the p-type well region 41, an n+-type impurity diffusion layer and a p+-type impurity diffusion layer are formed. Contact pins 50 are formed on the n+ type impurity diffusion layer, and wiring layers that function as source lines SL are formed on the contact pins 50 . Further, on the p+-type impurity diffusion layer, contact pins 51 are formed, and on the contact pins 51, a wiring layer that functions as a well wiring CPWELL is formed. The well wiring CPWELL is used to apply the erase voltage. The NAND memory cell array 23 shown in FIG. 4 is arranged in a plurality of numbers in the depth direction of the paper surface of FIG. 4 by a set of plural NAND strings NS arranged side by side in one row in the depth direction, 1 A single finger FNG line was formed. The other fingers FNG are formed, for example, in the left-right direction of FIG. 4 . In FIG. 3 , although four fingers FNG0 to 3 are shown, in FIG. 4 , an example in which three fingers are arranged between the contact pins 50 and 51 is shown. FIG. 5 is a diagram showing one example of the threshold value region of the first embodiment. FIG. 5 shows one example of the distribution of the threshold region of the non-volatile memory 3 of 4 bits/Cell. In the non-volatile memory 3, information is memorized by the charge amount of electrons accumulated in the charge accumulating layer 47 of the memory cell. Each memory cell has a threshold voltage corresponding to the charge amount of the electrons. In addition, the plural data values stored in the memory cells are made to correspond to plural regions (threshold value regions) whose threshold value voltages are different, respectively. S0 to S15 of FIG. 5 are for the distribution of the threshold values in the 16 threshold value regions. The horizontal axis of FIG. 5 represents the threshold voltage, and the vertical axis represents the number of memory cells (cell number). The threshold value distribution is the range in which the threshold value changes. In this way, each memory cell has 16 threshold value regions divided by 15 boundaries, and each threshold value region has its own threshold value distribution. In this embodiment, the region where the threshold voltage is lower than Vr1 is called region S0, and the region where the threshold voltage is higher than Vr1 and lower than Vr2 is called region S1, and the region where the threshold voltage is higher than Vr1 is called region S1. The region where the threshold voltage is higher than Vr2 and lower than Vr3 is called region S2, and the region where the threshold voltage is higher than Vr3 and lower than Vr4 is called region S3. In the present embodiment, the region where the threshold voltage is greater than Vr4 and less than or equal to Vr5 is called region S4, and the region where the threshold voltage is greater than Vr5 and less than or equal to Vr6 is called as region S4. The region S5 is defined as the region where the threshold voltage is higher than Vr6 and lower than Vr7 is referred to as region S6, and the region where the threshold voltage is higher than Vr7 and lower than Vr8 is referred to as region S7. In the present embodiment, the region where the threshold voltage is greater than Vr8 and less than or equal to Vr9 is called region S8, and the region where the threshold voltage is greater than Vr9 and less than or equal to Vr10 is called as region S8. The region S9 is defined as the region where the threshold voltage is higher than Vr10 and lower than Vr11 is called region S10, and the region where the threshold voltage is higher than Vr11 and lower than Vr12 is called region S11. In this embodiment, the region where the threshold voltage is higher than Vr12 and lower than Vr13 is referred to as region S12, and the region where the threshold voltage is higher than Vr13 and lower than Vr14 is referred to as region S12 The region S13 is made, and the region where the threshold voltage is larger than Vr14 and lower than Vr15 is called region S14, and the region where the threshold voltage is larger than Vr15 is called region S15. In addition, the threshold value distributions corresponding to the regions S0 to S15 are referred to as the first to sixteenth distributions. Vr1 to Vr15 are threshold value voltages that serve as boundaries of the respective threshold value regions. In the non-volatile memory 3, plural data values are made to correspond to plural threshold value regions of the memory cells, respectively. This correspondence is called data encoding. This data code is formulated in advance, and when the data is written (programmed), the memory cell is written in a manner that will be within the threshold value region corresponding to the memorized data value according to the data code. The inner charge storage layer 47 injects charges. However, during readout, a readout voltage is applied to the memory cell, and the data logic is determined according to the fact that the threshold value of the memory cell is lower or higher than the readout voltage. At the time of data readout, the logic of the data is determined according to the fact that the threshold value is lower or higher than the readout level of the boundary of the readout object. When the threshold value is the lowest, it is in the "deleted" state, and all bit data are defined as "1". When the threshold value is higher than the "deleted" state, it is regarded as the "programmed" state, and the data is defined as "1" or "0" according to the code. FIG. 6A is a diagram showing one example of the data encoding of the first embodiment, and also one example of the 1-4-5-5 data encoding. In this embodiment, the 16 threshold value areas shown in FIG. 5 are made to correspond to 16 data values of 4 bits, respectively. The relationship between the threshold voltages in FIG. 6A and the data values of the bits corresponding to the Top, Upper, Middle, and Lower pages is shown below.・The threshold voltage is the memory cell located in the S0 area, which is the state of "1111" in the memory.・The threshold voltage is the memory cell located in the S1 area, which is the state of "0111" in the memory.・The threshold voltage is the memory cell located in the S2 area, which is the state of "0011" in memory.・The threshold voltage is the memory cell located in the S3 area, which is the state of "1011" in the memory.・The threshold voltage is the memory cell located in the S4 area, which is the state of "1001" in memory.・The threshold voltage is the memory cell located in the S5 area, which is the state of "0001" in the memory.・The threshold voltage is the memory cell located in the S6 area, which is the state of "0101" in the memory.・The threshold voltage is the memory cell located in the S7 area, which is the state of "1101" in the memory.・The threshold voltage is the memory cell located in the S8 area, which is the state of "1100" in the memory.・The threshold voltage is the memory cell located in the S9 area, which is the state of "1110" in the memory.・The threshold voltage is the memory cell located in the S10 area, which is the state of "1010" in the memory.・The threshold voltage is the memory cell located in the S11 area, which means that the memory has a state of "1000".・The threshold voltage is the memory cell located in the S12 area, which is the state of "0000" in the memory.・The threshold voltage is the memory cell located in the S13 area, which is the state of "0100" in the memory.・The threshold voltage is the memory cell located in the S14 area, which is the state of "0110" in the memory.・The threshold voltage is the memory cell located in the S15 area, which is the state of "0010" in the memory. FIG. 6B is a diagram showing another example of the data encoding of the first embodiment, and one example of the 4-3-4-4 data encoding. The relationship between the threshold voltages in FIG. 6B and the data values of the bits corresponding to the Top, Upper, Middle, and Lower pages is shown below.・The threshold voltage is the memory cell located in the S0 area, which is the state of "1111" in the memory.・The threshold voltage is the memory cell located in the S1 area, which is the state of "0111" in the memory.・The threshold voltage is the memory cell located in the S2 area, which is the state of "0011" in memory.・The threshold voltage is the memory cell located in the S3 area, which is the state of "1011" in the memory.・The threshold voltage is the memory cell located in the S4 area, which is the state of "1010" in the memory.・The threshold voltage is the memory cell located in the S5 area, which is the state of "1110" in the memory.・The threshold voltage is the memory cell located in the S6 area, which is the state of "1100" in memory.・The threshold voltage is the memory cell located in the S7 area, which means that the memory has a state of "1000".・The threshold voltage is the memory cell located in the S8 area, which is the state of "1001" in the memory.・The threshold voltage is the memory cell located in the S9 area, which is the state of "0001" in memory.・The threshold voltage is the memory cell located in the S10 area, which means that the memory has "0000".・The threshold voltage is the memory cell located in the S11 area, which is the state of "0010" in the memory.・The threshold voltage is the memory cell located in the S12 area, which is the state of "0110" in the memory.・The threshold voltage is the memory cell located in the S13 area, which is the state of "0100" in the memory.・The threshold voltage is the memory cell located in the S14 area, which is the state of "0101" in the memory.・The threshold voltage is the memory cell located in the S15 area, which is the state of "1101" in the memory. As shown in Figures 6A and 6B, there is logic to allocate 4 bits of data for each memory cell at regions of threshold voltage. In addition, when the memory cell is in an unwritten state (“deleted” state), the threshold voltage of the memory cell is located in the S0 region. Also, in the symbols shown here, as in "in the S0 (deletion) state, the data of "1111" is memorized, and in the S1 state, the data of "0111" is memorized", and in any two Only 1-bit change of data is made between adjacent areas of . In this way, the data encoding shown in FIGS. 6A and 6B is a Gray code that changes data by only one bit between any two adjacent regions. In the code of the present embodiment shown in FIG. 6A, the threshold voltage for determining the boundary of the bit value of each page is as follows.・Threshold voltages that serve as boundaries for determining the bit value of the Top page are Vr1, Vr3, Vr5, Vr7, and Vr12.・The threshold value voltages used as the boundary for determining the bit value of the Upper page are Vr2, Vr6, Vr10, Vr13, and Vr15.・The threshold value voltages used to determine the boundary of the bit value of the Middle page are Vr4, Vr9, Vr11, and Vr14.・The threshold voltage that becomes the boundary for judging the bit value of the lower page is Vr8. In this way, the number of threshold voltages for determining the boundary of the bit value (hereinafter, referred to as the boundary number) is 1, 4, and 5 for the Lower page, Middle page, Upper page, and Top page, respectively. , 5. Hereinafter, such an encoding will be referred to as a 1-4-5-5 encoding using the number of boundaries of each of the Lower page, the Middle page, the Upper page, and the Top page. The first feature of the present embodiment is that the number of boundaries by which the bit value of each page changes is 5 at the maximum. In the case where 16 states are represented by 4 bits, the minimum value of the maximum number of boundaries is 4, and the code in Figure 6 is only 1 more than this, and the bias of the bit error is reduced. . In this way, the memory system 1 according to the present embodiment can suppress the bit error rate by having the first feature, and can also control the bias of the bit error for each page. inhibition. The second feature of the present embodiment is that the number of borders on the lower page is one, and the number of borders on the middle page is four, and it is the first stage that can "integrate the lower page and the middle page into one" The programming is carried out in two stages: "Programming" and "Second-stage programming that integrates the Upper page and the Top page into one". The third feature of the present embodiment is that the range of change from the threshold value region generated by the programming of the first stage to the threshold value region generated by the programming of the second stage is: few. That is, this means that the variation range of the threshold value region is small. The smaller the variation range of the threshold value region is, the more difficult it is to be affected by the interference between adjacent cells. The first to third features described above will be described in detail later. The control part 22 of the non-volatile memory 3 controls the programming of the NAND memory cell array 23 and the readout from the NAND memory cell array 23 based on the codes shown in FIG. 6A or FIG. 6B . In 3-dimensional memory cells, the miniaturization of memory cells has not progressed in the same way as in 2-dimensional memory cells. Therefore, in a three-dimensional memory cell, if the adjacent memory cells are in a generation with a wide interval between each other, the mutual interference between the cells is small. In this case, generally speaking, all the bits of each memory cell are programmed simultaneously (for example, if the bits are allocated to different pages, all the pages are programmed simultaneously). When all the bits of each memory cell are programmed simultaneously, the data encoding is not particularly limited to the combination. It is only necessary to determine which of the 16 threshold value areas to be located on the basis of the data of all the bits, and to make the determined threshold value area from the area of S0 which is the deletion state. Just program it. In this case, in general, a data encoding such as the 4-4-3-4 data encoding that minimizes the maximum number of boundaries is used. In 4-4-3-4 data encoding, when 15 boundaries between 16 threshold value areas are allocated to 4 pages, 4 boundaries are allocated to the lower page, and 4 boundaries are allocated to the middle page 4 boundaries, and allocate 3 boundaries for Upper pages and 4 boundaries for Top pages. In the case of this data encoding, since the bias in the number of boundaries between pages is small, as a result, the bias in the bit error rate between pages becomes small. This is because, the vast majority of the causes of bit errors are caused by the fact that the threshold value is shifted to the adjacent threshold value region, and if there are pages with a greater number of boundaries, the bit The number of meta errors will increase. This is because "even if the error rate as a memory cell is the same, the correction capability of the ECC circuit 10, which is necessary for correcting page data errors, must be strengthened." It is also effective for suppressing deterioration of the response performance, cost, and power consumption of the memory system 1 to the write request from the host 4 . In addition, the bias in the readout speed due to the bias in the number of boundaries is also reduced. In addition, in the NAND memory 5 of 4 bits/Cell, since the interval between adjacent threshold value regions is narrow, the influence caused by the mutual interference between cells is less than that of 1 bit/Cell. Cell or 2-bit/Cell NAND memory 5 becomes larger. Therefore, in the NAND memory 5 of the generation in which the miniaturization has progressed in recent years, in general, in order to suppress the mutual interference between cells, a plurality of programming stages, for example, two programming stages are used. The stage (hereinafter, it may be simply called a stage) is a programming method (Foggy-Fine programming) in which charges are sequentially injected into the charge storage layer 47 of the memory cell in small amounts. In this Foggy-Fine programming, after writing to the memory cell in the first stage (Foggy stage), writing to the adjacent cell is performed, and then back to the original memory cell , and write in the second stage (Fine stage). Each stage in this case is the execution unit of programming, and the programming of the memory cell corresponding to one word line WLi is completed by executing two programming stages. Whether in the programming of the first stage or the programming of the second stage, the programming is performed using the 16 threshold value regions. The threshold value distribution of the threshold value area at the end of the programming of the first stage has a wider width than the threshold value distribution of the threshold value area in the final data encoding. That is, in the Foggy stage, Foggy (rough) writing is performed. In this Foggy stage of programming, all four pages of input data are necessary. The programmed threshold value distribution of the Foggy stage is an intermediate state in which the adjacent distributions overlap each other, so the data cannot be read out. In the programming of the Fine stage, which is the second stage, the threshold value region after the programming of the Foggy stage is moved to the threshold value region in the final data encoding. That is, in the Fine stage, the writing of Fine is performed. The programming of this Fine stage is also the same, all four pages of input data are necessary. Since the threshold value distribution after programming in the Fine stage is the final state where the adjacent distributions are separated from each other, data can be read out after the programming in the Fine stage. In the case of 4-4-3-4 data encoding, although the bias of the number of boundaries is small, in the Foggy-Fine stylized data input, it is necessary to process 4 pages of data at each stage. enter. This results in an increase in the time spent in data entry and degrades the response performance of the memory system 1 with respect to write requests from the host 4 . In addition, in the memory system 1, the buffer amount (write buffer amount) of the write buffer (first memory unit) used to hold the data input to the NAND memory 5 in advance is increased. This write buffer is, in general, an area allocated to a part of the RAM 6 in the memory system 1 . As a countermeasure against these problems, in the present embodiment, the memory system 1 uses 1-4-5-5 data encoding for the non-volatile memory 3 having a three-dimensional structure, and further uses two stage to implement page by page writes. In this way, in the present embodiment, even in the nonvolatile memory 3 having a three-dimensional structure, it is possible to suppress the mutual interference between cells and the bias of the bit error rate between the pages, and at the same time. Decrease the write buffer size of the memory controller 2. In the write buffer of this embodiment, the first to fourth bits (each data of the Lower page, Middle page, Upper page, and Top page) are repeatedly input during the first programming and the second programming. The bit data of , after the second programming is started, can be discarded or invalidated, and the data of the other bits can be discarded or invalidated after the first programming is started. Here, the interference between adjacent memory cells will be described. The electric charge accumulated in the charge accumulation layer 47 of a certain memory cell disturbs the electric field of the adjacent memory cell, and as a result, it is applied to read the adjacent memory cell. The output threshold voltage produces noise that fluctuates. Caused by "programming and verifying are implemented under a certain electric field condition, and after the programming is completed, adjacent memory cells are programmed to different charges", read The output accuracy will be degraded. This interference between adjacent memory cells has become remarkable as the distance between memory cells is reduced due to the miniaturization of the manufacturing technology of memory devices. In addition, if the interference between adjacent memory cells is enlarged, it will occur between adjacent memory cells connected to different bit lines on the same word line WLi. Interference between adjacent memory cells can be achieved by changing the electric field conditions of the memory cells between "programming and verifying" and "reading after the adjacent memory cells have been programmed". The difference is narrowed and alleviated. As one of the methods for reducing the interference between adjacent memory cells connected to different bit lines on the same word line WLi, there is a method of dividing the programming into a plurality of The method of programming is carried out in such a way that there is no large change in the amount of charge in the charge storage layer 47 between the stages. In the programming sequence of the present embodiment, 4 bits on one word line WLi are programmed in two programming stages, that is, in the 1st stage and the 2nd stage. Each programming stage is the execution unit of programming, and the memory system 1 of this embodiment ends the writing of 4-bit data to the memory cell by executing two programming stages. In addition, in the present embodiment, in each of the two programming stages, some page data having 4 bits is used. Specifically, in the programming of the 1st stage, the data of the lower page, the middle page and the top page are used, and in the programming of the 2nd stage, the data of the middle page, the upper page and the top page are used. FIG. 7 is a diagram showing the programmed threshold value region in the first embodiment. In Figure 7, the threshold region is shown after programming the 1st and 2nd phases for the memory cell. (T1) of FIG. 7 shows the threshold value region of the deletion state which is the initial state before programming. (T2) of FIG. 7 shows the threshold value region after the programming (first programming) of the 1st stage. (T3) of FIG. 7 shows the threshold value region after the programming (second programming) of the 2nd stage. As shown in ( T1 ) of FIG. 7 , all the memory cells of the NAND memory cell array 23 are in the state of distribution S0 in the unwritten state (“deleted” state). The control part 22 of the non-volatile memory 3, as shown in (T2) of FIG. 7, in the programming of the 1st stage, responds to writing (memory) to the Lower page, the Middle page and the Top page The bit value of , for each of the memory cells, is maintained in the state of distribution S0, or a charge is injected to move it to a distribution higher than distribution S0. Specifically, the control unit 22 assumes that “when the bit values written to the Lower page, Middle page and Top page are all “1”, no charge is injected, and when writing to the Lower page And if any one of the bit values at the Middle page and the Top page is "0", it is programmed by injecting charge and moving the threshold voltage to a higher position. That is, when the bit value written to the Lower page, the Middle page, and the Top page is "011", it is moved to the distribution S1, and when it is written to the Lower page and the Middle page. And when the bit value at the Top page is "101", it is moved to the distribution S4, and when writing to the Lower page, the Middle page and the bit value at the Top page is "001" ”, it is moved to distribution S5, and when the bit value written to the Lower page, Middle page and Top page is “100”, it is moved to distribution S8, Also, when the bit value written to the Lower page, the Middle page, and the Top page is "110", it is moved to the distribution S9, and when the bit value written to the Lower page, the Middle page, and the Top page is When the bit value at the page is "000", it is moved to the distribution S12, and when writing to the lower page, the middle page and the top page, the bit value is "010". In this case, it is moved to distribution S14. Here, preferably, the distribution S1, the distribution S4, the distribution S5, the distribution S8, the distribution S9, the distribution S12, and the distribution S14 are the widths of the threshold value regions such that the threshold value voltage is somewhat reduced Expand and roughly stylize. That is, the rising width of the programmed voltage pulse described later is increased. Thereby, the time required for writing can be shortened. In addition, by programming so that the threshold voltage is somewhat reduced, the threshold value can be distributed so that it finally becomes a specific width in the programming of the 2nd stage. The width of the area for writing. Also, ideally, the adjacent distributions S8 and S9, and the adjacent threshold value distributions S12 and S14, the intervals between these are set to be smaller than the adjacent distributions. The interval between them is narrower. These adjacent threshold value distributions with narrowed interval write bit values are different from each other in the data of the Middle page. That is, the programmed data in the 1st stage looks like a binary value, so the data of the Lower page, the Middle page and the Top page can be read out. The information of the Middle page is narrowed between the different threshold value distributions to ensure that the information of the Lower page and the Top page has a different threshold value distribution interval to be wide, and the lower page and the top page can be read out. The margin of time increases. The threshold value distributions S0 to S14 shown in (T2) of FIG. 7 correspond to the 17th to 24th threshold value regions. Next, as shown in ( T3 ) of FIG. 7 , in the programming of the 2nd stage, two pages of the Middle page and the Upper page are required for data writing. In addition, the control unit 22 of the non-volatile memory 3 is such that the threshold value distribution after the programming of the 2nd stage becomes a 16-value level in a final state in which the adjacent distributions are separated. , to program. After the programming of the 2nd stage, it is possible to read out all page data. In the programming of the 2nd stage, the larger the change range of the threshold value of the memory cell from the end of the programming of the 1st stage is, the larger the interference system between adjacent cells becomes. Therefore, it is desirable to minimize the change amount of the threshold value distribution in which the change amount of the threshold value distribution of the memory cell is the largest. According to the present embodiment, the maximum threshold value distribution change amount is the amount of three threshold value distributions, and the case where S0 changes to S3, S4 changes to S7, and S8 changes to S11 case. The threshold value distributions S0 to S15 shown in (T3) of FIG. 7 correspond to the first to sixteenth threshold value regions. In addition, programming is typically performed by applying a programming voltage pulse once or a plurality of times. The voltage value is raised stepwise in a plurality of program application pulses. After each programming voltage pulse, a readout called verify is performed in order to confirm whether the memory cell has moved beyond the threshold level. By repeating this application and readout, it becomes possible to move the threshold value of the memory cell to the range of a specific threshold value distribution. In addition, the control unit 22 may continuously perform the programming of the 1st stage and the programming of the 2nd stage with respect to one word line WLi. However, in order to reduce the influence of interference between adjacent memory cells, it is also possible to The programming is performed in a non-consecutive order across the plurality of word lines WLi. FIG. 8A is a diagram showing a first example of the programming sequence of the first embodiment. FIG. 8B is a diagram showing a second example of the programming sequence of the first embodiment. FIG. 8C is a diagram showing a third example of the programming sequence of the first embodiment. In FIGS. 8A to 8C , in order to reduce the influence of interference between adjacent memory cells, programming is performed in two programming stages. FIG. 8A shows one example of the programming sequence in the NAND memory 5 in which one word string St is connected to each word line in each block. 8B and 8C show one example of the programming sequence in the NAND memory 5 in which four word strings St are connected to each word line in each block. In addition, in FIG. 8B and FIG. 8C , the four character strings St connected to the respective word lines are denoted as String0 to String 3 . When writing is started, the control unit 22 performs each programming stage while crossing the word line WLi in a specific discontinuous order. That is, the 1st stage and the 2nd stage for the same word line are not continuously implemented, but after the 1st stage is stylized for a certain word line, for different words. 2nd stage programming is performed on the meta line. If the programming of a certain word line is completed until the 2nd stage, and the programming of the 1st stage and the 2nd stage is continuously performed for the adjacent word line, the variation of the threshold voltage is will get bigger. On the other hand, if the variation of the threshold voltage of adjacent word lines is large, the interference between adjacent memory cells between the word lines becomes large. Therefore, in order to reduce the interference between adjacent memory cells between word lines, after programming the word lines until the 2nd stage is completed, the fluctuation amount of the threshold voltage of the adjacent word lines is reduced. to be valid. If it is the sequence of FIG. 8A , the programming stage of the adjacent word line after the programming is completed up to the 2nd stage for a certain word line becomes only the 2nd stage. In the case of programming the three-dimensionally structured NAND memory 5 in the programming sequence shown in FIG. 8A , when writing is started, the control unit 22 , based on the instruction from the processor 8 , Programming is performed in the order shown in (1) to (9) below. The control unit 22 programs the NAND memory 5 based on an instruction from the processor 8 , but the description of the content based on the instruction from the processor 8 is omitted below. (1) First, the control unit 22 executes the programming ST11 of the 1st stage of the word line WL0. (2) Next, the control unit 22 executes the programming ST12 of the 1st stage of the word line WL1. (3) Next, the control unit 22 executes the programming ST13 of the 2nd stage of the word line WL0. (4) Next, the control unit 22 executes the programming ST14 of the 1st stage of the word line WL2. (5) Next, the control unit 22 executes the programming ST15 of the 2nd stage of the word line WL1. (6) Next, the control unit 22 executes the programming ST16 of the 1st stage of the word line WL3. (7) Next, the control unit 22 executes the programming ST17 of the 2nd stage of the word line WL2. (8) Next, the control unit 22 executes the programming ST18 of the 1st stage of the word line WL4. (9) Next, the control unit 22 executes the programming ST19 of the 2nd stage of the word line WL3. Hereinafter, similarly, the control unit 22 executes the process from the lower left to the upper right in FIG. 8A and toward the upper right. In this way, in FIG. 8A, a plurality of memory cells in the non-volatile memory 3 are provided with a plurality of first memory cells connected to the first word line, and the sum and the first The memory controller 2 performs the first programming on the plural first memory cells after the second word lines adjacent to the word lines are connected to the plural second memory cells. The first programming is performed on the plurality of second memory cells, and after the first programming is performed on the plurality of second memory cells, the first programming is performed on the plurality of first memory cells. Perform the second programming. In the case of programming the NAND memory 5 having a three-dimensional structure in the programming sequence shown in FIG. 8B , when writing is started, the control unit 22 performs the following operations as shown in (11) to (24). sequence to implement programming. (11) First, the control unit 22 executes the programming ST21 of the 1st stage of the word string St0_word line WL0. (12) Next, the control unit 22 executes the programming ST22 of the 1st stage of the word string St1_word line WL0. (13) Next, the control unit 22 executes the programming ST23 of the 1st stage of the word string St2_word line WL0. (14) Next, the control unit 22 executes the programming ST24 of the 1st stage of the word string St3_word line WL0. (15) Next, the control unit 22 executes the programming ST25 of the 1st stage of the word string St0_word line WL1. (16) Next, the control unit 22 executes the programming ST26 of the 2nd stage of the word string St0_word line WL0. (17) Next, the control unit 22 executes the programming ST27 of the 1st stage of the word string St1_word line WL1. (18) Next, the control unit 22 executes programming ST28 of the 2nd stage of the word string St1_word line WL0. (19) Next, the control unit 22 executes the programming ST29 of the 1st stage of the word string St2_word line WL1. (20) Next, the control unit 22 executes the programming ST210 of the 2nd stage of the word string St2_word line WL0. (21) Next, the control unit 22 executes the programming ST211 of the 1st stage of the word string St3_word line WL1. (22) Next, the control unit 22 executes the programming ST212 of the 2nd stage of the word string St3_word line WL0. (23) Next, the control unit 22 executes the programming ST213 of the 1st stage of the word string St0_word line WL2. (24) Next, the control unit 22 executes the programming ST214 of the 2nd stage of the word string St0_word line WL1. Hereinafter, similarly, the control unit 22 executes the process from the lower left to the upper right and obliquely upward in FIG. 8B . In addition, in FIG. 8B, although the description is made for the case where the number of character strings St in the block is 4, the number of character strings St in the block may be three or less, or five. above. In the case of programming the NAND memory 5 having a three-dimensional structure in the programming sequence shown in FIG. 8C , when writing is started, the control unit 22 performs the following steps (31) to (50). sequence to implement programming. (31) First, the control unit 22 executes the programming ST31 of the 1st stage of the word string St0_word line WL0. (32) Next, the control unit 22 executes the programming ST32 of the 1st stage of the word string St1_word line WL0. (33) Next, the control unit 22 executes the programming ST33 of the 1st stage of the word string St2_word line WL0. (34) Next, the control unit 22 executes the programming ST34 of the 1st stage of the word string St3_word line WL0. (35) First, the control unit 22 executes the programming ST35 of the 1st stage of the word string St0_word line WL1. (36) Next, the control unit 22 executes the programming ST36 of the 1st stage of the word string St1_word line WL1. (37) Next, the control unit 22 executes the programming ST37 of the 1st stage of the word string St2_word line WL1. (38) Next, the control unit 22 executes the programming ST38 of the 1st stage of the word string St3_word line WL1. (39) Next, the control unit 22 executes the programming ST39 of the 2nd stage of the word string St0_word line WL0. (40) Next, the control unit 22 executes the programming ST310 of the 2nd stage of the word string St1_word line WL0. (41) Next, the control unit 22 executes the programming ST311 of the 2nd stage of the word string St2_word line WL0. (42) Next, the control unit 22 executes the programming ST312 of the 2nd stage of the word string St3_word line WL0. (43) Next, the control unit 22 executes the programming ST313 of the 1st stage of the word string St0_word line WL2. (44) Next, the control unit 22 executes the programming ST314 of the 1st stage of the word string St1_word line WL2. (45) Next, the control unit 22 executes the programming ST315 of the 1st stage of the word string St2_word line WL2. (46) Next, the control unit 22 executes the programming ST316 of the 1st stage of the word string St3_word line WL2. (47) Next, the control unit 22 executes programming ST317 of the 2nd stage of the word string St0_word line WL1. (48) Next, the control unit 22 executes the programming ST318 of the 2nd stage of the word string St1_word line WL1. (49) Next, the control unit 22 executes the programming ST319 of the 2nd stage of the word string St2_word line WL1. (50) Next, the control unit 22 executes the programming ST320 of the 2nd stage of the word string St3_word line WL1. In addition, in FIG. 8C, although the case where the number of word strings St in the block is four is described, the number of word strings St in the block may be three or less, or five. above. In this way, even if the word string St is plural, the programming sequence of each programming stage of the word line WLi in one word string St is the same as when there is one word string St. When there is a non-volatile memory 3 with a 3-dimensional structure of a plurality of word strings St in the block, the programming of the combined position of the word line WLi and the word string St is generally performed first with respect to the relative The same word line number in the different zigzag string St is programmed, and then advances to the next word line number. In the case of following such an order, if FIG. 8A is used as a combination of the number of strings St, for example, the order will be the same as that of FIG. 8B or FIG. 8C . Here, an example of the writing procedure according to the programming sequence according to the first embodiment will be described with reference to FIGS. 9 to 11 . In FIGS. 9-11 , the writing procedure is shown for the case of following the programming sequence shown in FIG. 8B or FIG. 8C . As before, the memory controller 2 advances the programming stage across word lines WLi in a non-continuous sequence, and therefore, batches certain word lines WLi (here, is a block) is stylized as a stylized sequence as a whole. FIG. 9 is a flowchart showing a first example of the entire writing procedure for one block according to the first embodiment. One block here is assumed to include word lines WLi including n+1 word lines WL0 to WLn (n is a natural number). Fig. 10 is a flow chart showing the writing procedure in the 1st stage due to the first embodiment, and Fig. 11 is a flow chart showing the writing procedure in the 2nd stage due to the first embodiment the flow chart. As shown in FIG. 9, when writing is started, the control unit 22 executes the programming of the 1st stage of the word string St0_word line WL0 (step S10). Next, the control unit 22 executes the programming of the 1st stage of the word string St1_word line WL0 (step S20). After that, the control unit 22 executes the same processing as steps S10 and S20 for each character string St. Next, the control unit 22 executes the programming of the 1st stage of the word string St3_word line WL0 (step S30). Furthermore, the control unit 22 executes the programming of the 1st stage of the word string St0_word line WL1 (step S40). Next, the control unit 22 executes the programming of the 2nd stage of the word string St0_word line WL0 (step S50). Next, the control unit 22 executes the programming of the 1st stage of the word string St1_word line WL1 (step S60). After that, the control unit 22 repeatedly performs the same processing as steps S40, S50, and S60 for each word line WLi of each word string St. Next, the control unit 22 executes the programming of the 1st stage of the word string St0_word line WLn (step S70). Next, the control unit 22 executes the programming of the 2nd stage of the word string St0_word line WLn-1 (step S80). After that, the control unit 22 repeatedly performs the same processing as steps S70 and S80 for each word line WLi of each word string St. Next, the control unit 22 executes the programming of the 2nd stage of the word string St3_word line WLn-1 (step S90). Next, the control unit 22 executes the programming of the 2nd stage of the word string St0_word line WLn (step S100). Next, the control unit 22 executes the programming of the 2nd stage of the word string St1_word line WLn (step S110). After that, the control unit 22 executes the same processing as steps S100 and S110 for each character string St. Next, the control unit 22 executes the programming of the 2nd stage of the word string St3_word line WLn (step S120). FIG. 10 is a flow chart showing the first example of the writing procedure in the 1st stage. In the programming of the 1st stage, first, the input start command of the lower page data is input to the non-volatile memory 3 from the memory controller 2 (step S210). After that, the lower page data is input to the non-volatile memory 3 from the memory controller 2 (step S215). Next, an input start command in which the data of the Middle page is input to the non-volatile memory 3 from the memory controller 2 (step S220 ). After that, Middle page data is input to the non-volatile memory 3 from the memory controller 2 (step S225). Next, the input start command is inputted from the memory controller 2 to the non-volatile memory 3 with the data of the Top page (step S230). After that, the top page data is input to the non-volatile memory 3 from the memory controller 2 (step S235). Furthermore, a program execution command of the 1st stage is input to the non-volatile memory 3 from the memory controller 2 (step S240 ), and thereby becomes chip_busy (step S245 ). When data writing is performed, the threshold voltage Vth is determined (step S250 ), and programmed voltage pulses are applied one to a plurality of times (step S255 ). After that, in order to confirm whether or not the memory cell has moved beyond the threshold level, data reading (verification) is performed (step S260). Further, it is determined whether the number of fail-bits of the data in the Lower page, the Middle page, and the Top page is smaller than the criterion (step S265). When the number of failed bits of the data is greater than or equal to the criterion, the processing from the application of the programming pulse to the criterion determination (steps S255 to S265 ) is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the determination reference, it becomes chip_ready (step S270). By repeating application, reading, and checking in this way, the threshold value of the memory cell can be moved to the range of a specific threshold value distribution. In addition, as mentioned above, the readout level after the programming voltage pulse is applied during the 1st-stage writing can also be slightly different from the readout level after the 2nd-stage writing, which is ideal because it is relatively 2nd-stage write followed by a read level and a lower level. That is, Vr1’≦Vr1, Vr4’≦Vr4, Vr5’≦Vr5, Vr8’≦Vr8, Vr9’≦Vr9, Vr12’≦Vr12, Vr14’≦Vr14. In addition, in the readout after the application of the programmed voltage pulse in the 1st-stage writing, the readout by Vr9' and the readout by Vr14' can also be omitted, and Vr9' is passed through Vr8 After the readout of ', the programming voltage pulse is applied a predetermined number of times, the writing is finished, Vr14', after the readout of Vr13', the programming voltage pulse is applied a predetermined number of times. After that, it is assumed that writing is completed. This is because, as described above, by narrowing the interval between the data of the Middle page in the programmed data in the 1st stage into different threshold value regions, it is possible to perform writing in the 2nd stage. The data of the lower page and the top page to be read out are different threshold value regions, and even by simple control of "applying programmed voltage pulses of a certain number of times", the interval can be sufficiently ensured to be wide. Furthermore, it is also possible to omit the readout after applying the programmed voltage pulses of Vr8', Vr9', Vr12', and Vr14', and after passing the readout of Vr5', apply a predetermined number of times respectively. After programming the voltage pulse, it is assumed that the writing is completed. In addition, it is also possible to omit the readout after applying the programmed voltage pulses of Vr4', Vr5', Vr8', Vr9', Vr12', and Vr14', and after the readout through Vr1' , and after applying a certain predetermined number of programmed voltage pulses, writing is completed. FIG. 11 is a flow chart showing the first example of the writing procedure of the 2nd stage. In the programming of the 2nd stage, first, the input start command is inputted from the memory controller 2 to the non-volatile memory 3 with the data of the Middle page (step S310). After that, the data of the Middle page is input to the non-volatile memory 3 from the memory controller 2 (step S320). Next, the input start command of the data of the Upper page is input to the non-volatile memory 3 from the memory controller 2 (step S330). After that, the data of the Upper page is input to the non-volatile memory 3 from the memory controller 2 (step S340). Next, a program execution command of the 2nd stage is input to the non-volatile memory 3 from the memory controller 2 (step S350 ), and thereby becomes chip_busy (step S360 ). After that, the control unit 22 reads the data of the lower page and the top page which are IDL (Internal Data Load) (step S370). Then, based on the previously input data of the Middle page and the data of the Lower page and the Top page caused by the IDL, the Vth (threshold voltage) of the programming target of the Upper page is determined (step S380 ). After that, using the determined Vth, data writing to the upper page is performed. More specifically, the voltage values of the plurality of programming pulses are gradually increased and written so as to become the determined threshold value voltage (step S390 ). Memory cells that reach the target threshold voltage are removed from the write target. After that, the written data is read out (step S400 ), and it is determined whether the number of failed bits is smaller than a criterion (step S410 ). When the number of failed bits of the data is greater than or equal to the criterion, the processing from the application of the programming pulse to the criterion determination (steps S390 to S410 ) is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the determination reference, it becomes chip_ready (step S420). Here, in the present embodiment, two features are provided. The first feature is that the data of the Middle page has been inputted in the programming of the 1st stage, and the threshold value area after the 1st programming is in the writing state that also includes the data of the Middle page, but, In the programming of the 2nd stage, the data of the Middle page is still input again. The second feature is that in the programming of the 1st stage, the adjacent threshold value areas for switching the data of the Middle page are narrowed, and the interval between the switching of the data of the Lower page and the data of the Top page is narrowed. Adjacent threshold values are distributed with each other, and their interval becomes wider. Thereby, the reliability of the lower page and the top page data read out by IDL can be improved. On the other hand, if the data of the Middle page is read out by IDL, the reliability may be lowered. However, in this embodiment, it is used in the 1st stage programming. The data of the middle page that has been updated is input again, so there is no problem of reliability reduction. Furthermore, the control unit 22 can also perform a plurality of times of readout in order to improve the reliability of the readout data of the IDL, and use the majority decision of the readout results at the page buffer in the chip as the connection It is used to write down the data. Of course, the control unit 22 can perform a plurality of readouts during the normal readout operation, and use the majority decision of the readout results in the wafer, and use it as readout data to the outside. FIG. 12 is a diagram for explaining a majority decision process for a read result of a complex number of times. In FIG. 12, as a result of reading out the data of a specific page, the correct bits are marked with a circle mark (○), and the wrong bits are marked with a cross mark (x). mark. In addition, in FIG. 12, the result of the majority vote in the case where the readout is performed three times is shown. The cases where the result of the majority decision is judged to be wrong at each position are (a) a case of being wrong three times, and (b) a case of being wrong two times. If the probability that each element is an error is p, then in the case of p=0.2, (a) the probability of three errors is p × p × p = 0.2 × 0.2 × 0.2, and (b) the probability of two errors The probability of , is (1-p)×p×p=(1-0.2)×0.2×0.2. Therefore, the probability that the result of the three-time majority vote is judged to be wrong is (p×p×p)+3×(1−p)×p×p=0.104. In this way, the control unit 22 can improve the reliability of the read data by performing the majority decision processing of the read results for a plurality of times in the page buffer 24 in the chip. Furthermore, the control unit 22 may perform writing in response to writing during the 1st-stage writing of WLn+1 in order to improve the reliability of the read data of the IDL during the 2nd-stage writing of the word line WLn. Data or threshold voltage to change the read voltage of word line WLn at IDL and read. Furthermore, in order to improve the reliability of the read data of the IDL during the 2nd-stage writing of the word line WLn, the control unit 22 may be adapted to respond to the 1st-stage writing of the word line WLn+1. The written data or the threshold voltage is used to change the non-selection voltage of the word line WLn+1 at IDL and read. At this time, the readout voltage of the word line WLn can be changed simultaneously and readout can be performed. When data writing to the upper page is performed, one or more programmed voltage pulses are applied. After that, in order to confirm whether the memory cell has moved beyond the threshold level, data reading (verification) of the upper page is performed. The readout level at this time is a specific level. Further, it is determined whether the number of failed bits of the data in the Upper page is smaller than the determination reference. When the number of failed bits of the data in the Upper page is greater than or equal to the criterion, the processing from the application of the programmed voltage pulse to the verification is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the criterion, it becomes chip_ready. Here, a modification of the writing program shown in FIG. 11 will be described. FIG. 13 is a flowchart showing a modification of the writing procedure in the 2nd stage of the first embodiment. In addition, in the flow chart of Fig. 13, "The IDL data that has been read out for the data programmed in the 1st stage is corrected, and the error is corrected and returned to the non-volatile memory 3." program. Specifically, first, a lower page read command is input to the non-volatile memory 3 from the memory controller 2 (step S510 ). Thereby, the system becomes chip_ready (step S512). Next, the control unit 22 reads the lower page data using the threshold voltage of Vr8'. After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr8' (step S514). After that, the system becomes chip_ready (step S516). If the lower page data read by the control unit 22 is output (step S518 ), the lower page data is sent to the ECC circuit 10 (step S520 ). Thereby, the ECC circuit 10 performs ECC correction on the lower page data (step S522). Next, the memory controller 2 receives the input start command of the data of the Lower page to the non-volatile memory 3 (step S524). Thereby, the ECC circuit 10 inputs the data of the lower page to the non-volatile memory 3 (step S526). Next, a read command of the top page is input to the non-volatile memory 3 from the memory controller 2 (step S528 ), and thereby becomes chip_busy (step S530 ). After that, the control unit 22 reads the top page data using the threshold voltages of Vr2' and Vr10'. After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr1', Vr4', Vr8', and Vr12' (step S532). After that, the system becomes chip_ready (step S534). If the top page data read by the control unit 22 is output (step S536 ), the top page data is sent to the ECC circuit 10 (step S538 ). Thereby, the ECC circuit 10 performs ECC correction on the top page data (step S540). Next, the input start command is input from the memory controller 2 to the non-volatile memory 3 to which the data of the Top page is input (step S542). Thereby, the ECC circuit 10 inputs the data of the top page to the non-volatile memory 3 (step S544). After that, the input start command is input from the memory controller 2 to the non-volatile memory 3 to which the data of the Middle page is input. (step S546). The subsequent steps are the same as the procedure of FIG. 11 . The threshold value voltage Vth of the programming target is based on the data of the Lower page and the top page from the ECC circuit 10, the data of the middle page which is input again, and the data of the upper page which is newly input. Determines the threshold voltage Vth of the programming target. In the programming of the 2nd stage above, the data input to the non-volatile memory 3 is only two pages of the Middle page and the Upper page. However, in this 2nd stage, at the threshold voltage Vth, which is the destination of programming of the memory cell, it is necessary to also include the Lower page and the Top page (the threshold voltage Vth before starting the 2nd stage). ) of 4 pages of data. Therefore, in the programming at this stage, as a pre-processing, the control unit 22 performs "first read out the lower page data and the top page data, and use the updated middle page and the inputted middle page with the data. The upper page is used to synthesize and determine the threshold voltage Vth of the programming target. In addition, the readout level during verification in the 2nd stage may be slightly different from the readout level after writing in the 2nd stage. Here, a comparison between the Foggy-Fine stylized processing program using the 4-3-4-4 data encoding and the stylized processing program of the present embodiment will be described. FIG. 14A is a diagram for illustrating the amount of data in the write buffer in the Foggy-Fine programming using the 4-3-4-4 data encoding. FIG. 14B is a diagram illustrating the amount of data written in the buffer in this embodiment. FIG. 14B shows an example of using 1-4-5-5 data encoding. In FIG. 14A and FIG. 14B, on the upper side, the timing table of data input and programming execution for block writing is shown, and on the lower side, it is for data retention in the write buffer for data retention. The timetable for the required period is shown. In addition, in FIGS. 14A and 14B , in order to simplify the description, the case where the number of character strings St in one block is 1 is shown. When the string St is a complex number, the amount of data written into the buffer that is a multiple of the string St is required. In the case of the Foggy-Fine programming of the 4-3-4-4 data encoding, in the Foggy stage, which is the first stage, data input for 4 pages is performed, and the 4 pages are Stylization of the amount (stylization of the Foggy stage). Also, in the case of the Foggy-Fine programming of the 4-3-4-4 data encoding, in the Fine stage, which is the second stage, data input for 4 pages is also performed, and this Stylization of 4 pages (stylization of Fine stage). However, at each word line WL0, WL1, WL2, . . , until programming is started at the Fine stage, it is necessary to write data corresponding to 4 pages in the Foggy stage. , pre-stored in the write buffer. In the Foggy-Fine programming, similarly, in order to reduce the interference between adjacent memory cells, the data corresponding to 4 pages of Lower/Middle/Upper/Top are not continuously written. For example, after the Foggy phase for word line WL0 is performed, and before the Fine phase for word line WL0 is performed, the Foggy phase for word line WL1 adjacent to word line WL0 is performed . Also, after the Foggy phase for word line WL0 is performed, and before the Fine phase for word line WL1 is performed, the Foggy phase for word line WL2 adjacent to word line WL1 is performed. . In the case of this method, it is necessary to keep the data of 4 pages of Lower/Middle/Upper/Top in the write buffer in advance until the data input of the second Fine stage is completed. Inside. In addition, in order to reduce the interference between adjacent memory cells, it is necessary to hold the data on the plural word lines WLi in the write buffer in advance. For example, when the Foggy phase is executed for word line WL2, it is necessary to hold three pages of data for word line WL1 and three pages of data for word line WL2 during writing into the buffer. As such, in the case of the Foggy-Fine programming of the 4-3-4-4 data encoding, it is necessary to keep a maximum of 8 pages of data in the write buffer. As shown in FIG. 14B, in the programming of this embodiment, for example, 1-4-5-5 data encoding is used to use two-stage programming. In the programming of this embodiment, in the 1st stage, data input for 3 pages (Lower page, Middle page, and Top page), and programming for these 3 pages (1st programming) are performed. ). Furthermore, in the case of programming in the present embodiment, in the 2nd stage, data input for two pages (Middle page and Upper page) and programming for one upper page ( 2nd stylized). However, at each word line WL0, WL1, WL2, . . . , except for the Middle page that is input in both stages, it is only necessary to store the data in the write buffer in advance when the data is input in each stage. However, if programming is started, the data can also be deleted from the write buffer. For example, if data is input at stage 1st, the data is stored in the write buffer. However, if programming is started at the 1st stage, the data of the lower page and the top page previously stored in the write buffer may also be deleted. Likewise, if data is input at the 2nd stage, the data is stored in the write buffer. However, if programming is started at the 2nd stage, it is also possible to delete all the data previously stored in the write buffer. Therefore, in the case of programming in this embodiment, it is necessary to hold the data in the write buffer in advance, even if the data is only 4 pages at maximum. In the programming of the present embodiment, similarly, in order to reduce the interference between adjacent memory cells, data corresponding to 4 pages of Lower/Middle/Upper/Top are not continuously written. For example, after the 1st stage for word line WL0 is executed, before the 2nd stage for word line WL0 is executed, the 1st stage for word line WL1 adjacent to word line WL0 is executed . Likewise, after the 1st stage for word line WL1 is executed, and before the 2nd stage for word line WL1 is executed, the 1st stage for word line WL2 adjacent to word line WL1 is executed implement. As described above, in the present embodiment, since page data other than the Middle page is only required for programming in one stage, it becomes possible to write into the buffer when the input of the data is completed. The data within is deleted. Therefore, in this embodiment, only a small number of pages need to be kept in the write buffer at the same time in advance. The page data programmed for the non-volatile memory 3 is temporarily held in the write buffer in the RAM 6, and then the data is input to the non-volatile memory 3 during programming. In the present embodiment, since the required capacity of the RAM 6 can be reduced, cost reduction can be achieved. In addition, when using the Foggy-Fine programming, the data transmission of all page data must be performed twice, so the transmission time will be consumed, and it will also consume power when more transmission is required. In the present embodiment, the page data other than the Middle page is completed by one data transfer for each page individually, so that the transfer time and power consumption can be reduced to about 1/2. Here, the page read process will be described. The method of page reading differs depending on whether the programming for the word line WLi containing the page to be read is before or after writing in the 2nd stage. Before the 2nd stage is written, the recorded data is only valid for the Lower page, the Middle page and the Top page. Therefore, the control unit 22 reads the data from the memory cell when the read page is the Lower page, the Middle page, and the Top page, but other pages (specifically, the Upper page) In the case of , the memory cell read operation is not performed, and control is performed to forcibly output all "1" as read data. On the other hand, in the case of the word line WLi that has ended up to the 2nd stage, the control unit 22 reads the memory cell regardless of whether the read page is the Top/Upper/Middle/Lower page. out. In this case, since the required readout voltages are different depending on what page the readout page is, the control unit 22 performs only necessary readout depending on the selected page. out. Hereinafter, the specific processing procedure of page reading will be described. FIG. 15 shows page readout at the word line where programming up to the 1st stage has ended (the programming of the 2nd stage has not yet ended) in the memory system 1 according to the first embodiment The processing procedure is shown as a flowchart. According to the data encoding of 1-4-5-5 shown in FIG. 6, since the boundary between the threshold value states changed by the lower page data is one, the control unit 22, according to the threshold value, is: The data is determined based on which of the two ranges separated by the boundary are located. For example, when the threshold voltage is smaller than Vr8', the control unit 22 performs control to output "1" as the data of the memory cell. On the other hand, when the threshold voltage is larger than Vr8', the control unit 22 performs control to output "0" as the data of the memory cell. In addition, since there are three boundaries between the threshold value states to which the data of the Middle page changes, the control unit 22 is based on the threshold value as the location of the four which are separated by these boundaries. Which one of the scopes is used to determine the data. In addition, since there are four boundaries between the threshold value states that the top page data changes, the control unit 22 is based on the threshold value as the position of the five which are separated by these boundaries. Which one of the scopes is used to determine the data. As shown in FIG. 15, in the case of writing the word line WLi before the 2nd stage, the control unit 22 selects the read page (step S610). When the page to be read is a lower page, the control unit 22 performs reading with one read voltage (step S612). This voltage is Vr8, but, as mentioned above, in the case of the word line before writing in the 2nd stage, as shown in FIG. 8(T2), it can also have a read voltage and a threshold A margin for the value voltage, such as Vr8'. After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr8 (step S614). In addition, when the readout page is a Middle page, the control unit 22 performs readout with three readout voltages (steps S616, S618, and S620). This voltage is Vr4, Vr9, and Vr14 as described above. However, in the case of the word line before writing in the 2nd stage, as shown in FIG. 8(T2), it can also have read The margins for the output voltage and the threshold voltage are, for example, Vr4', Vr9' and Vr14', respectively, instead of these. After that, the control unit 22, based on the readout result at the threshold value voltage of Vr4, the readout result at the threshold value voltage of Vr9, and the readout result at the threshold value voltage of Vr14, determines the The value of the read data is determined to be "0" or "1" (step S622). Here, as described above, since the data on the Middle page is distributed with different threshold values, the interval is narrow, and the read margin of the Middle page is narrowed, so the value of the read data will have significant reliability. The possibility of ground deterioration, and the data of the Middle page before the 2nd stage writing can also be defined as invalid. In this case, when the read page is the Middle page, the control unit 22 can also perform control to forcibly output all "1" as the output data of the memory cell. In addition, when the read page is the upper page, since the upper page is not programmed in the 1st programming, the control unit 22 compulsorily outputs all "1" as output data. (step S624). In addition, when the read page is the Top page, the control unit 22 performs read out with four read voltages (steps S626, S628, S630, and S632). This voltage is Vr1, Vr4, Vr8, and Vr12 as described above. However, in the case of the word line before writing in the 2nd stage, as shown in FIG. 8(T2), it can also be There are margins for the readout voltage and the threshold voltage, and instead of these, for example, Vr1', Vr4', Vr8', and Vr12' are respectively set. After that, the control unit 22 is based on the readout result at the threshold value voltage of Vr1, the readout result at the threshold value voltage of Vr4, the readout result at the threshold value voltage of Vr8, and the readout result at the threshold value voltage of Vr12. The value of the read data is determined to be "0" or "1" as a result of reading at the threshold voltage (step S634). FIG. 16A is a flowchart showing the processing procedure of the page read at the word line where the programming up to the 2nd stage ends in the memory system 1 of the first embodiment. When the stylized word line WLi is completed until the 2nd stage, the control unit 22 selects the read page (step S650). When the page to be read is a lower page, the control unit 22 performs the read out with the threshold voltage of one of Vr8 (step S652). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of one of Vr8 (step S654). In addition, when the read page is a Middle page, the control unit 22 performs read using the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (steps S656, S658, S660, and S662). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (step S664). . Also, when the read page is the Upper page, the control unit 22 reads out the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (steps S666, S668, S670, S672, S674). ). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the readout results at the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (step S676). In addition, when the read page is the Top page, the control unit 22 reads out the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12 (steps S678, S680, S682, S684, S686). ). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the readout results at the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12 (step S688). In addition, the memory controller 2 can manage and identify whether the programming for the word line WLi is before or after the end of writing in the 2nd stage. In the memory system 1, since the memory controller 2 performs programmed control, as long as the memory controller 2 records the progress status in advance, the memory controller 2 can easily control the non-volatile memory. The address of which of the sexual memory 3 is what the programmed state of being is as a reference. In this case, the memory controller 2, when reading from the non-volatile memory 3, recognizes the programmed state of the word line WLi containing the address of the target page, and issues and The read command corresponding to the identified state. In addition, as another method, it is also possible to set a flag cell at each of the word lines WLi respectively, and write in the flag cell in the 2nd stage of writing, according to the data of the flag cell , to manage and identify whether it is before or after the end of writing in the 2nd stage by the non-volatile memory 3 .

以下，針對頁面讀出處理之其中一變形例作說明。由其中一變形例所致之頁面讀出處理，係僅在針對包含有讀出對象頁面之字元線WLi的程式化乃身為進行了2nd階段之寫入之後時才能夠實行。由其中一變形例所致之頁面讀出處理，在將讀出對象之字元線之所有的資料讀出的情況時，讀出速度係會變快，在此點上，係為有效。 Hereinafter, one modification of the page readout process will be described. The page read process according to one of the modifications can be performed only when the programming of the word line WLi including the read target page is performed after the 2nd-stage writing is performed. The page read processing by one of the modified examples is effective in that the read speed is increased when all the data of the word line to be read is read out.

適合於由其中一變形例所致之頁面讀出處理的資料編碼，例如係身為如同圖16B一般者。以下，針對在此資料編碼的情況時之由其中一變形例所致之讀出處理作說明。在由其中一變形例所致之頁面讀出處理中，係將Top/Upper/Middle/Lower頁面之所有的頁面讀出。 The data encoding suitable for the page read processing by one of the modifications is, for example, the same as that shown in FIG. 16B . Hereinafter, the read processing by one of the modified examples in the case of data encoding will be described. In the page read processing by one of the modified examples, all pages of the Top/Upper/Middle/Lower pages are read out.

圖16C，係為對於由其中一變形例所致的讀出處理程序作展示之流程圖。又，圖16D，係為選擇字元線、ReadyBusy訊號線、輸出資料線之電壓波形圖。控制部22，係藉由15個的全部的讀出電壓Vr15~Vr1來依序進行讀出。首先，如同圖16D中所示一般，以身為最高的電壓之Vr15來進行讀出(步驟S690)，接著，一次作1個階段之降低地來以低的讀出電壓來依序繼續進行讀出(步驟S691~S707)。在為了決定各頁面之讀出資料所需要的讀出為結束時，該頁面之讀出資料係成為能夠輸出。 FIG. 16C is a flowchart showing the readout processing procedure by one of the modifications. 16D is a voltage waveform diagram of the selected word line, the ReadyBusy signal line, and the output data line. The control unit 22 sequentially reads out all the 15 readout voltages Vr15 to Vr1. First, as shown in FIG. 16D, reading is performed with Vr15, which is the highest voltage (step S690), and then the reading is sequentially continued with the lower reading voltage by decreasing the ground one stage at a time. out (steps S691 to S707). When the readout necessary to determine the readout data of each page is completed, the readout data of the page becomes available for output.

在由其中一變形例所致之頁面讀出處理中，於從Vr15起而依序進行讀出並直到Vr8之讀出為止而結束時(步驟S697)，Lower頁面之資料係被決定，並成為能夠將此資料 輸出(步驟S698)。在此步驟S698中，基於以讀出電壓Vr8所致的讀出資料，Lower頁面之資料係被決定。 In the page read processing by one of the modified examples, when reading is performed sequentially from Vr15 to the reading of Vr8 and ends (step S697 ), the data of the lower page is determined and becomes able to this data output (step S698). In this step S698, based on the read data by the read voltage Vr8, the data of the lower page is determined.

接著，於直到Vr4之讀出為止而結束時(步驟S702)，Middle頁面之資料係被決定(步驟S703)。在此步驟S703中，基於以讀出電壓Vr4、Vr9、Vr11以及Vr14所致的讀出資料，Middle頁面之資料係被決定。 Next, when the reading of Vr4 ends (step S702 ), the data of the Middle page is determined (step S703 ). In this step S703, based on the read data by the read voltages Vr4, Vr9, Vr11 and Vr14, the data of the Middle page is determined.

接著，於直到Vr2之讀出為止而結束時(步驟S705)，Upper頁面之資料係被決定(步驟S706)。在此步驟S706中，基於以讀出電壓Vr2、Vr6、Vr10、Vr13以及Vr15所致的讀出資料，Upper頁面之資料係被決定。 Next, when the readout of Vr2 ends (step S705 ), the data of the Upper page is determined (step S706 ). In this step S706, based on the read data by the read voltages Vr2, Vr6, Vr10, Vr13, and Vr15, the data of the Upper page is determined.

接著，於直到Vr1之讀出為止而結束時(步驟S707)，最終之Top頁面之資料係被決定(步驟S708)。在此步驟S708中，基於以讀出電壓Vr1、Vr3、Vr5、Vr7以及Vr12所致的讀出資料，Top頁面之資料係被決定。 Next, when the readout of Vr1 ends (step S707 ), the final Top page data is determined (step S708 ). In this step S708, based on the read data by the read voltages Vr1, Vr3, Vr5, Vr7 and Vr12, the data of the Top page is determined.

在由其中一變形例所致之頁面讀出處理中，直到能夠將任意之1個頁面之資料作輸出為止的延遲(latency)係變長，但是，將全部4個頁面作讀出的合計時間，係能夠較於前所說明的1次1個頁面地作了讀出的情況時之合計時間而更為縮短。如同圖16D中所示一般，作為讀出準備而將字元線從0來一直充電至身為高電壓之Vr15為止的時間，係僅需要耗費1次即可，又，在使讀出準位變化為下一個的電壓時的電壓變化之振幅係為小，電壓係在短時間內而成為安定，因此，係能夠將直到讀出電壓成為安定為止的待機時間縮短。因此，藉由所有的讀出電壓Vr15~Vr1來進行讀出的情況，選擇字元線之變遷時間的合計係變短，其結果，係能夠使合計的讀出時間高速化。 另外，於上，雖係以圖16B之資料編碼為例來作了說明，但是，基本上，不論是對於何種資料編碼，均能夠作適用。但是，由於係使讀出電壓從最大電壓起直到最小電壓為止地來依序變化並進行讀出，因此，係依照為了確定資料所需要的電壓之讀出為先結束的頁面之順序，而成為能夠進行資料輸出。因此，需要注意到，依存於資料編碼之形態，係會有並無法以Lower、Middle、Upper、Top之頁面順序來作讀出的情形。 如此這般，在第1實施形態中，在對於非揮發性記憶體3(具備有3維構造或2維構造之4bit/Cell之NAND記憶體)進行程式化時，係採用1-4-5-5資料編碼，並將程式化之階段設為2階段制。由於係如此這般地以2階段制而被作程式化，因此，在各階段處之資料程式化時所輸入的資料量係減少，而能夠對於在記憶體控制器2中所必要的寫入緩衝之量作抑制。又，由於在各頁面處之臨限值邊界的數量係為均一，因此，係能夠將非揮發性記憶體3之頁面間的位元錯誤率之偏頗降低，並且能夠將在ECC處所耗費的成本降低。又，由於資料傳輸，係除了1個頁面以外，而成為各頁面僅各一次，因此係能夠對於傳輸時間以及電力消耗作抑制。 又，由於係一面橫跨字元線WLi一面實行各程式化階段，因此係能夠將與鄰接字元線WLi之間的鄰接胞間干涉之量降低。又，由於係使用1-4-5-5資料編碼，因此，在2nd程式化中的臨限值分布之變化量係變小，故而係成為能夠對於鄰接胞間干涉量作抑制。又，藉由使1個頁面(具體而言，Middle頁面)在雙方的階段中而將資料作輸入，係能夠將2nd階段之前的IDL餘裕擴大，而成為能夠使寫入序列之信賴性提升。又，由於係使用1-4-5-5資料編碼，因此，在1st階段之程式化時，藉由將在Lower頁面處的臨限值邊界設為1個，並將在Middle頁面處之臨限值邊界設為2個，係能夠將1st階段之程式化、亦即是將Lower頁面以及Middle頁面之程式化高速化。另外，1st階段之程式化的高速化，係能夠藉由像是在反覆進行寫入與寫入驗證時，使寫入電壓逐次些許地階段性提升(step up)並將寫入時之階段電壓設為較2nd階段之程式化而更大之值等，來進行高速化。 (第2實施形態) 在第1實施形態中，雖係以1-4-5-5資料編碼為例來作了說明，但是，係可採用各種的資料編碼之變形。由第2實施形態所致之記憶體系統1的硬體構成，係與由第1實施形態所致之記憶體系統1共通。圖17～圖25，係對於由第2實施形態所致之記憶體系統1的資料編碼之例作展示。由第2實施形態所致之記憶體系統1，係使用1-4-5-5的資料編碼以外的資料編碼。 圖17，係為對於1-5-4-5資料編碼的其中一例作展示之圖。在圖17之例中，在2nd程式化結束時的臨限值區域之變遷數係為最大3個。於此，1st階段之程式化結束時的臨限值區域和2nd階段之程式化結束時的臨限值區域，其電壓分布範圍係並非完全相互一致，但是，在本說明書中，為了方便說明，係對於1st階段之程式化結束時的各臨限值區域而將電壓分布範圍最為接近的2nd階段之程式化結束時之臨限值區域附加對應，並將進行了2nd程式化時而有所變化的臨限值區域之數量，稱作變遷數。於圖17之情況，在1st階段處，係輸入Lower頁面、Middle頁面、Upper頁面之資料而進行程式化，在2nd階段處，係輸入Top頁面與Middle頁面之資料並進行程式化。Middle頁面之資料，係在1st階段與2nd階段處而重複被輸入。在1st階段之程式化結束時間點處而能夠藉由Middle頁面之資料之值來作分離之2個的臨限值區域之間隔，係設為較其他之臨限值區域之間隔而更窄。 圖18，係為對於1-5-4-5資料編碼的其中一例作展示之圖。在圖18之例中，在2nd程式化結束時的臨限值區域之變遷數係為最大3個。於圖18之情況，在1st階段處，係輸入Lower頁面、Middle頁面、Upper頁面之資料而進行程式化，在2nd階段處，係輸入Top頁面與Upper頁面之資料並進行程式化。Upper頁面之資料，係在1st階段與2nd階段處而重複被輸入。在1st階段之程式化結束時間點處而能夠藉由Upper頁面之資料之值來作分離之2個的臨限值區域之間隔，係設為較其他之臨限值區域之間隔而更窄。 圖19，係為對於3-5-2-5資料編碼的其中一例作展示之圖。在圖19之例中，在2nd程式化結束時的臨限值區域之變遷數係為最大3個。於圖19之情況，在1st階段處，係輸入Lower頁面、Middle頁面、Upper頁面之資料而進行程式化，在2nd階段處，係輸入Top頁面與Middle頁面之資料並進行程式化。Middle頁面之資料，係在1st階段與2nd階段處而重複被輸入。在1st階段之程式化結束時間點處而能夠藉由Middle頁面之資料之值來作分離之2個的臨限值區域之間隔，係設為較其他之臨限值區域之間隔而更窄。 圖20，係為對於3-3-4-5資料編碼的其中一例作展示之圖。在圖20之例中，在2nd程式化結束時的臨限值區域之變遷數係為最大3個。於圖20之情況，在1st階段處，係輸入Lower頁面、Middle頁面、Upper頁面之資料而進行程式化，在2nd階段處，係輸入Top頁面與Upper頁面之資料並進行程式化。 圖21，係為對於2-3-5-5資料編碼的其中一例作展示之圖。在圖21之例中，在2nd程式化結束時的臨限值區域之變遷數係為最大5個。於圖21之情況，在1st階段處，係輸入Lower頁面、Middle頁面、Top頁面之資料而進行程式化，在2nd階段處，係輸入Top頁面與Upper頁面之資料並進行程式化。Top頁面之資料，係在1st階段與2nd階段處而重複被輸入。於圖21之情況，在1st階段之程式化結束的時間點處，不論Top頁面之資料係為0或是1，3個的臨限值區域係均成為相同，臨限值區域之總數係成為5個。故而，係能夠將各臨限值區域之間隔擴廣，而能夠正確地進行在1st階段之程式化結束的時間點處之資料讀出。 圖22，係為對於3-2-5-5資料編碼的其中一例作展示之圖。在圖22之例中，在2nd程式化結束時的臨限值區域之變遷數係為最大5個。於圖22之情況，在1st階段處，係輸入Lower頁面、Middle頁面、Top頁面之資料而進行程式化，在2nd階段處，係輸入Top頁面與Upper頁面之資料並進行程式化。Top頁面之資料，係在1st階段與2nd階段處而重複被輸入。於圖22之情況，在1st階段之程式化結束的時間點處，不論Top頁面之資料係為0或是1，2個的臨限值區域係均成為相同，臨限值區域之總數係成為6個。 圖23，係為對於3-4-4-4資料編碼的其中一例作展示之圖。在圖23之例中，在2nd程式化結束時的臨限值區域之變遷數係為最大7個。於圖23之情況，在1st階段處，係輸入Lower頁面、Middle頁面、Upper頁面之資料而進行程式化，在2nd階段處，係輸入Top頁面與Upper頁面之資料並進行程式化。Upper頁面之資料，係在1st階段與2nd階段處而重複被輸入。在1st階段之程式化結束時間點處而能夠藉由Upper頁面之資料之值來作分離之2個的臨限值區域之間隔，係設為較其他之臨限值區域之間隔而更窄。 圖24，係為對於3-4-4-4資料編碼的其中一例作展示之圖。在圖24之例中，在2nd程式化結束時的臨限值區域之變遷數係為最大8個。於圖24之情況，在1st階段處，係輸入Lower頁面、Middle頁面、Top頁面之資料而進行程式化，在2nd階段處，係輸入Top頁面與Upper頁面之資料並進行程式化。Top頁面之資料，係在1st階段與2nd階段處而重複被輸入。於圖24之情況，在1st階段之程式化結束的時間點處，不論Top頁面之資料係為0或是1，2個的臨限值區域係均成為相同，臨限值區域之總數係成為6個。 圖17～圖24，係僅為資料編碼之例，而亦可採用其他的資料編碼。 例如，在2nd程式化結束時的臨限值區域之變遷數係成為最大3個之例，除了圖17～圖20以外，係亦存在有以下之圖25～圖27。圖25，係為對於1-4-5-5資料編碼的其中一例作展示之圖。在圖25之例中，在1st程式化結束了的時間點處，係被產生有6個的相異之臨限值區域。其中，Middle頁面為1而Lower頁面為1之臨限值區域、和Middle頁面為0而Lower頁面為1之臨限值區域，係不論Top頁面為0或是1，均成為相同之臨限值區域。因此，雖然原本應該要被產生有8個的臨限值區域，但是係被匯集為6個的臨限值區域。 圖26，係為對於2-5-3-5資料編碼的其中一例作展示之圖。在圖26之例中，在1st程式化結束了的時間點處，係被產生有7個的相異之臨限值區域。其中，Middle頁面為1而Lower頁面為1之臨限值區域，係不論Top頁面為0或是1，均成為相同之臨限值區域。因此，雖然原本應該要被產生有8個的臨限值區域，但是係被匯集為7個的臨限值區域。 圖27，係為對於3-4-5-3資料編碼的其中一例作展示之圖。在圖27之例中，在1st程式化結束了的時間點處，係被產生有7個的相異之臨限值區域。其中，Middle頁面為1而Lower頁面為1之臨限值區域，係不論Top頁面為0或是1，均成為相同之臨限值區域。因此，雖然原本應該要被產生有8個的臨限值區域，但是係被匯集為7個的臨限值區域。 除此之外，係亦可考慮有其他的資料編碼之例。以下，將針對各資料編碼的碼分配作展示之圖作列記。圖28，係對於3-2-5-5資料編碼之其中一例作展示，圖29，係對於3-2-5-5資料編碼之其中一例作展示，圖30，係對於1-5-5-4資料編碼之其中一例作展示。又，圖31，係對於1-5-4-5資料編碼之其中一例作展示，圖32，係對於1-4-5-5資料編碼之其中一例作展示，圖33，係對於1-5-3-6資料編碼之其中一例作展示。又，圖34，係對於1-3-6-5資料編碼之其中一例作展示，圖35，係對於1-2-6-6資料編碼之其中一例作展示，圖36，係對於1-2-6-6資料編碼之其中一例作展示。 又，圖37，係對於1-2-6-6資料編碼之其中一例作展示，圖38，係對於1-4-6-4資料編碼之其中一例作展示，圖39，係對於1-4-4-6資料編碼之其中一例作展示。又，圖40，係對於1-4-6-4資料編碼之其中一例作展示，圖41，係對於1-4-4-6資料編碼之其中一例作展示，圖42，係對於2-5-2-6資料編碼之其中一例作展示。又，圖43，係對於2-5-2-6資料編碼之其中一例作展示，圖44，係對於2-5-2-6資料編碼之其中一例作展示，圖45，係對於3-3-3-6資料編碼之其中一例作展示。又，圖46，係對於3-3-6-3資料編碼之其中一例作展示，圖47，係對於2-3-4-6資料編碼之其中一例作展示，圖48，係對於3-4-2-6資料編碼之其中一例作展示。 又，圖49，係對於2-3-4-6資料編碼之其中一例作展示，圖50，係對於3-2-6-4資料編碼之其中一例作展示，圖51，係對於3-2-4-6資料編碼之其中一例作展示。又，圖52，係對於3-2-6-4資料編碼之其中一例作展示，圖53，係對於3-4-2-6資料編碼之其中一例作展示，圖54，係對於3-2-4-6資料編碼之其中一例作展示。又，圖55，係對於5-3-2-5資料編碼之其中一例作展示，圖56，係對於3-5-2-5資料編碼之其中一例作展示，圖57，係對於3-2-5-5資料編碼之其中一例作展示。又，圖58，係對於2-3-5-5資料編碼之其中一例作展示，圖59，係對於2-3-5-5資料編碼之其中一例作展示，圖60，係對於2-3-5-5資料編碼之其中一例作展示。 又，圖61，係對於5-4-2-4資料編碼之其中一例作展示，圖62，係對於4-5-2-4資料編碼之其中一例作展示，圖63，係對於5-4-2-4資料編碼之其中一例作展示。又，圖64，係對於2-4-5-4資料編碼之其中一例作展示，圖65，係對於2-4-5-4資料編碼之其中一例作展示，圖66，係對於2-5-4-4資料編碼之其中一例作展示。又，圖67，係對於2-5-4-4資料編碼之其中一例作展示，圖68，係對於2-5-4-4資料編碼之其中一例作展示，圖69，係對於1-5-4-5資料編碼之其中一例作展示。又，圖70，係對於1-4-5-5資料編碼之其中一例作展示，圖71，係對於1-5-5-4資料編碼之其中一例作展示，圖72，係對於1-4-5-5資料編碼之其中一例作展示。 又，圖73，係對於1-5-5-4資料編碼之其中一例作展示，圖74，係對於1-5-4-5資料編碼之其中一例作展示，圖75，係對於1-5-5-4資料編碼之其中一例作展示。又，圖76，係對於1-5-4-5資料編碼之其中一例作展示，圖77，係對於1-4-5-5資料編碼之其中一例作展示，圖78，係對於1-4-5-5資料編碼之其中一例作展示。又，圖79，係對於1-4-5-5資料編碼之其中一例作展示，圖80，係對於1-4-5-5資料編碼之其中一例作展示，圖81，係對於3-5-4-3資料編碼之其中一例作展示。又，圖82，係對於3-4-5-3資料編碼之其中一例作展示，圖83，係對於3-5-3-4資料編碼之其中一例作展示，圖84，係對於3-4-3-5資料編碼之其中一例作展示。 又，圖85，係對於3-4-5-3資料編碼之其中一例作展示，圖86，係對於3-4-3-5資料編碼之其中一例作展示，圖87，係對於3-3-5-4資料編碼之其中一例作展示。又，圖88，係對於3-3-5-4資料編碼之其中一例作展示，圖89，係對於4-5-3-3資料編碼之其中一例作展示，圖90，係對於3-5-4-3資料編碼之其中一例作展示。又，圖91，係對於3-4-5-3資料編碼之其中一例作展示，圖92，係對於3-3-4-5資料編碼之其中一例作展示，圖93，係對於3-3-4-5資料編碼之其中一例作展示。 又，圖94，係對於3-3-4-5資料編碼之其中一例作展示，圖95，係對於3-4-5-3資料編碼之其中一例作展示，圖96，係對於3-3-5-4資料編碼之其中一例作展示。又，圖97，係對於3-3-4-5資料編碼之其中一例作展示，圖98，係對於4-3-4-4資料編碼之其中一例作展示，圖99，係對於3-4-4-4資料編碼之其中一例作展示。又，圖100，係對於3-4-4-4資料編碼之其中一例作展示，圖101，係對於4-3-4-4資料編碼之其中一例作展示，圖102，係對於3-4-4-4資料編碼之其中一例作展示。又，圖103，係對於3-4-4-4資料編碼之其中一例作展示，圖104，係對於3-4-4-4資料編碼之其中一例作展示，圖105，係對於3-4-4-4資料編碼之其中一例作展示。又，圖106，係對於4-4-3-4資料編碼之其中一例作展示，圖107，係對於4-4-3-4資料編碼之其中一例作展示。 如此這般，藉由在1st階段和2nd階段處，將一部分之頁面的資料重複作輸入，並將其他之頁面的資料，僅在1st階段以及2nd階段之其中一方處作輸入而進行程式化，係能夠降低胞間相互干涉，並且亦能夠削減寫入緩衝之容量，並且亦可對於在將各位元資料作寫入時的位元錯誤率之偏頗作抑制。特別是，在1-4-5-5、1-5-4-5、3-3-4-5或者是3-5-2-5資料編碼的情況時，由於各頁面資料之邊界數係為均一，並且在2nd階段之程式化時的臨限值區域之變遷數係為3以下，因此，係能夠對於位元錯誤率之偏頗作抑制，並且能夠降低胞間相互干涉。 (第3實施形態) 由第3實施形態所致之記憶體系統1，係為將寫入緩衝之容量相較於第1以及第2實施形態而更進一步作了削減者。 由第3實施形態所致之記憶體系統1的硬體構成，係與由第1以及第2實施形態所致之記憶體系統1共通。在第3實施形態中，係將與1st階段之程式化重複地而亦在2nd階段之程式化中作輸入的頁面之資料，於1st階段之程式化開始後，仍持續保持於非揮發性記憶體3之內部的頁面緩衝24中。藉由此，在2nd階段之程式化中，係能夠省略該頁面之資料輸入的程序，並且成為能夠將所有的頁面之資料輸入設為僅有1次。藉由此，係能夠將寫入緩衝之容量作削減。 進而，在本實施形態中，係將字元線WLn-1之2nd階段的程式化和字元線WLn之1st階段的程式化作統整而進行之。如此這般，頁面緩衝24，係將第1～第4位元(Lower頁面、Middle頁面、Upper頁面、Top頁面)中的於1st階段之程式化2nd階段之程式化時會被重複輸入的位元之資料，在開始1st階段之程式化之前而作記憶，並在開始了2nd階段之程式化之後設為能夠廢棄或無效化。以下，在本實施形態中，亦同樣的，係針對使用與第1實施形態之在圖6中所作了說明者相同之1-4-5-5資料編碼之例，來進行說明。 在圖9所示之程式化的流程圖中，1st階段之程式化和2nd階段之程式化，係使實行時序相互偏移，在各者的程式化時，係需要進行各者之程式化指令與程式化資料之輸入。相對於此，在本實施形態中，係將1st階段之程式化和2nd階段之程式化的程式化指令與程式化資料輸入盡可能地作統整而進行之。 例如，如同在圖8B所示一般，除了區塊之開頭和結束的端部之外，字元線WLn之1st階段和字元線WLn-1之2nd階段的程式化係絕對為連續。因此，在本實施形態中，係將此部份設為統合的指令輸入。亦即是，藉由1次的指令輸入，字元線WLn之Lower頁面、Middle頁面以及Top頁面與字元線WLn-1之Upper頁面之各程式化資料係被整批地輸入。此係身為與採用有Foggy-Fine的情況時之藉由1次的程式化指令而使Lower/Middle/Upper/Top頁面之資料被整批地(但是，於此情況，係為相同字元線WLi內之頁面)作了4個頁面之量之輸入一事相同的資料量之輸入。 如此這般，藉由將程式化指令以及程式化資料之輸入作統整，在記憶體控制器2所進行的控制中之指令輸入和輪詢(關於chip busy是否回復到的ready一事的定期性之檢查)之頻度係減少，記憶體系統1之高速化與控制的簡單化係成為可能。 於此，針對依循於由第3實施形態所致的程式化順序之寫入程序的其中一例，使用圖108以及圖109而作說明。在圖108以及圖109中，係對於在依循了圖8B中所示之程式化順序的情況時之寫入程序作展示。 圖108，係為對於由第3實施形態所致的1個區塊之量之全體的寫入程序作展示之流程圖。於此之1個區塊，假設係具備有字元線WL0～WLn(n為自然數)之n＋1根的字元線WLi。如同圖108中所示一般，若是開始進行寫入(步驟S710)，則係進行字串St0～St3之字元線WL0之1st階段的程式化之處理(步驟S712)。藉由此，控制部22，係實施字串St0～St3之字元線WL0之1st階段的程式化(步驟S714)。 又，控制部22，係實施字串St0＿字元線WL1之1st階段的程式化和字串St0＿字元線WL0之2nd階段的程式化(步驟S716)。 接著，控制部22，係實施字串St1＿字元線WL1之1st階段的程式化和字串St1＿字元線WL0之2nd階段的程式化(步驟S718)。接著，控制部22，係實施字串St2＿字元線WL1之1st階段的程式化和字串St2＿字元線WL0之2nd階段的程式化(步驟S720)。之後，控制部22，係對於各字串之各字元線WLi而反覆進行同樣的處理。 接著，係實施字串St0＿字元線WLn之1st階段的程式化和字串St0＿字元線WLn-1之2nd階段的程式化(步驟S722)。接著，控制部22，係實施字串St1＿字元線WLn之1st階段的程式化和字串St1＿字元線WLn-1之2nd階段的程式化(步驟S724)。之後，控制部22，係對於各字串之各字元線WLi而反覆進行同樣的處理。 接著，控制部22，係實施字串St3＿字元線WLn之1st階段的程式化和字串St3＿字元線WLn-1之2nd階段的程式化(步驟S726)。接著，控制部22，係實施字串St0～St3之字元線WLn之2nd階段的程式化(步驟S728、S730、S732)。 如此這般，在區塊之開頭處，係與第1實施形態相同地而被實施僅有1st階段之程式化，在區塊之最後處，係與第1實施形態相同地而被實施僅有2nd階段之程式化。於此情況，僅有1st階段之程式化，係依循於圖8B中所示之程序而被實行，僅有2nd階段之程式化，係依循於圖8C中所示之程序而被實行。又，在圖108之流程圖中，除了區塊之開頭與最後以外，係將字元線WLn之1st階段的程式化和字元線WLn-1之2nd階段的程式化作統整而進行之。藉由此，記憶體控制器2所進行的指令輸入和輪詢之頻度係減少，而能夠將記憶體系統1之處理高速化。 圖109，係為對於第3實施形態的1st階段以及2nd階段中之寫入程序作展示之流程圖。如同圖109中所示一般，在1st階段以及2nd階段之程式化中，於1st階段之程式化被作了實行之後，接著2nd階段之程式化係被實行。具體而言，首先，係從記憶體控制器2對於非揮發性記憶體3而被輸入有字元線WLn-1之Upper頁面之資料的輸入開始指令(步驟S750)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有字元線WLn-1之Upper頁面之資料(步驟S752)。 接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有字元線WLn之Lower頁面之資料的輸入開始指令(步驟S754)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有字元線WLn之Lower頁面之資料(步驟S756)。 接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有字元線WLn之Middle頁面之資料的輸入開始指令(步驟S758)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有字元線WLn之Middle頁面之資料(步驟S760)。Middle頁面之資料，係並不僅是被輸入至非揮發性記憶體3處，而亦被記憶在頁面緩衝24中。在記憶於頁面緩衝24中之後，係能夠將寫入緩衝內之Middle資料廢棄或無效化。 接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有字元線WLn之Top頁面之資料的輸入開始指令(步驟S762)。之後，係從記憶體控制器2對於非揮發性記憶體3而被輸入有字元線WLn之Top頁面之資料(步驟S764)。 接著，係從記憶體控制器2對於非揮發性記憶體3而被輸入有1st階段以及2nd階段之程式化實行指令(步驟S766)，並藉由此而成為chip_busy(步驟S768)。 之後，對於字元線WLn之Lower頁面、Middle頁面以及Top頁面，係被施加有1～複數次的程式化電壓脈衝(步驟S770)。之後，為了對於記憶體胞是否超越臨限值邊界準位地而作了移動一事作確認，係進行有字元線WLn之Lower頁面和Top頁面之資料讀出(步驟S772)。 進而，係確認在Lower頁面和Top頁面中之資料的失敗位元數量是否為較判定基準而更小(步驟S774)。當Lower頁面與Top頁面中之資料的失敗位元數量係為判定基準以上的情況時，步驟S770～S774之處理係被反覆進行。而，若是資料的失敗位元數量成為較判定基準而更小，則字元線WLn-1之Lower頁面與Top頁面資料係被讀出(步驟S776)。 之後，基於字元線WLn-1之Lower與Top頁面資料和從頁面緩衝24所被讀出的Middle頁面之資料，Upper頁面之程式化目標的臨限值電壓Vth係被決定(步驟S778)。之後，使用被決定了的臨限值電壓Vth，對於字元線WLn-1之Upper頁面之資料寫入係被進行(步驟S780)。 在對於Upper頁面之資料寫入時，對於字元線WLn-1之Upper頁面，係被施加有1～複數次的程式化電壓脈衝。之後，為了對於記憶體胞是否超越臨限值邊界準位地而作了移動一事作確認，係進行有字元線WLn-1之Upper頁面之資料讀出(步驟S782)。 進而，係進行有判定在Upper頁面中之資料的失敗位元數量是否為較判定基準而更小之驗證(步驟S784)。當在Upper頁面中之資料的失敗位元數量係為判定基準以上的情況時，程式化電壓脈衝施加和資料讀出、驗證之處理係被反覆進行。而，若是資料的失敗位元數量成為較判定基準而更小，則係成為chip_ready(步驟S786)。 另外，在針對同一字元線的1st階段之程式化中，於複數之頁面的資料輸入開始指令與資料輸入處理中之頁面的順序係為任意，不論是何者之頁面先被作輸入均可。又，在針對同一字元線的2nd階段之程式化中，於複數之頁面的資料輸入開始指令與資料輸入處理中之頁面的順序亦為任意。但是，各個的字元線編號和2個的階段之程式化之處理之順序，係絕對需要成為在圖109中所示之順序。 如此這般，在圖109中，係針對使字元線WLn之1st階段的程式化在較字元線WLn-1之2nd階段的程式化更之前而被實行的情況作說明。此係為了藉由使字元線WLn之1st階段的程式化先被進行來成為不會使16值之臨限值電壓Vth所被作寫入的字元線WLn-1之胞受到鄰接之胞的影響之故。 如同上述一般，在本實施形態中，字元線WLn-1之Upper頁面之資料和字元線WLn之Lower頁面、Middle頁面以及Top頁面之資料之4個頁面之量的資料，係被連續地輸入。 又，作為另一變形例，係亦可在程式化指令之輸入後，作為IDL，而在先進行了字元線WLn-1之Lower頁面、Middle頁面以及Top頁面之資料的讀出之後，進行字元線WLn之Lower頁面、Middle頁面以及Top頁面之程式化，接著，字元線WLn-1之Upper頁面之程式化目標的臨限值電壓Vth被作決定，並藉由所被決定了的臨限值電壓Vth來進行字元線WLn-1之Upper頁面之程式化。若是設為此種構成，則係能夠在受到由字元線WLn之寫入所致的鄰接胞間干涉之影響之前，先進行IDL之字元線WLn-1之Lower頁面、Middle頁面以及Top頁面之資料的讀出。 另外，在本實施形態中的由字元線WLn之1st階段與字元線WLn-1之2nd階段之統整的指令所致之程式化的實際之實行順序，係能夠作變形。亦即是，圖109中所示之字元線WLn之Lower頁面、Middle頁面以及Top頁面的程式化、和作為IDL之字元線WLn-1之Lower頁面、Middle頁面以及Top頁面之資料的讀出，係不論何者為先均可，而可作交換。藉由將字元線WLn-1之Lower頁面、Middle頁面以及Top頁面之資料的讀出在字元線WLn之Lower頁面、Middle頁面以及Top頁面的程式化之前而先進行，係成為能夠並不受到起因於字元線WLn之Lower頁面、Middle頁面以及Top頁面的程式化所致之影響地而進行IDL。 如此這般，在第3實施形態中，由於係將字元線WLn-1之2nd階段的程式化和字元線WLn之1st階段的程式化作統整而進行之，因此指令輸入和輪詢之頻度係減少。故而，係成為能夠達成記憶體系統1之高速化以及控制之簡單化。 圖110，係為用以對於在第3實施形態之程式化中之寫入緩衝量(緩衝資料量)作說明之圖。在本實施形態中，係以1-4-5-5資料編碼而使用有2階段的程式化。在本實施形態之程式化中，於1st階段中，係進行有3個頁面之量(Lower頁面和Middle頁面以及Top頁面)的資料輸入、和此3個頁面之量的程式化(1st程式化)。又，在本實施形態之程式化的情況時，於2nd階段中，係進行有1個頁面之量(Upper頁面)的資料輸入、和Upper頁面之1個頁面之量的程式化(2nd程式化)。 而，在各字元線WL0、WL1、WL2、…處，係只要在各階段之資料輸入時將資料預先儲存在寫入緩衝中即可，若是程式化被開始，則係亦可將資料從寫入緩衝內而刪除。例如，若是在1st階段處而資料被作輸入，則此資料係被儲存在寫入緩衝內。而，若是在1st階段處而程式化被開始，則係亦可將預先被儲存在寫入緩衝內之Lower頁面和Top頁面以及Middle頁面之資料刪除。但是，Middle頁面之資料，由於係在2nd階段處亦被作使用，因此，直到2nd階段處之程式化被開始為止，係有必要預先記憶在頁面緩衝24中。同樣的，若是在2nd階段處而資料被作輸入，則此資料係被儲存在寫入緩衝內。而，若是在2nd階段處而程式化被開始，則係亦可將預先被儲存在寫入緩衝內之資料全部刪除。因此，在本實施形態之程式化的情況時，有必要預先保持在寫入緩衝內之資料，就算是最大亦係僅為3個頁面之量的資料，而可成為較第1實施形態而更為減少。 在本實施形態之程式化中，亦同樣的，為了將鄰接記憶體胞間干涉降低，Lower/Middle/Upper/Top之4個頁面之量的資料係並不被連續地作寫入。例如，在對於字元線WL0之1st階段被作了實行之後，於對於字元線WL0之2nd階段被實行之前，對於與字元線WL0相鄰接之字元線WL1的1st階段係被實行。同樣的，在對於字元線WL1之1st階段被作了實行之後，於對於字元線WL1之2nd階段被實行之前，對於與字元線WL1相鄰接之字元線WL2的1st階段係被實行。 如此這般，在本實施形態中，由於所有的頁面資料，係僅在1次的階段之程式化中而為必要，因此，若是該資料輸入結束，則係成為能夠將寫入緩衝內之資料刪除。因此，在本實施形態中，有必要預先同時保持在寫入緩衝內之頁面數量，係僅需要較第1實施形態而更少即可。 被對於非揮發性記憶體3而進行程式化的頁面資料，係先在RAM6內之寫入緩衝中暫時被作保持，之後在程式化時被資料輸入至非揮發性記憶體3中。在本實施形態中，由於係成為能夠將此RAM6之必要容量縮小，因此係成為使成本被削減。 又，在本實施形態中，由於係藉由各頁面之各者的1次之資料傳輸而結束，因此，相較於第1實施形態，係亦僅需要較少的頁面資料之傳輸時間，而成為能夠將傳輸時之消耗電力作削減。 關於在本實施形態中之頁面讀出處理，由於係與在第1實施形態中所作了說明的處理程序相同，故省略其說明。 另外，在本實施形態中，為了新的需要繼續作保持之頁面之資料，係需要將NAND快閃記憶體內部之頁面緩衝24作增加。在如同圖8A中所示一般之於區塊內存在有1個的字串之NAND快閃記憶體之程式化中，需要作增加的頁面緩衝24之量，係為1個頁面的資料之量。相對於此，在如同圖8B或圖8C中所示一般之於區塊內存在有4個的字串之NAND快閃記憶體之程式化中，需要作增加的頁面緩衝24之量，係為4個頁面的資料之量。此係因為，在從實行某一個的字串之1st階段之程式化起直到實行相同字串之2nd階段之程式化為止的期間中，係需要實行其他之3個的字串之1st階段之程式化，其結果，係需要針對4個的字串之全部，而分別保持1個頁面之量的資料之故。 在本實施形態中，雖係以1-4-5-5資料編碼為例來作了說明，但是，係可採用各種的資料編碼之變形，並明顯地能夠實現於上所述之實施形態。 在上述之第1～第3實施形態中，雖係針對使用NAND記憶體5來構成非揮發性記憶體3的情況而作了說明，但是，係亦可使用像是ReRAM(Resistive Random Access Memory)或MRAM6(Magneto-Resistive Random Access Memory)、PRAM(Phase Change Random Access Memory)、FeRAM(Ferroeletric Random Access Memory)等之其他型態的非揮發性記憶體3。 在上述之第1～第3實施形態中，雖係針對於1st階段之程式化中係進行3個頁面之量的資料之寫入，於2nd階段之程式化中係進行2個頁面之量的資料之寫入的情況，來作了說明，但是，係亦可對於1st階段之程式化中的頁面數量和2nd階段之程式化中的頁面數量之分配作變更。例如，係亦可構成為在1st階段之程式化中係進行2個頁面之量的資料之寫入，而在2nd階段之程式化中係進行3個頁面之量的資料之寫入。 雖係針對本揭示之數種實施形態作了說明，但是，該些實施形態，係僅為作為例子所提示者，而並非為對於本發明之範圍作限定者。此些之新穎的實施形態，係可藉由其他之各種形態來實施，在不脫離發明之要旨的範圍內，係可進行各種之省略、置換、變更。此些之實施形態或其變形，係亦被包含於發明之範圍或要旨中，並且亦被包含在申請專利範圍中所記載的發明及其均等範圍內。 In the page read process according to one of the modifications, the delay until data of any one page can be output becomes longer, but the total time to read out all four pages is long. , the total time can be shortened more than the above-described case where one page is read at a time. As shown in FIG. 16D , it takes only one time to charge the word line from 0 to Vr15 which is a high voltage in preparation for reading. The amplitude of the voltage change when changing to the next voltage is small, and the voltage becomes stable in a short time, so the standby time until the read voltage becomes stable can be shortened. Therefore, when reading is performed using all of the read voltages Vr15 to Vr1, the total of the transition times of the selected word lines is shortened, and as a result, the total read time can be accelerated. In addition, although the data encoding shown in FIG. 16B is used as an example for description, basically, it can be applied to any kind of data encoding. However, since the readout voltage is sequentially changed from the maximum voltage to the minimum voltage and readout is performed, the readout of the voltage required to determine the data is in the order of the page that ends first. Data output is possible. Therefore, it should be noted that depending on the form of data encoding, there may be cases where the page order of Lower, Middle, Upper, and Top cannot be read. In this way, in the first embodiment, when programming the non-volatile memory 3 (a NAND memory having a 4-bit/Cell having a 3-dimensional structure or a 2-dimensional structure), 1-4-5 is used. -5 data encoding, and the programming stage is set to 2-stage system. Since it is programmed in a two-stage system in this way, the amount of data inputted at the time of data programming at each stage is reduced, and the writing required in the memory controller 2 can be reduced. The amount of buffer is suppressed. In addition, since the number of threshold value boundaries at each page is uniform, it is possible to reduce the bias of the bit error rate among pages of the non-volatile memory 3, and to reduce the cost of ECC. reduce. In addition, since data transfer is performed only once for each page except for one page, it is possible to suppress transfer time and power consumption. In addition, since each programming stage is performed while crossing the word line WLi, the amount of interference between adjacent cells with adjacent word lines WLi can be reduced. In addition, since the 1-4-5-5 data encoding is used, the amount of change in the threshold value distribution in the 2nd programming becomes small, so that the amount of interference between adjacent cells can be suppressed. In addition, by inputting data in one page (specifically, the Middle page) in both stages, the IDL margin before the 2nd stage can be expanded, and the reliability of the write sequence can be improved. In addition, since the 1-4-5-5 data encoding is used, in the programming of the 1st stage, the threshold value boundary at the Lower page is set to one, and the threshold value at the Middle page is set to one. By setting the limit boundary to two, it is possible to speed up the programming of the 1st stage, that is, the programming of the Lower page and the Middle page. In addition, the programming speed of the 1st stage can be increased by, for example, when writing and writing verification are repeatedly performed, the writing voltage is gradually increased in steps (step up), and the step voltage at the time of writing can be increased. Speed up by setting it to a larger value than the programming of the 2nd stage. (Second Embodiment) In the first embodiment, the 1-4-5-5 data encoding was described as an example, but various modifications of the data encoding can be employed. The hardware configuration of the memory system 1 according to the second embodiment is common to the memory system 1 according to the first embodiment. 17 to 25 show examples of data encoding in the memory system 1 according to the second embodiment. In the memory system 1 according to the second embodiment, data codes other than the data codes of 1-4-5-5 are used. FIG. 17 is a diagram showing one example of 1-5-4-5 data encoding. In the example of FIG. 17, the transition number of the threshold value region at the end of the 2nd programming is a maximum of three. Here, the voltage distribution ranges of the threshold value region at the end of programming of the 1st stage and the threshold value region of the end of the programming of the 2nd stage are not completely consistent with each other. However, in this specification, for convenience of description, For each threshold value region at the end of programming of the 1st stage, the threshold value region at the end of the programming of the 2nd stage with the closest voltage distribution range is added to the corresponding threshold value region, and changes when the 2nd programming is performed. The number of threshold value regions of , is called the transition number. In the case of FIG. 17 , in the 1st stage, the data of the Lower page, the Middle page, and the Upper page are input and programmed, and in the 2nd stage, the data of the Top page and the Middle page are input and programmed. The information on the Middle page is repeatedly input at the 1st stage and the 2nd stage. The interval between the two threshold value areas that can be separated by the value of the data of the Middle page at the programming end time point of the 1st stage is set to be narrower than the interval between the other threshold value areas. FIG. 18 is a diagram showing one example of 1-5-4-5 data encoding. In the example of FIG. 18 , the number of transitions in the threshold value region at the end of the 2nd programming is a maximum of three. In the case of FIG. 18 , in the 1st stage, the data of the Lower page, the Middle page, and the Upper page are input and programmed, and in the 2nd stage, the data of the Top page and the Upper page are input and programmed. The data of the upper page is repeatedly input at the 1st stage and the 2nd stage. The interval between the two threshold value regions that can be separated by the data value of the Upper page at the programming end time point of the 1st stage is set to be narrower than the interval between the other threshold value regions. FIG. 19 is a diagram showing one example of 3-5-2-5 data encoding. In the example of FIG. 19, the transition number of the threshold value region at the end of the 2nd programming is a maximum of three. In the case of FIG. 19, in the 1st stage, the data of the Lower page, the Middle page, and the Upper page are input and programmed, and in the 2nd stage, the data of the Top page and the Middle page are input and programmed. The information on the Middle page is repeatedly input at the 1st stage and the 2nd stage. The interval between the two threshold value areas that can be separated by the value of the data of the Middle page at the programming end time point of the 1st stage is set to be narrower than the interval between the other threshold value areas. FIG. 20 is a diagram showing one example of 3-3-4-5 data encoding. In the example of FIG. 20, the transition number of the threshold value region at the end of the 2nd programming is a maximum of three. In the case of FIG. 20 , in the 1st stage, the data of the Lower page, the Middle page, and the Upper page are input and programmed, and in the 2nd stage, the data of the Top page and the Upper page are input and programmed. FIG. 21 is a diagram showing one example of 2-3-5-5 data encoding. In the example of FIG. 21, the number of transitions of the threshold value region at the end of the 2nd programming is a maximum of five. In the case of FIG. 21, in the 1st stage, the data of the Lower page, the Middle page, and the Top page are input and programmed, and in the 2nd stage, the data of the Top page and the Upper page are input and programmed. The information of the top page is repeatedly input at the 1st stage and the 2nd stage. In the case of Fig. 21, at the time point when the programming of the 1st stage ends, regardless of whether the data of the Top page is 0 or 1, the three threshold value areas become the same, and the total number of threshold value areas becomes 5. Therefore, the interval between each threshold value region can be widened, and the data reading at the time point when the programming of the 1st stage is completed can be performed correctly. FIG. 22 is a diagram showing one example of 3-2-5-5 data encoding. In the example of FIG. 22, the number of transitions of the threshold value region at the end of the 2nd programming is a maximum of five. In the case of FIG. 22 , in the 1st stage, the data of the Lower page, the Middle page, and the Top page are input and programmed, and in the 2nd stage, the data of the Top page and the Upper page are input and programmed. The information of the top page is repeatedly input at the 1st stage and the 2nd stage. In the case of Fig. 22, at the time point when the programming of the 1st stage ends, regardless of whether the data of the Top page is 0 or 1, the two threshold value areas become the same, and the total number of threshold value areas becomes 6. FIG. 23 is a diagram showing one example of 3-4-4-4 data encoding. In the example of FIG. 23, the number of transitions of the threshold value region at the end of the 2nd programming is a maximum of seven. In the case of FIG. 23, in the 1st stage, the data of the Lower page, the Middle page, and the Upper page are input and programmed, and in the 2nd stage, the data of the Top page and the Upper page are input and programmed. The data of the upper page is repeatedly input at the 1st stage and the 2nd stage. The interval between the two threshold value regions that can be separated by the data value of the Upper page at the programming end time point of the 1st stage is set to be narrower than the interval between the other threshold value regions. FIG. 24 is a diagram showing one example of 3-4-4-4 data encoding. In the example of FIG. 24, the transition number of the threshold value region at the end of the 2nd programming is a maximum of eight. In the case of FIG. 24, in the 1st stage, the data of the Lower page, the Middle page, and the Top page are input and programmed, and in the 2nd stage, the data of the Top page and the Upper page are input and programmed. The information of the top page is repeatedly input at the 1st stage and the 2nd stage. In the case of Fig. 24, at the time point when the programming of the 1st stage ends, regardless of whether the data of the Top page is 0 or 1, the two threshold value areas become the same, and the total number of threshold value areas becomes 6. Figures 17 to 24 are only examples of data encoding, and other data encodings may also be used. For example, when the number of transitions of the threshold value region at the end of the 2nd programming is a maximum of three, in addition to FIGS. 17 to 20 , the following FIGS. 25 to 27 also exist. FIG. 25 is a diagram showing one example of 1-4-5-5 data encoding. In the example of FIG. 25, at the time point when the 1st programming is completed, six different threshold value regions are generated. Among them, the threshold value area where the Middle page is 1 and the Lower page is 1, and the threshold value area where the Middle page is 0 and the Lower page is 1, are the same threshold value regardless of whether the Top page is 0 or 1 area. Therefore, although 8 threshold value areas should be generated originally, they are collected into 6 threshold value areas. FIG. 26 is a diagram showing one example of 2-5-3-5 data encoding. In the example of FIG. 26, at the time point when the 1st programming is completed, seven different threshold value regions are generated. Among them, the threshold value area where the Middle page is 1 and the Lower page is 1, is the same threshold value area regardless of whether the Top page is 0 or 1. Therefore, although eight threshold value areas should be generated originally, they are collected into seven threshold value areas. FIG. 27 is a diagram showing one example of 3-4-5-3 data encoding. In the example of FIG. 27, at the time point when the 1st programming is completed, seven different threshold value regions are generated. Among them, the threshold value area where the Middle page is 1 and the Lower page is 1, is the same threshold value area regardless of whether the Top page is 0 or 1. Therefore, although eight threshold value areas should be generated originally, they are collected into seven threshold value areas. In addition, other data coding examples can also be considered. Below, the diagram showing the code assignment for each data code will be listed. Figure 28 shows one example of 3-2-5-5 data coding, Figure 29 shows one example of 3-2-5-5 data coding, and Figure 30 shows 1-5-5 One example of -4 data encoding is shown. Also, Figure 31 shows one example of 1-5-4-5 data coding, Figure 32 shows one example of 1-4-5-5 data coding, and Figure 33 shows 1-5 data coding. -One example of data encoding in 3-6 is shown. Also, Fig. 34 shows one example of 1-3-6-5 data coding, Fig. 35 shows one example of 1-2-6-6 data coding, and Fig. 36 shows 1-2 -6-6 One example of data encoding is shown. Also, Figure 37 shows one example of 1-2-6-6 data coding, Figure 38 shows one example of 1-4-6-4 data coding, and Figure 39 shows 1-4 -4-6 One example of data encoding is shown. Also, Fig. 40 shows one example of 1-4-6-4 data coding, Fig. 41 shows one example of 1-4-4-6 data coding, and Fig. 42 shows 2-5 -2-6 One example of data encoding is shown. Also, Fig. 43 shows one example of 2-5-2-6 data coding, Fig. 44 shows one example of 2-5-2-6 data coding, and Fig. 45 shows 3-3 data coding. -One example of data encoding in 3-6 is shown. Also, Fig. 46 shows one example of 3-3-6-3 data coding, Fig. 47 shows one example of 2-3-4-6 data coding, and Fig. 48 shows 3-4 data coding -2-6 One example of data encoding is shown. Also, Figure 49 shows one example of 2-3-4-6 data coding, Figure 50 shows one example of 3-2-6-4 data coding, and Figure 51 shows 3-2 -4-6 One example of data encoding is shown. Also, Figure 52 shows one example of 3-2-6-4 data coding, Figure 53 shows one example of 3-4-2-6 data coding, and Figure 54 shows 3-2 -4-6 One example of data encoding is shown. Also, Figure 55 shows one example of 5-3-2-5 data coding, Figure 56 shows one example of 3-5-2-5 data coding, and Figure 57 shows 3-2 One of the examples of -5-5 data codes is shown. Also, Figure 58 shows one example of 2-3-5-5 data coding, Figure 59 shows one example of 2-3-5-5 data coding, and Figure 60 shows 2-3 One of the examples of -5-5 data codes is shown. Also, Figure 61 shows one example of 5-4-2-4 data encoding, Figure 62 shows one example of 4-5-2-4 data encoding, and Figure 63 shows 5-4 -2-4 One example of data encoding is shown. Also, Figure 64 shows one example of 2-4-5-4 data encoding, Figure 65 shows one example of 2-4-5-4 data encoding, and Figure 66 shows 2-5 -4-4 One example of data encoding is shown. Also, Figure 67 shows one example of 2-5-4-4 data encoding, Figure 68 shows one example of 2-5-4-4 data encoding, and Figure 69 shows 1-5 One of the examples of -4-5 data encoding is shown. Also, Figure 70 shows one example of 1-4-5-5 data coding, Figure 71 shows one example of 1-5-5-4 data coding, and Figure 72 shows 1-4 One of the examples of -5-5 data codes is shown. Also, Figure 73 shows one example of 1-5-5-4 data coding, Figure 74 shows one example of 1-5-4-5 data coding, and Figure 75 shows 1-5 -5-4 One example of data encoding is shown. Also, Figure 76 shows one example of 1-5-4-5 data coding, Figure 77 shows one example of 1-4-5-5 data coding, and Figure 78 shows 1-4 One of the examples of -5-5 data codes is shown. Also, Figure 79 shows one example of 1-4-5-5 data coding, Figure 80 shows one example of 1-4-5-5 data coding, and Figure 81 shows 3-5 data coding -4-3 One example of data encoding is shown. Also, Fig. 82 shows one example of 3-4-5-3 data coding, Fig. 83 shows one example of 3-5-3-4 data coding, and Fig. 84 shows 3-4 data coding. One of the examples of -3-5 data codes is shown. Also, Fig. 85 shows one example of 3-4-5-3 data coding, Fig. 86 shows one example of 3-4-3-5 data coding, and Fig. 87 shows 3-3 data coding. -5-4 One example of data encoding is shown. Also, Figure 88 shows one example of 3-3-5-4 data encoding, Figure 89 shows one example of 4-5-3-3 data encoding, and Figure 90 shows 3-5 -4-3 One example of data encoding is shown. Also, Fig. 91 shows one example of 3-4-5-3 data coding, Fig. 92 shows one example of 3-3-4-5 data coding, and Fig. 93 shows 3-3 data coding. One of the examples of -4-5 data encoding is shown. Also, Fig. 94 shows one example of 3-3-4-5 data coding, Fig. 95 shows one example of 3-4-5-3 data coding, and Fig. 96 shows 3-3 data coding. -5-4 One example of data encoding is shown. Also, Fig. 97 shows one example of 3-3-4-5 data coding, Fig. 98 shows one example of 4-3-4-4 data coding, and Fig. 99 shows 3-4 data coding. -4-4 One example of data encoding is shown. Also, Fig. 100 shows one example of 3-4-4-4 data encoding, Fig. 101 shows one example of 4-3-4-4 data encoding, and Fig. 102 shows 3-4 data encoding. -4-4 One example of data encoding is shown. Also, Figure 103 shows one example of 3-4-4-4 data encoding, Figure 104 shows one example of 3-4-4-4 data encoding, and Figure 105 shows 3-4 data encoding -4-4 One example of data encoding is shown. Also, Fig. 106 shows one example of 4-4-3-4 data encoding, and Fig. 107 shows one example of 4-4-3-4 data encoding. In this way, by repeatedly inputting the data of a part of the pages at the 1st stage and the 2nd stage, and inputting the data of the other pages only at one of the 1st stage and the 2nd stage, the programming is performed, It can reduce the mutual interference between cells, and can also reduce the capacity of the write buffer, and can also suppress the bias of the bit error rate when writing each bit of metadata. In particular, in the case of 1-4-5-5, 1-5-4-5, 3-3-4-5 or 3-5-2-5 data encoding, the boundary number coefficient of each page data It is uniform, and the transition number of the threshold value region in the programming of the 2nd stage is 3 or less, so the bias of the bit error rate can be suppressed, and the mutual interference between cells can be reduced. (Third Embodiment) The memory system 1 according to the third embodiment further reduces the capacity of the write buffer compared to the first and second embodiments. The hardware configuration of the memory system 1 according to the third embodiment is common to the memory system 1 according to the first and second embodiments. In the third embodiment, the data of the page that is repeated with the programming of the 1st stage and also inputted in the programming of the 2nd stage is kept in the non-volatile memory after the programming of the 1st stage starts. in page buffer 24 within body 3. Thereby, in the programming of the 2nd stage, the data input procedure of the page can be omitted, and the data input of all the pages can be made only once. Thereby, the capacity of the write buffer can be reduced. Furthermore, in the present embodiment, the programming of the 2nd stage of the word line WLn-1 and the programming of the 1st stage of the word line WLn are integrated and performed. In this way, the page buffer 24 is the bits that will be repeatedly input during the programming in the 1st stage and the 2nd stage in the 1st to 4th bits (Lower page, Middle page, Upper page, Top page) The meta data is memorized before starting the programming of the 1st stage, and can be discarded or invalidated after the programming of the 2nd stage is started. Hereinafter, in the present embodiment, similarly, an example of using the same 1-4-5-5 data encoding as described in FIG. 6 of the first embodiment will be described. In the programming flow chart shown in FIG. 9, the programming of the 1st stage and the programming of the 2nd stage are performed by offsetting the execution timings. When programming each, it is necessary to carry out the programming instructions of each. and input of programmed data. On the other hand, in this embodiment, the programming command and programming data input of the programming of the 1st stage and the programming of the 2nd stage are integrated as much as possible. For example, as shown in FIG. 8B, the programming of the 1st stage of word line WLn and the 2nd stage of word line WLn-1 is absolutely continuous except for the beginning and end of the block. Therefore, in this embodiment, this part is used as an integrated command input. That is, by one command input, the programming data of the Lower page, Middle page, and Top page of the word line WLn and the Upper page of the word line WLn-1 are input in a batch. This is the same as when using Foggy-Fine, the data of the Lower/Middle/Upper/Top page is batched by one programming command (however, in this case, it is the same character (pages in line WLi) input the same amount of data for the input of 4 pages. In this way, by integrating the input of programmed commands and programmed data, command input and polling in the control performed by the memory controller 2 (periodicity regarding whether the chip busy is returned to ready) The frequency of inspection) is reduced, and the speed-up of the memory system 1 and the simplification of control become possible. Here, an example of the writing procedure according to the programming sequence according to the third embodiment will be described with reference to FIGS. 108 and 109 . In FIGS. 108 and 109, the writing procedure is shown for the case where the programming sequence shown in FIG. 8B is followed. FIG. 108 is a flowchart showing the entire writing procedure for one block according to the third embodiment. One block here is assumed to include word lines WLi including n+1 word lines WL0 to WLn (n is a natural number). As shown in FIG. 108 , when writing is started (step S710 ), the programming process of the 1st stage of the word line WL0 of the word string St0 to St3 is performed (step S712 ). Thereby, the control unit 22 executes the programming of the 1st stage of the word line WL0 of the word strings St0 to St3 (step S714). Further, the control unit 22 executes the programming of the 1st stage of the word string St0_word line WL1 and the programming of the 2nd stage of the word string St0_word line WL0 (step S716). Next, the control unit 22 executes the programming of the 1st stage of the word string St1_word line WL1 and the programming of the 2nd stage of the word string St1_word line WL0 (step S718). Next, the control unit 22 executes the programming of the 1st stage of the word string St2_word line WL1 and the programming of the 2nd stage of the word string St2_word line WL0 (step S720). After that, the control unit 22 repeatedly performs the same process for each word line WLi of each word string. Next, the programming of the 1st stage of the word string St0_word line WLn and the programming of the 2nd stage of the word string St0_word line WLn-1 are performed (step S722). Next, the control unit 22 executes the programming of the 1st stage of the word string St1_word line WLn and the programming of the 2nd stage of the word string St1_word line WLn-1 (step S724). After that, the control unit 22 repeatedly performs the same process for each word line WLi of each word string. Next, the control unit 22 executes the programming of the 1st stage of the word string St3_word line WLn and the programming of the 2nd stage of the word string St3_word line WLn-1 (step S726). Next, the control unit 22 executes the programming of the 2nd stage of the word lines WLn of the word strings St0 to St3 (steps S728, S730, and S732). In this way, at the beginning of the block, the programming of only the 1st stage is implemented in the same way as in the first embodiment, and at the end of the block, the same as in the first embodiment, only the programming is implemented. Stylization of the 2nd stage. In this case, only the programming of the 1st stage is carried out following the procedure shown in FIG. 8B, and only the programming of the 2nd stage is carried out following the procedure shown in FIG. 8C. In addition, in the flowchart of FIG. 108, the programming of the 1st stage of the word line WLn and the programming of the 2nd stage of the word line WLn-1 are performed in a unified manner, except for the beginning and the end of the block. . Thereby, the frequency of command input and polling performed by the memory controller 2 is reduced, and the processing speed of the memory system 1 can be accelerated. FIG. 109 is a flowchart showing the writing procedure in the 1st stage and the 2nd stage of the third embodiment. As shown in FIG. 109, in the programming of the 1st stage and the 2nd stage, after the programming of the 1st stage is carried out, the programming of the 2nd stage is carried out. Specifically, first, the memory controller 2 receives the input start command of the data of the Upper page of the word line WLn-1 to the non-volatile memory 3 (step S750). After that, the data of the Upper page of the word line WLn-1 is input to the non-volatile memory 3 from the memory controller 2 (step S752). Next, an input start command is given from the memory controller 2 to the nonvolatile memory 3 to which the data of the Lower page of the word line WLn is input (step S754). After that, the data of the Lower page of the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S756). Next, an input start command is issued from the memory controller 2 to the nonvolatile memory 3 to which the data of the Middle page of the word line WLn is input (step S758). After that, the data of the Middle page of the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S760). The data of the Middle page is not only input to the non-volatile memory 3, but also stored in the page buffer 24. After being stored in the page buffer 24, the Middle data written in the buffer can be discarded or invalidated. Next, an input start command is input from the memory controller 2 to the non-volatile memory 3 to which the data of the Top page of the word line WLn is input (step S762). After that, the data of the Top page of the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S764). Next, the program execution commands of the 1st stage and the 2nd stage are input to the non-volatile memory 3 from the memory controller 2 (step S766 ), and thereby become chip_busy (step S768 ). After that, one or more programming voltage pulses are applied to the lower page, the middle page and the top page of the word line WLn (step S770). After that, in order to confirm whether the memory cell has moved beyond the threshold level, data reading of the lower page and the top page having the word line WLn is performed (step S772). Furthermore, it is checked whether the number of failed bits of the data in the Lower page and the Top page is smaller than the determination reference (step S774). When the number of failed bits of the data in the Lower page and the Top page is greater than or equal to the determination criterion, the processing of steps S770 to S774 is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the determination reference, the data of the lower page and the top page of the word line WLn-1 are read (step S776). Then, based on the lower and top page data of the word line WLn-1 and the data of the middle page read out from the page buffer 24, the threshold voltage Vth of the programming target of the upper page is determined (step S778). After that, using the determined threshold voltage Vth, data writing to the upper page of the word line WLn-1 is performed (step S780). When data is written to the upper page, the upper page of the word line WLn-1 is applied with one or more programmed voltage pulses. After that, in order to confirm whether the memory cell has moved beyond the threshold level, data reading of the upper page with the word line WLn-1 is performed (step S782). Further, verification is performed to determine whether the number of failed bits of the data in the Upper page is smaller than the determination reference (step S784). When the number of failed bits of the data in the Upper page is more than the criterion, the process of applying the programmed voltage pulse and reading and verifying the data is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the determination reference, it becomes chip_ready (step S786). In addition, in the programming of the 1st stage for the same word line, the order of the data input start command on a plurality of pages and the pages in the data input process is arbitrary, whichever page is input first. In addition, in the programming of the 2nd stage for the same word line, the order of the data input start command on a plurality of pages and the pages in the data input process is also arbitrary. However, the sequence of processing of the programming of the respective word line numbers and the two stages absolutely needs to be the sequence shown in FIG. 109 . In this way, in FIG. 109, a description is given of the case where the programming of the 1st stage of the word line WLn is performed before the programming of the 2nd stage of the word line WLn-1. This is to prevent the cell of the word line WLn-1 to which the 16-value threshold voltage Vth is written by first performing the programming of the 1st stage of the word line WLn from the adjacent cells. of influence. As described above, in this embodiment, the data of the upper page of the word line WLn-1 and the data of four pages of the data of the lower page, the middle page and the top page of the word line WLn are continuously enter. In addition, as another modification, after the programming command is input, it can be used as the IDL, and the data of the lower page, the middle page and the top page of the word line WLn-1 are read out first, and then the data can be read out. The programming of the lower page, the middle page and the top page of the word line WLn, then, the threshold voltage Vth of the programming target of the upper page of the word line WLn-1 is determined, and by the determined The threshold voltage Vth is used to program the Upper page of the word line WLn-1. With this configuration, the lower page, middle page, and top page of the word line WLn-1 of the IDL can be performed before being affected by the interference between adjacent cells caused by the writing of the word line WLn. reading of the data. In addition, in this embodiment, the actual execution sequence of programming by the integrated command of the 1st stage of the word line WLn and the 2nd stage of the word line WLn-1 can be modified. That is, the lower page, the middle page and the top page of the word line WLn shown in FIG. 109 are stylized, and the data of the lower page, the middle page and the top page of the word line WLn-1 of the IDL are read. Out, whichever comes first can be exchanged. By reading the data of the Lower page, Middle page and Top page of word line WLn-1 before programming the Lower page, Middle page and Top page of word line WLn, it becomes possible to not The IDL is performed under the influence of the stylization of the Lower page, Middle page, and Top page due to word line WLn. In this way, in the third embodiment, since the programming of the 2nd stage of the word line WLn-1 and the programming of the 1st stage of the word line WLn are performed in a unified manner, command input and polling are performed. The frequency is reduced. Therefore, it is possible to achieve high speed of the memory system 1 and simplification of control. FIG. 110 is a diagram for explaining the write buffer amount (buffer data amount) in the programming of the third embodiment. In this embodiment, 1-4-5-5 data encoding is used, and two-stage programming is used. In the programming of this embodiment, in the 1st stage, data input for 3 pages (Lower page, Middle page, and Top page), and programming for these 3 pages (1st programming) are performed. ). In the case of programming in this embodiment, in the 2nd stage, data input for one page (Upper page) and programming for one page of Upper page (2nd programming) are performed. ). However, at each word line WL0, WL1, WL2, . . ., it is only necessary to store the data in the write buffer in advance when the data is input at each stage. If programming is started, the data can also be stored from the Write to the buffer and delete it. For example, if data is input at stage 1st, the data is stored in the write buffer. However, if programming is started at the 1st stage, the data of the lower page, the top page and the middle page previously stored in the write buffer may also be deleted. However, since the data of the Middle page is also used at the 2nd stage, it is necessary to store it in the page buffer 24 in advance until the programming at the 2nd stage is started. Likewise, if data is input at the 2nd stage, the data is stored in the write buffer. However, if programming is started at the 2nd stage, it is also possible to delete all the data previously stored in the write buffer. Therefore, in the case of programming of the present embodiment, it is necessary to hold the data in the write buffer in advance, even if the data is only three pages at the maximum, which can be more than the first embodiment. to reduce. In the programming of the present embodiment, similarly, in order to reduce the interference between adjacent memory cells, data corresponding to 4 pages of Lower/Middle/Upper/Top are not continuously written. For example, after the 1st stage for word line WL0 is executed, before the 2nd stage for word line WL0 is executed, the 1st stage for word line WL1 adjacent to word line WL0 is executed . Likewise, after the 1st stage for word line WL1 is executed, and before the 2nd stage for word line WL1 is executed, the 1st stage for word line WL2 adjacent to word line WL1 is executed implement. In this way, in the present embodiment, since all the page data is only required for the programming in one stage, when the input of the data is completed, it becomes the data that can be written into the buffer. delete. Therefore, in this embodiment, the number of pages that need to be simultaneously held in the write buffer in advance is only required to be smaller than that in the first embodiment. The page data programmed for the non-volatile memory 3 is temporarily held in the write buffer in the RAM 6, and then the data is input to the non-volatile memory 3 during programming. In the present embodiment, since the required capacity of the RAM 6 can be reduced, the cost can be reduced. Furthermore, in the present embodiment, since the data transfer is completed once for each page, compared with the first embodiment, the transfer time of the page data is also less, and the It becomes possible to reduce power consumption during transmission. Since the page read processing in this embodiment is the same as the processing procedure described in the first embodiment, the description thereof is omitted. In addition, in the present embodiment, for the new data of the page that needs to be kept continuously, it is necessary to increase the page buffer 24 inside the NAND flash memory. In programming a NAND flash memory with 1 string within a block as shown in FIG. 8A, the amount of page buffer 24 that needs to be added is the amount of 1 page of data . In contrast, in the programming of a NAND flash memory having 4 strings within a block as shown in FIG. 8B or FIG. 8C, the amount of additional page buffer 24 required is 4 pages of data. This is because during the period from when the programming of the 1st stage of a certain string is executed until the programming of the 2nd stage of the same string is executed, it is necessary to execute the programming of the 1st stage of the other three strings. As a result, it is necessary to hold data corresponding to one page for all of the four character strings. In the present embodiment, the 1-4-5-5 data encoding has been described as an example, but various modifications of the data encoding can be employed, and it is obvious that the above-described embodiment can be implemented. In the above-mentioned first to third embodiments, the case where the non-volatile memory 3 is formed by using the NAND memory 5 has been described. However, a ReRAM (Resistive Random Access Memory) such as ReRAM (Resistive Random Access Memory) Or other types of non-volatile memory 3 such as MRAM6 (Magneto-Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FeRAM (Ferroeletric Random Access Memory) and so on. In the above-mentioned first to third embodiments, although the data writing of three pages is performed in the programming of the 1st stage, the programming of the 2nd stage is performed for the amount of two pages. The case of data writing has been described, but it is also possible to change the allocation of the number of pages in the programming of the 1st stage and the number of pages in the programming of the 2nd stage. For example, in the programming of the 1st stage, the data writing of the amount of 2 pages may be performed, and in the programming of the 2nd stage, the writing of the data of the amount of three pages may be performed. Although several embodiments of the present disclosure have been described, these embodiments are presented as examples only, and are not intended to limit the scope of the present invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are also included in the scope and gist of the invention, and are also included in the inventions described in the claims and their equivalents.

1:記憶體系統 2:記憶體控制器 3:非揮發性記憶體 4:主機處理器 5:NAND記憶體 6:RAM 7:ROM 8:處理器 9:主機介面 10:ECC電路 11:記憶體介面 12:內部匯流排 21:NAND I/O介面 22:控制部 23:NAND記憶體胞陣列 24:頁面緩衝 31:震盪器 32:序列器 33:指令使用者介面 34:電壓供給部 35:列計數器 36:序列存取控制器 37:行解碼器 38:感測放大器 41:p型井區域 42,43,44:配線層 45:記憶體洞(memory hole) 46:區塊絕緣膜 47:電荷積蓄層 48:閘極絕緣膜 49:導電膜1: Memory system 2: Memory Controller 3: Non-volatile memory 4: Host processor 5: NAND memory 6: RAM 7: ROM 8: Processor 9: Host Interface 10: ECC circuit 11: Memory interface 12: Internal busbar 21:NAND I/O interface 22: Control Department 23: NAND memory cell array 24: page buffering 31: Oscillator 32: Sequencer 33: Command UI 34: Voltage supply part 35: Column Counter 36: Serial access controller 37: Line Decoder 38: Sense Amplifier 41: p-well area 42, 43, 44: Wiring layer 45: memory hole 46: Block insulating film 47: Charge accumulation layer 48: Gate insulating film 49: Conductive film

[圖1]係為對於由第1實施形態所致的記憶體系統之概略構成作展示之區塊圖。 [圖2]係為對於本實施形態的非揮發性記憶體之內部構成之其中一例作展示之區塊圖。 [圖3]係為對於3維構造的NAND記憶體胞陣列之其中一例作展示之電路圖。 [圖4]係為3維構造的NAND記憶體之NAND記憶體胞陣列之一部分區域的剖面圖。 [圖5]係為對於第1實施形態之臨限值區域的其中一例作展示之圖。 [圖6A]係為對於第1實施形態之資料編碼的其中一例作展示之圖。 [圖6B]係為對於第1實施形態之資料編碼的另外一例作展示之圖。 [圖7]係為對於第1實施形態中之程式化後的臨限值區域作展示之圖。 [圖8A]係為對於第1實施形態之程式化順序的第1例作展示之圖。 [圖8B]係為對於第1實施形態之程式化順序的第2例作展示之圖。 [圖8C]係為對於第1實施形態之程式化順序的第3例作展示之圖。 [圖9]係為對於由第1實施形態所致的1個區塊之量之全體的寫入程序之第1例作展示之流程圖。 [圖10]係為對於由第1實施形態所致的1st階段中之寫入程序作展示之流程圖。 [圖11]係為對於2nd階段之寫入程序之第1例作展示之流程圖。 [圖12]係為用以對於複數次數之讀出結果的多數決處理作說明的圖。 [圖13]係為對於在第1實施形態的2nd階段中之寫入程序之變形例作展示之流程圖。 [圖14A]係為用以對於在採用了4-3-4-4資料編碼之Foggy-Fine程式化中之寫入緩衝的資料量作說明之圖。 [圖14B]係為對於在本實施形態中之寫入緩衝的資料量作說明之圖。 [圖15]係為對於在直到1st階段為止之程式化為結束的字元線處之頁面讀出的處理程序作展示之流程圖。 [圖16A]係為對於在直到2nd階段為止之程式化為結束的字元線處之頁面讀出的處理程序作展示之流程圖。 [圖16B]係為針對適合於由其中一變形例所致之頁面讀出處理的資料編碼作展示之圖。 [圖16C]係為對於由其中一變形例所致的讀出處理程序作展示之流程圖。 [圖16D]係為選擇字元線、ReadyBusy訊號線、輸出資料線之電壓波形圖。 [圖17]係為對於1-5-4-5資料編碼的其中一例作展示之圖。 [圖18]係為對於1-5-4-5資料編碼的其中一例作展示之圖。 [圖19]係為對於3-5-2-5資料編碼的其中一例作展示之圖。 [圖20]係為對於3-3-4-5資料編碼的其中一例作展示之圖。 [圖21]係為對於2-3-5-5資料編碼的其中一例作展示之圖。 [圖22]係為對於3-2-5-5資料編碼的其中一例作展示之圖。 [圖23]係為對於3-4-4-4資料編碼的其中一例作展示之圖。 [圖24]係為對於3-4-4-4資料編碼的其中一例作展示之圖。 [圖25]係為對於1-4-5-5資料編碼的其中一例作展示之圖。 [圖26]係為對於2-5-3-5資料編碼的其中一例作展示之圖。 [圖27]係為對於3-4-5-3資料編碼的其中一例作展示之圖。 [圖28]係為對於3-2-5-5資料編碼的其中一例作展示之圖。 [圖29]係為對於3-2-5-5資料編碼的其中一例作展示之圖。 [圖30]係為對於1-5-5-4資料編碼的其中一例作展示之圖。 [圖31]係為對於1-5-4-5資料編碼的其中一例作展示之圖。 [圖32]係為對於1-4-5-5資料編碼的其中一例作展示之圖。 [圖33]係為對於1-5-3-6資料編碼的其中一例作展示之圖。 [圖34]係為對於1-3-6-5資料編碼的其中一例作展示之圖。 [圖35]係為對於1-2-6-6資料編碼的其中一例作展示之圖。 [圖36]係為對於1-2-6-6資料編碼的其中一例作展示之圖。 [圖37]係為對於1-2-6-6資料編碼的其中一例作展示之圖。 [圖38]係為對於1-4-6-4資料編碼的其中一例作展示之圖。 [圖39]係為對於1-4-4-6資料編碼的其中一例作展示之圖。 [圖40]係為對於1-4-6-4資料編碼的其中一例作展示之圖。 [圖41]係為對於1-4-4-6資料編碼的其中一例作展示之圖。 [圖42]係為對於2-5-2-6資料編碼的其中一例作展示之圖。 [圖43]係為對於2-5-2-6資料編碼的其中一例作展示之圖。 [圖44]係為對於2-5-2-6資料編碼的其中一例作展示之圖。 [圖45]係為對於3-3-3-6資料編碼的其中一例作展示之圖。 [圖46]係為對於3-3-6-3資料編碼的其中一例作展示之圖。 [圖47]係為對於2-3-4-6資料編碼的其中一例作展示之圖。 [圖48]係為對於3-4-2-6資料編碼的其中一例作展示之圖。 [圖49]係為對於2-3-4-6資料編碼的其中一例作展示之圖。 [圖50]係為對於3-2-6-4資料編碼的其中一例作展示之圖。 [圖51]係為對於3-2-4-6資料編碼的其中一例作展示之圖。 [圖52]係為對於3-2-6-4資料編碼的其中一例作展示之圖。 [圖53]係為對於3-4-2-6資料編碼的其中一例作展示之圖。 [圖54]係為對於3-2-4-6資料編碼的其中一例作展示之圖。 [圖55]係為對於5-3-2-5資料編碼的其中一例作展示之圖。 [圖56]係為對於3-5-2-5資料編碼的其中一例作展示之圖。 [圖57]係為對於3-2-5-5資料編碼的其中一例作展示之圖。 [圖58]係為對於2-3-5-5資料編碼的其中一例作展示之圖。 [圖59]係為對於2-3-5-5資料編碼的其中一例作展示之圖。 [圖60]係為對於2-3-5-5資料編碼的其中一例作展示之圖。 [圖61]係為對於5-4-2-4資料編碼的其中一例作展示之圖。 [圖62]係為對於4-5-2-4資料編碼的其中一例作展示之圖。 [圖63]係為對於5-4-2-4資料編碼的其中一例作展示之圖。 [圖64]係為對於2-4-5-4資料編碼的其中一例作展示之圖。 [圖65]係為對於2-4-5-4資料編碼的其中一例作展示之圖。 [圖66]係為對於2-5-4-4資料編碼的其中一例作展示之圖。 [圖67]係為對於2-5-4-4資料編碼的其中一例作展示之圖。 [圖68]係為對於2-5-4-4資料編碼的其中一例作展示之圖。 [圖69]係為對於1-5-4-5資料編碼的其中一例作展示之圖。 [圖70]係為對於1-4-5-5資料編碼的其中一例作展示之圖。 [圖71]係為對於1-5-5-4資料編碼的其中一例作展示之圖。 [圖72]係為對於1-4-5-5資料編碼的其中一例作展示之圖。 [圖73]係為對於1-5-5-4資料編碼的其中一例作展示之圖。 [圖74]係為對於1-5-4-5資料編碼的其中一例作展示之圖。 [圖75]係為對於1-5-5-4資料編碼的其中一例作展示之圖。 [圖76]係為對於1-5-4-5資料編碼的其中一例作展示之圖。 [圖77]係為對於1-4-5-5資料編碼的其中一例作展示之圖。 [圖78]係為對於1-4-5-5資料編碼的其中一例作展示之圖。 [圖79]係為對於1-4-5-5資料編碼的其中一例作展示之圖。 [圖80]係為對於1-4-5-5資料編碼的其中一例作展示之圖。 [圖81]係為對於3-5-4-3資料編碼的其中一例作展示之圖。 [圖82]係為對於3-4-5-3資料編碼的其中一例作展示之圖。 [圖83]係為對於3-5-3-4資料編碼的其中一例作展示之圖。 [圖84]係為對於3-4-3-5資料編碼的其中一例作展示之圖。 [圖85]係為對於3-4-5-3資料編碼的其中一例作展示之圖。 [圖86]係為對於3-4-3-5資料編碼的其中一例作展示之圖。 [圖87]係為對於3-3-5-4資料編碼的其中一例作展示之圖。 [圖88]係為對於3-3-5-4資料編碼的其中一例作展示之圖。 [圖89]係為對於4-5-3-3資料編碼的其中一例作展示之圖。 [圖90]係為對於3-5-4-3資料編碼的其中一例作展示之圖。 [圖91]係為對於3-4-5-3資料編碼的其中一例作展示之圖。 [圖92]係為對於3-3-4-5資料編碼的其中一例作展示之圖。 [圖93]係為對於3-3-4-5資料編碼的其中一例作展示之圖。 [圖94]係為對於3-3-4-5資料編碼的其中一例作展示之圖。 [圖95]係為對於3-4-5-3資料編碼的其中一例作展示之圖。 [圖96]係為對於3-3-5-4資料編碼的其中一例作展示之圖。 [圖97]係為對於3-3-4-5資料編碼的其中一例作展示之圖。 [圖98]係為對於4-3-4-4資料編碼的其中一例作展示之圖。 [圖99]係為對於3-4-4-4資料編碼的其中一例作展示之圖。 [圖100]係為對於3-4-4-4資料編碼的其中一例作展示之圖。 [圖101]係為對於4-3-4-4資料編碼的其中一例作展示之圖。 [圖102]係為對於3-4-4-4資料編碼的其中一例作展示之圖。 [圖103]係為對於3-4-4-4資料編碼的其中一例作展示之圖。 [圖104]係為對於3-4-4-4資料編碼的其中一例作展示之圖。 [圖105]係為對於3-4-4-4資料編碼的其中一例作展示之圖。 [圖106]係為對於4-4-3-4資料編碼的其中一例作展示之圖。 [圖107]係為對於4-4-3-4資料編碼的其中一例作展示之圖。 [圖108]係為對於第3實施形態的1個區塊之量之全體的寫入程序作展示之流程圖。 [圖109]係為對於第3實施形態的1st階段以及2nd階段中之寫入程序作展示之流程圖。 [圖110]係為用以對於在第3實施形態之程式化中之寫入緩衝量作說明之圖。FIG. 1 is a block diagram showing the schematic configuration of the memory system according to the first embodiment. FIG. 2 is a block diagram showing an example of the internal structure of the non-volatile memory of the present embodiment. [FIG. 3] is a circuit diagram showing one example of a NAND memory cell array with a three-dimensional structure. FIG. 4 is a cross-sectional view of a part of a region of a NAND memory cell array of a 3-dimensional NAND memory. FIG. 5 is a diagram showing one example of the threshold value region of the first embodiment. FIG. 6A is a diagram showing one example of the data encoding of the first embodiment. 6B is a diagram showing another example of the data encoding of the first embodiment. [ Fig. 7 ] is a diagram showing a programmed threshold value region in the first embodiment. 8A is a diagram showing a first example of the programming sequence of the first embodiment. 8B is a diagram showing a second example of the programming sequence of the first embodiment. 8C is a diagram showing a third example of the programming sequence of the first embodiment. FIG. 9 is a flowchart showing a first example of the entire writing procedure for one block according to the first embodiment. Fig. 10 is a flowchart showing the writing procedure in the 1st stage by the first embodiment. [ FIG. 11 ] is a flow chart showing the first example of the writing procedure of the 2nd stage. [ Fig. 12 ] A diagram for explaining a majority decision process for a read result of a complex number of times. 13 is a flowchart showing a modification of the writing procedure in the 2nd stage of the first embodiment. [FIG. 14A] is a diagram for explaining the amount of data in the write buffer in the Foggy-Fine programming using the 4-3-4-4 data encoding. FIG. 14B is a diagram illustrating the amount of data written in the buffer in this embodiment. Fig. 15 is a flowchart showing the processing procedure of the page read at the word line where the programming up to the 1st stage ends. [FIG. 16A] It is a flowchart showing the processing procedure of the page read at the word line where programming is ended up to the 2nd stage. [FIG. 16B] is a diagram showing data encoding suitable for page readout processing by one of the modifications. [ Fig. 16C ] is a flowchart showing a readout processing procedure by one of the modified examples. [FIG. 16D] is a voltage waveform diagram of the selected word line, the ReadyBusy signal line, and the output data line. [Fig. 17] is a diagram showing one example of 1-5-4-5 data encoding. [FIG. 18] is a diagram showing one example of 1-5-4-5 data encoding. [Fig. 19] is a diagram showing one example of 3-5-2-5 data encoding. [Fig. 20] is a diagram showing one example of 3-3-4-5 data encoding. [Fig. 21] is a diagram showing one example of 2-3-5-5 data encoding. [Fig. 22] is a diagram showing one example of 3-2-5-5 data encoding. [Fig. 23] is a diagram showing one example of 3-4-4-4 data encoding. [FIG. 24] is a diagram showing one example of 3-4-4-4 data encoding. [FIG. 25] is a diagram showing one example of 1-4-5-5 data encoding. [Fig. 26] is a diagram showing one example of 2-5-3-5 data encoding. [Fig. 27] is a diagram showing one example of 3-4-5-3 data encoding. [Fig. 28] is a diagram showing one example of 3-2-5-5 data encoding. [FIG. 29] is a diagram showing one example of 3-2-5-5 data encoding. [FIG. 30] is a diagram showing one example of 1-5-5-4 data encoding. [FIG. 31] is a diagram showing one example of 1-5-4-5 data encoding. [Fig. 32] is a diagram showing one example of 1-4-5-5 data encoding. [FIG. 33] is a diagram showing one example of 1-5-3-6 data encoding. [Fig. 34] is a diagram showing one example of 1-3-6-5 data encoding. [Fig. 35] is a diagram showing one example of 1-2-6-6 data encoding. [Fig. 36] is a diagram showing one example of 1-2-6-6 data encoding. [Fig. 37] is a diagram showing one example of 1-2-6-6 data encoding. [Fig. 38] is a diagram showing one example of 1-4-6-4 data encoding. [FIG. 39] is a diagram showing one example of 1-4-4-6 data encoding. [Fig. 40] is a diagram showing one example of 1-4-6-4 data encoding. [FIG. 41] is a diagram showing one example of 1-4-4-6 data encoding. [Fig. 42] is a diagram showing one example of 2-5-2-6 data encoding. [FIG. 43] is a diagram showing one example of 2-5-2-6 data encoding. [Fig. 44] is a diagram showing one example of 2-5-2-6 data encoding. [Fig. 45] is a diagram showing one example of 3-3-3-6 data encoding. [Fig. 46] is a diagram showing one example of 3-3-6-3 data encoding. [FIG. 47] is a diagram showing one example of 2-3-4-6 data encoding. [Fig. 48] is a diagram showing one example of 3-4-2-6 data encoding. [Fig. 49] is a diagram showing one example of 2-3-4-6 data encoding. [Fig. 50] is a diagram showing one example of 3-2-6-4 data encoding. [Fig. 51] is a diagram showing one example of 3-2-4-6 data encoding. [Fig. 52] is a diagram showing one example of 3-2-6-4 data encoding. [Fig. 53] is a diagram showing one example of 3-4-2-6 data encoding. [Fig. 54] is a diagram showing one example of 3-2-4-6 data encoding. [Fig. 55] is a diagram showing one example of 5-3-2-5 data encoding. [Fig. 56] is a diagram showing one example of 3-5-2-5 data encoding. [Fig. 57] is a diagram showing one example of 3-2-5-5 data encoding. [Fig. 58] is a diagram showing one example of 2-3-5-5 data encoding. [Fig. 59] is a diagram showing one example of 2-3-5-5 data encoding. [Fig. 60] is a diagram showing one example of 2-3-5-5 data encoding. [Fig. 61] is a diagram showing one example of 5-4-2-4 data encoding. [Fig. 62] is a diagram showing one example of 4-5-2-4 data encoding. [Fig. 63] is a diagram showing one example of 5-4-2-4 data encoding. [Fig. 64] is a diagram showing one example of 2-4-5-4 data encoding. [Fig. 65] is a diagram showing one example of 2-4-5-4 data encoding. [Fig. 66] is a diagram showing one example of 2-5-4-4 data encoding. [Fig. 67] is a diagram showing one example of 2-5-4-4 data encoding. [Fig. 68] is a diagram showing one example of 2-5-4-4 data encoding. [Fig. 69] is a diagram showing one example of 1-5-4-5 data encoding. [Fig. 70] is a diagram showing one example of 1-4-5-5 data encoding. [Fig. 71] is a diagram showing one example of 1-5-5-4 data encoding. [Fig. 72] is a diagram showing one example of 1-4-5-5 data encoding. [Fig. 73] is a diagram showing one example of 1-5-5-4 data encoding. [Fig. 74] is a diagram showing one example of 1-5-4-5 data encoding. [Fig. 75] is a diagram showing one example of 1-5-5-4 data encoding. [Fig. 76] is a diagram showing one example of 1-5-4-5 data encoding. [Fig. 77] is a diagram showing one example of 1-4-5-5 data encoding. [Fig. 78] is a diagram showing one example of 1-4-5-5 data encoding. [Fig. 79] is a diagram showing one example of 1-4-5-5 data encoding. [Fig. 80] is a diagram showing one example of 1-4-5-5 data encoding. [Fig. 81] is a diagram showing one example of 3-5-4-3 data encoding. [Fig. 82] is a diagram showing one example of 3-4-5-3 data encoding. [Fig. 83] is a diagram showing one example of 3-5-3-4 data encoding. [Fig. 84] is a diagram showing one example of 3-4-3-5 data encoding. [Fig. 85] is a diagram showing one example of 3-4-5-3 data encoding. [Fig. 86] is a diagram showing one example of 3-4-3-5 data encoding. [Fig. 87] is a diagram showing one example of 3-3-5-4 data encoding. [Fig. 88] is a diagram showing one example of 3-3-5-4 data encoding. [FIG. 89] is a diagram showing one example of 4-5-3-3 data encoding. [Fig. 90] is a diagram showing one example of 3-5-4-3 data encoding. [Fig. 91] is a diagram showing one example of 3-4-5-3 data encoding. [Fig. 92] is a diagram showing one example of 3-3-4-5 data encoding. [Fig. 93] is a diagram showing one example of 3-3-4-5 data encoding. [Fig. 94] is a diagram showing one example of 3-3-4-5 data encoding. [Fig. 95] is a diagram showing one example of 3-4-5-3 data encoding. [Fig. 96] is a diagram showing one example of 3-3-5-4 data encoding. [Fig. 97] is a diagram showing one example of 3-3-4-5 data encoding. [Fig. 98] is a diagram showing one example of 4-3-4-4 data encoding. [Fig. 99] is a diagram showing one example of 3-4-4-4 data encoding. [FIG. 100] is a diagram showing one example of 3-4-4-4 data encoding. [FIG. 101] is a diagram showing one example of 4-3-4-4 data encoding. [Fig. 102] is a diagram showing one example of 3-4-4-4 data encoding. [FIG. 103] is a diagram showing one example of 3-4-4-4 data encoding. [FIG. 104] is a diagram showing one example of 3-4-4-4 data encoding. [Fig. 105] is a diagram showing one example of 3-4-4-4 data encoding. [Fig. 106] is a diagram showing one example of 4-4-3-4 data encoding. [Fig. 107] is a diagram showing one example of 4-4-3-4 data encoding. Fig. 108 is a flowchart showing the entire writing procedure for one block in the third embodiment. Fig. 109 is a flowchart showing the writing procedure in the 1st stage and the 2nd stage of the third embodiment. FIG. 110 is a diagram for explaining the write buffer amount in the programming of the third embodiment.

2:記憶體控制器 2: Memory Controller

3:非揮發性記憶體 3: Non-volatile memory

4:主機處理器 4: Host processor

5:NAND記憶體 5: NAND memory

6:RAM 6: RAM

7:ROM 7: ROM

8:處理器 8: Processor

9:主機介面 9: Host Interface

10:ECC電路 10: ECC circuit

11:記憶體介面 11: Memory interface

12:內部匯流排 12: Internal busbar

Claims (13)

一種記憶體系統，係具備有： 非揮發性記憶體，係具有複數之記憶體胞，該複數之記憶體胞，係各別藉由16個臨限值區域，而能夠記憶藉由第1～第4位元來作表現的4位元之資料，該16個的臨限值區域，係包含有代表資料被作了刪除的刪除狀態之第1臨限值區域、和電壓準位為較前述第1臨限值區域而更高並代表資料被作了寫入的寫入狀態之第2～第16臨限值區域；和 記憶體控制器，係在使前述非揮發性記憶體進行了將前述第1位元、前述第2位元、前述第4位元之資料作寫入的第1程式化之後，使前述非揮發性記憶體進行將前述第3位元之資料作寫入的第2程式化， 在存在於前述第1～第16臨限值區域中之相鄰接之臨限值區域間之15個的邊界中，被使用在前述第1位元之資料之值的判定中之第1邊界之數量、被使用在前述第2位元之資料之值的判定中之第2邊界之數量、被使用在前述第3位元之資料之值的判定中之第3邊界之數量、被使用在前述第4位元之資料之值的判定中之第4邊界之數量，此些之數量中之最大之值係為5，第2大之值係為4， 前述記憶體控制器，係構成為以使在前述記憶體胞中之臨限值區域會因應於前述第1位元、前述第2位元、前述第4位元之資料而成為代表資料為被作了刪除的刪除狀態之第17臨限值區域和電壓準位為較前述第17臨限值區域而更高並代表資料被作了寫入的寫入狀態之第18～第24臨限值區域之其中一者之臨限值區域的方式，來使前述非揮發性記憶體進行前述第1程式化， 前述記憶體控制器，係構成為以使在前述記憶體胞中之臨限值區域會因應於前述第3位元之資料而從前述第17～第24臨限值區域中之任一者之臨限值區域來成為前述第1～第16臨限值區域中之2個的臨限值區域內之任一者之臨限值區域的方式，來使前述非揮發性記憶體進行前述第2程式化， 位置於前述2個的臨限值區域中之電壓準位為最低之臨限值區域和電壓準位為最高之臨限值區域之間的臨限值區域之個數，係為2個以內， 前述記憶體控制器，在使前述非揮發性記憶體進行前述第2程式化的情況時，係構成為將前述第2位元之資料和前述第3位元之資料對於前述非揮發性記憶體作輸入。A memory system having: The non-volatile memory has a plurality of memory cells, and the plurality of memory cells respectively use 16 threshold value regions, and can store 4 represented by the 1st to 4th bits. For bit data, the 16 threshold value areas include the first threshold value area representing the deletion state of the data being deleted, and the voltage level is higher than the aforementioned first threshold value area and represent the 2nd to 16th threshold value areas of the write state in which the data has been written; and The memory controller makes the non-volatile memory perform the first programming of writing the data of the first bit, the second bit, and the fourth bit, so as to make the non-volatile memory The second programming that writes the data of the aforementioned third bit into the memory is performed, Among the 15 boundaries existing between adjacent threshold value areas among the first to 16th threshold value areas, the first boundary used for the determination of the value of the data of the first bit number, the number of the second boundary used in the determination of the value of the data of the second bit, the number of the third boundary used in the determination of the value of the data of the third bit, The number of the fourth boundary in the determination of the value of the data of the fourth bit above, the largest value of these numbers is 5, the second largest value is 4, The memory controller is configured so that the threshold value area in the memory cell becomes representative data in response to the data of the first bit, the second bit, and the fourth bit. The 17th threshold value region and the voltage level of the deletion state in which the deletion has been performed are higher than the aforementioned 17th threshold value region and represent the 18th to 24th threshold values of the write state in which data has been written. The non-volatile memory is subjected to the first programming by means of the threshold value region of one of the regions, The memory controller is configured such that the threshold value region in the memory cell is changed from any one of the 17th to 24th threshold value regions in response to the data of the third bit. The non-volatile memory is made to perform the above-mentioned 2 stylized, The number of threshold value areas between the threshold value area where the voltage level is the lowest and the threshold value area where the voltage level is the highest in the aforementioned two threshold value areas is within 2, The memory controller, in the case of performing the second programming on the non-volatile memory, is configured to assign the data of the second bit and the data of the third bit to the non-volatile memory as input. 如請求項1所記載之記憶體系統，其中， 前述記憶體控制器，係以會使在存在於前述第1～第16臨限值區域中之相鄰接之臨限值區域間之15個的邊界中，前述第1位元之值為相異的前述邊界之數量、前述第2位元之值為相異的前述邊界之數量、前述第3位元之值為相異的前述邊界之數量、以及前述第4位元之值為相異的前述邊界之數量，依序成為(1、4、5、5)、(1、5、4、5)或者是(3、3、4、5)的方式，來使前述非揮發性記憶體進行前述第1程式化以及前述第2程式化。The memory system as recited in claim 1, wherein, The memory controller is such that the value of the first bit in the 15 boundaries between adjacent threshold areas existing in the first to sixteenth threshold areas is the same as the value of the first bit. The number of the aforementioned boundaries that are different, the value of the second bit is the number of the aforementioned boundaries that are different, the value of the third bit is the number of the aforementioned boundaries that are different, and the value of the fourth bit is different. The number of the aforesaid boundaries is sequentially (1, 4, 5, 5), (1, 5, 4, 5) or (3, 3, 4, 5) to make the aforesaid non-volatile memory The aforementioned first programming and the aforementioned second programming are performed. 一種記憶體系統，係具備有： 非揮發性記憶體，係具有複數之記憶體胞，該複數之記憶體胞，係各別藉由16個臨限值區域，而能夠記憶藉由第1～第4位元來作表現的4位元之資料，該16個的臨限值區域，係包含有代表資料被作了刪除的刪除狀態之第1臨限值區域、和電壓準位為較前述第1臨限值區域而更高並代表資料被作了寫入的寫入狀態之第2～第16臨限值區域；和 記憶體控制器，係在使前述非揮發性記憶體進行了將前述第1位元、前述第2位元、前述第4位元之資料作寫入的第1程式化之後，使前述非揮發性記憶體進行將前述第3位元之資料作寫入的第2程式化， 在存在於前述第1～第16臨限值區域中之相鄰接之臨限值區域間之15個的邊界中，被使用在前述第1位元之資料之值的判定中之第1邊界之數量、被使用在前述第2位元之資料之值的判定中之第2邊界之數量、被使用在前述第3位元之資料之值的判定中之第3邊界之數量、被使用在前述第4位元之資料之值的判定中之第4邊界之數量，係依序為(3、5、2、5)， 前述記憶體控制器，係構成為以使在前述記憶體胞中之臨限值區域會因應於前述第1位元、前述第2位元、前述第4位元之資料而成為代表資料為被作了刪除的刪除狀態之第17臨限值區域和電壓準位為較前述第17臨限值區域而更高並代表資料被作了寫入的寫入狀態之第18～第24臨限值區域之其中一者之臨限值區域的方式，來使前述非揮發性記憶體進行前述第1程式化， 前述記憶體控制器，係構成為以使在前述記憶體胞中之臨限值區域會因應於前述第3位元之資料而從前述第17～第24臨限值區域中之任一者之臨限值區域來成為前述第1～第16臨限值區域中之2個的臨限值區域內之任一者之臨限值區域的方式，來使前述非揮發性記憶體進行前述第2程式化， 位置於前述2個的臨限值區域中之電壓準位為最低之臨限值區域和電壓準位為最高之臨限值區域之間的臨限值區域之個數，係為2個以內， 前述記憶體控制器，在使前述非揮發性記憶體進行前述第2程式化的情況時，係構成為將前述第2位元之資料和前述第3位元之資料對於前述非揮發性記憶體作輸入。A memory system having: The non-volatile memory has a plurality of memory cells, and the plurality of memory cells respectively use 16 threshold value regions, and can store 4 represented by the 1st to 4th bits. For bit data, the 16 threshold value areas include the first threshold value area representing the deletion state in which the data has been deleted, and the voltage level is higher than the aforementioned first threshold value area and represent the 2nd to 16th threshold value areas of the write state in which the data has been written; and The memory controller makes the non-volatile memory perform the first programming of writing the data of the first bit, the second bit and the fourth bit into the non-volatile memory. The second programming that writes the data of the aforementioned third bit into the memory is performed, Among the 15 boundaries existing between adjacent threshold value areas among the first to 16th threshold value areas, the first boundary used for the determination of the value of the data of the first bit number, the number of the second boundary used in the determination of the value of the data of the second bit, the number of the third boundary used in the determination of the value of the data of the third bit, The number of the fourth boundary in the determination of the value of the data of the fourth bit is (3, 5, 2, 5) in sequence, The memory controller is configured such that the threshold value area in the memory cell becomes representative data in response to the data of the first bit, the second bit, and the fourth bit as the target data. The 17th threshold value region and the voltage level of the deletion state in which the deletion has been performed are higher than the aforementioned 17th threshold value region and represent the 18th to 24th threshold values of the write state in which data has been written. The non-volatile memory is subjected to the first programming by means of the threshold value region of one of the regions, The memory controller is configured such that the threshold value region in the memory cell is changed from any one of the 17th to 24th threshold value regions in response to the data of the third bit. The non-volatile memory is made to perform the second threshold value region in such a manner that the threshold value region becomes the threshold value region of any one of the two threshold value regions of the first to sixteenth threshold value regions. stylized, The number of threshold value regions located between the threshold value regions where the voltage level is the lowest and the threshold value region where the voltage level is the highest in the aforementioned two threshold value regions is within 2, The memory controller, in the case of performing the second programming on the non-volatile memory, is configured to assign the data of the second bit and the data of the third bit to the non-volatile memory as input. 如請求項1～3中之任一項所記載之記憶體系統，其中， 前述記憶體控制器，係以會使前述第17～第24臨限值區域中之前述第2位元之資料之值為相異的2個的臨限值區域之間之電壓準位之差成為較前述第1位元之資料之值為相異的2個的臨限值區域之間之電壓準位之差而更小並且成為較前述第4位元之資料之值為相異的2個的臨限值區域之間之電壓準位之差而更小的方式，來使前述非揮發性記憶體進行前述第1程式化。The memory system according to any one of claims 1 to 3, wherein, The memory controller is based on the voltage level difference between the two threshold value regions that make the data value of the second bit in the 17th to 24th threshold value regions different. The difference between the voltage levels between the two threshold value regions that are different from the value of the data of the 1st bit is smaller and the value of the data of the 4th bit is 2 different. The first programming is performed on the non-volatile memory in such a manner that the difference in voltage level between the threshold value regions becomes smaller. 如請求項4所記載之記憶體系統，其中， 前述記憶體控制器，係以會相較於前述第2位元之資料之值為相異的前述第1程式化時之2個的臨限值區域之間之間隔，而使對於前述2個的臨限值區域而藉由前述第3位元之資料來進行前述第2程式化所得到的4個的臨限值區域中之相鄰接之臨限值區域之間隔變得更廣的方式，來使前述非揮發性記憶體進行前述第2程式化。The memory system as recited in claim 4, wherein, The memory controller is based on the interval between the two threshold value regions in the first programming, which are different from the data value of the second bit, so that the two A method in which the interval between adjacent threshold value areas becomes wider among the four threshold value areas obtained by performing the above-mentioned second programming using the data of the third bit. , to perform the second programming on the non-volatile memory. 如請求項1～3中之任一項所記載之記憶體系統，其中， 前述第1位元，係身為最下位之Lower位元，前述第2位元，係身為第2小之Middle位元，前述第3位元，係身為第2大之Upper位元，前述第4位元，係身為最上位之Top位元。The memory system according to any one of claims 1 to 3, wherein, The aforementioned first bit is the lowest bit, the aforementioned second bit is the second smallest Middle bit, the aforementioned third bit is the second largest Upper bit, The aforementioned fourth bit is the top bit. 如請求項1～3中之任一項所記載之記憶體系統，其中， 係具備有記憶前述第1～第4位元之資料的揮發性之第1記憶部， 在被記憶於前述第1記憶部中之前述第1～第4位元中的於前述第1程式化以及前述第2程式化時會被重複輸入的位元之資料，係在開始了前述第2程式化之後成為能夠廢棄或無效化，其以外的位元之資料，係在開始了前述第1程式化之後成為能夠廢棄或無效化。The memory system according to any one of claims 1 to 3, wherein, It is provided with a volatile first memory part that stores the data of the first to fourth bits mentioned above, Among the first to fourth bits stored in the first memory section, the data of the bits that will be repeatedly input during the first programming and the second programming is the start of the first 2 After programming, it can be discarded or invalidated, and the data of other bits can be discarded or invalidated after the first programming is started. 如請求項1～3中之任一項所記載之記憶體系統，其中， 係具備有記憶前述第1～第4位元之資料的揮發性之第1記憶部；和 記憶前述第1～第4位元中之會在前述第1程式化以及前述第2程式化中而被重複輸入的位元之資料的非揮發性之第2記憶部， 被記憶於前述第1記憶部中之前述第1～第4位元之資料，係在開始了前述第1程式化之後成為能夠廢棄或無效化， 在被記憶於前述第2記憶部中之前述第1～第4位元中的於前述第1程式化以及前述第2程式化時會被重複輸入的位元之資料，係在開始前述第1程式化之前被記憶在前述第2記憶部中，並在開始了前述第2程式化之後成為能夠廢棄或無效化。The memory system according to any one of claims 1 to 3, wherein, It is a volatile first memory part with memory of the data of the first to fourth bits; and a non-volatile second memory portion that memorizes the data of the bits of the first to fourth bits that are repeatedly input in the first programming and the second programming, The data of the first to fourth bits stored in the first storage unit can be discarded or invalidated after the first programming is started. Among the first to fourth bits stored in the second memory section, the data of the bits that will be repeatedly input during the first programming and the second programming are at the beginning of the first It is memorized in the said 2nd memory|storage part before programming, and can be discarded or invalidated after the said 2nd programming is started. 如請求項8所記載之記憶體系統，其中， 前述第2記憶部，係以字元線作為單位而被作設置。The memory system as recited in claim 8, wherein, The aforementioned second memory portion is provided in units of word lines. 如請求項1～3中之任一項所記載之記憶體系統，其中， 前述非揮發性記憶體內之前述複數之記憶體胞，係具備有被與第1字元線作連接之複數之第1記憶體胞、和被與和前述第1字元線相鄰接的第2字元線作連接之複數之第2記憶體胞， 前述記憶體控制器，係在對於前述複數之第1記憶體胞而使其進行了前述第1程式化之後，對於前述複數之第2記憶體胞而使其進行前述第1程式化，之後，對於前述複數之第1記憶體胞而使其進行前述第2程式化。The memory system according to any one of claims 1 to 3, wherein, The plurality of memory cells in the non-volatile memory include a plurality of first memory cells connected to the first word line, and a first memory cell connected to the first word line. The second memory cell of the plural connected by the 2-word line, The memory controller, after performing the first programming on the plurality of first memory cells, performs the first programming on the plurality of second memory cells, and thereafter, The second programming is performed on the plurality of first memory cells. 如請求項1～3中之任一項所記載之記憶體系統，其中， 前述非揮發性記憶體，係至少具備有使2以上的前述記憶體胞分別被作連接的第1字元線以及第2字元線， 前述記憶體控制器，係將對於被與前述第1字元線作連接的記憶體胞之前述第1程式化和對於被與前述第2字元線作連接的記憶體胞之前述第2程式化之連續的實行，藉由相連續的指令以及資料輸入來對於前述非揮發性記憶體下達指示。The memory system according to any one of claims 1 to 3, wherein, The non-volatile memory includes at least a first word line and a second word line for connecting two or more of the memory cells, respectively, The memory controller executes the first program for the memory cell connected to the first word line and the second program for the memory cell connected to the second word line The continuous implementation of the transformation issues instructions to the aforementioned non-volatile memory through successive commands and data input. 如請求項1～3中之任一項所記載之記憶體系統，其中， 前述非揮發性記憶體，係具備有： 控制部，係基於將藉由前述第1程式化而被作了程式化的資料讀出所得到之資料、和在前述第1程式化以及前述第2程式化時被重複作輸入的前述第2位元之資料、以及藉由前述第2程式化而被作了程式化的前述第3位元之輸入資料，來決定藉由前述第2程式化而被作程式化的位元之資料之臨限值電壓。The memory system according to any one of claims 1 to 3, wherein, The aforementioned non-volatile memory includes: The control unit is based on the data obtained by reading the data programmed by the first programming, and the second programming that is repeatedly input in the first programming and the second programming The bit data, and the input data of the third bit programmed by the second programming, determine the occurrence of the bit data programmed by the second programming. Limit voltage. 如請求項12所記載之記憶體系統，其中，係具備有： 錯誤訂正部，係將藉由前述第1程式化而被作了程式化的資料讀出並進行錯誤訂正， 前述控制部，係基於藉由前述錯誤訂正部而作了錯誤訂正後的資料、和前述第2位元之資料、以及前述第3位元之輸入資料，來決定藉由前述第2程式化而被作程式化的位元之資料之前述臨限值電壓。The memory system as described in claim 12, wherein the system has: The error correction section reads and corrects errors by reading the data programmed by the first programming described above, The control unit determines the error correction by the second programming based on the data after error correction by the error correction unit, the data of the second bit, and the input data of the third bit. The aforementioned threshold voltage for the data of the programmed bit.
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