JP7414669B2 - memory system - Google Patents

Description

Embodiments of the present disclosure relate to memory systems.

In NAND flash memory, it is common to write multi-value data consisting of multiple bits into memory cells, and TLC (Triple Level Cell) technology, which writes multi-value data consisting of 3 bits into memory cells, has been put into practical use. . In the future, it is thought that QLC (Quadruple Level Cell) technology, which writes multivalued data consisting of 4 bits, will become mainstream.

In QLC, in order to avoid mutual interference between cells, 4-bit data is simultaneously written into the first memory cell, 4-bit data is written simultaneously into the adjacent cell, and then 4-bit data is written into the first memory cell again. A method of simultaneously rewriting bit data is being considered. However, this technique requires that 4-bit data be held in a write buffer within the memory controller until rewriting is complete.

In recent years, NAND memories have become three-dimensional, which increases the memory capacity of the write buffer required, resulting in an increase in the cost of a memory controller with a built-in write buffer. Therefore, even in three-dimensional nonvolatile memory, measures are required to reduce the write buffer amount of the memory controller.

As a measure to reduce the write buffer size of the memory controller while avoiding mutual interference between cells, when writing each bit of data to a memory cell, it is written in two stages, eliminating the need to rewrite all bits of data. There are known methods to do this.

However, this method has a problem in that the bit error rate when writing each bit data to the memory cell is highly biased.

To improve the reliability of QLC technology, it is necessary to avoid mutual interference between cells, reduce the capacity of the write buffer in the memory controller, and suppress the bias in the bit error rate when writing each bit of data. .

JP 2018-5959 Publication

One aspect of the present disclosure provides a memory system that can avoid mutual interference between cells, reduce the capacity of a write buffer in a memory controller, and suppress bias in bit error rate when writing each bit data. be.

According to the present embodiment, each has a first threshold area indicating an erased state in which data is erased, and a written state in which data is written at a voltage level higher than the first threshold area. A non-volatile memory having a plurality of memory cells capable of storing 4-bit data represented by the 1st to 4th bits by 16 threshold areas including the second to 16th threshold areas shown in FIG. ,
After causing the nonvolatile memory to execute a first program for writing the data of the first bit, the second bit, and the fourth bit, a second program for writing the data of the third bit is executed for the nonvolatile memory. memory controller,
Equipped with
The number of first boundaries used to determine the value of the first bit data among the 15 boundaries existing between adjacent threshold areas among the first to 16th threshold areas; the number of second boundaries used to determine the value of the second bit data; the number of third boundaries used to determine the value of the third bit data; and the determination of the value of the fourth bit data. The maximum value of the number of fourth boundaries used for is 5, the second largest value is 4,
The memory controller is configured such that a threshold region in the memory cell has a seventeenth threshold value indicating an erased state in which data is erased according to data of the first bit, the second bit, and the fourth bit. area and the 18th to 24th threshold areas, which indicate a write state in which data is written and whose voltage level is higher than the 17th threshold area. The memory controller is configured to cause the nonvolatile memory to perform one program, and the memory controller is configured to set the threshold area of the memory cell to the seventeenth to twenty-fourth threshold values according to the data of the third bit. The second program is configured to change from one of the threshold areas to one of the two threshold areas among the first to sixteenth threshold areas. configured to cause the non-volatile memory to perform;
The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level among the two threshold regions is 2 or less,
The memory system is configured such that the memory controller inputs the second bit data and the third bit data to the nonvolatile memory when causing the nonvolatile memory to execute the second program. is provided.

FIG. 1 is a block diagram showing a schematic configuration of a memory system according to a first embodiment. FIG. 2 is a block diagram showing an example of the internal configuration of a nonvolatile memory according to the present embodiment. FIG. 2 is a circuit diagram showing an example of a NAND memory cell array having a three-dimensional structure. FIG. 2 is a cross-sectional view of a partial region of a NAND memory cell array of a three-dimensional NAND memory. FIG. 3 is a diagram showing an example of a threshold region according to the first embodiment. FIG. 3 is a diagram showing an example of data coding according to the first embodiment. The figure which shows another example of data coding of 1st Embodiment. FIG. 3 is a diagram showing a threshold area after programming in the first embodiment. FIG. 3 is a diagram showing a first example of the program order of the first embodiment. FIG. 7 is a diagram showing a second example of the program order of the first embodiment. FIG. 7 is a diagram showing a third example of the program order of the first embodiment. 2 is a flowchart showing a first example of a procedure for writing an entire block according to the first embodiment. 5 is a flowchart showing a write procedure in the 1st stage according to the first embodiment. 5 is a flowchart showing a first example of a writing procedure in the 2nd stage. FIG. 6 is a diagram for explaining majority decision processing of the results of reading a plurality of times. 7 is a flowchart showing a modification of the writing procedure in the 2nd stage according to the first embodiment. The figure explaining the data amount of the write buffer in the Foggy-Fine program which adopted 4-3-4-4 data coding. FIG. 3 is a diagram illustrating the amount of data in a write buffer in this embodiment. 12 is a flowchart showing a page read processing procedure for a word line whose programming has been completed up to the 1st stage. 7 is a flowchart showing a page read processing procedure for a word line whose programming has been completed up to the 2nd stage. FIG. 7 is a diagram illustrating data coding suitable for page read processing according to a modified example. 7 is a flowchart showing a read processing procedure according to a modified example. Voltage waveform diagram of selected word line, ReadyBusy signal line, and output data line. The figure which shows an example of 1-5-4-5 data coding. The figure which shows an example of 1-5-4-5 data coding. 3-5-2-5 A diagram showing an example of data coding. 3-3-4-5 A diagram showing an example of data coding. 2-3-5-5 A diagram showing an example of data coding. 3-2-5-5 A diagram showing an example of data coding. The figure which shows an example of 3-4-4-4 data coding. The figure which shows an example of 3-4-4-4 data coding. The figure which shows an example of 1-4-5-5 data coding. 2-5-3-5 A diagram showing an example of data coding. 3-4-5-3 A diagram showing an example of data coding. 3-2-5-5 A diagram showing an example of data coding. 3-2-5-5 A diagram showing an example of data coding. The figure which shows an example of 1-5-5-4 data coding. The figure which shows an example of 1-5-4-5 data coding. The figure which shows an example of 1-4-5-5 data coding. 1-5-3-6 A diagram showing an example of data coding. 1-3-6-5 A diagram showing an example of data coding. 1-2-6-6 A diagram showing an example of data coding. 1-2-6-6 A diagram showing an example of data coding. 1-2-6-6 A diagram showing an example of data coding. The figure which shows an example of 1-4-6-4 data coding. The figure which shows an example of 1-4-4-6 data coding. The figure which shows an example of 1-4-6-4 data coding. The figure which shows an example of 1-4-4-6 data coding. 2-5-2-6 A diagram showing an example of data coding. 2-5-2-6 A diagram showing an example of data coding. 2-5-2-6 A diagram showing an example of data coding. 3-3-3-6 A diagram showing an example of data coding. 3-3-6-3 A diagram showing an example of data coding. 2-3-4-6 A diagram showing an example of data coding. 3-4-2-6 A diagram showing an example of data coding. 2-3-4-6 A diagram showing an example of data coding. 3-2-6-4 A diagram showing an example of data coding. 3-2-4-6 A diagram showing an example of data coding. 3-2-6-4 A diagram showing an example of data coding. 3-4-2-6 A diagram showing an example of data coding. 3-2-4-6 A diagram showing an example of data coding. 5-3-2-5 A diagram showing an example of data coding. 3-5-2-5 A diagram showing an example of data coding. 3-2-5-5 A diagram showing an example of data coding. 2-3-5-5 A diagram showing an example of data coding. 2-3-5-5 A diagram showing an example of data coding. 2-3-5-5 A diagram showing an example of data coding. 5-4-2-4 A diagram showing an example of data coding. 4-5-2-4 A diagram showing an example of data coding. 5-4-2-4 A diagram showing an example of data coding. The figure which shows an example of 2-4-5-4 data coding. The figure which shows an example of 2-4-5-4 data coding. The figure which shows an example of 2-5-4-4 data coding. The figure which shows an example of 2-5-4-4 data coding. The figure which shows an example of 2-5-4-4 data coding. The figure which shows an example of 1-5-4-5 data coding. The figure which shows an example of 1-4-5-5 data coding. The figure which shows an example of 1-5-5-4 data coding. The figure which shows an example of 1-4-5-5 data coding. The figure which shows an example of 1-5-5-4 data coding. The figure which shows an example of 1-5-4-5 data coding. The figure which shows an example of 1-5-5-4 data coding. The figure which shows an example of 1-5-4-5 data coding. The figure which shows an example of 1-4-5-5 data coding. The figure which shows an example of 1-4-5-5 data coding. The figure which shows an example of 1-4-5-5 data coding. The figure which shows an example of 1-4-5-5 data coding. 3-5-4-3 A diagram showing an example of data coding. 3-4-5-3 A diagram showing an example of data coding. 3-5-3-4 A diagram showing an example of data coding. 3-4-3-5 A diagram showing an example of data coding. 3-4-5-3 A diagram showing an example of data coding. 3-4-3-5 A diagram showing an example of data coding. 3-3-5-4 A diagram showing an example of data coding. 3-3-5-4 A diagram showing an example of data coding. 4-5-3-3 A diagram showing an example of data coding. 3-5-4-3 A diagram showing an example of data coding. 3-4-5-3 A diagram showing an example of data coding. 3-3-4-5 A diagram showing an example of data coding. 3-3-4-5 A diagram showing an example of data coding. 3-3-4-5 A diagram showing an example of data coding. 3-4-5-3 A diagram showing an example of data coding. 3-3-5-4 A diagram showing an example of data coding. 3-3-4-5 A diagram showing an example of data coding. The figure which shows an example of 4-3-4-4 data coding. The figure which shows an example of 3-4-4-4 data coding. The figure which shows an example of 3-4-4-4 data coding. FIG. 4 is a diagram showing an example of 4-3-4-4 data coding. The figure which shows an example of 3-4-4-4 data coding. The figure which shows an example of 3-4-4-4 data coding. The figure which shows an example of 3-4-4-4 data coding. The figure which shows an example of 3-4-4-4 data coding. FIG. 4 is a diagram showing an example of 4-4-3-4 data coding. FIG. 4 is a diagram showing an example of 4-4-3-4 data coding. 12 is a flowchart showing the entire writing procedure for one block according to the third embodiment. 10 is a flowchart showing a write procedure in a 1st stage and a 2nd stage according to a third embodiment. FIG. 7 is a diagram for explaining the write buffer amount in the program of the third embodiment.

FIG. 1 is a block diagram showing a schematic configuration of a memory system 1 according to the first embodiment. The memory system 1 in FIG. 1 includes a memory controller 2 and a nonvolatile memory 3. The memory system 1 in FIG. 1 is connectable to a host processor (hereinafter simply referred to as host) 4. The host 4 is, for example, an electronic device such as a personal computer or a mobile terminal.

The nonvolatile memory 3 is a memory that stores data in a nonvolatile manner, and includes, for example, a NAND flash memory (hereinafter sometimes referred to as a NAND memory) 5. In this embodiment, an example will be described in which the nonvolatile memory 3 is a 4-bit/Cell (QLC: Quad Level Cell) NAND memory 5 having memory cells that can store 4-bit data per memory cell. The nonvolatile memory 3 according to this embodiment has a three-dimensional structure in which memory cells are stacked three-dimensionally. Each of the nonvolatile memories 3 has a first threshold area indicating an erased state in which data is erased, and a first threshold area indicating a written state in which data is written at a voltage level higher than the first threshold area. It has a plurality of memory cells capable of storing 4-bit data represented by the 1st to 4th bits by 16 threshold regions including the 2nd to 16th threshold regions. For example, the first bit is the least significant Lower bit, the second bit is the second smallest Middle bit, the third bit is the second largest Upper bit, and the fourth bit is the most significant Top bit.

The memory controller 2 controls writing of data to the nonvolatile memory 3 according to a write command from the host 4. Furthermore, the memory controller 2 controls reading of data from the nonvolatile memory 3 according to a read command from the host 4. The memory controller 2 includes a RAM (Random Access Memory) 6, a ROM (Read Only Memory) 7, a processor 8, a host interface 9, an ECC (Error Check and Correct) circuit 10, and a memory interface 11. The RAM 6, processor 8, host interface 9, ECC circuit 10, and memory interface 11 are connected by a common internal bus 12.

As described later, the memory controller 2 of this embodiment causes the nonvolatile memory 3 to execute a first program for writing the data of the first bit, the second bit, and the fourth bit, and then writes the data of the third bit. The second program is caused to be executed in the nonvolatile memory 3. Among the 15 boundaries existing between adjacent threshold areas among the first to 16th threshold areas, the number of first boundaries used to determine the value of the data of the first bit, The number of second boundaries used to determine the value of the data of the bit, the number of third boundaries used to determine the value of the data of the third bit, and the number of the fourth boundary used to determine the value of the data of the fourth bit. The largest value of the number of boundaries is 5, and the second largest value is 4. The memory controller 2 is arranged such that the threshold area in the memory cell is a 17th threshold area indicating an erased state in which data is erased, and a The first program is programmed into the non-volatile memory so that the voltage level is higher than the 17th threshold area and the voltage level is higher than the 17th threshold area, indicating a written state in which data is written. 3. The memory controller 2 changes the threshold area in the memory cell from any one of the 17th to 24th threshold areas to the first to 16th threshold area according to the data of the third bit. The non-volatile memory 3 is configured to perform the second program so as to be set to one of the two threshold areas of the threshold areas. The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level among the two threshold regions is two or less. The memory controller 2 is configured to input second bit data and third bit data to the nonvolatile memory 3 when the nonvolatile memory 3 executes the second program.

More specifically, the memory controller 2 selects the first bit between adjacent threshold areas among 15 boundaries between 16 threshold areas (first to 16th threshold areas). The number of boundaries with different values of , the number of boundaries with different values of the second bit, the number of boundaries with different values of the third bit, and the number of boundaries with different values of the fourth bit are (1, 4, 5, 5) The first program and the second program are executed in the nonvolatile memory so that the program becomes (1, 5, 4, 5), or (3, 3, 4, 5).

Alternatively, the memory controller 2 of this embodiment causes the nonvolatile memory 3 to execute a first program for writing data of the first bit, second bit, and fourth bit, and then a second program for writing data of the third bit. The non-volatile memory 3 performs this. Among the 15 boundaries existing between adjacent threshold areas among the first to 16th threshold areas, the number of first boundaries used to determine the value of the data of the first bit, The number of second boundaries used to determine the value of the data of the bit, the number of third boundaries used to determine the value of the data of the third bit, and the number of the fourth boundary used to determine the value of the data of the fourth bit. The number of boundaries is (3, 5, 2, 5) in order. The memory controller 2 is arranged such that the threshold area in the memory cell is a 17th threshold area indicating an erased state in which data is erased, and a The first program is programmed into the non-volatile memory so that the voltage level is higher than the 17th threshold area and the voltage level is higher than the 17th threshold area, indicating a written state in which data is written. 3. The memory controller 2 changes the threshold area in the memory cell from any one of the 17th to 24th threshold areas to the first to 16th threshold area according to the data of the third bit. The non-volatile memory 3 is configured to perform the second program so as to be set to one of the two threshold areas of the threshold areas. The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level among the two threshold regions is two or less. The memory controller 2 is configured to input second bit data and third bit data to the nonvolatile memory 3 when the nonvolatile memory 3 executes the second program.

The memory controller 2 determines that the difference in voltage level between two threshold regions having different values of the data of the second bit among the seventeenth to twenty-fourth threshold regions is the difference in the voltage level between the two threshold regions having different values of the data of the first bit. The first program is performed so that the difference in voltage level between the two threshold regions is smaller than the difference in voltage level between the two threshold regions, and the value of the data of the fourth bit is smaller than the difference in voltage level between the two threshold regions. It may also be performed by non-volatile memory.

Alternatively, the memory controller 2 may program the second threshold area with the data of the third bit for the two threshold areas, rather than the interval between the two threshold areas during the first programming in which the value of the data of the second bit is different. The second program may be performed in the nonvolatile memory so that the distance between adjacent threshold areas among the four threshold areas obtained by performing the above steps is wide.

The host interface 9 outputs commands, user data (write data), etc. received from the host 4 to the internal bus 12. Further, the host interface 9 transmits user data read from the nonvolatile memory 3, responses from the processor 8, etc. to the host 4.

The memory interface 11 controls the process of writing user data and the like into the nonvolatile memory 3 and the process of reading it from the nonvolatile memory 3 based on instructions from the processor 8 .

The processor 8 controls the memory controller 2 in an integrated manner. The processor 8 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When the processor 8 receives a command from the host 4 via the host interface 9, it performs control according to the command. For example, the processor 8 instructs the memory interface 11 to write user data and parity to the nonvolatile memory 3 in accordance with a command from the host 4. Further, the processor 8 instructs the memory interface 11 to read user data and parity from the nonvolatile memory 3 in accordance with a command from the host 4 .

User data is stored in RAM 6 via internal bus 12. Processor 8 determines a storage area (memory area) on nonvolatile memory 3 for user data stored in RAM 6. The processor 8 determines a memory area on the nonvolatile memory 3 for data in units of pages (page data) that are write units. In this specification, user data stored in one page of the nonvolatile memory 3 is defined as unit data. Unit data is generally encoded and stored in the nonvolatile memory 3 as a code word, but encoding is not essential. Although the memory controller 2 may store unit data in the nonvolatile memory 3 without encoding it, FIG. 1 shows a configuration in which encoding is performed as an example of the configuration. If the memory controller 2 does not perform encoding, the page data matches the unit data. Moreover, one code word may be generated based on one unit data, or one code word may be generated based on divided data obtained by dividing unit data. Further, one code word may be generated using a plurality of unit data.

The processor 8 determines the memory area of the nonvolatile memory 3 to which data will be written for each unit of data. A physical address is assigned to a memory area of the nonvolatile memory 3. The processor 8 manages the memory area to which unit data is written using physical addresses. The processor 8 instructs the memory interface 11 to designate the determined memory area (physical address) and write the user data into the nonvolatile memory 3. On the other hand, the host 4 manages data using logical addresses. Therefore, the processor 8 manages the correspondence between logical addresses and physical addresses of user data. When the processor 8 receives a read command including a logical address from the host 4, it identifies a physical address corresponding to the logical address, specifies the physical address, and instructs the memory interface 11 to read user data.

In this specification, a plurality of memory cells commonly connected to one word line are defined as a memory cell group MG. One memory cell group MG becomes a write (program) unit. In this embodiment, the nonvolatile memory 3 is a 4-bit/cell NAND memory 5, and one memory cell group MG has a data amount equal to 4 bits×number of bits. Each bit written to each memory cell corresponds to a different page. In this embodiment, four pages of one memory cell group MG are divided into Lower page (first page), Middle page (second page), Upper page (third page), and Top page (fourth page). ).

The ECC circuit 10 encodes user data stored in the RAM 6 to generate code words. Further, the ECC circuit 10 decodes the code word read from the nonvolatile memory 3. The ECC circuit 10 corrects bit errors included in the code word read from the nonvolatile memory 3, and then decodes the code word into user data.

The RAM 6 temporarily stores user data received from the host 4 before being stored in the nonvolatile memory 3, and temporarily stores data read from the nonvolatile memory 3 before being transmitted to the host 4. The RAM 6 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

FIG. 1 shows a configuration example in which the memory controller 2 includes an ECC circuit 10 and a memory interface 11, respectively. However, the ECC circuit 10 may be built into the memory interface 11. Furthermore, the ECC circuit 10 may be built into the nonvolatile memory 3.

When receiving a write request from the host 4, the memory system 1 operates as follows. Processor 8 temporarily stores the write data in RAM 6. Processor 8 reads data stored in RAM 6 and inputs it to ECC circuit 10 . The ECC circuit 10 encodes input data and inputs a code word to the memory interface 11. The memory interface 11 writes the input code word into the nonvolatile memory 3.

When receiving a read request from the host 4, the memory system 1 operates as follows. The memory interface 11 inputs the code word read from the nonvolatile memory 3 to the ECC circuit 10. The ECC circuit 10 decodes the input code word and temporarily stores the decoded data in the RAM 6. Processor 8 transmits the data stored in RAM 6 to host 4 via host interface 9. Note that the nonvolatile memory 3 may be composed of a plurality of chips, and the nonvolatile memory 3 and the memory interface 11 may be connected by a through silicon via (TSV).

Note that the configuration of the memory controller 2 shown in FIG. 1 is an example, and there are various other derivative configurations such as the internal bus 12 having a divided structure or a hierarchical structure, or additional functional blocks being connected. can be taken.

FIG. 2 is a block diagram showing an example of the internal configuration of the nonvolatile memory 3 of this embodiment. The nonvolatile memory 3 includes a NAND I/O interface 21, a control section 22, a NAND memory cell array (memory cell section) 23, and a page buffer (second storage section) 24. The nonvolatile memory 3 is formed, for example, on a semiconductor substrate (for example, a silicon substrate) and made into a chip.

The control unit 22 controls the operation of the nonvolatile memory 3 based on commands and the like from the memory controller 2 via the NAND I/O interface 21 . Specifically, when a write request is input, the control unit 22 controls to write the data requested to be written to a specified address on the NAND memory cell array 23. Furthermore, when a read request is input, the control unit 22 controls to read the data requested to be read from the NAND memory cell array 23 and output it to the memory controller 2 via the NAND I/O interface 21. The page buffer 24 is a buffer that temporarily stores data input from the memory controller 2 when writing to the NAND memory cell array 23, and temporarily stores data read from the NAND memory cell array 23.

As will be described later, the control unit 22 reads data obtained by reading data programmed by the 1st stage program, bit data that is input redundantly in the 1st stage and 2nd stage programs, and the 2nd stage program. Based on the input data of the bit programmed in the second stage program, the threshold voltage of the data of the bit programmed in the second stage program is determined.

The control section 22 includes an oscillator 31, a sequencer 32, a command user interface 33, a voltage supply section 34, a column counter 35, and a serial access controller 36. Further, the NAND memory cell array 23 includes a row decoder 37 and a sense amplifier 38.

The NAND I/O interface 21 is a circuit for transmitting and receiving IO signals and control signals to and from the memory controller 2. The command user interface 33 acquires commands and addresses from among the commands, addresses, and data received from the memory controller 2 via the IO signal line based on the control signal. The command user interface 33 passes the acquired command and address to the sequencer 32.

The oscillator 31 is a circuit that generates a clock. A clock generated by the oscillator 31 is supplied to each component including the sequencer 32. Sequencer 32 is a state machine driven by a clock supplied from oscillator 31. The sequencer 32 executes control such as access to the NAND memory cell array 23. For example, the sequencer 32 issues commands for controlling various internal voltages, operation timings, etc. in response to commands received from the command user interface 33. Furthermore, the sequencer 32 supplies the block address and page address included in the address received from the command user interface 33 to the row decoder 37. Furthermore, the sequencer 32 supplies the column address included in the address received from the command user interface 33 to the column counter 35.

The voltage supply section 34 generates various internal voltages to be supplied to the word line and various internal voltages to be supplied to the bit line, and supplies them to the row decoder 37 and the sense amplifier 38. During a program operation or a read operation, the column counter 35 starts with the column address supplied from the sequencer 32 and advances the column address sequentially according to a control signal supplied from the serial access controller 36.

During a program operation, the page buffer 24 sequentially stores data received from the serial access controller 36 in the column address area designated by the column counter 35. Further, during a read operation, the page buffer 24 sequentially sends the data of the column address specified by the column address, among the stored data, to the serial access controller 36.

During a program operation, the serial access controller 36 stores data serially received from the NAND I/O interface 21 for each bit width of the IO signal line into the page buffer 24 . Furthermore, during a read operation, the serial access controller 36 sends data serially received from the page buffer 24 for each bit width of the IO signal line to the NAND I/O interface 21 .

During a program operation and a read operation, the row decoder 37 decodes a block address and a page address and selects a word line corresponding to a page to be accessed included in the accessed block BLK. Each row decoder 37 applies an appropriate voltage to the selected word line and unselected word line.

During a program operation, the sense amplifier 38 transfers the corresponding data stored in the page buffer 24 to the memory cell transistor. Further, during a read operation, the sense amplifier 38 senses data read from the selected word line to the bit line, and stores the obtained data in the page buffer 24. The data stored in the page buffer 24 is sent to the memory controller 2 via the serial access controller 36 and the NAND I/O interface 21.

FIG. 3 is a circuit diagram showing an example of a NAND memory cell array 23 having a three-dimensional structure. FIG. 3 shows the circuit configuration of one block BLK among a plurality of blocks in the three-dimensionally structured NAND memory cell array 23. Other blocks of the NAND memory cell array 23 also have the same circuit configuration as in FIG. 3. Note that this embodiment is also applicable to a memory cell with a two-dimensional structure.

As shown in FIG. 3, the block BLK has, for example, four fingers FNG (FNG0 to FNG3). Each finger FNG also includes multiple NAND strings NS. Each NAND string NS includes, for example, eight cascade-connected memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2. In this specification, each finger FNG may be referred to as a string St.

Note that the number of memory cell transistors MT in the NAND string NS is not limited to eight. Memory cell transistor MT is arranged between selection transistors ST1 and ST2 so that its current path is connected in series. The current path of the memory cell transistor MT7 at one end of this series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 at the other end is connected to one end of the current path of the selection transistor ST2. It is connected.

The gates of the selection transistors ST1 of the fingers FNG0 to FNG3 are commonly connected to select gate lines SGD0 to SGD3, respectively. On the other hand, the gates of the selection transistors ST2 are commonly connected to the same selection gate line SGS among the plurality of fingers FNG. Further, the control gates of memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. That is, the word lines WL0 to WL7 and the select gate line SGS are commonly connected among the fingers FNG0 to FNG3 in the same block BLK, whereas the select gate line SGD is connected in common among the fingers FNG0 to FNG3 in the same block BLK. is also independent for each of the fingers FNG0 to FNG3.

Word lines WL0 to WL7 are connected to the control gate electrodes of memory cell transistors MT0 to MT7 constituting the NAND string NS, respectively, and the i-th memory cell in each NAND string NS in the same finger FNG is The transistors MTi (i=0-n) are commonly connected by the same word line WLi (i=0-n). That is, the control gate electrodes of memory cell transistors MTi in the same row in block BLK are connected to the same word line WLi.

Each NAND string NS is connected to a word line WLi and also to a bit line. Each memory cell in each NAND string NS can be identified by an address identifying the word line WLi and select gate lines SGD0 to SGD3 and an address identifying the bit line. As described above, the data of memory cells (memory cell transistors MT) in the same block BLK are erased all at once. On the other hand, data reading and writing are performed in units of physical sectors MS. One physical sector MS includes a plurality of memory cells connected to one word line WLi and belonging to one finger FNG.

The memory controller 2 performs writing (programming) in units of all NAND strings NS connected to one word line in one finger. Therefore, the unit of data amount that the memory controller 2 programs is 4 bits×number of bit lines.

During a read operation and a program operation, one word line WLi and one select gate line SGD are selected according to a physical address, and a physical sector MS is selected. Note that in this specification, writing data to a memory cell is referred to as a program as necessary.

FIG. 4 is a cross-sectional view of a partial region of the NAND memory cell array 23 of the NAND memory 5 having a three-dimensional structure. As shown in FIG. 4, a plurality of NAND strings NS are formed in the vertical direction on a p-well region (P-well) 41 of a semiconductor substrate. That is, on the p-type well region 41, there are a plurality of wiring layers 42 functioning as select gate lines SGS, a plurality of wiring layers 43 functioning as word lines WLi, and a plurality of wiring layers 44 functioning as select gate lines SGD. It is formed in the vertical direction.

A memory hole 45 is formed that penetrates these wiring layers 42, 43, and 44 and reaches the p-type well region 41. A block insulating film 46 , a charge storage layer 47 , and a gate insulating film 48 are sequentially formed on the side surface of the memory hole 45 , and a conductive film 49 is further embedded in the memory hole 45 . The conductive film 49 functions as a current path of the NAND string NS, and is a region where a channel is formed when the memory cell transistor MT and selection transistors ST1 and ST2 operate.

In each NAND string NS, a selection transistor ST2, a plurality of memory cell transistors MT, and a selection transistor ST1 are sequentially stacked on the p-type well region 41. A wiring layer functioning as a bit line BL is formed at the upper end of the conductive film 49.

Furthermore, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed within the surface of the p type well region 41. A contact plug 50 is formed on the n+ type impurity diffusion layer, and a wiring layer functioning as a source line SL is formed on the contact plug 50. Further, a contact plug 51 is formed on the p+ type impurity diffusion layer, and a wiring layer functioning as a well wiring CPWELL is formed on the contact plug 51. The well wiring CPWELL is used to apply an erase voltage.

A plurality of NAND memory cell arrays 23 shown in FIG. 4 are arranged in the depth direction of the paper surface of FIG. 4, and one finger FNG is formed by a set of a plurality of NAND strings NS aligned in a row in the depth direction. Other fingers FNG are formed, for example, in the left-right direction in FIG. Although four fingers FNG0 to FNG3 are shown in FIG. 3, FIG. 4 shows an example in which three fingers are arranged between contact plugs 50 and 51.

FIG. 5 is a diagram illustrating an example of a threshold region according to the first embodiment. FIG. 5 shows an example of the distribution of the threshold area of the nonvolatile memory 3 of 4 bits/cell. In the nonvolatile memory 3, information is stored using the amount of charge of electrons stored in the charge storage layer 47 of the memory cell. Each memory cell has a threshold voltage depending on the amount of electron charge. Then, a plurality of data values stored in a memory cell are respectively made to correspond to a plurality of regions (threshold regions) having different threshold voltages.

In FIG. 5, S0 to S15 indicate threshold distributions within the 16 threshold regions. The horizontal axis in FIG. 5 indicates the threshold voltage, and the vertical axis indicates the number of memory cells (cell number). The threshold distribution is the range in which the threshold varies. Thus, each memory cell has 16 threshold regions separated by 15 boundaries, and each threshold region has a unique threshold distribution.

In this embodiment, a region where the threshold voltage is Vr1 or less is called region S0, a region where the threshold voltage is greater than Vr1 and less than Vr2 is called region S1, and a region where the threshold voltage is greater than Vr2 and less than Vr3. The region where the threshold voltage is greater than Vr3 and equal to or less than Vr4 is called the region S3. In addition, in this embodiment, a region where the threshold voltage is greater than Vr4 and less than or equal to Vr5 is referred to as region S4, and a region where the threshold voltage is greater than Vr5 and less than or equal to Vr6 is referred to as region S5, and the region where the threshold voltage is greater than Vr5 and less than or equal to Vr6 is referred to as region S5. The region where the threshold voltage is greater than Vr6 and equal to or less than Vr7 is referred to as region S6, and the region where the threshold voltage is greater than Vr7 and equal to or less than Vr8 is referred to as region S7. Furthermore, in this embodiment, a region where the threshold voltage is greater than Vr8 and less than or equal to Vr9 is referred to as region S8, and a region where the threshold voltage is greater than Vr9 and less than or equal to Vr10 is referred to as region S9, and the region where the threshold voltage is greater than Vr9 and less than or equal to Vr10 is referred to as region S9. A region where the threshold voltage is greater than Vr10 and less than or equal to Vr11 is referred to as region S10, and a region where the threshold voltage is greater than Vr11 and less than or equal to Vr12 is referred to as region S11. Furthermore, in this embodiment, a region where the threshold voltage is greater than Vr12 and less than or equal to Vr13 is referred to as region S12, and a region where the threshold voltage is greater than Vr13 and less than or equal to Vr14 is referred to as region S13, and the region where the threshold voltage is greater than Vr13 and less than or equal to Vr13 is referred to as region S13. The region in which the threshold voltage is greater than Vr14 and less than or equal to Vr15 is referred to as region S14, and the region in which the threshold voltage is greater than Vr15 is referred to as region S15.

Further, the threshold distributions corresponding to the regions S0 to S15 are referred to as first to sixteenth distributions. Vr1 to Vr15 are threshold voltages serving as boundaries of each threshold region.

In the nonvolatile memory 3, a plurality of data values are respectively associated with a plurality of threshold regions of a memory cell. This correspondence is called data coding. This data coding is determined in advance, and when data is written (programmed), charges are injected into the charge storage layer 47 in the memory cell so that it falls within a threshold region corresponding to the data value to be stored according to the data coding. At the time of reading, a read voltage is applied to the memory cell, and the data logic is determined depending on whether the threshold value of the memory cell is lower or higher than the read voltage.

When reading data, the logic of the data is determined depending on whether the threshold value is lower or higher than the read level at the boundary of the read target. When the threshold value is the lowest, it is an "erased" state, and all bits of data are defined as "1". If the threshold is higher than the "erased" state, it is a "programmed" state, and the data is defined as "1" or "0" according to the coding.

FIG. 6A is a diagram showing an example of data coding according to the first embodiment, and shows an example of 1-4-5-5 data coding. In this embodiment, the 16 threshold areas shown in FIG. 5 correspond to 16 4-bit data values, respectively. The relationship between the threshold voltage in FIG. 6A and the data values of the bits corresponding to the Top, Upper, Middle, and Lower pages is as shown below.

-A memory cell whose threshold voltage is within the S0 region is in a state where "1111" is stored.
-A memory cell whose threshold voltage is within the S1 region is in a state where "0111" is stored.
-A memory cell whose threshold voltage is within the S2 region is in a state where "0011" is stored.
-A memory cell whose threshold voltage is within the S3 region is in a state where "1011" is stored.
-A memory cell whose threshold voltage is within the S4 region is in a state where "1001" is stored.
-A memory cell whose threshold voltage is within the S5 region is in a state where "0001" is stored.
-A memory cell whose threshold voltage is within the S6 region is in a state where "0101" is stored.
-A memory cell whose threshold voltage is within the S7 region is in a state where "1101" is stored.
-A memory cell whose threshold voltage is within the S8 region is in a state where "1100" is stored.
-A memory cell whose threshold voltage is within the S9 region is in a state where "1110" is stored.
-A memory cell whose threshold voltage is within the S10 region is in a state where "1010" is stored.
-A memory cell whose threshold voltage is within the S11 region is in a state where "1000" is stored.
-A memory cell whose threshold voltage is within the S12 region is in a state where "0000" is stored.
-A memory cell whose threshold voltage is within the S13 region is in a state where "0100" is stored.
-A memory cell whose threshold voltage is within the S14 region is in a state where "0110" is stored.
-A memory cell whose threshold voltage is within the S15 region is in a state where "0010" is stored.

FIG. 6B is a diagram showing another example of data coding in the first embodiment, and shows an example of 4-3-4-4 data coding. The relationship between the threshold voltage in FIG. 6B and the data values of the bits corresponding to the Top, Upper, Middle, and Lower pages is as shown below.

-A memory cell whose threshold voltage is within the S0 region is in a state where "1111" is stored.
-A memory cell whose threshold voltage is within the S1 region is in a state where "0111" is stored.
-A memory cell whose threshold voltage is within the S2 region is in a state where "0011" is stored.
-A memory cell whose threshold voltage is within the S3 region is in a state where "1011" is stored.
-A memory cell whose threshold voltage is within the S4 region is in a state where "1010" is stored.
- A memory cell whose threshold voltage is within the S5 region is in a state where "1110" is stored.
- A memory cell whose threshold voltage is within the S6 region is in a state where "1100" is stored.
-A memory cell whose threshold voltage is within the S7 region is in a state where "1000" is stored.
-A memory cell whose threshold voltage is within the S8 region is in a state where "1001" is stored.
- A memory cell whose threshold voltage is within the S9 region is in a state where "0001" is stored.
- A memory cell whose threshold voltage is within the S10 region is in a state where "0000" is stored.
-A memory cell whose threshold voltage is within the S11 region is in a state where "0010" is stored.
-A memory cell whose threshold voltage is within the S12 region is in a state where "0110" is stored.
-A memory cell whose threshold voltage is within the S13 region is in a state where "0100" is stored.
-A memory cell whose threshold voltage is within the S14 region is in a state where "0101" is stored.
-A memory cell whose threshold voltage is within the S15 region is in a state where "1101" is stored.

As shown in FIGS. 6A and 6B, the logic of 4-bit data of each memory cell can be assigned to each region of threshold voltage. Note that when the memory cell is in an unwritten state (“erased” state), the threshold voltage of the memory cell is within the S0 region. In addition, in the code shown here, one bit is stored between any two adjacent areas, such as storing data "1111" in the S0 (erased) state and storing data "0111" in the S1 state. Only the data changes. In this way, the data coding shown in FIGS. 6A and 6B is a Gray code in which only one bit of data changes between any two adjacent regions.

In the coding of this embodiment shown in FIG. 6A, the threshold voltages serving as boundaries for determining the bit values of each page are as shown below.

- Threshold voltages serving as boundaries for determining the top page bit value are Vr1, Vr3, Vr5, Vr7, and Vr12.
- Threshold voltages serving as boundaries for determining the bit value of the Upper page are Vr2, Vr6, Vr10, Vr13, and Vr15.
- Threshold voltages serving as boundaries for determining the bit value of the Middle page are Vr4, Vr9, Vr11, and Vr14.
- The threshold voltage that is the boundary for determining the bit value of the Lower page is Vr8.

In this way, the number of threshold voltages that serve as boundaries for determining bit values (hereinafter referred to as the number of boundaries) is 1, 4, 5, and 5 for the Lower page, Middle page, Upper page, and Top page, respectively. It is. Hereinafter, such coding will be referred to as 1-4-5-5 coding using the number of boundaries for each of the Lower page, Middle page, Upper page, and Top page.

The first feature of this embodiment is that the number of boundaries at which the bit value changes for each page is five at maximum. When 16 states are represented by 4 bits, the minimum value of the maximum number of boundaries is 4, and the coding of FIG. 6 has only one more than this, which reduces the bias of bit errors. In this way, the memory system 1 according to the present embodiment, having the first feature, can suppress the bit error rate and also suppress the bias of bit errors from page to page.

The second feature of this embodiment is that the number of boundaries for the Lower page is one, and the number of boundaries for the Middle page is four. It is possible to program in two stages, including a second stage program in which pages are grouped together.

The third feature of this embodiment is that the range of change from the threshold area generated by the first stage program to the threshold area generated by the second stage program is small. That is, the width of change in the threshold area is small. The smaller the width of change in the threshold area, the less susceptible to interference between adjacent cells. The first to third features described above will be explained in detail later.

The control unit 22 of the nonvolatile memory 3 controls programming to and reading from the NAND memory cell array 23 based on the coding shown in FIG. 6A or 6B.

In three-dimensional memory cells, miniaturization of memory cells has not progressed as much as in two-dimensional memory cells. Therefore, in three-dimensional memory cells, if the generation has a wide interval between adjacent memory cells, mutual interference between cells is small. In this case, a technique is generally used in which all bits of each memory cell are programmed at the same time, for example, if each bit is assigned to a different page, all pages are programmed at the same time.

When programming all bits of each memory cell at the same time, any particular combination of data coding does not matter. Based on the data of all the bits, it is determined in which of the 16 threshold areas it is located, and programming can be performed from the area of S0, which is in the erased state, to the determined threshold area. In this case, data coding such as 4-4-3-4 data coding in which the maximum number of boundaries takes a minimum value is generally employed. In 4-4-3-4 data coding, when distributing 15 boundaries between 16 threshold areas into 4 pages, 4 boundaries are assigned to the Lower page, 4 boundaries are assigned to the Middle page, and 3 boundaries are assigned to the Upper page. 4 borders are distributed on the top page. In the case of this data coding, since the deviation in the number of boundaries between pages is small, as a result, the deviation in the bit error rate between pages is small. This is because most of the causes of bit errors are caused by shifting of the threshold value to adjacent threshold areas, and the more boundaries the page has, the greater the number of bit errors. This means that even if the error rate as a memory cell is the same, the correction ability of the ECC circuit 10 required to correct errors in page data must be strengthened. This is also effective for suppressing deterioration in response performance, cost, and power consumption of the memory system 1 to write requests. Furthermore, the deviation in read speed caused by the deviation in the number of boundaries is also reduced.

In addition, in the 4-bit/Cell NAND memory 5, the interval between adjacent threshold regions becomes narrower, so the influence of mutual interference between cells becomes larger compared to the 1-bit/Cell or 2-bit/Cell NAND memory 5. . For this reason, in the recent generation of NAND memory 5 with advanced miniaturization, in order to suppress mutual interference between cells, multiple program stages, for example two program stages (hereinafter sometimes simply referred to as stages) are used. Therefore, a programming method (Foggy-Fine programming) is adopted in which charges are injected little by little into the charge storage layer 47 of the memory cell. In this Foggy-Fine program, after writing to the memory cell in the first stage (Foggy stage), writing to the adjacent cell is performed, and then the program returns to the first memory cell and starts the second stage (Fine stage). Write. Each stage in this case is a program execution unit, and programming of a memory cell corresponding to one word line WLi is completed by executing two program stages.

Both the first stage program and the second stage program are executed using 16 threshold areas. The threshold distribution of the threshold region at the end of the program of the first stage has a wider width than the threshold distribution of the threshold region in the final data coding. That is, in the Foggy stage, Foggy (rough) writing is performed. This Foggy stage program requires all four pages of input data. The threshold distribution after programming in the Foggy stage is in an intermediate state where adjacent distributions overlap each other, so data cannot be read. In the program of the second stage, Fine stage, the threshold area after programming of the Foggy stage is moved to the threshold area in the final data coding. That is, in the Fine stage, Fine writing is performed. This Fine stage program also requires all four pages of input data. Since the threshold distribution after programming in the Fine stage is the final state in which adjacent distributions are separated, data can be read out after programming in the Fine stage.

In the case of 4-4-3-4 data coding, the deviation in the number of boundaries is small, but in the data input of the Foggy-Fine program, data input for four pages is required at each stage. This increases the time required for data input and deteriorates the response performance of the memory system 1 to write requests from the host 4. Furthermore, in the memory system 1, the buffer amount (write buffer amount) of the write buffer (first storage section) for holding data to be input to the NAND memory 5 is increased. Generally, a part of the RAM 6 in the memory system 1 is allocated to this write buffer.

As a countermeasure against these problems, in the present embodiment, the memory system 1 adopts 1-4-5-5 data coding for the nonvolatile memory 3 having a three-dimensional structure, and furthermore, in two stages, page by page ( Perform page-by-page) writing. As a result, in this embodiment, even in the nonvolatile memory 3 having a three-dimensional structure, the write buffer amount of the memory controller 2 is reduced while suppressing mutual interference between cells and bias in bit error rate between pages. In the write buffer of this embodiment, among the first to fourth bits (lower page, middle page, upper page, and top page data), bit data is input redundantly during the first program and the second program. can be discarded or invalidated after starting the second program, and data of other bits can be discarded or invalidated after starting the first program.

Here, interference between adjacent memory cells will be explained. Charges accumulated in the charge storage layer 47 of one memory cell disturb the electric field of the adjacent memory cell, and as a result, give noise that changes the threshold voltage when reading the adjacent memory cell. Programming and verifying are performed under certain electric field conditions, and after the programming is completed, adjacent memory cells are programmed with different charges, which causes read accuracy to deteriorate. This interference between adjacent memory cells becomes more noticeable as memory device manufacturing technology becomes finer and memory cell spacing becomes smaller. This interference between adjacent memory cells mainly occurs between adjacent memory cells connected to different bit lines on the same word line WLi.

Interference between adjacent memory cells can be alleviated by reducing the difference in the electric field conditions of the memory cells between programming and verifying and reading after adjacent memory cells have been programmed. One way to reduce interference between adjacent memory cells connected to different bit lines on the same word line WLi is to divide the program into multiple stages, and between each stage, the charge storage layer 47 is There is a way to execute a program so that large changes in the amount of charge do not occur.

In the program sequence in this embodiment, 4 bits on one word line WLi are programmed by two program stages, ie, a 1st stage and a 2nd stage. Each program stage is a program execution unit, and the memory system 1 of this embodiment completes writing of 4-bit data to a memory cell by executing two program stages. Furthermore, in this embodiment, 4-bit data of any page is used for each of the two program stages. Specifically, the 1st stage program uses Lower page data, Middle page data, and Top page data, and the 2nd stage program uses Middle page data, Upper page data, and Top page data.

FIG. 7 is a diagram showing the threshold area after programming in the first embodiment. FIG. 7 shows the threshold region after programming the memory cell in the 1st stage and the 2nd stage. (T1) in FIG. 7 shows the threshold area in the erased state, which is the initial state before programming. (T2) in FIG. 7 shows the threshold area after the 1st stage program (first program). (T3) in FIG. 7 shows the threshold area after the 2nd stage program (second program).

As shown at (T1) in FIG. 7, all memory cells of the NAND memory cell array 23 are in a state of distribution S0 in an unwritten state (“erased” state). As shown in (T2) in FIG. 7, in the 1st stage program, the control unit 22 of the non-volatile memory 3 controls each memory cell according to the bit values to be written (stored) in the Lower page, Middle page, and Top page. The distribution S0 is left as is, or the distribution is moved to a position above the distribution S0 by injecting charge.

Specifically, if the bit values to be written to the Lower page, Middle page, and Top page are all “1”, the control unit 22 does not inject charge, and instead injects the bit values to be written to the Lower page, Middle page, and Top page. If any one of them is "0", charge is injected and programmed to move the threshold voltage higher.

In other words, if the bit value written to the Lower page, Middle page, and Top page is "011", the bit value written to the Lower page, Middle page, and Top page is "101", to the distribution S4, and If the bit value written to the Lower page, Middle page, and Top page is "001", go to distribution S5, and if the bit value written to the Lower page, Middle page, and Top page is "100", go to distribution S8, and to the Lower page. If the bit value written to the Middle page and Top page is "110", the flow goes to distribution S9, and if the bit value written to the Lower page, Middle page, and Top page is "000", the flow goes to distribution S12; If the bit value written to the page and top page is "010", it is moved to distribution S14.

Preferably, distribution S1, distribution S4, distribution S5, distribution S8, distribution S9, distribution S12, and distribution S14 are roughly programmed by widening the width of the threshold region so that the threshold voltage becomes somewhat lower. That is, the rise width of the program voltage pulse, which will be described later, is increased. Thereby, the time required for writing can be shortened. By programming so that the threshold voltage is somewhat lower, it is possible to write the width of the threshold distribution region so that it finally becomes a predetermined width in the 2nd stage programming.

Preferably, the intervals between the adjacent distributions S8 and S9 and between the adjacent threshold distributions S12 and S14 are narrower than the intervals between the adjacent distributions. The write bit values of adjacent threshold distributions with narrower intervals have different middle page data. In other words, since the data after programming in the 1st stage looks like binary, it is possible to read the Lower page, Middle page data, and Top page, but the interval between the threshold distributions where the Middle page data differs is narrowed. By doing so, the interval between the threshold distributions where the data of the Lower page and the Top page are different is ensured wide, and the margin when reading the Lower page and the Top page is increased. The threshold distributions S0 to S14 shown in (T2) of FIG. 7 correspond to the 17th to 24th threshold regions.

Next, as shown at (T3) in FIG. 7, in the 2nd stage program, two pages, a Middle page and an Upper page, are required for data writing. Then, the control unit 22 of the nonvolatile memory 3 programs the threshold distribution after programming in the 2nd stage so that the final state in which each adjacent distribution is separated has 16 levels. After the 2nd stage programming, all page data can be read.

In the 2nd stage programming, the larger the change in the threshold value of the memory cell from the end of the 1st stage programming, the greater the interference between adjacent cells. Therefore, it is preferable that the amount of change in the threshold distribution of the memory cell is the largest and the amount of change in the threshold distribution is the smallest. According to this embodiment, the maximum amount of change in the threshold distribution is for three threshold distributions: when S0 changes to S3, when S4 changes to S7, and when S8 changes to S11. This is the case. The threshold distributions S0 to S15 shown in (T3) of FIG. 7 correspond to the first to sixteenth threshold regions.

Note that programming is typically performed by applying a programming voltage pulse one or more times. In multiple program application pulses, the voltage value is increased stepwise. After each program voltage pulse, a read, called a verify, is performed to determine whether the memory cell has moved beyond the threshold boundary level. By repeating this application and reading, it becomes possible to move the threshold value of the memory cell within the range of a predetermined threshold distribution.

Note that the control unit 22 may perform the 1st stage program and the 2nd stage program consecutively for one word line WLi, but in order to reduce the influence of interference between adjacent memory cells, It is also possible to perform programming in a non-sequential order across word lines WLi.

FIG. 8A is a diagram showing a first example of the program order of the first embodiment. FIG. 8B is a diagram showing a second example of the program order of the first embodiment. FIG. 8C is a diagram showing a third example of the program order of the first embodiment. In FIGS. 8A to 8C, programming is performed in two program stages in order to reduce the influence of interference between adjacent memory cells. FIG. 8A shows an example of a program order in the NAND memory 5 in which one string St is connected to each word line in each block. Further, FIGS. 8B and 8C show an example of a program order in the NAND memory 5 in which four strings St are connected to each word line in each block. Note that in FIGS. 8B and 8C, the four strings St connected to each word line are expressed as Strings 0 to 3.

When writing starts, the control unit 22 advances through each program stage while straddling the word lines WLi in a predetermined non-sequential order. That is, the 1st stage and 2nd stage for the same word line are not executed consecutively, but after the 1st stage is programmed for a certain word line, the 2nd stage is programmed for a different word line.

After completing programming up to the 2nd stage for a certain word line, if programming for the 1st stage and 2nd stage is successively performed for adjacent word lines, the amount of variation in threshold voltage increases. When the amount of variation in the threshold voltage of adjacent word lines is large, interference between adjacent memory cells between word lines becomes large. Therefore, in order to reduce the interference between adjacent memory cells between word lines, it is effective to reduce the amount of variation in the threshold voltage of the adjacent word lines after the word lines complete programming up to the 2nd stage. In the sequence of FIG. 8A, after a certain word line completes programming up to the 2nd stage, the programming stage of the adjacent word line is only the 2nd stage.

When programming the three-dimensionally structured NAND memory 5 in the programming order shown in FIG. Run the program with . The control unit 22 programs the NAND memory 5 based on instructions from the processor 8, but the description that it is based on instructions from the processor 8 will be omitted below.

(1) First, the control unit 22 executes the 1st stage program ST11 for the word line WL0.
(2) Next, the control unit 22 executes the 1st stage program ST12 for the word line WL1.
(3) Next, the control unit 22 executes the 2nd stage program ST13 for the word line WL0.
(4) Next, the control unit 22 executes the 1st stage program ST14 for the word line WL2.
(5) Next, the control unit 22 executes the 2nd stage program ST15 for the word line WL1.
(6) Next, the control unit 22 executes the 1st stage program ST16 for the word line WL3.
(7) Next, the control unit 22 executes the 2nd stage program ST17 for the word line WL2.
(8) Next, the control unit 22 executes the 1st stage program ST18 for the word line WL4.
(9) Next, the control unit 22 executes the 2nd stage program ST19 for the word line WL3.

Similarly, the control unit 22 proceeds with the process diagonally upward from the lower left to the upper right in FIG. 8A. In this manner, in FIG. 8A, a plurality of memory cells in the nonvolatile memory 3 are connected to a plurality of first memory cells connected to a first word line and a second word line adjacent to the first word line. and a plurality of second memory cells, the memory controller 2 causes the plurality of first memory cells to perform the first program, and then executes the first program to the plurality of second memory cells. Then, the first programming is performed on the plurality of second memory cells, and then the second programming is performed on the plurality of first memory cells.

When programming the three-dimensional NAND memory 5 in the program order shown in FIG. 8B, when writing starts, the control unit 22 executes the program in the order shown in (11) to (24) below.

(11) First, the control unit 22 executes the 1st stage program ST21 of the string St0_word line WL0.
(12) Next, the control unit 22 executes the 1st stage program ST22 of the string St1_word line WL0.
(13) Next, the control unit 22 executes the 1st stage program ST23 of the string St2_word line WL0.
(14) Next, the control unit 22 executes the 1st stage program ST24 of the string St3_word line WL0.
(15) Next, the control unit 22 executes the 1st stage program ST25 for the string St0_word line WL1.
(16) Next, the control unit 22 executes the 2nd stage program ST26 of the string St0_word line WL0.
(17) Next, the control unit 22 executes the 1st stage program ST27 of the string St1_word line WL1.
(18) Next, the control unit 22 executes the 2nd stage program ST28 of the string St1_word line WL0.
(19) Next, the control unit 22 executes the 1st stage program ST29 of the string St2_word line WL1.
(20) Next, the control unit 22 executes the 2nd stage program ST210 of the string St2_word line WL0.
(21) Next, the control unit 22 executes the 1st stage program ST211 of the string St3_word line WL1.
(22) Next, the control unit 22 executes the 2nd stage program ST212 of the string St3_word line WL0.
(23) Next, the control unit 22 executes the 1st stage program ST213 of the string St0_word line WL2.
(24) Next, the control unit 22 executes the 2nd stage program ST214 for the string St0_word line WL1.

Similarly, the control unit 22 proceeds with the process diagonally upward from the lower left to the upper right in FIG. 8B. Note that in FIG. 8B, a case has been described in which there are four strings St in a block, but the number of strings St in a block may be three or less, or five or more.

When programming the three-dimensional NAND memory 5 in the program order shown in FIG. 8C, when writing starts, the control unit 22 executes the program in the order shown in (31) to (50) below.

(31) First, the control unit 22 executes the 1st stage program ST31 of the string St0_word line WL0.
(32) Next, the control unit 22 executes the 1st stage program ST32 of the string St1_word line WL0.
(33) Next, the control unit 22 executes the 1st stage program ST33 of the string St2_word line WL0.
(34) Next, the control unit 22 executes the 1st stage program ST34 of the string St3_word line WL0.
(35) First, the control unit 22 executes the 1st stage program ST35 for the string St0_word line WL1.
(36) Next, the control unit 22 executes the 1st stage program ST36 of the string St1_word line WL1.
(37) Next, the control unit 22 executes the 1st stage program ST37 for the string St2_word line WL1.
(38) Next, the control unit 22 executes the 1st stage program ST38 for the string St3_word line WL1.
(39) Next, the control unit 22 executes the 2nd stage program ST39 of the string St0_word line WL0.
(40) Next, the control unit 22 executes the 2nd stage program ST310 of the string St1_word line WL0.
(41) Next, the control unit 22 executes the 2nd stage program ST311 of the string St2_word line WL0.
(42) Next, the control unit 22 executes the 2nd stage program ST312 of the string St3_word line WL0.
(43) Next, the control unit 22 executes the 1st stage program ST313 of the string St0_word line WL2.
(44) Next, the control unit 22 executes the 1st stage program ST314 of the string St1_word line WL2.
(45) Next, the control unit 22 executes the 1st stage program ST315 of the string St2_word line WL2.
(46) Next, the control unit 22 executes the 1st stage program ST316 of the string St3_word line WL2.
(47) Next, the control unit 22 executes the 2nd stage program ST317 for the string St0_word line WL1.
(48) Next, the control unit 22 executes the 2nd stage program ST318 of the string St1_word line WL1.
(49) Next, the control unit 22 executes the 2nd stage program ST319 of the string St2_word line WL1.
(50) Next, the control unit 22 executes the 2nd stage program ST320 of the string St3_word line WL1.

Note that in FIG. 8C, a case has been described in which the number of strings St in a block is four, but the number of strings St in a block may be three or less, or may be five or more.

In this way, even if there are a plurality of strings St, the order of programming of each program stage of the word line WLi within one string St is the same as when there is only one string St. In the case of a nonvolatile memory 3 with a three-dimensional structure in which a plurality of strings St exist in a block, the combination position of a word line WLi and a string St is generally programmed by first programming the same word line number in a different string St. and then advances to the next word line number. If such an order is followed, if the strings in FIG. 8A are combined by the number of strings St, the order will be as shown in FIG. 8B or 8C, for example.

Here, an example of a write procedure according to the program order according to the first embodiment will be explained using FIGS. 9 to 11. 9 to 11 show the write procedure in the case of following the program order shown in FIG. 8B or 8C. As described above, the memory controller 2 advances the program stage while straddling the word lines WLi in a non-continuous order, so it executes the program using a group of word lines WLi (here, a block) as a group of the program sequence. do.

FIG. 9 is a flowchart showing a first example of a procedure for writing an entire block according to the first embodiment. It is assumed here that one block has n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). FIG. 10 is a flowchart showing the write procedure in the 1st stage according to the first embodiment, and FIG. 11 is a flowchart showing the write procedure in the 2nd stage according to the first embodiment.

As shown in FIG. 9, when writing starts, the control unit 22 executes the 1st stage program of the string St0_word line WL0 (step S10). Next, the control unit 22 executes the 1st stage program of the string St1_word line WL0 (step S20). After this, the control unit 22 executes the same processing as steps S10 and S20 for each string St. Then, the control unit 22 executes the 1st stage program for string St3_word line WL0 (step S30).

Further, the control unit 22 executes the 1st stage program of the string St0_word line WL1 (step S40). Next, the control unit 22 executes the 2nd stage program of the string St0_word line WL0 (step S50). Next, the control unit 22 executes the 1st stage program for the string St1_word line WL1 (step S60). After that, the control unit 22 repeats the processes such as steps S40, S50, and S60 for each word line WLi of each string St.

Then, the control unit 22 executes the 1st stage program of the string St0_word line WLn (step S70). Next, the control unit 22 executes the 2nd stage program for the string St0_word line WLn-1 (step S80). After this, the control unit 22 repeats the processes such as steps S70 and S80 for each word line WLi of each string St.

Then, the control unit 22 executes the 2nd stage program for string St3_word line WLn-1 (step S90). Next, the control unit 22 executes the 2nd stage program of the string St0_word line WLn (step S100). Next, the control unit 22 executes the 2nd stage program of the string St1_word line WLn (step S110). After that, the control unit 22 performs the same processing as steps S100 and S110 for each string St. Then, the control unit 22 executes the 2nd stage program for string St3_word line WLn (step S120).

FIG. 10 is a flowchart showing a first example of the write procedure of the 1st stage. In the first stage program, first, a lower page data input start command is input from the memory controller 2 to the nonvolatile memory 3 (step S210). Then, the lower page data is input from the memory controller 2 to the nonvolatile memory 3 (step S215). Next, a middle page data input start command is input from the memory controller 2 to the nonvolatile memory 3 (step S220). Then, Middle page data is input from the memory controller 2 to the nonvolatile memory 3 (step S225). Next, a top page data input start command is input from the memory controller 2 to the nonvolatile memory 3 (step S230). Then, the top page data is input from the memory controller 2 to the nonvolatile memory 3 (step S235). Further, a 1st stage program execution command is input from the memory controller 2 to the nonvolatile memory 3 (step S240), and the chip becomes busy (step S245).

When writing data, a threshold voltage Vth is determined (step S250), and one to a plurality of program voltage pulses are applied (step S255). Then, data reading (verification) is performed to check whether the memory cell has moved beyond the threshold boundary level (step S260).

Furthermore, it is checked whether the number of fail bits of data in the Lower page, Middle page, and Top page is smaller than a criterion (step S265). If the number of fail bits of the data is equal to or greater than the criterion, the processing from application of the program pulse to criterion determination (steps S255 to S265) is repeated. Then, when the number of fail bits of the data becomes smaller than the criterion, the chip becomes ready (step S270). By repeating the application, reading, and confirmation in this way, it is possible to move the threshold value of the memory cell within the range of a predetermined threshold distribution.

Note that, as described above, the read level after application of the program voltage pulse during 1st stage writing may be slightly different from the read level after 2nd stage writing, and is preferably lower than the read level after 2nd stage writing. level. That is, Vr1'≦Vr1, Vr4'≦Vr4, Vr5'≦Vr5, Vr8'≦Vr8, Vr9'≦Vr9, Vr12'≦Vr12, and Vr14'≦Vr14.

In addition, in the read after application of the program voltage pulse in the 1st stage write, the read by Vr9' and the read by Vr14' are omitted, and Vr9' passes the read of Vr8' and after applying a certain specified number of program voltage pulses. The writing may be completed, and after Vr14' passes the reading of Vr13', the writing may be completed after applying a certain prescribed number of program voltage pulses.

As mentioned above, by narrowing the interval between the threshold areas where the data of the Middle page differs in the data after programming in the 1st stage, the data of the Lower page and the Top page that are read during writing in the 2nd stage are different. This is because the interval between the threshold regions can be ensured to be sufficiently wide even with simple control of applying a certain number of program voltage pulses.

Furthermore, even if reading after applying program voltage pulses of Vr8', Vr9', Vr12' and Vr14' is omitted, and after passing the reading of Vr5', writing is completed after applying a certain number of program voltage pulses for each. good. In addition, the readout after applying the program voltage pulses of Vr4', Vr5', Vr8', Vr9', Vr12', and Vr14' is omitted, and after passing the readout of Vr1', the program voltage pulses are applied a certain number of times. Writing may be completed after applying .

FIG. 11 is a flowchart showing a first example of the write procedure of the 2nd stage. In the second stage program, first, a command to start inputting Middle page data is input from the memory controller 2 to the nonvolatile memory 3 (step S310). Then, data of the Middle page is input from the memory controller 2 to the nonvolatile memory 3 (step S320).

Next, a command to start inputting Upper page data is input from the memory controller 2 to the nonvolatile memory 3 (step S330). Then, the data of the Upper page is input from the memory controller 2 to the nonvolatile memory 3 (step S340). Next, a 2nd stage program execution command is input from the memory controller 2 to the nonvolatile memory 3 (step S350), and the chip becomes busy (step S360).

After that, the control unit 22 reads the Lower page and Top page data as IDL (Internal Data Load) (Step S370). Then, Vth (threshold voltage) of the program destination of the Upper page is determined based on the previously input Middle page data and the data of the Lower page and Top page by IDL (step S380). Thereafter, data is written to the Upper page using the determined Vth. More specifically, the voltage values of the plurality of program pulses are gradually increased and written so as to reach the determined threshold voltage (step S390). Memory cells that have reached the target threshold voltage are excluded from being programmed.

Thereafter, the written data is read (step S400), and it is determined whether the number of fail bits is smaller than a criterion (step S410). If the number of fail bits of the data is equal to or greater than the criterion, the processing from application of the program pulse to criterion determination (steps S390 to S410) is repeated. Then, when the number of fail bits of the data becomes smaller than the criterion, the chip becomes ready (step S420).

Here, this embodiment has two features. The first feature is that the Middle page data has already been input in the 1st stage program, and the threshold area after the 1st program is in a written state that also includes the Middle page data, but even in the 2nd stage program. This is again entering the data for the Middle page. The second feature is that in the 1st stage program, the distance between adjacent threshold areas where the data of the Middle page is switched is narrow, and the interval between adjacent threshold areas where the data of the Lower page and the data of the Top page are switched is narrow. On the contrary, the intervals are getting wider. This makes it possible to improve the reliability of the Lower page and Top page data read by IDL. On the other hand, if the data on the Middle page is read using IDL, there is a risk that the reliability will decrease, but in this embodiment, the data on the Middle page used in the 1st stage program is input again, so the reliability decreases. There is no risk of it happening.

Furthermore, in order to improve the reliability of the IDL read data, the control unit 22 can read the IDL multiple times, take a majority vote on the read results in the page buffer in the chip, and use it as the next write data. be. Of course, during a normal read operation, the control unit 22 can also read data a plurality of times, take a majority vote on the read results within the chip, and use the result as read data to the outside.

FIG. 12 is a diagram for explaining majority decision processing of the results of reading a plurality of times. In FIG. 12, as a result of reading data of a predetermined page, correct bits are indicated by circles (◯), and incorrect bits are indicated by cross marks (×). Further, FIG. 12 shows the result of majority voting when reading is performed three times.

For each bit, the result of the majority vote is determined to be incorrect if (a) it is incorrect three times, or (b) if it is incorrect twice. Let p be the probability that each bit is incorrect. When p = 0.2, (a) the probability of making an error three times is p x p x p = 0.2 x 0.2 x 0.2, and ( b) The probability of making a mistake twice is (1-p)×p×p=(1-0.2)×0.2×0.2.

Therefore, the number of times when the three majority voting results are determined to be incorrect is (p×p×p)+3×(1−p)×p×p=0.104. In this way, the control unit 22 can improve the reliability of read data by performing majority voting on the results of reading a plurality of times using the page buffer 24 in the chip.

Furthermore, in order to improve the reliability of the IDL read data in the 2nd stage writing of the word line WLn, the control unit 22 controls the word line in the IDL according to the data written in the 1st stage writing of WLn+1 or the threshold voltage. Reading may be performed by changing the read voltage of line WLn.

Furthermore, in order to improve the reliability of the IDL read data in the 2nd stage writing of the word line WLn, the control unit 22 performs the following according to the data written in the 1st stage writing of the word line WLn+1 or the threshold voltage. Reading may be performed by changing the non-selection voltage of word line WLn+1 in IDL. At this time, reading may be performed by changing the read voltage of the word line WLn at the same time.

When writing data to the Upper page, one to a plurality of program voltage pulses are applied. Then, in order to confirm whether the memory cell has moved beyond the threshold boundary level, data reading (verification) of the Upper page is performed. The read level at this time is a predetermined level.

Furthermore, it is checked whether the number of fail bits of data in the Upper page is smaller than the criteria. If the number of failed bits of data in the Upper page is equal to or greater than the criterion, the verification process from application of the program voltage pulse is repeated. Then, when the number of data fail bits becomes smaller than the criterion, the chip becomes ready.

Here, a modification of the writing procedure shown in FIG. 11 will be described. FIG. 13 is a flowchart showing a modification of the writing procedure in the 2nd stage according to the first embodiment. Note that in the flowchart of FIG. 13, a procedure is added in which error correction is performed on the IDL data read from the data programmed in the 1st stage and then returned to the nonvolatile memory 3. Specifically, first, a lower page read command is input from the memory controller 2 to the nonvolatile memory 3 (step S510). As a result, the chip becomes busy (step S512). Next, the control unit 22 reads the lower page data at a threshold voltage of Vr8'. Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr8' (step S514). After this, the chip becomes ready (step S516).

When the control unit 22 outputs the read Lower page data (Step S518), this Lower page data is transmitted to the ECC circuit 10 (Step S520). As a result, the ECC circuit 10 performs ECC correction on the lower page data (step S522).

Next, a lower page data input start command is input from the memory controller 2 to the nonvolatile memory 3 (step S524). As a result, the ECC circuit 10 inputs the data of the lower page to the nonvolatile memory 3 (step S526).

Next, a top page read command is input from the memory controller 2 to the nonvolatile memory 3 (step S528), and the chip becomes busy (step S530). After that, the control unit 22 reads the top page data at the threshold voltages of Vr2' and Vr10'. Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr1', Vr4', Vr8', and Vr12' (step S532). ). After this, the chip becomes ready (step S534).

When the control unit 22 outputs the read top page data (step S536), this top page data is transmitted to the ECC circuit 10 (step S538). As a result, the ECC circuit 10 performs ECC correction on the top page data (step S540). Next, a top page data input start command is input from the memory controller 2 to the nonvolatile memory 3 (step S542). As a result, the ECC circuit 10 inputs the top page data to the nonvolatile memory 3 (step S544).

Thereafter, a command to start inputting Middle page data is input from the memory controller 2 to the nonvolatile memory 3. (Step S546). The subsequent steps are similar to the procedure shown in FIG. The threshold voltage Vth of the program destination is determined based on the Lower page data and Top page data from the ECC circuit 10, the re-input Middle page data, and the newly input Upper page data. A value voltage Vth is determined.

In the above-described 2nd stage program, data is input to the nonvolatile memory 3 only in two pages, the Middle page and the Upper page. However, in this 2nd stage, the threshold voltage Vth, which is the destination of memory cell programming, contains data for 4 pages including the Lower page and the Top page (threshold voltage Vth before starting the 2nd stage). is necessary. Therefore, in the program at this stage, as preprocessing, the control unit 22 first reads the Lower page data and the Top page data, and then combines the data with the input Middle page and Upper page to create the program destination. The operation of determining the threshold voltage Vth is performed. Note that the read level at the time of verifying the 2nd stage may be slightly different from the read level after writing in the 2nd stage.

Here, a comparison between the processing procedure of the Foggy-Fine program that employs 4-3-4-4 data coding and the program processing procedure of this embodiment will be explained. FIG. 14A is a diagram illustrating the amount of data in the write buffer in a Foggy-Fine program that employs 4-3-4-4 data coding. FIG. 14B is a diagram illustrating the amount of data in the write buffer in this embodiment. FIG. 14B shows an example using 1-4-5-5 data coding.

In FIGS. 14A and 14B, the upper side shows a time chart of data input and program execution for block writing, and the lower side shows a time chart of the period required to hold data in the write buffer. Note that, in order to simplify the explanation, FIGS. 14A and 14B show a case where the number of strings St in one block is one. When there are multiple strings St, the amount of data in the write buffer is required to be equal to the number of strings St.

In the case of a Foggy-Fine program with 4-3-4-4 data coding, the first stage, Foggy stage, involves inputting data for 4 pages and creating a program for these 4 pages (Foggy stage program). It will be done. In addition, in the case of a Foggy-Fine program with 4-3-4-4 data coding, even in the second stage, Fine stage, there is data input for 4 pages, and a program for these 4 pages (Fine stage program). will be carried out.

For each word line WL0, WL1, WL2, . . ., it is necessary to store four pages worth of data written in the Foggy stage in the write buffer until programming is started in the Fine stage.

In the Foggy-Fine program as well, data for four pages of Lower/Middle/Upper/Top are not written consecutively in order to reduce interference between adjacent memory cells. For example, after the Foggy stage is performed on the word line WL0, and before the Fine stage is performed on the word line WL0, the Foggy stage is performed on the word line WL1 adjacent to the word line WL0. Furthermore, after the Foggy stage is executed on the word line WL0 and before the Fine stage is executed on the word line WL1, the Foggy stage is executed on the word line WL2 adjacent to the word line WL1. In this method, it is necessary to hold data for four pages of Lower/Middle/Upper/Top in the write buffer until data input for the second and final Fine stage is completed. Furthermore, in order to reduce interference between adjacent memory cells, it is necessary to hold data on a plurality of word lines WLi in a write buffer. For example, when the Foggy stage is executed for word line WL2, three pages of data for word line WL1 and three pages of data for word line WL2 must be held in the write buffer. There is. Thus, in the case of a Foggy-Fine program with 4-3-4-4 data coding, a maximum of eight pages of data must be held in the write buffer.

As shown in FIG. 14B, the program of this embodiment uses, for example, a two-stage program with 1-4-5-5 data coding. In the program of this embodiment, in the 1st stage, data input for three pages (Lower page, Middle page, and Top page) and a program for these three pages (1st program) are performed. Further, in the case of the program of this embodiment, in the second stage, data input for two pages (Middle page and Upper page) and a program for one page of the Upper page (second program) are performed.

Then, for each word line WL0, WL1, WL2, etc., except for the middle page that is input in both stages, it is only necessary to store data in the write buffer when inputting data in each stage, and the program Once the write buffer is started, data may be deleted from within the write buffer. For example, when data is input in the 1st stage, this data is stored in the write buffer. Then, when the program is started in the 1st stage, the data of the Lower page and Top page stored in the write buffer may be deleted. Similarly, when data is input in the 2nd stage, this data is stored in the write buffer. Then, when the program is started in the 2nd stage, all data stored in the write buffer may be deleted. Therefore, in the case of the program of this embodiment, the data that needs to be held in the write buffer is at most 4 pages worth of data.

Also in the program of this embodiment, data for four pages of Lower/Middle/Upper/Top are not written consecutively in order to reduce interference between adjacent memory cells. For example, after the 1st stage is performed on the word line WL0, and before the 2nd stage is performed on the word line WL0, the 1st stage is performed on the word line WL1 adjacent to the word line WL0. Similarly, after the 1st stage to the word line WL1 is performed, and before the 2nd stage to the word line WL1 is performed, the 1st stage to the word line WL2 adjacent to the word line WL1 is performed.

In this manner, in this embodiment, the page data other than the Middle page is required only for one stage of the program, and therefore, once the data input is completed, the data in the write buffer can be discarded. Therefore, in this embodiment, the number of pages that need to be held simultaneously in the write buffer can be reduced.

Page data to be programmed into the non-volatile memory 3 is temporarily held in a write buffer in the RAM 6, and then input into the non-volatile memory 3 at the time of programming. In this embodiment, it is possible to reduce the required capacity of the RAM 6, thereby reducing costs.

Furthermore, when the Foggy-Fine program is used, all page data must be transferred twice, which increases the transfer time and requires additional power consumption during transfer. In this embodiment, page data other than the Middle page is completed by one data transfer for each page, so it is possible to reduce the transfer time and power consumption to approximately 1/2.

Here, page read processing will be explained. The method of reading a page differs depending on whether the word line WLi including the page to be read is programmed before or after writing in the 2nd stage.

Before 2nd stage writing, only the Lower page, Middle page, and Top page are valid recorded data. Therefore, the control unit 22 reads data from memory cells when the read page is the Lower page, Middle page, and Top page, but when the read page is other pages (specifically, the Upper page), the control unit 22 performs the memory cell read operation. is not performed, and control is performed to forcibly output all "1"s as read data.

On the other hand, in the case of the word line WLi that has completed up to the 2nd stage, the control unit 22 reads the memory cell regardless of whether the read page is Top/Upper/Middle/Lower page. In this case, since the required read voltage differs depending on which page is to be read, the control unit 22 executes only the necessary read according to the selected page.

The specific processing procedure for page reading will be described below. FIG. 15 is a flowchart showing a page read processing procedure for a word line for which programming has been completed up to the 1st stage (programming for the 2nd stage has not been completed) in the memory system 1 according to the first embodiment. According to the 1-4-5-5 data coding shown in FIG. 6, there is one boundary between the threshold states where the lower page data changes, so the control unit 22 controls two ranges separated by the boundary. The data is determined depending on where the threshold is located. For example, when the threshold voltage is lower than Vr8', the control unit 22 performs control to output "1" as data of the memory cell. On the other hand, when the threshold voltage is higher than Vr8', the control unit 22 performs control to output "0" as data of the memory cell.

Furthermore, since there are three boundaries between the threshold states where the data of the Middle page changes, the control unit 22 determines in which of the four ranges separated by those boundaries the threshold is located. Determine the data. Furthermore, since there are four boundaries between the threshold states where the data on the top page changes, the control unit 22 determines in which of the five ranges separated by those boundaries the threshold is located. Determine the data.

As shown in FIG. 15, in the case of the word line WLi before 2nd stage writing, the control unit 22 selects a read page (step S610). If the read page is the Lower page, the control unit 22 performs read with one read voltage (step S612). This voltage is Vr8, but as described above, in the case of the word line before 2nd stage writing, it may be Vr8', for example, with a margin between the read voltage and the threshold voltage, as shown in FIG. 8 (T2). . Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr8 (step S614).

Further, when the read page is the Middle page, the control unit 22 performs read using three read voltages (steps S616, S618, S620). As mentioned above, these voltages are Vr4, Vr9, and Vr14, but in the case of the word line before 2nd stage writing, for example, with a margin between the read voltage and the threshold voltage, as shown in FIG. Instead, Vr4', Vr9', and Vr14' may be used, respectively. Then, the control unit 22 determines the value of the read data based on the read result at the threshold voltage of Vr4, the read result at the threshold voltage of Vr9, and the read result at the threshold voltage of Vr14. is determined to be "0" or "1" (step S622).Here, as mentioned above, because the interval between the threshold distributions where the data of the Middle page differs is narrow and the read margin of the Middle page is narrow, , the reliability of the read data value may be extremely poor, and the Middle page data before 2nd stage writing may be defined as invalid.In that case, if the read page is the Middle page, the control unit 22 , control may be performed to forcibly output "1" as the output data of the memory cells.

Furthermore, when the read page is the Upper page, since the 1st program does not program the Upper page, the control unit 22 forcibly outputs "1" as all output data (step S624).

Further, when the read page is the top page, the control unit 22 performs read using four read voltages (steps S626, S628, S630, and S632). These voltages are Vr1, Vr4, Vr8, and Vr12 as described above, but in the case of the word line before 2nd stage writing, as shown in FIG. 8 (T2), with a margin between the read voltage and the threshold voltage, For example, they may be replaced with Vr1', Vr4', Vr8', and Vr12', respectively. The control unit 22 then calculates the read result at the threshold voltage of Vr1, the read result at the threshold voltage of Vr4, the read result at the threshold voltage of Vr8, and the read result at the threshold voltage of Vr12. Based on this, the value of the read data is determined to be "0" or "1" (step S634).

FIG. 16A is a flowchart illustrating a page read processing procedure for a word line for which programming has been completed up to the 2nd stage in the memory system 1 according to the first embodiment. In the case of the word line WLi for which programming has been completed up to the 2nd stage, the control unit 22 selects a read page (step S650). If the read page is the Lower page, the control unit 22 performs read at one threshold voltage of Vr8 (step S652). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at one threshold voltage of Vr8 (step S654).

Furthermore, when the read page is the Middle page, the control unit 22 performs read at the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (steps S656, S658, S660, and S662). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (step S664).

Further, when the read page is the Upper page, the control unit 22 performs read at the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (steps S666, S668, S670, S672, S674). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (step S676).

Further, when the read page is the top page, the control unit 22 performs read at the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12 (steps S678, S680, S682, S684, and S686). Then, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12 (step S688).

Note that the memory controller 2 can manage and identify whether the program for the word line WLi is before or after the completion of the 2nd stage write. In the memory system 1, the memory controller 2 controls the program, so if the memory controller 2 records its progress, the memory controller 2 can determine which addresses in the nonvolatile memory 3 are in what program state. You can easily see if there is one. In this case, when reading from the nonvolatile memory 3, the memory controller 2 identifies what kind of program state the word line WLi including the target page address is in, and issues a read command according to the identified state. . Another method is to provide a flag cell for each word line WLi, write the flag cell during the 2nd stage write, and manage and identify in the nonvolatile memory 3 whether it is before or after the completion of the 2nd stage write, depending on the data in the flag cell. is also possible.

A modified example of page read processing will be described below. The page read process according to the first modified example can be executed only after the second stage of the program to the word line WLi including the page to be read has been written. The page read process according to the first modified example is effective in that the read speed becomes faster when all data of the word line to be read is read.

Data coding suitable for page read processing according to a modified example is as shown in FIG. 16B, for example. A reading process according to a modified example in this data coding case will be described below. In the page read processing according to a modified example, all pages of Top/Upper/Middle/Lower pages are read.

FIG. 16C is a flowchart showing a read processing procedure according to a modified example. Further, FIG. 16D is a voltage waveform diagram of the selected word line, ReadyBusy signal line, and output data line. The control unit 22 sequentially performs reading using all 15 read voltages Vr15 to Vr1. First, as shown in FIG. 16D, reading is performed at the highest voltage Vr15 (step S690), and then reading is continued at lower read voltages one step at a time (steps S691 to S707). When the reading necessary to determine the read data of each page is completed, the read data of that page can be output.

In the page read process according to the first modification, when the data is sequentially read from Vr15 to Vr8 (step S699), the data of the lower page is determined, and this data can be output (step S700). In step S700, lower page data is determined based on the read data at read voltage Vr8.

Subsequently, when reading up to Vr4 is completed (step S702), the data of the Middle page is determined (step S703). In this step S703, the data of the Middle page is determined based on the read data at the read voltages Vr4, Vr9, Vr11, and Vr14.

Subsequently, when reading up to Vr2 is completed (step S705), the data of the Upper page is determined (step S706). In step S706, Upper page data is determined based on the read data at read voltages Vr2, Vr6, Vr10, Vr13, and Vr15.

Subsequently, when the reading up to Vr1 is completed (step S707), the data of the final top page is determined (step S708). In step S708, top page data is determined based on the read data at read voltages Vr1, Vr3, Vr5, Vr7, and Vr12.

In the page read processing according to the first variation, the latency until it becomes possible to output the data of any one page is longer, but the total time to read all four pages is the total time when reading one page at a time as explained earlier. It can be made shorter than As shown in FIG. 16D, it only takes one time to charge the word line from zero to the high voltage Vr15 in preparation for reading, and the amplitude of the voltage change when changing the read level to the next voltage is small and takes a short time. Since the voltage is stabilized at , the waiting time until the read voltage becomes stable can be shortened. Therefore, when reading with all the read voltages Vr15 to Vr1, the total transition time of the selected word lines becomes shorter, and as a result, the total read time can be increased.

Note that although the explanation has been given above using the data coding in FIG. 16B as an example, basically any data coding can be applied. However, since reading is performed by sequentially changing the read voltage from the maximum voltage to the minimum voltage, data can be output in the order of the pages for which reading of the voltage necessary to determine the data is completed. Therefore, it must be noted that depending on the data coding format, pages cannot be read in the order of Lower, Middle, Upper, and Top.

In this way, in the first embodiment, 1-4-5-5 data coding is adopted when programming the non-volatile memory 3 (a 4-bit/cell NAND memory with a three-dimensional structure or a two-dimensional structure). The program was divided into two stages. Since programming is performed in a two-stage system in this manner, the amount of data input during data programming in each stage is reduced, making it possible to suppress the amount of write buffer required for the memory controller 2. Furthermore, since the number of threshold boundaries in each page is uniform, it is possible to reduce the bias in the bit error rate between pages of the nonvolatile memory 3, and it is also possible to reduce the cost required for ECC. Further, since data is transferred only once for each page except for one page, transfer time and power consumption can be reduced.

Furthermore, since each program stage is executed while straddling the word line WLi, the amount of interference between adjacent cells with the adjacent word line WLi can be reduced. Furthermore, since 1-4-5-5 data coding is used, the amount of change in the threshold distribution in the 2nd program is small, making it possible to suppress the amount of interference between adjacent cells. In addition, by inputting data in both stages for the first page (specifically the Middle page), the IDL margin before the second stage can be expanded, making it possible to improve the reliability of the write sequence. Become. In addition, since 1-4-5-5 data coding is used, when programming the 1st stage, by setting one threshold boundary on the Lower page and two threshold boundaries on the Middle page, it is possible to program the 1st stage. In other words, it is possible to speed up the programs of the Lower page and Middle page. In addition, the speed of the 1st stage program can be increased by increasing the write voltage little by little when repeating write and write verify, and making the step voltage at the time of writing a larger value than when programming the 2nd stage. Can be done.

(Second embodiment)
Although the first embodiment has been described using 1-4-5-5 data coding as an example, various data coding modifications are possible. The hardware configuration of the memory system 1 according to the second embodiment is common to the memory system 1 according to the first embodiment. 17 to 25 show examples of data coding in the memory system 1 according to the second embodiment. The memory system 1 according to the second embodiment uses data coding other than 1-4-5-5 data coding.

FIG. 17 is a diagram showing an example of 1-5-4-5 data coding. In the example of FIG. 17, the maximum number of transitions in the threshold area at the end of the second program is three. Here, although the voltage distribution ranges of the threshold region at the time of completion of programming of the 1st stage and the threshold region of the threshold region at the time of completion of programming of the 2nd stage do not completely match, in this specification, for convenience, By associating each threshold region at the completion of the program with the threshold region at the completion of the 2nd stage program whose voltage distribution range is closest, the number of threshold regions that changed when the 2nd program was performed is changed. It's called a number. In the case of FIG. 17, in the 1st stage, the data of the Lower page, Middle page, and Upper page are input and the program is performed, and in the 2nd stage, the data of the Top page and the Middle page are input and the program is performed. The data of the Middle page is entered redundantly in the 1st stage and the 2nd stage. The interval between the two threshold areas that can be separated by the data value of the Middle page at the time of completion of the first stage program is narrower than the interval between the other threshold areas.

FIG. 18 is a diagram showing an example of 1-5-4-5 data coding. In the example of FIG. 18, the maximum number of transitions in the threshold area at the end of the second program is three. In the case of FIG. 18, in the 1st stage, the data of the Lower page, Middle page, and Upper page are input and the program is performed, and in the 2nd stage, the data of the Top page and the Upper page are input and the program is performed. The data of the Upper page is input redundantly in the 1st stage and the 2nd stage. The interval between the two threshold areas that can be separated by the data value of the Upper page at the time of completion of the 1st stage program is narrower than the interval between the other threshold areas.

FIG. 19 is a diagram showing an example of 3-5-2-5 data coding. In the example of FIG. 18, the maximum number of transitions in the threshold area at the end of the second program is three. In the case of FIG. 18, in the 1st stage, the data of the Lower page, Middle page, and Upper page are input and the program is performed, and in the 2nd stage, the data of the Top page and the Middle page are input and the program is performed. The data of the Middle page is entered redundantly in the 1st stage and the 2nd stage. The interval between the two threshold areas that can be separated by the data value of the Middle page at the time of completion of the first stage program is narrower than the interval between the other threshold areas.

FIG. 20 is a diagram showing an example of 3-3-4-5 data coding. In the example of FIG. 20, the maximum number of transitions in the threshold area at the end of the second program is three. In the case of FIG. 20, in the 1st stage, the data of the Lower page, Middle page, and Upper page are input and the program is performed, and in the 2nd stage, the data of the Top page and the Upper page are input and the program is performed.

FIG. 21 is a diagram showing an example of 2-3-5-5 data coding. In the example of FIG. 21, the maximum number of transitions in the threshold area at the end of the second program is five. In the case of FIG. 21, in the 1st stage, the data of the Lower page, Middle page, and Top page are input and the program is performed, and in the 2nd stage, the data of the Top page and the Upper page are input and the program is performed. Top page data is entered redundantly in the 1st stage and the 2nd stage. In the case of FIG. 21, when the 1st stage program is completed, the three threshold areas are the same regardless of whether the data on the top page is 0 or 1, and the total number of threshold areas is five. Therefore, the interval between each threshold area can be widened, and data can be read correctly at the time when the first stage program is completed.

FIG. 22 is a diagram showing an example of 3-2-5-5 data coding. In the example of FIG. 22, the maximum number of transitions in the threshold area at the end of the second program is five. In the case of FIG. 22, in the 1st stage, the data of the Lower page, Middle page, and Top page are input and the program is performed, and in the 2nd stage, the data of the Top page and the Upper page are input and the program is performed. Top page data is entered redundantly in the 1st stage and the 2nd stage. In the case of FIG. 22, when the 1st stage program is completed, the two threshold areas are the same whether the data on the top page is 0 or 1, and the total number of threshold areas is six.

FIG. 23 is a diagram showing an example of 3-4-4-4 data coding. In the example of FIG. 23, the maximum number of transitions in the threshold area at the end of the second program is seven. In the case of FIG. 23, in the 1st stage, the data of the Lower page, Middle page, and Upper page are input and the program is performed, and in the 2nd stage, the data of the Top page and the Upper page are input and the program is performed. The data of the Upper page is input redundantly in the 1st stage and the 2nd stage. The interval between the two threshold areas that can be separated by the data value of the Upper page at the time of completion of the 1st stage program is narrower than the interval between the other threshold areas.

FIG. 24 is a diagram showing an example of 3-4-4-4 data coding. In the example of FIG. 24, the maximum number of transitions in the threshold area at the end of the 2nd program is eight. In the case of FIG. 24, in the 1st stage, the data of the Lower page, Middle page, and Top page are input and the program is performed, and in the 2nd stage, the data of the Top page and the Upper page are input and the program is performed. Top page data is entered redundantly in the 1st stage and the 2nd stage. In the case of FIG. 24, when the 1st stage program is completed, the two threshold areas are the same whether the data on the top page is 0 or 1, and the total number of threshold areas is six.

17-24 are merely examples of data coding, and other data coding may be employed.

For example, in addition to FIGS. 17 to 20, the following FIGS. 25 to 27 exist in which the number of transitions in the threshold area becomes three at most at the end of the 2nd program. FIG. 25 is a diagram showing an example of 1-4-5-5 data coding. In the example of FIG. 25, six different threshold areas are generated when the first program is completed. Among these, the threshold area where the Middle page is 1 and the Lower page is 1, and the threshold area where the Middle page is 0 and the Lower page is 1 are the same whether the Top page is 0 or 1. . For this reason, originally eight threshold areas should be generated, but they are aggregated into six threshold areas.

FIG. 26 is a diagram showing an example of 2-5-3-5 data coding. In the example of FIG. 26, seven different threshold areas are generated when the first program is completed. Among these, the threshold area where the Middle page is 1 and the Lower page is 1 is the same threshold area whether the Top page is 0 or 1. For this reason, originally eight threshold areas should be generated, but they are aggregated into seven threshold areas.

FIG. 27 is a diagram showing an example of 3-4-5-3 data coding. In the example of FIG. 27, seven different threshold areas are generated when the first program is completed. Among these, the threshold area where the Middle page is 1 and the Lower page is 1 is the same threshold area whether the Top page is 0 or 1. For this reason, originally eight threshold areas should be generated, but they are aggregated into seven threshold areas.

Other examples of data coding are also possible. Below, diagrams showing code allocation for each data coding are listed. FIG. 28 shows an example of 3-2-5-5 data coding, FIG. 29 shows an example of 3-2-5-5 data coding, and FIG. 30 shows an example of 1-5-5-4 data coding. Further, FIG. 31 shows an example of 1-5-4-5 data coding, FIG. 32 shows an example of 1-4-5-5 data coding, and FIG. 33 shows an example of 1-5-3-6 data coding. . Further, FIG. 34 shows an example of 1-3-6-5 data coding, FIG. 35 shows an example of 1-2-6-6 data coding, and FIG. 36 shows an example of 1-2-6-6 data coding. .

Further, FIG. 37 shows an example of 1-2-6-6 data coding, FIG. 38 shows an example of 1-4-6-4 data coding, and FIG. 39 shows an example of 1-4-4-6 data coding. . Also, FIG. 40 shows an example of 1-4-6-4 data coding, FIG. 41 shows an example of 1-4-4-6 data coding, and FIG. 42 shows an example of 2-5-2-6 data coding. . Further, FIG. 43 shows an example of 2-5-2-6 data coding, FIG. 44 shows an example of 2-5-2-6 data coding, and FIG. 45 shows an example of 3-3-3-6 data coding. . Also, FIG. 46 shows an example of 3-3-6-3 data coding, FIG. 47 shows an example of 2-3-4-6 data coding, and FIG. 48 shows an example of 3-4-2-6 data coding. .

Further, FIG. 49 shows an example of 2-3-4-6 data coding, FIG. 50 shows an example of 3-2-6-4 data coding, and FIG. 51 shows an example of 3-2-4-6 data coding. . Further, FIG. 52 shows an example of 3-2-6-4 data coding, FIG. 53 shows an example of 3-4-2-6 data coding, and FIG. 54 shows an example of 3-2-4-6 data coding. . Further, FIG. 55 shows an example of 5-3-2-5 data coding, FIG. 56 shows an example of 3-5-2-5 data coding, and FIG. 57 shows an example of 3-2-5-5 data coding. . Further, FIG. 58 shows an example of 2-3-5-5 data coding, FIG. 59 shows an example of 2-3-5-5 data coding, and FIG. 60 shows an example of 2-3-5-5 data coding. .

Also, FIG. 61 shows an example of 5-4-2-4 data coding, FIG. 62 shows an example of 4-5-2-4 data coding, and FIG. 63 shows an example of 5-4-2-4 data coding. . Also, FIG. 64 shows an example of 2-4-5-4 data coding, FIG. 65 shows an example of 2-4-5-4 data coding, and FIG. 66 shows an example of 2-5-4-4 data coding. . Also, FIG. 67 shows an example of 2-5-4-4 data coding, FIG. 68 shows an example of 2-5-4-4 data coding, and FIG. 69 shows an example of 1-5-4-5 data coding. . Further, FIG. 70 shows an example of 1-4-5-5 data coding, FIG. 71 shows an example of 1-5-5-4 data coding, and FIG. 72 shows an example of 1-4-5-5 data coding. .

Further, FIG. 73 shows an example of 1-5-5-4 data coding, FIG. 74 shows an example of 1-5-4-5 data coding, and FIG. 75 shows an example of 1-5-5-4 data coding. . Also, FIG. 76 shows an example of 1-5-4-5 data coding, FIG. 77 shows an example of 1-4-5-5 data coding, and FIG. 78 shows an example of 1-4-5-5 data coding. . Further, FIG. 79 shows an example of 1-4-5-5 data coding, FIG. 80 shows an example of 1-4-5-5 data coding, and FIG. 81 shows an example of 3-5-4-3 data coding. . Further, FIG. 82 shows an example of 3-4-5-3 data coding, FIG. 83 shows an example of 3-5-3-4 data coding, and FIG. 84 shows an example of 3-4-3-5 data coding. .

Also, FIG. 85 shows an example of 3-4-5-3 data coding, FIG. 86 shows an example of 3-4-3-5 data coding, and FIG. 87 shows an example of 3-3-5-4 data coding. . Further, FIG. 88 shows an example of 3-3-5-4 data coding, FIG. 89 shows an example of 4-5-3-3 data coding, and FIG. 90 shows an example of 3-5-4-3 data coding. . Further, FIG. 91 shows an example of 3-4-5-3 data coding, FIG. 92 shows an example of 3-3-4-5 data coding, and FIG. 93 shows an example of 3-3-4-5 data coding. .

Further, FIG. 94 shows an example of 3-3-4-5 data coding, FIG. 95 shows an example of 3-4-5-3 data coding, and FIG. 96 shows an example of 3-3-5-4 data coding. . Also, FIG. 97 shows an example of 3-3-4-5 data coding, FIG. 98 shows an example of 4-3-4-4 data coding, and FIG. 99 shows an example of 3-4-4-4 data coding. . Also, FIG. 100 shows an example of 3-4-4-4 data coding, FIG. 101 shows an example of 4-3-4-4 data coding, and FIG. 102 shows an example of 3-4-4-4 data coding. . Further, Fig. 103 shows an example of 3-4-4-4 data coding, Fig. 104 shows an example of 3-4-4-4 data coding, and Fig. 105 shows an example of 3-4-4-4 data coding. . Further, FIG. 106 shows an example of 4-4-3-4 data coding, and FIG. 107 shows an example of 4-4-3-4 data coding.

In this way, by inputting the data of some pages redundantly in the 1st stage and the 2nd stage, and inputting the data of other pages only in either the 1st stage or the 2nd stage, you can program the cell. It is possible to reduce mutual interference between data and the write buffer, reduce the capacity of the write buffer, and suppress unevenness in the bit error rate when writing each bit data. In particular, in the case of 1-4-5-5, 1-5-4-5, 3-3-4-5, or 3-5-2-5 data coding, the number of boundaries of each page data is uniform; In addition, since the number of transitions in the threshold region during programming of the 2nd stage is 3 or less, it is possible to suppress bias in the bit error rate and to reduce mutual interference between cells.

(Third embodiment)
The memory system 1 according to the third embodiment reduces the write buffer capacity more than the first and second embodiments.

The hardware configuration of the memory system 1 according to the third embodiment is common to the memory system 1 according to the first and second embodiments. In the third embodiment, page data that is input in the 2nd stage program overlappingly with the 1st stage program is continued to be held in the page buffer 24 inside the nonvolatile memory 3 after the 1st stage program is started. As a result, in the 2nd stage program, it is possible to omit the data input procedure for that page and to input data for all pages only once. This allows the capacity of the write buffer to be reduced.

Furthermore, in this embodiment, the 2nd stage programming of the word line WLn-1 and the 1st stage programming of the word line WLn are performed together. In this way, the page buffer 24 stores data of bits that are input redundantly in the 1st stage program and the 2nd stage program among the 1st to 4th bits (Lower page, Middle page, Upper page, Top page). is stored before starting the 1st stage program, and can be discarded or invalidated after starting the 2nd stage program. Hereinafter, an example will be described in which the same 1-4-5-5 data coding as that described in FIG. 6 of the first embodiment is used in this embodiment as well.

In the program flowchart shown in FIG. 9, the execution timings of the 1st stage program and the 2nd stage program are shifted, and respective program commands and program data are input during each program. In contrast, in this embodiment, program commands and program data input for the 1st stage and 2nd stage are performed together as much as possible.

For example, as shown in FIG. 8B, the programs of the 1st stage of word line WLn and the 2nd stage of word line WLn-1 are always continuous except at the beginning and end of the block. Therefore, in this embodiment, this part is treated as a single command input. That is, by inputting a command once, each program data of the Lower page, Middle page, and Top page of the word line WLn and the Upper page of the word line WLn-1 are input all at once. Even if Foggy-Fine is adopted, data for Lower/Middle/Upper/Top pages can be input for 4 pages (in this case, pages within the same word line WLi) with one program command. This is the same amount of data input as was previously used.

By consolidating the input of program commands and program data in this way, the frequency of command input and polling (regular checking whether the chip busy state has returned to ready) in the control performed by the memory controller 2 is reduced. It is possible to speed up the memory system 1 and simplify control.

Here, an example of a write procedure according to the program order according to the third embodiment will be explained using FIGS. 108 and 109. FIGS. 108 and 109 show the write procedure when the program order shown in FIG. 8B is followed.

FIG. 108 is a flowchart showing the entire writing procedure for one block according to the third embodiment. It is assumed here that one block has n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). As shown in FIG. 108, when writing is started (step S710), the 1st stage program of the word line WL0 of strings St0 to St3 is processed (step S712). Thereby, the control unit 22 executes the 1st stage program of the word line WL0 of the strings St0 to St3 (step S714).

Further, the control unit 22 executes a 1st stage program for the string St0_word line WL1 and a 2nd stage program for the string St0_word line WL0 (step S716).

Next, the control unit 22 executes the 1st stage program of the string St1_word line WL1 and the 2nd stage program of the string St1_word line WL0 (step S718). Next, the control unit 22 executes a 1st stage program for the string St2_word line WL1 and a 2nd stage program for the string St2_word line WL0 (step S720). Thereafter, the control unit 22 repeats the same process for each word line WLi of each string.

Next, the 1st stage programming of the string St0_word line WLn and the 2nd stage programming of the string St0_word line WLn-1 are performed (step S722). Next, the control unit 22 executes a 1st stage program for the string St1_word line WLn and a 2nd stage program for the string St1_word line WLn-1 (step S724). Thereafter, the control unit 22 repeats the same process for each word line WLi of each string.

Next, the control unit 22 executes a 1st stage program for the string St3_word line WLn and a 2nd stage program for the string St3_word line WLn-1 (step S726). Next, the control unit 22 executes the 2nd stage program for the word lines WLn of the strings St0 to St3 (steps S728, S730, S732).

In this way, at the beginning of the block, a program for only the 1st stage is executed as in the first embodiment, and at the end of the block, a program for only the 2nd stage is executed as in the first embodiment. In this case, the program for only the 1st stage is executed according to the procedure shown in FIG. 8B, and the program for only the 2nd stage is executed according to the procedure shown in FIG. 8C. In addition, in the flowchart of FIG. 108, the 1st stage program of the word line WLn and the 2nd stage program of the word line WLn-1 are performed together except at the beginning and end of the block. This reduces the frequency of command input and polling performed by the memory controller 2, and speeds up the processing of the memory system 1.

FIG. 109 is a flowchart showing the write procedure in the 1st stage and the 2nd stage according to the third embodiment. As shown in FIG. 109, in the 1st stage and 2nd stage programs, after the 1st stage program is executed, the 2nd stage program is executed. Specifically, first, a command to start inputting data of the Upper page of word line WLn-1 is input from the memory controller 2 to the nonvolatile memory 3 (step S750). Then, the data of the Upper page of the word line WLn-1 is input from the memory controller 2 to the nonvolatile memory 3 (step S752).

Next, a command to start inputting data of the lower page of word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S754). Then, the data of the lower page of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S756).

Next, a command to start inputting data of the Middle page of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S758). Then, the data of the Middle page of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S760). The middle page data is not only input to the nonvolatile memory 3 but also stored in the page buffer 24. After being stored in the page buffer 24, the Middle data in the write buffer can be discarded or invalidated.

Next, a command to start inputting data of the top page of word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S762). Then, the data of the top page of the word line WLn is input from the memory controller 2 to the nonvolatile memory 3 (step S764).

Next, program execution commands for the 1st stage and 2nd stage are input from the memory controller 2 to the nonvolatile memory 3 (step S766), and the chip becomes busy (step S768).

After this, one to a plurality of program voltage pulses are applied to the Lower page, Middle page, and Top page of the word line WLn (step S770). Then, in order to check whether the memory cell has moved beyond the threshold boundary level, data is read from the Lower page and Top page of the word line WLn (step S772).

Furthermore, it is checked whether the number of fail bits of the data in the Lower page and the Top page is smaller than the criteria (step S774). If the number of fail bits of data in the Lower page and Top page is equal to or greater than the criterion, the processes of steps S770 to S774 are repeated. Then, when the number of data fail bits becomes smaller than the criterion, the Lower page and Top page data of word line WLn-1 are read out (step S776).

Then, the threshold voltage Vth of the Upper page program destination is determined based on the Lower and Top page data of the word line WLn-1 and the Middle page data read from the page buffer 24 (step S778). ). Thereafter, data is written to the Upper page of word line WLn-1 using the determined threshold voltage Vth (step S780).

When writing data to the Upper page, one to a plurality of program voltage pulses are applied to the Upper page of word line WLn-1. Then, in order to check whether the memory cell has moved beyond the threshold boundary level, data is read from the Upper page of word line WLn-1 (step S782).

Furthermore, verification is performed to check whether the number of fail bits of data in the Upper page is smaller than the criteria (step S784). If the number of data fail bits in the Upper page is equal to or greater than the criterion, the program voltage pulse application, data read, and verify processing are repeated. Then, when the number of fail bits of the data becomes smaller than the criterion, the chip becomes ready (step S786).

Note that in the 1st stage program for the same word line, the order of the pages in the data input start command and data input processing for a plurality of pages is arbitrary, and any page may be input first. Furthermore, in the 2nd stage program for the same word line, the order of pages in data input start command and data input processing for a plurality of pages is also arbitrary. However, the respective word line numbers and the processing order of the two stage programs must be in the order shown in FIG. 109.

In this manner, in FIG. 109, a case has been described in which the 1st stage program of the word line WLn is executed before the 2nd stage program of the word line WLn-1. This is because the programming of the 1st stage of word line WLn is performed first, so that the cell of word line WLn-1 to which the 16-value threshold voltage Vth is written is not affected by the adjacent cell. be.

As described above, in this embodiment, data for four pages, including the data of the Upper page of word line WLn-1, and the data of the Lower page, Middle page, and Top page of word line WLn, are input continuously. .

As another modification, after inputting a program command, the data of the Lower page, Middle page, and Top page of word line WLn-1 are first read as IDL, and then the data of the Lower page, Middle page, and Top page of word line WLn-1 are read as IDL. Page and Top page are programmed, and then the threshold voltage Vth of the program destination of the Upper page of the word line WLn-1 is determined, and the determined threshold voltage Vth is used for the Upper page of the word line WLn-1. You can also run the program. In this way, data in the Lower page, Middle page, and Top page of the IDL word line WLn-1 can be read before interference occurs between adjacent cells due to writing on the word line WLn.

Note that in this embodiment, the actual order of execution of the program based on a batch of commands for the 1st stage of the word line WLn and the 2nd stage of the word line WLn-1 can be modified. That is, the programming of the Lower page, Middle page, and Top page of the word line WLn shown in FIG. Often, they can be replaced. By reading the data of the Lower page, Middle page, and Top page of word line WLn-1 before programming the Lower page, Middle page, and Top page of word line WLn, the Lower page, Middle page of word line WLn IDL is possible without being affected by the top page program.

In this way, in the third embodiment, the 2nd stage programming of the word line WLn-1 and the 1st stage programming of the word line WLn are performed at the same time, so the frequency of command input and polling is reduced. Therefore, the speed of the memory system 1 can be increased and the control can be simplified.

FIG. 110 is a diagram for explaining the write buffer amount (buffer data amount) in the program of the third embodiment. In this embodiment, a two-stage program with 1-4-5-5 data coding is used. In the program of this embodiment, in the 1st stage, data input for three pages (Lower page, Middle page, and Top page) and a program for these three pages (1st program) are performed. Furthermore, in the case of the program of this embodiment, in the second stage, data input for one page (upper page) and a program for one page of the upper page (second program) are performed.

Then, for each word line WL0, WL1, WL2, etc., data can be stored in the write buffer when inputting data at each stage, and when the program is started, the data is stored in the write buffer. May be deleted. For example, when data is input in the 1st stage, this data is stored in the write buffer. Then, when the program is started in the 1st stage, the data of the Lower page, Top page, and Middle page stored in the write buffer may be deleted. However, since the data of the Middle page is also used in the 2nd stage, it is necessary to store it in the page buffer 24 until the 2nd stage program is started. Similarly, when data is input in the 2nd stage, this data is stored in the write buffer. Then, when the program is started in the 2nd stage, all data stored in the write buffer may be deleted. Therefore, in the case of the program of this embodiment, the data that needs to be held in the write buffer is three pages worth of data at most, which is even less than the first embodiment.

Also in the program of this embodiment, data for four pages of Lower/Middle/Upper/Top are not written consecutively in order to reduce interference between adjacent memory cells. For example, after the 1st stage is performed on the word line WL0, and before the 2nd stage is performed on the word line WL0, the 1st stage is performed on the word line WL1 adjacent to the word line WL0. Similarly, after the 1st stage to the word line WL1 is performed, and before the 2nd stage to the word line WL1 is performed, the 1st stage to the word line WL2 adjacent to the word line WL1 is performed.

In this manner, in this embodiment, all page data is needed only for one stage of programming, so once the data input is completed, the data in the write buffer can be discarded. Therefore, in this embodiment, the number of pages that need to be simultaneously held in the write buffer is even smaller than in the first embodiment.

Page data to be programmed into the non-volatile memory 3 is temporarily held in a write buffer in the RAM 6, and then input into the non-volatile memory 3 at the time of programming. In this embodiment, it is possible to reduce the required capacity of the RAM 6, resulting in cost reduction.

In addition, in this embodiment, each page is completed with one data transfer, so the time required to transfer page data is shorter than in the first embodiment, and it is possible to reduce power consumption during transfer. .

The page read processing in this embodiment is the same as the processing procedure described in the first embodiment, so the explanation will be omitted.

Note that in this embodiment, it is necessary to increase the page buffer 24 inside the NAND flash memory in order to store new page data. When programming a NAND flash memory in which one string exists in a block as shown in FIG. 8A, the amount of page buffer 24 that needs to be increased is one page of data. On the other hand, in a NAND flash memory program where four strings exist in a block as shown in FIG. 8B or FIG. 8C, the amount of page buffer 24 that needs to be increased is four pages of data. This means that after executing the 1st stage program for one string, and before executing the 2nd stage program for the same string, the 1st stage programs for the other three strings must be executed, and in the end, This is because it is necessary to hold one page worth of data for each of all four strings.

Although this embodiment has been explained using 1-4-5-5 data coding as an example, it is possible to make various modifications to the data coding, and it is possible to realize the embodiment described above. it is obvious.

In the first to third embodiments described above, the case where the nonvolatile memory 3 is configured using the NAND memory 5 has been described. ), PRAM (Phase Change Random Access Memory), FeRAM (Ferroeletric Random Access Memory), and other types of nonvolatile memory 3 may be used.

In the first to third embodiments described above, the case where the 1st stage program writes 3 pages of data and the 2nd stage program writes 2 pages of data is explained. You may change the number of pages and the distribution of the number of pages in the 2nd stage program. For example, the first stage program may write two pages of data, and the second stage program may write three pages of data.

Although several embodiments of the present disclosure have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

1 memory system, 2 memory controller, 3 nonvolatile memory, 4 host processor, 5 NAND memory, 6 RAM, 7 ROM, 8 processor, 9 host interface, 10 ECC circuit, 11 memory interface, 12 internal bus, 21 NAND I/O Interface, 22 Control unit, 23 NAND memory cell array, 24 Page buffer, 31 Oscillator, 32 Sequencer, 33 Command user interface, 34 Voltage supply unit, 35 Column counter, 36 Serial access controller, 37 Row decoder, 38 Sense amplifier, 41p type well region, 42, 43, 44 wiring layer, 45 memory hole, 46 block insulating film, 47 charge storage layer, 48 gate insulating film, 49 conductive film

Claims (13)

Each has a first threshold area indicating an erased state in which data is erased, and second to sixteenth threshold areas indicating a written state in which data is written at a voltage level higher than the first threshold area. a non-volatile memory having a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by 16 threshold regions including a threshold region;
After causing the nonvolatile memory to execute a first program for writing the data of the first bit, the second bit, and the fourth bit, a second program for writing the data of the third bit is executed for the nonvolatile memory. memory controller,
Equipped with
The number of first boundaries used to determine the value of the first bit data among the 15 boundaries existing between adjacent threshold areas among the first to 16th threshold areas; the number of second boundaries used to determine the value of the second bit data; the number of third boundaries used to determine the value of the third bit data; and the determination of the value of the fourth bit data. The maximum value of the number of fourth boundaries used for is 5, the second largest value is 4,
The memory controller is configured such that a threshold region in the memory cell has a seventeenth threshold value indicating an erased state in which data is erased according to data of the first bit, the second bit, and the fourth bit. area and the 18th to 24th threshold areas, which indicate a write state in which data is written and whose voltage level is higher than the 17th threshold area. The memory controller is configured to cause the nonvolatile memory to perform one program, and the memory controller is configured to set the threshold area of the memory cell to the seventeenth to twenty-fourth threshold values according to the data of the third bit. The second program is configured to change from one of the threshold areas to one of the two threshold areas among the first to sixteenth threshold areas. configured to cause the non-volatile memory to perform;
The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level among the two threshold regions is 2 or less,
The memory system is configured such that the memory controller inputs the second bit data and the third bit data to the nonvolatile memory when causing the nonvolatile memory to execute the second program. . The memory controller determines the number of boundaries in which the value of the first bit differs among 15 boundaries existing between adjacent threshold areas among the first to sixteenth threshold areas; The number of boundaries where the value of the second bit differs, the number of boundaries where the value of the third bit differs, and the number of boundaries where the value of the fourth bit differs are (1, 4, 5, 5), ( 1, 5, 4, 5) or (3, 3, 4, 5) in the nonvolatile memory. Each has a first threshold area indicating an erased state in which data is erased, and second to sixteenth threshold areas indicating a written state in which data is written at a voltage level higher than the first threshold area. a non-volatile memory having a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by 16 threshold regions including a threshold region;
After causing the nonvolatile memory to execute a first program for writing the data of the first bit, the second bit, and the fourth bit, a second program for writing the data of the third bit is executed for the nonvolatile memory. memory controller,
Equipped with
The number of first boundaries used to determine the value of the first bit data among the 15 boundaries existing between adjacent threshold areas among the first to 16th threshold areas; the number of second boundaries used to determine the value of the second bit data; the number of third boundaries used to determine the value of the third bit data; and the determination of the value of the fourth bit data. The number of fourth boundaries used for is (3, 5, 2, 5) in order,
The memory controller is configured such that a threshold region in the memory cell has a seventeenth threshold value indicating an erased state in which data is erased according to data of the first bit, the second bit, and the fourth bit. area and the 18th to 24th threshold areas, which indicate a write state in which data is written and whose voltage level is higher than the 17th threshold area. The memory controller is configured to cause the nonvolatile memory to perform one program, and the memory controller is configured to set the threshold area of the memory cell to the seventeenth to twenty-fourth threshold values according to the data of the third bit. The second program is configured to change from one of the threshold areas to one of the two threshold areas among the first to sixteenth threshold areas. configured to cause the non-volatile memory to perform;
The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level among the two threshold regions is 2 or less,
The memory system is configured such that the memory controller inputs the second bit data and the third bit data to the nonvolatile memory when causing the nonvolatile memory to execute the second program. . The memory controller is configured such that a difference in voltage level between two threshold regions having different values of the data of the second bit among the seventeenth to twenty-fourth threshold regions is determined by smaller than the difference in voltage level between two threshold regions having different values, and smaller than the difference in voltage level between two threshold regions having different values of the fourth bit data. The memory system according to any one of claims 1 to 3, wherein the first program is executed in the nonvolatile memory. The memory controller is configured to set the data of the third bit to the two threshold areas in a manner that is larger than the interval between the two threshold areas during the first programming in which the values of the data of the second bit are different. 5. The memory according to claim 4, wherein the second program is performed on the non-volatile memory so that intervals between adjacent threshold regions among four threshold regions obtained by performing the second program are widened. system. The first bit is the least significant Lower bit, the second bit is the second smallest Middle bit, the third bit is the second largest Upper bit, and the fourth bit is the most significant Top bit. 6. The memory system according to any one of 1 to 5. comprising a volatile first storage section that stores the first to fourth bit data;
Among the first to fourth bits stored in the first storage unit, bit data that is input redundantly during the first program and the second program is discarded after the second program is started. 7. The memory system according to claim 1, wherein data of other bits can be discarded or invalidated after starting the first program. a volatile first storage unit that stores the first to fourth bit data;
a non-volatile second storage unit that stores data of bits that are input redundantly in the first program and the second program among the first to fourth bits;
The data of the first to fourth bits stored in the first storage unit can be discarded or invalidated after starting the first program,
Among the first to fourth bits stored in the second storage unit, bit data that is input redundantly in the first program and the second program is stored in the first program before starting the first program. The memory system according to any one of claims 1 to 6, wherein the memory system is stored in a second storage unit and can be discarded or invalidated after starting the second program. 9. The memory system according to claim 8, wherein the second storage section is provided in units of word lines. The plurality of memory cells in the nonvolatile memory include a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line adjacent to the first word line. having a cell;
The memory controller causes the plurality of first memory cells to perform the first programming, and then causes the plurality of second memory cells to perform the first programming, and then causes the plurality of first memory cells to perform the first programming. The memory system according to any one of claims 1 to 9, wherein the second programming is performed on memory cells. The nonvolatile memory has at least a first word line and a second word line to which two or more of the memory cells are connected,
The memory controller executes consecutive executions of the first program for memory cells connected to the first word line and the second program for memory cells connected to the second word line, using consecutive commands and commands. 10. A memory system according to any preceding claim, wherein the non-volatile memory is instructed by a data input. The non-volatile memory stores data obtained by reading data programmed by the first program, data of the second bit that is input redundantly in the first program and the second program, and the second bit data. 12. Any one of claims 1 to 11, further comprising a control unit that determines a threshold voltage of the data of the bit programmed in the second program based on the input data of the third bit programmed in the program. Memory system as described in Section. comprising an error correction unit that reads data programmed by the first program and performs error correction;
The control unit adjusts the bit data programmed by the second program based on the data after error correction by the error correction unit, the second bit data, and the third bit input data. 13. The memory system of claim 12, determining a threshold voltage.

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