TW202331729A - memory system - Google Patents

Abstract

An embodiment of the invention provides a memory system capable of avoiding the mutual interference between cells to reduce the capacity of writing in a buffer, and suppressing bias of a bit error rate. In the memory system of the embodiment, a memory controller in the memory system is configured to enable a nonvolatile memory to execute a first programming such that a threshold region in the memory cell becomes any threshold region of a seventeenth threshold region indicating an erased state in which data is erased and eighteenth to twenty-fourth threshold regions having a higher voltage level than that of the seventeenth threshold region and indicating a written state in which data is written according to the data of the first bit, the second bit, and the fourth bit, and configured to allow the nonvolatile memory to execute a second programming such that the threshold region in the memory cell becomes any threshold region in two threshold regions among the first to sixteenth threshold regions from any threshold region of the seventeenth to twenty-fourth threshold regions according to the data of the third bit. When driving the nonvolatile memory to execute the second programing, the memory controller is configured to input the data of the second bit and the data of the third bit to the nonvolatile memory.

Description

memory system

The embodiments disclosed herein relate to memory systems. [Related Application]

This application enjoys the priority of the basic application of Japanese Patent Application No. 2019-210823 (filing date: November 21, 2019) and Japanese Patent Application No. 2020-113206 (filing date: June 30, 2020) . This application includes all the contents of the basic application by referring to these basic applications.

In NAND flash memory, generally speaking, multi-value data composed of complex bits is written to the memory cell, and TLC that writes multi-valued data composed of 3 bits to the memory cell (Triple Level Cell) technology is put into practical use. In the future, it can be expected that the QLC (Quadruple Level Cell) technology for writing multi-valued data composed of 4 bits will become the mainstream.

In QLC, in order to avoid mutual interference between cells, it is reviewed that "after writing 4-bit data into the first memory cell at the same time, write 4-bit data into the adjacent cells at the same time. , and then rewrite the 4-bit data simultaneously to the first memory cell again. However, in this method, it is necessary to keep the 4-bit data in the write buffer in the memory controller in advance until the end of rewriting.

In recent years, the NAND memory system has been three-dimensionalized, and the memory capacity of the necessary write buffer is increased, and there is a problem that the cost of the memory controller with a built-in write buffer becomes high. Therefore, in the 3-dimensional non-volatile memory, it is also necessary to review the countermeasures for reducing the write buffer amount of the memory controller.

As a countermeasure to avoid mutual interference between cells and simultaneously reduce the write buffer amount of the memory controller, it is well known that when writing the data of each bit to the memory cell, by dividing it into two Write in stages, and become a method that does not need to rewrite all the bit data.

However, in this method, there is a problem that the bit error rate when writing each bit of metadata to the memory cell is highly biased.

In order to improve the reliability of QLC technology, it is necessary to avoid mutual interference between cells and reduce the capacity of the write buffer in the memory controller, and also to bias the bit error rate when writing each bit of data Inhibited memory system.

In one aspect of the present disclosure, a method is provided that can avoid inter-cell interference and reduce the capacity of the write buffer in the memory controller and also prevent bit errors when writing bit data. Rate bias acts as a suppressed memory system.

According to this embodiment, a memory system is provided, which has: a non-volatile memory with a plurality of memory cells, and the plurality of memory cells are respectively passed through 16 thresholds area, and can store 4-bit data represented by the 1st to 4th bits, the 16 threshold value areas include the first threshold representing the deletion status of the data being deleted The value area, and the voltage level are higher than the first threshold area and represent the 2nd to 16th threshold areas of the writing state in which the data has been written; and

The memory controller makes the aforementioned non-volatile memory after the first programming of writing the data of the aforementioned 1st bit, the aforementioned 2nd bit, and the aforementioned 4th bit into the aforementioned non-volatile memory. The non-volatile memory performs the second programming of writing the data of the aforementioned third bit,

Among the 15 boundaries existing between the adjacent threshold value areas in the aforementioned 1st to 16th threshold value areas, the first boundary used in the determination of the value of the aforementioned 1st bit data The number of the second boundary used in the determination of the value of the second bit data, the number of the third boundary used in the determination of the value of the third bit data, the number of the third boundary used in the The number of the 4th boundary in the determination of the value of the data of the 4th bit above, the maximum value of these numbers is 5, and the second largest value is 4,

The aforementioned memory controller is configured so that the threshold value area in the aforementioned memory cell will become representative data corresponding to the data of the aforementioned 1st bit, the aforementioned 2nd bit, and the aforementioned 4th bit. The 17th threshold area and the voltage level of the erased state are higher than the aforementioned 17th threshold area and represent the 18th to 24th thresholds of the written state in which data has been written. One of the threshold areas of the areas is used to make the aforementioned non-volatile memory carry out the aforementioned first programming,

The aforementioned memory controller is configured such that the threshold value area in the aforementioned memory cell changes from any one of the aforementioned 17th to 24th threshold value areas in response to the aforementioned 3rd bit data. The threshold value area becomes the threshold value area of any one of the two threshold value areas in the aforementioned first to sixteenth threshold area areas, so that the aforementioned non-volatile memory performs the aforementioned second stylized,

The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level in the aforementioned two threshold regions shall be within 2,

The aforementioned memory controller, when performing the second programming of the aforementioned non-volatile memory, is configured to transfer the aforementioned second-bit data and the aforementioned third-bit data to the aforementioned non-volatile memory for input.

FIG. 1 is a block diagram showing a schematic configuration of a memory system 1 according to the first embodiment. The memory system 1 in FIG. 1 is equipped with a memory controller 2 and a non-volatile memory 3 . The memory system 1 in FIG. 1 can be connected to a host processor (hereinafter simply referred to as a host) 4 . The host 4 is, for example, an electronic device such as a personal computer or a portable terminal.

The non-volatile memory 3 is a memory that stores data in a non-volatile manner, for example, it includes a NAND flash memory (hereinafter also referred to as a NAND memory) 5 . In this embodiment, the non-volatile memory 3 is a 4bit/Cell (QLC: Quad Level Cell) NAND with memory cells capable of storing 4-bit data at each memory cell. An example of memory 5 is used for illustration. The non-volatile memory 3 according to this embodiment has a three-dimensional structure in which memory cells are layered three-dimensionally. The non-volatile memory 3 has a plurality of memory cells, and the plurality of memory cells are capable of memorizing the performance of the 1st to 4th bits through 16 threshold areas respectively. For 4-bit data, the 16 threshold areas include the first threshold area representing the deletion status of the data being deleted, and the voltage level is higher than the first threshold area It also represents the 2nd to 16th threshold value areas of the writing state where the data has been written. For example, the first bit is the lowest bit of Lower, the aforementioned second bit is the second smallest Middle bit, and the aforementioned third bit is the second largest Upper bit , the aforementioned 4th bit is the top bit of the body.

The memory controller 2 controls the writing of data in the non-volatile memory 3 according to the writing command from the host computer 4 . Also, the memory controller 2 controls the reading of data from the non-volatile memory 3 in accordance with the read command from the host computer 4 . The memory controller 2 is provided with a RAM (Random Access Memory) 6, a ROM (Read Only Memory) 7, a processor 8, a host interface 9, an ECC (Error Check and Correct) circuit 10 and a memory interface 11. The RAM 6 , the processor 8 , the host interface 9 , the ECC circuit 10 and the memory interface 11 are connected through a common internal bus 12 .

As will be described later, the memory controller 2 of the present embodiment is the first program for writing the data of the first bit, the second bit, and the fourth bit in the non-volatile memory 3 Afterwards, the second programming of writing the data of the third bit is performed on the non-volatile memory 3 . Among the 15 boundaries existing between the adjacent threshold value areas in the 1st to 16th threshold value areas, the number of the first boundaries used in the determination of the value of the data of the first bit , the number of the second boundary used in the determination of the value of the data of the second bit, the number of the third boundary used in the determination of the value of the data of the third bit, and the number of the third boundary used in the fourth bit For the number of the fourth boundary in the determination of the value of the data, the largest value among these numbers is 5, and the second largest value is 4. The memory controller 2 is configured so that the threshold value area in the memory cell will correspond to the data of the first bit, the second bit, and the fourth bit to represent data that has been deleted The 17th threshold area of the erase state and the voltage level are higher than the 17th threshold area and represent one of the 18th to 24th threshold areas of the writing state in which data has been written The non-volatile memory 3 is first programmed in the manner of the threshold value area. The memory controller 2 is configured so that the threshold value area in the memory cell will be changed from the threshold value of any one of the 17th to the 24th threshold value area in response to the data of the 3rd bit The second programming of the non-volatile memory 3 is performed in such a manner that the area becomes one of the two threshold areas of the first to sixteenth threshold areas. The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level located in the two threshold regions is within two. The memory controller 2 is configured to input the second-bit data and the third-bit data to the non-volatile memory 3 when performing the second programming on the non-volatile memory 3 .

More specifically, the memory controller 2 is configured to make the adjacent threshold areas in 15 boundaries among the 16 threshold areas (1st to 16th threshold areas) Between, the value of the first bit is the number of different boundaries, the value of the second bit is the number of different boundaries, the value of the third bit is the number of different boundaries, and the fourth bit The value of the value is the number of different boundaries, and the order becomes (1, 4, 5, 5), (1, 5, 4, 5) or (3, 3, 4, 5) in order to make the non-volatile Sexual memory undergoes 1st stylization and 2nd stylization.

Or, the memory controller 2 of this embodiment is after the first programming of writing the data of the first bit, the second bit, and the fourth bit into the non-volatile memory 3 , making the non-volatile memory 3 carry out the second programming of writing the data of the third bit. Among the 15 boundaries existing between the adjacent threshold value areas in the 1st to 16th threshold value areas, the number of the first boundaries used in the determination of the value of the data of the first bit , the number of the second boundary used in the determination of the value of the data of the second bit, the number of the third boundary used in the determination of the value of the data of the third bit, and the number of the third boundary used in the fourth bit The number of the fourth boundary in the determination of the value of the data is (3, 5, 2, 5) in sequence. The memory controller 2 is configured so that the threshold value area in the memory cell will correspond to the data of the first bit, the second bit, and the fourth bit to represent data that has been deleted The 17th threshold area of the erase state and the voltage level are higher than the 17th threshold area and represent one of the 18th to 24th threshold areas of the writing state in which data has been written The non-volatile memory 3 is first programmed in the manner of the threshold value area. The memory controller 2 is configured so that the threshold value area in the memory cell will be changed from the threshold value of any one of the 17th to the 24th threshold value area in response to the data of the 3rd bit The second programming of the non-volatile memory 3 is performed in such a manner that the area becomes one of the two threshold areas of the first to sixteenth threshold areas. The number of threshold regions between the threshold region with the lowest voltage level and the threshold region with the highest voltage level located in the two threshold regions is within two. The memory controller 2 is configured to input the second-bit data and the third-bit data to the non-volatile memory 3 when performing the second programming on the non-volatile memory 3 .

The memory controller 2 can also use the voltage level difference between the two threshold areas that make the value of the second bit data in the 17th to 24th threshold areas to be different The voltage level difference between the two threshold areas that are different from the data value of the first bit becomes smaller and becomes two different values than the data value of the fourth bit The non-volatile memory is first programmed in such a way that the voltage level difference between the threshold regions is smaller.

Or, the memory controller 2 can also use the interval between the 2 threshold areas when the value of the data of the 2nd bit is different compared with the value of the 2nd bit, so that for There are 2 threshold value regions and the method that the distance between the adjacent threshold value regions among the 4 threshold value regions obtained by performing the second programming with the data of the third bit becomes wider , to program the second non-volatile memory.

The host interface 9 outputs the command received from the host 4, user data (write data), etc. to the internal bus 12. Also, the host interface 9 transmits the user data read from the non-volatile memory 3 or the response from the processor 8 to the host 4.

The memory interface 11 is based on the instructions of the processor 8, and performs the processing of writing user data and the like to the non-volatile memory 3 and the processing of reading the user data from the non-volatile memory 3 control.

The processor 8 performs overall control over the memory controller 2 . The processor 8 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), and the like. When the processor 8 receives a command from the host 4 via the host interface 9, it performs control in accordance with the command. For example, the processor 8 follows the instructions from the host computer 4 and gives instructions to the memory interface 11 to write the user data and parity check codes of the non-volatile memory 3 . Furthermore, the processor 8 follows the instruction from the host computer 4, and instructs the memory interface 11 to read user data and parity check codes from the non-volatile memory 3.

User data is stored in RAM 6 via internal bus 12 . The processor 8 determines a storage area (memory area) on the non-volatile memory 3 for user data stored in the RAM 6 . The processor 8 determines the memory area on the non-volatile memory 3 for the data (page data) of the page unit which is a writing unit. In this specification, user data stored in one page of the non-volatile memory 3 is defined as unit data. The unit data is generally coded and stored in the non-volatile memory 3 as a code word, but the code is not necessary. The memory controller 2 may also store the unit data in the non-volatile memory 3 without encoding. However, in FIG. 1 , as one example of the configuration, the configuration for encoding is shown. When the memory controller 2 does not perform encoding, the page data and the unit data are consistent with each other. Also, one codeword may be generated based on one unit data, or one codeword may be generated based on division data obtained by dividing the unit data. In addition, it is also possible to generate one codeword using plural unit data.

The processor 8 determines the memory area of the non-volatile memory 3 to be written into for each of the unit data. A physical address is allocated to the memory area of the non-volatile memory 3 . The processor 8 uses the physical address to manage the memory area of the writing target of the unit data. The processor 8 issues instructions to the memory interface 11 by designating the determined memory area (physical address) and writing user data into the non-volatile memory 3 . On the other hand, the host computer 4 manages data through logical addresses. Therefore, the processor 8 manages the corresponding relationship between the logical address and the physical address of the user data. Processor 8, when having received the situation that contains the read command of logical address from main frame 4, system specifies the physical address corresponding to logical address, and specifies for physical address and for The memory interface 11 issues an instruction to read user data.

In this specification, plural memory cells connected in common with one word line are defined as a memory cell group MG. One memory cell group MG is the unit of writing (programming). In this embodiment, the non-volatile memory 3 is a 4bit/Cell NAND memory 5, and one memory cell group MG has a data amount of 4 bits×number of bits. The bits written into each memory cell correspond to different pages. In this embodiment, the four pages of one memory cell group MG are referred to as the Lower page (the first page), the Middle page (the second page), the Upper page (the third page), and the Top page (the first page). 4 pages).

The ECC circuit 10 encodes the user data stored in the RAM 6 and generates a code word. Also, the ECC circuit 10 decodes the code word read from the non-volatile memory 3 . The ECC circuit 10 decodes the user data after correcting the bit errors contained in the code word read from the non-volatile memory 3 .

RAM6 temporarily stores the user data received from the host computer 4 until it is memorized in the non-volatile memory 3, or read from the non-volatile memory 3 The data is temporarily stored until sending a message to the host computer 4 . RAM6 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

In FIG. 1 , a configuration example in which a memory controller 2 is provided with an ECC circuit 10 and a memory interface 11 is shown. However, the ECC circuit 10 can also be embedded in the memory interface 11 . In addition, the ECC circuit 10 may also be embedded in the non-volatile memory 3 .

When a write request is received from the host computer 4, the memory system 1 operates as follows. The processor 8 temporarily stores the written data in the RAM6. The processor 8 reads the data stored in the RAM 6 and inputs it to the ECC circuit 10 . The ECC circuit 10 encodes the inputted data, and inputs the code word to the memory interface 11. The memory interface 11 writes the input code word to the non-volatile memory 3 .

When a read request is received from the host computer 4, the memory system 1 operates as follows. The memory interface 11 inputs the code word read from the non-volatile memory 3 to the ECC circuit 10 . The ECC circuit 10 decodes the input codeword and temporarily stores the decoded data in the RAM6. The processor 8 sends the data stored in the RAM 6 to the host 4 via the host interface 9 . In addition, the non-volatile memory 3 may also be composed of a plurality of chips, and the non-volatile memory 3 and the memory interface 11 may also pass through through holes (TSV: Through Silicon Via) to connect.

In addition, the configuration of the memory controller 2 shown in FIG. 1 is merely an example, and the internal bus bar 12 may be formed into a split structure or a hierarchical structure, or may be connected with additional functional blocks, etc. Various other forms of derivatives.

FIG. 2 is a block diagram showing an example of the internal structure of the non-volatile memory 3 of this embodiment. The non-volatile memory 3 is provided with a NAND I/O interface 21 , a control unit 22 , a NAND memory cell array (memory cell unit) 23 , and a page buffer (second memory unit) 24 . The non-volatile memory 3 is, for example, formed on a semiconductor substrate (such as a silicon substrate) and chipped.

The control unit 22 controls the operation of the non-volatile memory 3 based on commands and the like received from the memory controller 2 through the NAND I/O interface 21 . Specifically, when a write request is input, the control unit 22 writes the data requested to be written to the specified address on the NAND memory cell array 23. And control. Also, the control unit 22, when a read request is input, reads the data requested to be read from the NAND memory cell array 23 and controls the memory through the NAND I/O interface 21. 2 as the output way to control. The page buffer 24 temporarily stores the data input from the memory controller 2 and reads the data from the NAND memory cell array 23 when the NAND memory cell array 23 is written. Temporarily used as a buffer for storage.

As will be described later, the control unit 22 is based on the data obtained by reading out the data programmed in the 1st stage and the bit repeatedly input in the programming of the 1st stage and the 2nd stage. The data of the cell and the input data of the bit programmed by the programming of the 2nd stage determine the threshold voltage of the data of the bit programmed by the programming of the 2nd stage.

The control unit 22 is provided with an oscillator 31 , a sequencer 32 , an instruction user interface 33 , a voltage supply unit 34 , a column counter 35 , and a sequence access controller 36 . Also, the NAND memory cell array 23 is provided with a row decoder 37 and a sense amplifier 38 .

The NAND I/O interface 21 is a circuit for sending and receiving IO signals and control signals to and from the memory controller 2 . The command user interface 33 obtains the command and address received from the memory controller 2 through the IO signal line, and the command and address in the data based on the control signal. The command user interface 33 delivers the acquired command and address to the sequencer 32 .

The oscillator 31 is a circuit for generating a clock. The clock generated by the oscillator 31 is supplied to each component including the sequencer 32 . The sequencer 32 is a state machine driven by the clock pulse supplied from the oscillator 31 . The sequencer 32 controls access to the NAND memory cell array 23 and the like. For example, the sequencer 32 responds to commands received from the command user interface 33 to issue various commands for controlling internal voltages or operation sequences. Also, the sequencer 32 supplies the block address and page address included in the address received from the command user interface 33 to the row decoder 37 . Furthermore, the sequencer 32 supplies the column address included in the address received from the command user interface 33 to the column counter 35 .

The voltage supply unit 34 generates various internal voltages supplied to the word lines and various internal voltages supplied to the bit lines, and supplies them to the row decoder 37 and the sense amplifier 38 . When the column counter 35 is programmed or read, the column address supplied from the sequencer 32 is used as the head, and the column address is set according to the control signal supplied from the sequence access controller 36. Advance sequentially.

The page buffer 24 stores the data received from the serial access controller 36 sequentially in the row address area designated by the row counter 35 during the programming operation. In addition, the page buffer 24 sends the data of the column address specified by the above column address among the stored data to the serial access controller 36 sequentially during the read operation.

The serial access controller 36 stores the data sequentially received from the NAND I/O interface 21 at the bit width of the IO signal line in the page buffer 24 during the programming operation. Moreover, the serial access controller 36 sends the data sequentially received from the page buffer 24 at the bit width of the IO signal line to the NAND I/O interface 21 during the read operation.

The row decoder 37 decodes the block address and the page address during programming and reading, and selects the page corresponding to the page to be accessed included in the block BLK of the access target. The corresponding character line. After that, each row decoder 37 applies an appropriate voltage to the selected word line and the non-selected word line.

The sense amplifier 38 transmits the corresponding data stored in the page buffer 24 to the transistor of the memory cell during the programming operation. In addition, the sense amplifier 38 senses the data read from the selected word line to the bit line during the read operation, and stores the obtained data in the page buffer 24 . The data stored in the page buffer 24 is sent to the memory controller 2 through the serial access controller 36 and the NAND I/O interface 21 .

FIG. 3 is a circuit diagram showing an example of a 3-dimensional NAND memory cell array 23 . FIG. 3 shows the circuit configuration of one block BLK among the plurality of blocks in the three-dimensionally structured NAND memory cell array 23 . Other blocks of the NAND memory cell array 23 also have the same circuit configuration as that in FIG. 3 . In addition, this embodiment can also be applied to memory cells with a 2-dimensional structure.

As shown in FIG. 3 , the block BLK includes, for example, four fingers FNG (FNG0-FNG3). Also, each refers to FNG, which includes a plurality of NAND strings NS. Each of the NAND strings NS includes, for example, eight memory cell transistors MT (MT0 to MT7) connected in series, and selection transistors ST1 and ST2. In this specification, each finger FNG may be referred to as a word string St.

In addition, the number of memory cell transistors MT in the NAND string NS is not limited to 8. The memory cell transistor MT is arranged between the selection transistors ST1 and ST2 so that the current paths thereof are connected in series. The current path of the memory cell transistor MT7 at one end side of the series connection is connected with one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 at the other end side is connected by It is connected with one end of the current path of the selection transistor ST2.

Refers to the gates of the selection transistor ST1 of each of FNG0-FNG3, which are respectively connected to the selection gate lines SGD0-SGD3 in common. On the other hand, the gate of the selection transistor ST2 is commonly connected to the same selection gate line SGS between the plurality of fingers FNG. Moreover, the control gates of the memory cell transistors MT0-MT7 located in the same block BLK are respectively connected to the word lines WL0-WL7 in common. That is, the word lines WL0 to WL7 and the selection gate line SGS are commonly connected between the plurality of fingers FNG0 to FNG3 in the same block BLK. In contrast, the selection gate line SGD, Even if they are in the same block BLK, they refer to each of FNG0 to FNG3 and are independent from each other.

The control gate electrodes of the memory cell transistors MT0-MT7 constituting the NAND string NS are respectively connected to the word lines WL0-WL7, and the same refers to the first in each NAND string NS in the FNG. The i memory cell transistors MTi (i=0-n) are commonly connected through the same word line WLi (i=0-n). That is, the control gate electrodes of the memory cell transistors MTi in the same row in the block BLK are connected to the same word line WLi.

Each NAND string NS is connected to a word line WLi and is also connected to a bit line. Each memory cell in each NAND string NS can be identified by the address for identifying the word line WLi and the select gate lines SGD0-SGD3 and the address for identifying the bit line. As mentioned above, the data of the memory cells (memory cell transistors MT) located in the same block BLK are deleted in batches. On the other hand, data reading and writing are performed in units of physical sectors MS. One physical sector MS is connected to one word line WLi, and includes a plurality of memory cells belonging to one FNG.

The memory controller 2 writes (programs) all the NAND strings NS connected to one word line in one finger as a unit. Therefore, the unit of the amount of data programmed by the memory controller 2 is 4 bits×the number of bit lines.

During the read operation and the programming operation, one word line WLi and one select gate line SGD are selected according to the physical address, and the physical sector MS is selected. In addition, in this specification, writing data to a memory cell is called a program according to need.

FIG. 4 is a cross-sectional view of a part of the NAND memory cell array 23 of the NAND memory 5 with a three-dimensional structure. As shown in FIG. 4, a plurality of NAND strings NS are formed in the vertical direction on the p-well region (P-well) 41 of the semiconductor substrate. That is, in the p-type well region 41, a plurality of wiring layers 42 functioning as select gate lines SGS and a plurality of wiring layers functioning as word lines WLi are formed in the vertical direction. 43, and a plurality of wiring layers 44 functioning as the selection gate line SGD.

Also, a memory hole 45 that penetrates these wiring layers 42 , 43 , and 44 and reaches the p-type well region 41 is formed. On the side of the memory hole 45 , a block insulating film 46 , a charge storage layer 47 and a gate insulating film 48 are sequentially formed, and furthermore, a conductive film 49 is embedded in the memory hole 45 . The conductive film 49 functions as a current path of the NAND string NS, and is a region where channels are formed when the memory cell transistor MT and the selection transistors ST1 and ST2 operate.

At each NAND string NS, on the p-well region 41, a selection transistor ST2, a plurality of memory cell transistors MT, and a selection transistor ST1 are laminated in sequence. On the upper end of the conductive film 49, a wiring layer functioning as a bit line BL is formed.

Furthermore, an n + -type impurity diffusion layer and a p + -type impurity diffusion layer are formed in the surface of the p-type well region 41 . The contact plug 50 is formed on the n+ type impurity diffusion layer, and the wiring layer functioning as the source line SL is formed on the contact plug 50 . Further, on the p+ type impurity diffusion layer, a contact plug 51 is formed, and on the contact plug 51, a wiring layer functioning as a well wiring CPWELL is formed. The well wiring CPWELL is used to apply the erasure voltage.

The NAND memory cell array 23 shown in FIG. 4 is arranged in plural in the depth direction of the paper of FIG. A denoted FNG system is formed. Other fingers FNG are formed, for example, in the left-right direction in FIG. 4 . In FIG. 3 , four fingers FNG0 to 3 are shown, but in FIG. 4 , an example in which three fingers are arranged between the contact pins 50 and 51 is shown.

Fig. 5 is a diagram showing an example of the threshold value region in the first embodiment. FIG. 5 shows an example of the distribution of the threshold area of the 4-bit/Cell non-volatile memory 3 . In the non-volatile memory 3, information is memorized by the charge amount of electrons accumulated in the charge storage layer 47 of the memory cell. Each memory cell has a threshold voltage corresponding to the electric charge of electrons. In addition, the plural data values stored in the memory cells are made to correspond to plural regions (threshold regions) with different threshold voltages.

S0-S15 in FIG. 5 are for displaying the distribution of threshold values in 16 threshold value regions. The horizontal axis of FIG. 5 represents the threshold voltage, and the vertical axis represents the number of memory cells (number of cells). Threshold value distribution refers to the range of threshold value variation. In this way, each memory cell has 16 threshold areas divided by 15 boundaries, and each threshold area has an inherent threshold distribution.

In this embodiment, the region where the threshold voltage is below Vr1 is called region S0, and the region where the threshold voltage is greater than Vr1 and below Vr2 is called region S1. The region where the threshold voltage is greater than Vr2 and equal to or less than Vr3 is called region S2, and the region where the threshold voltage becomes greater than Vr3 and equal to or less than Vr4 is called region S3. Also, in this embodiment, the region where the threshold voltage is higher than Vr4 and below Vr5 is called region S4, and the region where the threshold voltage is larger than Vr5 and below Vr6 is called S4. The region S5 is defined as the region where the threshold voltage is higher than Vr6 and lower than Vr7 is called region S6, and the region where the threshold voltage is higher than Vr7 and lower than Vr8 is called region S7. Also, in this embodiment, the region where the threshold voltage is greater than Vr8 and below Vr9 is called region S8, and the region where the threshold voltage is greater than Vr9 and below Vr10 is called S8. The region S9 is defined as the region where the threshold voltage is higher than Vr10 and lower than Vr11, called region S10, and the region where the threshold voltage is higher than Vr11 and lower than Vr12 is called region S11. Also, in this embodiment, the region where the threshold voltage is greater than Vr12 and below Vr13 is referred to as region S12, and the region where the threshold voltage is greater than Vr13 and below Vr14 is referred to as S12. As region S13, the region where the threshold voltage is larger than Vr14 and below Vr15 is called region S14, and the region where the threshold voltage is larger than Vr15 is called region S15.

Also, the threshold value distributions corresponding to the regions S0 to S15 are referred to as first to sixteenth distributions. Vr1 to Vr15 are the threshold voltages that serve as the boundaries of the respective threshold regions.

In the non-volatile memory 3, the plural data values correspond to the plural threshold value regions of the memory cells. This correspondence is called data encoding. This data code is formulated in advance, and when the data is written (programmed), it follows the data code and will become in the threshold value area corresponding to the memorized data value, to the memory cell The inner charge storage layer 47 injects charges. However, when reading, the read voltage is applied to the memory cell, and the data logic is determined according to whether the threshold value of the memory cell is lower or higher than the read voltage.

When reading data, the logic of data is determined according to whether the threshold value is lower or higher than the read level of the boundary of the read object. When the threshold value is the lowest, it is in the "delete" state, and all bits of data are defined as "1". When the threshold value is higher than the "deleted" state, it is the "programmed" state, and the data is defined as "1" or "0" according to the encoding.

Fig. 6A is a diagram showing an example of the data encoding of the first embodiment, and an example of the 1-4-5-5 data encoding. In this embodiment, the 16 threshold value regions shown in FIG. 5 correspond to 16 data values of 4 bits, respectively. The relationship between the threshold voltage in FIG. 6A and the data values corresponding to the bits of the Top, Upper, Middle, and Lower pages is as follows.

・Threshold voltage is the memory cell located in the S0 area, which is the state of "1111" in memory. ・Threshold voltage is the memory cell located in the S1 area, which is the state of "0111" in memory. ・Threshold voltage is the memory cell located in the S2 area, which is the state of "0011" in memory. ・Threshold voltage is the memory cell located in the S3 area, which is the state of "1011" in memory. ・Threshold voltage is the memory cell located in the S4 area, which is the state of "1001" in memory. ・Threshold voltage is the memory cell located in the S5 area, which is the state of “0001” in memory. ・Threshold voltage is the memory cell located in the S6 area, which is the state of “0101” in memory. ・Threshold voltage is the memory cell located in the S7 area, which is the state of “1101” in memory. ・Threshold voltage is the memory cell located in the S8 area, which is the state of "1100" in memory. ・Threshold voltage is the memory cell located in the S9 area, which is the state of "1110" in memory. ・Threshold voltage is the memory cell located in the S10 area, which is the state of "1010" in memory. ・Threshold voltage is the memory cell located in the S11 area, which is the state of "1000" in memory. ・Threshold voltage is the memory cell located in the S12 area, which is the state of "0000" in memory. ・Threshold voltage is the memory cell located in the S13 area, which is the state of "0100" in memory. ・Threshold voltage is the memory cell located in the S14 area, which is the state of "0110" in memory. ・Threshold voltage is the memory cell located in the S15 area, which is the state of "0010" in memory.

Fig. 6B is a diagram showing another example of the data encoding of the first embodiment, and an example of the 4-3-4-4 data encoding. The relationship between the threshold voltage in FIG. 6B and the data values corresponding to the bits of the Top, Upper, Middle, and Lower pages is as follows.

・Threshold voltage is the memory cell located in the S0 area, which is the state of "1111" in memory. ・Threshold voltage is the memory cell located in the S1 area, which is the state of "0111" in memory. ・Threshold voltage is the memory cell located in the S2 area, which is the state of "0011" in memory. ・Threshold voltage is the memory cell located in the S3 area, which is the state of "1011" in memory. ・Threshold voltage is the memory cell located in the S4 area, which is the state of "1010" in memory. ・Threshold voltage is the memory cell located in the S5 area, which is the state of “1110” in memory. ・Threshold voltage is the memory cell located in the S6 area, which is the state of "1100" in memory. ・Threshold voltage is the memory cell located in the S7 area, which is the state of "1000" in memory. ・Threshold voltage is the memory cell located in the S8 area, which is the state of “1001” in memory. ・Threshold voltage is the memory cell located in the S9 area, which is the state of "0001" in memory. ・Threshold voltage is the memory cell located in the S10 area, which is the state of “0000” in memory. ・Threshold voltage is the memory cell located in the S11 area, which is the state of "0010" in memory. ・Threshold voltage is the memory cell located in the S12 area, which is the state of "0110" in memory. ・Threshold voltage is the memory cell located in the S13 area, which is the state of "0100" in memory. ・Threshold voltage is the memory cell located in the S14 area, which is the state of "0101" in memory. ・Threshold voltage is the memory cell located in the S15 area, which is the state of "1101" in memory.

As shown in FIG. 6A and FIG. 6B , it is logic capable of allocating 4-bit data of each memory cell at each region of the threshold voltage. In addition, when the memory cell is in an unwritten state ("erased" state), the threshold voltage of the memory cell is located in the S0 region. Also, in the symbols shown here, it is like "the data of "1111" is stored in the state of S0 (deletion), and the data of "0111" is stored in the state of S1", and any two Only one bit of data is changed between adjacent areas. In this way, the data encoding shown in FIG. 6A and FIG. 6B is a Gray code in which only one bit of data is changed between any two adjacent regions.

In the encoding of this embodiment shown in FIG. 6A, the threshold voltage used to determine the boundary of the bit value of each page is as follows.

・Threshold voltages used to determine the boundary of the bit value of the Top page are Vr1, Vr3, Vr5, Vr7, and Vr12. ・The threshold voltages used to determine the boundary of the bit value of the Upper page are Vr2, Vr6, Vr10, Vr13, and Vr15. ・Vr4, Vr9, Vr11, Vr14 are the threshold voltages used to determine the boundary of the bit value of the Middle page. ・The threshold voltage used to determine the boundary of the bit value of the Lower page is Vr8.

In this way, the number of threshold voltages used to determine the boundary of the bit value (hereinafter referred to as the number of boundaries) is 1, 4, and 5 for the Lower page, Middle page, Upper page, and Top page, respectively. , 5. Hereinafter, this kind of encoding is called 1-4-5-5 encoding using the number of boundaries of each of the Lower page, Middle page, Upper page, and Top page.

The first feature of this embodiment is that the number of boundaries where the bit value of each page changes is five at most. When 16 states are represented by 4 bits, the minimum value of the maximum number of boundaries is 4, and the encoding in Figure 6 is only 1 more than this, and the bias of bit errors becomes less . In this way, the memory system 1 caused by this embodiment can suppress the bit error rate by possessing the first feature, and can also control the bias of the bit error for each page. inhibition.

The second feature of this embodiment is that the number of borders on the Lower page is 1, and the number of borders on the Middle page is 4, so that it becomes possible to "integrate the Lower page and the Middle page into one" in the first stage. The stylization is performed in two stages of "stylization of the upper page and the top page" and "stylization of the second stage of integrating the upper page and the top page".

The third feature of this embodiment is that the range of change from the threshold area produced by the stylization of the first stage to the threshold area produced by the stylization of the second stage is few. That is, it means that the range of variation in the threshold area is small. The smaller the range of change in the threshold area, the more difficult it is to be affected by the interference between adjacent cells. For the first to third features above, a detailed description will be given later.

The control unit 22 of the non-volatile memory 3 controls the programming of the NAND memory cell array 23 and the readout from the NAND memory cell array 23 based on the code shown in FIG. 6A or FIG. 6B .

For 3-dimensional memory cells, the miniaturization of memory cells has not progressed as in 2-dimensional memory cells. Therefore, in a 3-dimensional memory cell, if the generations of adjacent memory cells are widely spaced from each other, the mutual interference between cells is small. In this case, generally speaking, all bits of each memory cell are programmed simultaneously (for example, if each bit is allocated to a different page, then all pages are programmed simultaneously).

In the case of programming all the bits of each memory cell at the same time, the data encoding is not particularly limited to the combination. It is only necessary to determine which of the 16 threshold value areas to be located based on the data of all bits, and to make the determined threshold value area from the area of S0 which is in the deleted state. Just programmatically. In this case, generally speaking, a data encoding such as 4-4-3-4 data encoding that minimizes the maximum number of borders is used. In 4-4-3-4 data encoding, when allocating 15 boundaries between 16 threshold areas to 4 pages, 4 boundaries are allocated to the Lower page, and 4 boundaries are allocated to the Middle page. 4 boundaries, and allocate 3 boundaries for the Upper page, and allocate 4 boundaries for the Top page. In the case of data encoding, since the bias in the number of boundaries between pages is small, as a result, the bias in the bit error rate between pages becomes small. This is because most of the causes of bit errors are caused by the fact that the threshold value is shifted to the adjacent threshold value area, and if there are more pages with a larger number of boundaries, the bit error The number of meta errors will become more and more. This matter, because it will lead to "even if the error rate is the same as the memory cell, the correction ability of the ECC circuit 10 necessary for correcting the error of the page data must be strengthened", therefore, in order to It is also effective in suppressing deterioration in response performance, cost, and power consumption of the memory system 1 to a write request from the host computer 4 . Also, the bias in readout speed caused by the bias in the number of boundaries is also reduced.

In addition, in the NAND memory 5 of 4 bits/Cell, since the interval between adjacent threshold value regions is narrow, the influence caused by mutual interference between cells is smaller than that of 1 bit/cell. Cell or 2-bit/Cell NAND memory 5 series becomes larger. Therefore, in the NAND memory 5 of the generation in which miniaturization has progressed in recent years, in general, in order to suppress inter-cell interference, a programming stage using plural numbers, for example, using two programming stages is adopted. Stage (hereinafter, it will also be simply referred to as stage) is a stylized method (Foggy-Fine stylized) for injecting a small amount of charges one by one into the charge storage layer 47 of the memory cell. In this Foggy-Fine programming, after writing to a memory cell in the first stage (Foggy stage), write to an adjacent cell, and then return to the original memory cell place, and write in the second phase (Fine phase). Each stage in this case is the execution unit of programming, and the programming of the memory cell corresponding to one word line WLi is completed by executing two programming stages.

No matter in the stylization of the first stage or the stylization of the second stage, the stylization is carried out using 16 threshold value areas. The threshold distribution of the threshold region at the end of the programming of the first stage has a wider width than the threshold distribution of the threshold region in the final data encoding. That is, in the Foggy stage, Foggy (rough) writing is performed. In this Foggy stage of programming, all 4 pages of input data are necessary. The stylized threshold distribution in the Foggy stage is in an intermediate state where adjacent distributions overlap each other, so data cannot be read out. In the programming of the Fine stage which is the second stage, the programmed threshold area of the Foggy stage is moved to the threshold area in the final data code. That is, in the Fine stage, writing of Fine is performed. The stylization of this Fine stage is also the same, and all 4 pages of input data are necessary. The threshold value distribution after programming in the Fine stage is the final state where adjacent distributions are separated from each other, so data can be read out after programming in the Fine stage.

In the case of 4-4-3-4 data encoding, although the deviation of the number of boundaries is small, in the Foggy-Fine stylized data input, 4 pages of data are required at each stage enter. This will increase the time spent in data input and deteriorate the response performance of the memory system 1 to the write request from the host computer 4 . Also, in the memory system 1, the buffer size (write buffer size) of the write buffer (first storage unit) used to hold data for input to the NAND memory 5 is increased. Generally speaking, this write buffer is an area allocated to a part of the RAM 6 in the memory system 1 .

As a countermeasure against these problems, in the present embodiment, the memory system 1 adopts 1-4-5-5 data encoding for the non-volatile memory 3 having a three-dimensional structure, and further uses two stage to implement the page unit (page by page) write. Thus, in this embodiment, even in the non-volatile memory 3 having a three-dimensional structure, it is possible to suppress inter-cell interference and bias in the bit error rate between pages, and at the same time Reduce the write buffer size of the memory controller 2. The write buffer in this embodiment is to repeatedly input data in the first to fourth bits (the data of the Lower page, Middle page, Upper page, and Top page) during the first programming and the second programming The data of the bit is set to be discardable or invalid after the second programming is started, and the data of the other bits is set to be discardable or invalid after the first programming is started.

Here, the inter-cell interference of adjacent memory is described. The charge accumulated in the charge accumulation layer 47 of a certain memory cell will cause disturbance to the electric field of the adjacent memory cell, and as a result, it will give the next adjacent memory cell The noise of the threshold voltage changes when output. It originated from the fact that "programming and verification are carried out under a certain electric field condition, and after the programming is completed, the adjacent memory cells are programmed into different charges", read The output accuracy system will become somewhat degraded. This interference between adjacent memory cells becomes significant as the distance between memory cells shrinks with the miniaturization of the manufacturing technology of memory devices. Also, if the interference between adjacent memory cells is enlarged, it will occur between adjacent memory cells connected to different bit lines on the same word line WLi.

The interference between adjacent memory cells can be determined by the electric field conditions of the memory cells between "programming and verification" and "reading after adjacent memory cells have been programmed". The fact that the differences narrowed was somewhat relieved. As one of the methods to reduce the interference between adjacent memory cells connected to different bit lines on the same word line WLi, there is a division of programming into plural The method of stylization is carried out in such a way that there is no large change in the amount of charge in the charge storage layer 47 between the stages.

In the programming sequence of this embodiment, 4 bits on one word line WLi are programmed in two programming stages, that is, in a 1st stage and a 2nd stage. Each programming stage is the execution unit of programming, and the memory system 1 of this embodiment ends by executing 2 programming stages to write 4-bit data to the memory cell. Also, in this embodiment, in each of the two programming stages, the data of some pages having 4 bits is used. Specifically, in the stylization of the 1st stage, the data of the Lower page, Middle page, and Top page are used, and in the stylization of the 2nd stage, the data of the Middle page, Upper page, and Top page are used.

Fig. 7 is a diagram showing the stylized threshold value area in the first embodiment. In FIG. 7, there is shown the threshold value region after the programming of the 1st stage and the 2nd stage for the memory cell. (T1) of FIG. 7 shows the threshold area of the deleted state which is the initial state before stylization. (T2) in Fig. 7 shows the threshold area after the stylization of the 1st stage (the first stylization). (T3) in Figure 7 shows the threshold area after the stylization of the 2nd stage (second stylization).

As shown in (T1) of FIG. 7 , all memory cells of the NAND memory cell array 23 are in the state of distribution S0 in the unwritten state ("delete" state). The control unit 22 of the non-volatile memory 3 is generally shown in (T2) of FIG. For each of the memory cells, the bit value is maintained in the state of the distribution S0, or the charge is injected to move it to a distribution higher than the distribution S0.

Specifically, the control unit 22 is based on "when the bit values written into the Lower page, the Middle page, and the Top page are all "1", the charge is not injected, and when the bit value written into the Lower page As long as any one of the bit values at the Middle page and the Top page is "0", it is programmed by injecting charge and moving the threshold voltage to a higher level.

That is, when the bit value written to the Lower page, Middle page, and Top page is "011", it is moved to distribution S1, and when written to the Lower page and Middle page And when the bit value at the Top page is "101", it is moved to the distribution S4, and when the bit value written to the Lower page and Middle page and the Top page is "001" In the case of ", it is moved to the distribution S5, and when the bit value written to the Lower page, Middle page, and Top page is "100", it is moved to the distribution S8, Also, when the bit value written to the Lower page, Middle page, and Top page is "110", it is moved to distribution S9, and when written to the Lower page, Middle page, and Top page When the bit value at the page is "000", it is moved to the distribution S12, and when the bit value written to the Lower page, Middle page, and Top page is "010", In this case, it is moved to distribution S14.

Here, ideally, distribution S1, distribution S4, distribution S5, distribution S8, distribution S9, distribution S12, and distribution S14 are to reduce the width of the threshold value region in such a way that the threshold voltage will be somewhat reduced. Broadened and roughly stylized. That is, the rising range of the programming voltage pulse described later is increased. Thereby, the time required for writing can be shortened. Also, by programming in such a way that the threshold voltage is somewhat lower, it is possible to distribute the threshold value in such a way that it will eventually become a specific width in the programming of the 2nd stage. The width of the area for writing.

Also, ideally, the adjacent distribution S8 and distribution S9, and the adjacent threshold value distribution S12 and distribution S14, the distance between each of these is set to be smaller than that of other adjacent distributions. The intervals are narrower. The write bit values between the adjacent threshold distributions with narrowed intervals are different because the data of the Middle page are different. That is to say, the stylized data in the 1st stage looks like a binary value (binary), so it can be read out from the Lower page, Middle page data, and Top page. However, by adding The interval between different threshold value distributions of the data on the Middle page is narrowed to ensure a wide interval between the different threshold value distributions of the data on the Lower page and the Top page, and the readout of the Lower page and the Top page When the margin (margin) increases. The threshold value distributions S0-S14 shown in (T2) of FIG. 7 correspond to the 17th-24th threshold value regions.

Next, as shown in ( T3 ) of FIG. 7 , in programming at the 2nd stage, two pages, the Middle page and the Upper page, are required for data writing. In addition, the control unit 22 of the non-volatile memory 3 is such that the threshold value distribution after programming in the 2nd stage becomes a 16-value level in the final state where each adjacent distribution is separated. , to programmatically. After programming in the 2nd stage, all page data can be read out.

In the programming of the 2nd stage, if the change range of the threshold value of the memory cell from the end of the programming of the 1st stage is larger, the interference between adjacent cells will become larger. Therefore, ideally, the variation of the threshold distribution of the memory cells is minimized when the variation of the threshold distribution of the memory cells is the largest. If according to the present embodiment, then the variation of the maximum threshold value distribution is the amount of 3 threshold value distributions, and as S0 changes to S3, S4 changes to S7 and S8 changes as The case of S11. The threshold value distributions S0-S15 shown in (T3) of FIG. 7 correspond to the first to sixteenth threshold value regions.

In addition, programming is typically performed by applying one or a plurality of programming voltage pulses. During the programmed application of pulses for multiple times, the voltage value is increased step by step. After each programming voltage pulse, to confirm whether the memory cell has moved beyond a threshold boundary level, a readout called verify is performed. By repeatedly performing this application and reading, it becomes possible to move the threshold value of the memory cell to the range of the specific threshold value distribution.

In addition, although the control unit 22 may continuously implement the programming of the 1st stage and the programming of the 2nd stage for one word line WLi, in order to reduce the influence of interference between adjacent memory cells, it may Programming is performed in non-contiguous order across word lines WLi of the plurality.

Fig. 8A is a diagram showing the first example of the stylized sequence of the first embodiment. Fig. 8B is a diagram showing the second example of the stylized sequence of the first embodiment. Fig. 8C is a diagram showing the third example of the stylized sequence of the first embodiment. In FIGS. 8A to 8C , in order to reduce the influence of interference between adjacent memory cells, programming is performed in two programming stages. FIG. 8A shows an example of the programming sequence in the NAND memory 5 in which one word string St is connected to each word line in each block. 8B and 8C show an example of the programming order in the NAND memory 5 in which four word strings St are connected to each word line in each block. In addition, in FIG. 8B and FIG. 8C, the four character strings St connected to each word line are denoted as String0-3.

If writing is started, the control unit 22 performs each programming stage while straddling the word line WLi in a specific discontinuous order. That is to say, the 1st stage and the 2nd stage for the same character line are not carried out continuously, but after the stylization of the 1st stage is carried out for a certain character line, for different characters The stylization of the 2nd stage is carried out for the element line.

If the programming of a certain word line is completed up to the 2nd stage, and the programming of the 1st stage and the 2nd stage are continuously performed for the adjacent word line, the fluctuation amount of the threshold voltage is will get bigger. However, if the variation of the threshold voltage of adjacent word lines is large, the interference between adjacent memory cells between the word lines will become larger. Therefore, in order to reduce the interference between adjacent memory cells between word lines, it is necessary to reduce the fluctuation amount of the threshold voltage of adjacent word lines after programming the word lines until the 2nd stage. is valid. In the sequence shown in FIG. 8A , the stylization stage of adjacent word lines after the stylization of a certain word line is completed up to the 2nd stage is only the 2nd stage.

When programming the NAND memory 5 with the three-dimensional structure in the programming sequence shown in FIG. Programming is performed in the order shown in (1) to (9) below. The control unit 22 performs programming to the NAND memory 5 based on the instruction from the processor 8, however, the description of the content based on the instruction from the processor 8 is omitted below.

(1) First, the control unit 22 executes the programming ST11 of the 1st stage of the word line WL0. (2) Next, the control unit 22 executes the programming ST12 of the 1st stage of the word line WL1. (3) Next, the control unit 22 executes programming ST13 of the 2nd stage of the word line WL0. (4) Next, the control unit 22 executes programming ST14 of the 1st stage of the word line WL2. (5) Next, the control unit 22 executes programming ST15 of the 2nd stage of the word line WL1. (6) Next, the control unit 22 executes programming ST16 of the 1st stage of the word line WL3. (7) Next, the control unit 22 executes programming ST17 of the 2nd stage of the word line WL2. (8) Next, the control unit 22 executes programming ST18 of the 1st stage of the word line WL4. (9) Next, the control unit 22 executes programming ST19 of the 2nd stage of the word line WL3.

Hereinafter, similarly, the control unit 22 performs processing from the lower left to the upper right in FIG. 8A and then proceeds obliquely upward. In this way, in FIG. 8A, the plurality of memory cells in the non-volatile memory 3 are provided with a plurality of first memory cells connected to the first word line, and and and the first The plurality of second memory cells connected by the second word lines adjacent to the word lines, the memory controller 2, after performing the first programming for the first memory cells of the plurality, The first programming is performed on the plural second memory cells, and then, after the first programming is performed on the plural second memory cells, the plural first memory cells are programmed Proceed to the 2nd stylization.

When programming the NAND memory 5 with the three-dimensional structure in the programming sequence of FIG. 8B , if writing is started, the control unit 22 is shown by the following (11)-(24) The sequence to implement the stylization.

(11) First, the control unit 22 executes the programming ST21 of the 1st stage of the word string St0_word line WL0. (12) Next, the control unit 22 executes the programming ST22 of the 1st stage of the word string St1_word line WL0. (13) Next, the control unit 22 executes the programming ST23 of the 1st stage of the word string St2_word line WL0. (14) Next, the control unit 22 executes the programming ST24 of the 1st stage of the word string St3_word line WL0. (15) Next, the control unit 22 executes the programming ST25 of the 1st stage of the word string St0_word line WL1. (16) Next, the control unit 22 executes the programming ST26 of the 2nd stage of the word string St0_word line WL0. (17) Next, the control unit 22 executes the programming ST27 of the 1st stage of the word string St1_word line WL1. (18) Next, the control unit 22 executes the programming ST28 of the 2nd stage of the word string St1-word line WL0. (19) Next, the control unit 22 executes the programming ST29 of the 1st stage of the word string St2_word line WL1. (20) Next, the control unit 22 executes the programming ST210 of the 2nd stage of the word string St2_word line WL0. (21) Next, the control unit 22 executes the programming ST211 of the 1st stage of the word string St3_word line WL1. (22) Next, the control unit 22 executes the programming ST212 of the 2nd stage of the word string St3_word line WL0. (23) Next, the control unit 22 executes the programming ST213 of the 1st stage of the word string St0_word line WL2. (24) Next, the control unit 22 executes the programming ST214 of the 2nd stage of the word string St0_word line WL1.

Hereinafter, similarly, the control unit 22 performs processing from the lower left toward the upper right in FIG. 8B and then proceeds obliquely upward. In addition, in Fig. 8B, although the description is made for the case where there are 4 character strings St in the block, the character string St in the block may also be 3 or less, and may also be 5 above.

When programming the NAND memory 5 of the three-dimensional structure with the programming sequence of FIG. 8C , if writing is started, the control unit 22 is shown by the following (31)-(50) The sequence to implement the stylization.

(31) First, the control unit 22 executes the programming ST31 of the 1st stage of the word string St0_word line WL0. (32) Next, the control unit 22 executes the programming ST32 of the 1st stage of the word string St1_word line WL0. (33) Next, the control unit 22 executes the programming ST33 of the 1st stage of the word string St2_word line WL0. (34) Next, the control unit 22 executes the programming ST34 of the 1st stage of the word string St3_word line WL0. (35) First, the control unit 22 executes the programming ST35 of the 1st stage of the word string St0_word line WL1. (36) Next, the control unit 22 executes the programming ST36 of the 1st stage of the word string St1_word line WL1. (37) Next, the control unit 22 executes the programming ST37 of the 1st stage of the word string St2_word line WL1. (38) Next, the control unit 22 executes the programming ST38 of the 1st stage of the word string St3_word line WL1. (39) Next, the control unit 22 executes the programming ST39 of the 2nd stage of the word string St0_word line WL0. (40) Next, the control unit 22 executes the programming ST310 of the 2nd stage of the word string St1-word line WL0. (41) Next, the control unit 22 executes the programming ST311 of the 2nd stage of the word string St2_word line WL0. (42) Next, the control unit 22 executes the programming ST312 of the 2nd stage of the word string St3_word line WL0. (43) Next, the control unit 22 executes the programming ST313 of the 1st stage of the word string St0_word line WL2. (44) Next, the control unit 22 executes the programming ST314 of the 1st stage of the word string St1_word line WL2. (45) Next, the control unit 22 executes the programming ST315 of the 1st stage of the word string St2_word line WL2. (46) Next, the control unit 22 executes the programming ST316 of the 1st stage of the word string St3_word line WL2. (47) Next, the control unit 22 executes the programming ST317 of the 2nd stage of the word string St0_word line WL1. (48) Next, the control unit 22 executes the programming ST318 of the 2nd stage of the word string St1_word line WL1. (49) Next, the control unit 22 executes the programming ST319 of the 2nd stage of the word string St2_word line WL1. (50) Next, the control unit 22 executes the programming ST320 of the 2nd stage of the word string St3_word line WL1.

In addition, in Fig. 8C, although the description is made for the case where there are 4 character strings St in the block, the character string St in the block can also be 3 or less, and can also be 5 above.

In this way, even if the word string St becomes plural, the stylization order of each stylization stage of the word line WLi in one word string St is the same as when there is one word string St. When there is a non-volatile memory 3 with a 3-dimensional structure of a complex word string St in the block, the stylization of the combined position of the word line WLi and the word string St, generally speaking, first for the relative The same word line number in the different zigzag string St is programmed, and then advances to the next word line number. In the case of following this sequence, if FIG. 8A is combined by the number of character strings St, for example, the sequence will be the same as that of FIG. 8B or FIG. 8C.

Here, an example of the writing procedure according to the programming order according to the first embodiment will be described using FIGS. 9 to 11 . In FIGS. 9 to 11, the writing process is shown for the case of following the stylized sequence shown in FIG. 8B or FIG. 8C. As previously mentioned, the memory controller 2 advances the programming stage while crossing the word lines WLi in a discontinuous order, therefore, the entire batch of certain word lines WLi (herein, system as a block) is stylized as a whole of the stylized sequence.

Fig. 9 is a flow chart showing a first example of the entire write procedure for one block by the first embodiment. Here, one block is assumed to have n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). Fig. 10 is a flow chart showing the writing procedure in the 1st stage caused by the first embodiment, and Fig. 11 is a flow chart showing the writing procedure in the 2nd stage caused by the first embodiment The flow chart.

As shown in FIG. 9, when writing is started, the control unit 22 executes programming of the 1st stage of the word string St0_word line WL0 (step S10). Next, the control unit 22 executes programming of the 1st stage of the word string St1_word line WL0 (step S20). Thereafter, the control unit 22 executes the same processing as steps S10 and S20 for each character string St. Next, the control unit 22 executes programming of the 1st stage of the word string St3_word line WL0 (step S30).

Furthermore, the control unit 22 executes programming of the 1st stage of the word string St0_word line WL1 (step S40). Next, the control unit 22 executes programming of the 2nd stage of the word string St0_word line WL0 (step S50). Next, the control unit 22 executes programming of the 1st stage of the word string St1_word line WL1 (step S60). Thereafter, the control unit 22 repeats the general processing of steps S40, S50, and S60 for each word line WLi of each word string St.

Next, the control unit 22 executes programming of the 1st stage of the word string St0_word line WLn (step S70). Next, the control unit 22 executes programming of the 2nd stage of the word string St0_word line WLn-1 (step S80). Thereafter, the control unit 22 repeats the general processing of steps S70 and S80 for each word line WLi of each word string St.

Next, the control unit 22 executes programming of the 2nd stage of the word string St3_word line WLn-1 (step S90). Next, the control unit 22 executes programming of the 2nd stage of the word string St0_word line WLn (step S100). Next, the control unit 22 executes programming of the 2nd stage of the word string St1_word line WLn (step S110). Thereafter, the control unit 22 performs the same processing as steps S100 and S110 for each character string St. Next, the control unit 22 executes programming of the 2nd stage of the word string St3_word line WLn (step S120).

Fig. 10 is a flow chart showing the first example of the writing program in the 1st stage. In the programming of the 1st stage, first, an input start command of Lower page data is input to the non-volatile memory 3 from the memory controller 2 (step S210). Afterwards, the Lower page data is input from the memory controller 2 to the non-volatile memory 3 (step S215). Next, an input start command of Middle page data is input to the non-volatile memory 3 from the memory controller 2 (step S220). Afterwards, the Middle page data is input from the memory controller 2 to the non-volatile memory 3 (step S225). Next, the memory controller 2 starts inputting the data of the Top page to the non-volatile memory 3 (step S230). Afterwards, the top page data is input to the non-volatile memory 3 from the memory controller 2 (step S235). Furthermore, a programming execution command of the 1st stage is input to the non-volatile memory 3 from the memory controller 2 (step S240), and thus becomes chip_busy (step S245).

When data writing is performed, the threshold voltage Vth is determined (step S250 ), and one to a plurality of programming voltage pulses are applied (step S255 ). Afterwards, in order to confirm whether the memory cell has been moved beyond the threshold boundary level, data is read (verified) (step S260).

Furthermore, it is determined whether the number of fail-bits of the data in the Lower page, Middle page, and Top page is smaller than the criteria (step S265). When the number of failed bits of the data is greater than the judgment criterion, the processing from the application of the programming pulse to the judgment of the criteria (steps S255-S265) is repeated. On the other hand, if the number of failed bits of the data is smaller than the criterion, it becomes chip_ready (step S270). In this way, by repeatedly applying, reading, and confirming, it becomes possible to move the threshold value of the memory cell to the range of the specific threshold value distribution.

In addition, as mentioned above, the readout level after the programming voltage pulse is applied in the 1st stage of writing can also be slightly different from the readout level after the 2nd stage of writing, which is more ideal. The read level after writing in the 2nd stage is lower. That is, Vr1'≦Vr1, Vr4'≦Vr4, Vr5'≦Vr5, Vr8'≦Vr8, Vr9'≦Vr9, Vr12'≦Vr12, Vr14'≦Vr14.

In addition, in the readout after the programming voltage pulse application in the 1st stage writing, the readout by Vr9' and the readout by Vr14' can also be omitted, and Vr9' is passed through Vr8 After the reading of ', after applying a certain number of programming voltage pulses, it is set as the end of writing, Vr14' is after the reading of Vr13', after applying a certain number of programming voltage pulses After that, it is assumed that writing is completed.

This is because, as mentioned above, by narrowing the interval between the different threshold value regions for the data of the Middle page in the programmed data in the 1st stage, it is possible to write in the 2nd stage. The intervals between the different threshold value regions of the data read out from the Lower page and the Top page can be fully ensured even by simple control of "applying a certain number of programmed voltage pulses".

Furthermore, it is also possible to omit the readout after application of the programming voltage pulses of Vr8', Vr9', Vr12', and Vr14', and after passing the readout of Vr5', after applying a certain predetermined number of times After the programming voltage pulse, the programming is considered to be complete. In addition, it is also possible to omit the readout after the programming voltage pulses of Vr4', Vr5', Vr8', Vr9', Vr12', and Vr14' are applied, and after passing the readout of Vr1' , after a predetermined number of programming voltage pulses are applied, the programming is considered to be completed.

Fig. 11 is a flow chart showing the first example of the writing procedure in the 2nd stage. In the programming of the 2nd stage, firstly, the data of the Middle page is inputted from the memory controller 2 to the non-volatile memory 3 to start commanding (step S310). Afterwards, the data of the Middle page is input to the non-volatile memory 3 from the memory controller 2 (step S320).

Next, the memory controller 2 inputs the input data of the Upper page to the non-volatile memory 3 and starts an instruction (step S330). Afterwards, the data of the Upper page is input to the non-volatile memory 3 from the memory controller 2 (step S340). Next, a programming execution command of the 2nd stage is input to the non-volatile memory 3 from the memory controller 2 (step S350), and thus becomes chip_busy (step S360).

After that, the control unit 22 reads the data of the Lower page and the Top page which are IDL (Internal Data Load) (step S370). Afterwards, based on the previously input data of the Middle page and the data of the Lower page and Top page generated by IDL, the Vth (threshold voltage) of the programming target of the Upper page is determined (step S380 ). After that, using the determined Vth, writing of data to the Upper page is performed. More specifically, the voltage values of the plurality of programming pulses are gradually increased and written so as to become the determined threshold voltage (step S390 ). Memory cells that have reached the target threshold voltage are removed from the write target.

Afterwards, the written data is read (step S400), and it is determined whether the number of failed bits is smaller than the criteria (step S410). When the number of failed bits of the data is greater than the judgment criterion, the processing from the application of the programming pulse to the judgment of the criteria (steps S390-S410) is repeated. On the other hand, if the number of failed bits of the data is smaller than the criterion, it becomes chip_ready (step S420).

Here, in this embodiment, there are two features. The first feature is that the data on the Middle page has already been input in the stylization of the 1st stage, and the threshold area after the 1st stylization is the writing state that also includes the data on the Middle page. However, In the programming of the 2nd stage, the data of the Middle page is still input again. The second feature is that in the stylization of the 1st stage, the interval between the adjacent threshold value areas where the data of the Middle page is switched is narrowed. On the contrary, the data of the Lower page and the data of the Top page are switched. Adjacent threshold values are distributed to each other, and the interval becomes wider. Thereby, the reliability of the data of the lower page and the top page read by IDL can be improved. On the other hand, if the data on the Middle page is read out by IDL, the reliability may be lowered. However, in this embodiment, because it will be used in the 1st stage programming The information on the Middle page that has been entered is re-entered, so there will be no problem of lowering reliability.

Furthermore, the control unit 22 can also perform a plurality of readouts in order to improve the reliability of the readout data of the IDL, and use the majority decision of the readout results at the page buffer in the chip as a connection. Write down the data and use it. Of course, the control unit 22 can also perform a plurality of times of readout in normal readout operations and use the majority of the readout results within the wafer as readout data to the outside.

Fig. 12 is a diagram for explaining the majority decision processing of the reading results of plural times. In Fig. 12, as the result of reading the data of a specific page, the correct bit is marked with a circle mark (○), and the wrong bit is marked with a cross mark (×). Make a mark. In addition, in FIG. 12, the results of the majority vote are shown for the case where reading is performed three times.

At each cell, the case where the result of the majority vote is judged to be wrong is (a) the case where all three times are wrong, and (b) the case where two times are wrong. If the probability of each bit being wrong is set to p, then in the case of p=0.2, the probability of (a) 3 times of mistakes is p×p×p=0.2×0.2×0.2, (b) 2 times of mistakes The probability of , is (1-p)×p×p=(1-0.2)×0.2×0.2.

Therefore, the probability that the result of three times of majority voting is judged to be wrong is (p×p×p)+3×(1-p)×p×p=0.104. In this way, the control unit 22 can improve the reliability of the read data by performing the majority processing of the read results of a plurality of times at the page buffer 24 in the chip.

Furthermore, the control unit 22 may perform writing in response to writing in the 1st stage of WLn+1 in order to improve the reliability of reading data from the IDL that is being written in the 2nd stage of word line WLn. Data or threshold voltage to change the read voltage of the word line WLn at IDL and read.

Furthermore, the control unit 22 may also respond to the writing in the 1st stage of the word line WLn+1 in order to improve the reliability of the read data of the IDL which is being written in the 2nd stage of the word line WLn. The written data or the threshold voltage is read by changing the non-selection voltage of the word line WLn+1 at IDL. At this time, the reading voltage of the word line WLn can also be changed simultaneously to perform reading.

When writing data into the Upper page, one to a plurality of programming voltage pulses are applied. Afterwards, in order to confirm whether the memory cell has been moved beyond the threshold boundary level, data reading (verification) with the Upper page is carried out. The readout level at this time is a specific level.

Furthermore, it is judged whether the number of failed bits of the data in the Upper page is smaller than the judgment criterion. When the number of failed bits of the data in the upper page exceeds the judgment standard, the process from the application of the programming voltage pulse to the verification is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the criterion, it becomes chip_ready.

Here, a modification example of the writing procedure shown in FIG. 11 will be described. Fig. 13 is a flow chart showing a modified example of the writing process in the 2nd stage of the first embodiment. In addition, in the flow chart of FIG. 13 , it is added that "the IDL data read out of the programmed data in the 1st stage is corrected for errors and sent back to the non-volatile memory 3." program. Specifically, first, a command to read the Lower page is input from the memory controller 2 to the non-volatile memory 3 (step S510). By this, the system becomes chip_ready (step S512). Next, the control unit 22 reads the data of the lower page by using the threshold voltage of Vr8'. After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr8' (step S514). After that, the system becomes chip_ready (step S516).

If the Lower page data read by the control unit 22 is output (step S518), then the Lower page data is sent to the ECC circuit 10 (step S520). Thus, the ECC circuit 10 performs ECC correction on the data of the Lower page (step S522).

Next, an instruction to start inputting the data of the Lower page is input from the memory controller 2 to the non-volatile memory 3 (step S524). Thus, the ECC circuit 10 inputs the data of the Lower page to the non-volatile memory 3 (step S526).

Next, a command to read the Top page is input to the non-volatile memory 3 from the memory controller 2 (step S528), and thus becomes chip_busy (step S530). Afterwards, the control unit 22 reads the top page data by using the threshold voltages of Vr2' and Vr10'. Afterwards, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results at the threshold voltages of Vr1', Vr4', Vr8', and Vr12'. (step S532). Thereafter, the system becomes chip_ready (step S534).

If the Top page data read by the control unit 22 is output (step S536), then the Top page data is sent to the ECC circuit 10 (step S538). Thus, the ECC circuit 10 performs ECC correction on the top page data (step S540). Next, an input start instruction is given from the memory controller 2 to the non-volatile memory 3 with the data of the Top page input (step S542). Thus, the ECC circuit 10 inputs the data of the Top page to the non-volatile memory 3 (step S544).

Afterwards, the non-volatile memory 3 is input with an input start command of the Middle page data from the memory controller 2 . (step S546). Subsequent steps are the same as the procedure shown in FIG. 11 . The threshold voltage Vth of the stylized target is based on the data of the Lower page and the Top page from the ECC circuit 10, the data of the Middle page that has been input again, and the data of the newly input Upper page. Determines the threshold voltage Vth of the programmed target.

In the programming of the above-mentioned 2nd stage, the data input for the non-volatile memory 3 is only 2 pages of the Middle page and the Upper page. However, in this 2nd stage, at the threshold voltage Vth which is the destination of programming the memory cell, it is necessary to also include the Lower page and the Top page (threshold voltage Vth before starting the 2nd stage) ) of 4 pages of information. Therefore, in the stylization at this stage, as a pre-processing, the control unit 22 is to "first read out the Lower page data and the Top page data, and then use the input Middle page and the inputted Middle page for the data." Use the Upper page to synthesize and determine the "threshold voltage Vth" of the stylized target. In addition, the readout level during verification in the 2nd stage may also be slightly different from the readout level after writing in the 2nd stage.

Here, a comparison between the Foggy-Fine stylized processing program using 4-3-4-4 data coding and the stylized processing program of this embodiment will be described. FIG. 14A is a diagram for explaining the amount of data in the write buffer in Foggy-Fine programming using 4-3-4-4 data encoding. Fig. 14B is a diagram for explaining the amount of data in the write buffer in this embodiment. Fig. 14B shows an example of adopting 1-4-5-5 data coding.

In Fig. 14A and Fig. 14B, at the upper side, the timing table for data input and program execution of block writing is shown, and at the lower side, it is for data retention in order to write data in the buffer A schedule of the required periods is shown. In addition, in FIG. 14A and FIG. 14B , in order to simplify the description, the case where the number of word strings St in one block is 1 is shown. When the strings St are plural, the amount of data to be written into the buffer that is a multiple of the number of strings St is required.

In the case of Foggy-Fine programming of 4-3-4-4 data coding, in the Foggy stage which is the first stage, data input of 4 pages is performed, and these 4 pages The amount of stylization (stylization of the Foggy stage). Also, in the case of Foggy-Fine programming of 4-3-4-4 data coding, in the Fine stage which is the second stage, data input with the amount of 4 pages is also performed, and this Stylization of the amount of 4 pages (stylization of the Fine stage).

However, at each word line WL0, WL1, WL2, ..., until programming is started at the Fine stage, it is necessary to write the data of 4 pages written in the Foggy stage. , pre-stored in the write buffer.

In Foggy-Fine programming, similarly, in order to reduce the interference between adjacent memory cells, the data of 4 pages of Lower/Middle/Upper/Top are not continuously written. For example, after the Foggy phase for word line WL0 is performed, before the Fine phase for word line WL0 is performed, the Foggy phase for word line WL1 adjacent to word line WL0 is performed. . Also, after the Foggy phase for word line WL0 is performed, before the Fine phase for word line WL1 is performed, the Foggy phase for word line WL2 adjacent to word line WL1 is performed. . In the case of this method, it is necessary to keep the data of 4 pages of Lower/Middle/Upper/Top in the write buffer in advance until the data input of the second Fine stage is finally completed. Inside. Furthermore, in order to reduce the interference between adjacent memory cells, it is necessary to store the data at the multiple word lines WLi in the write buffer in advance. For example, when the Foggy phase is performed for word line WL2, it is necessary to keep data for 3 pages for word line WL1 and data for 3 pages for word line WL2 during the write process. into the buffer. In this way, in the case of Foggy-Fine programming of 4-3-4-4 data encoding, it is necessary to keep the data of a maximum of 8 pages in the write buffer.

As shown in FIG. 14B, in the stylization of this embodiment, for example, 1-4-5-5 data encoding is used to use 2-stage stylization. In the stylization of this embodiment, in the 1st stage, there are three pages (Lower page, Middle page, and Top page) of data input, and the stylization of these three pages (1st stylization) ). Also, in the case of programming in this embodiment, in the 2nd stage, there are two pages (Middle page and Upper page) of data input and one page of Upper page programming ( 2nd stylized).

And, at each word line WL0, WL1, WL2, ..., except for the Middle page that is input in both stages, it is only necessary to store the data in the write buffer in advance when the data is input in each stage. Yes, data can also be deleted from the write buffer if programming is started. For example, if data is input at the 1st stage, the data is stored in the write buffer. And, if programming is started at the 1st stage, the data of the Lower page and the Top page previously stored in the write buffer can also be deleted. Likewise, if data is input at the 2nd stage, the data is stored in the write buffer. And, if programming is started at the 2nd stage, all the data stored in the write buffer in advance can be deleted. Therefore, in the case of programming in this embodiment, it is necessary to hold the data in the write buffer in advance, even if it is a maximum of 4 pages of data.

In the programming of this embodiment, similarly, in order to reduce the interference between adjacent memory cells, the data of 4 pages of Lower/Middle/Upper/Top are not continuously written. For example, after the 1st phase for word line WL0 is performed, before the 2nd phase for word line WL0 is performed, the 1st phase for word line WL1 adjacent to word line WL0 is performed. . Likewise, after the 1st phase for word line WL1 is performed, before the 2nd phase for word line WL1 is performed, the 1st phase for word line WL2 adjacent to word line WL1 is performed. carry out.

In this way, in this embodiment, since the page data other than the Middle page are necessary for programming in only one stage, when the input of the data is completed, it becomes possible to write to the buffer The data in it will be deleted. Therefore, in this embodiment, the number of pages that need to be simultaneously held in the write buffer in advance needs to be only a small number.

The page data programmed to the non-volatile memory 3 is temporarily held in the write buffer in the RAM 6, and then the data is input to the non-volatile memory 3 during programming. In this embodiment, since the required capacity of the RAM 6 can be reduced, cost reduction can be achieved.

In addition, when using Foggy-Fine programming, since it is necessary to transfer data of all page data twice, it will consume time for the transfer and also consume power when more transfers are required. In the present embodiment, since data of pages other than the Middle page is individually completed with one data transfer, the transfer time and power consumption can be suppressed to about 1/2.

Here, the page reading process will be described. The method of page reading differs depending on whether the programming of the word line WLi including the page to be read is before or after writing in the 2nd stage.

In the case of writing before the 2nd stage, only the Lower page, Middle page, and Top page are valid for the recorded data. Therefore, the control unit 22 reads the data from the memory cell when the read page is the Lower page, the Middle page, and the Top page, but the other pages (specifically, the Upper page) In this case, the memory cell read operation is not performed, and control is performed to forcibly output all "1" as read data.

On the other hand, in the case of the word line WLi that has been completed until the 2nd stage, the control unit 22 reads the memory cell regardless of whether the read page is a Top/Upper/Middle/Lower page. out. In this case, since the required read voltages are different depending on what kind of page the read page is, the control unit 22 only performs the necessary read according to the selected page. out.

The specific processing procedure for page reading will be described below. Fig. 15 is the reading of the page at the word line where the stylization until the 1st stage is completed (the stylization of the 2nd stage has not yet ended) in the memory system 1 caused by the first embodiment The processing procedure is shown as a flow chart. If according to the 1-4-5-5 data coding shown in Fig. 6, then because the boundary system between the threshold value states that Lower page data changes is 1, therefore, control unit 22, is according to the threshold value The data is determined by which of the two ranges separated by the boundary is located. For example, when the threshold voltage is lower than Vr8', the control unit 22 controls to output "1" as the data of the memory cell. On the other hand, when the threshold voltage is greater than Vr8', the control unit 22 controls to output "0" as the data of the memory cell.

Also, since there are three boundaries between the threshold states that the Middle page data changes, the control unit 22 is located at the four separated by these boundaries according to the thresholds. One of the ranges determines the data. Also, since there are 4 boundaries between the threshold states that the Top page data changes, the control unit 22 is located at the 5 separated by these boundaries according to the thresholds. One of the ranges determines the data.

As shown in FIG. 15, when the word line WLi before the 2nd stage is written, the control unit 22 selects a read page (step S610). When the page to be read is a Lower page, the control unit 22 performs reading with one read voltage (step S612 ). This voltage is Vr8, but, as mentioned above, in the case of the word line before writing in the 2nd stage, as shown in FIG. 8 (T2), the system may also have a read voltage and a threshold. The spare ground of the value voltage, such as Vr8'. Afterwards, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at the threshold voltage of Vr8 (step S614).

Also, when the read page is a Middle page, the control unit 22 reads with three read voltages (steps S616, S618, and S620). This voltage is Vr4, Vr9, and Vr14 as described above, however, in the case of the word line before writing in the 2nd stage, as shown in FIG. 8 (T2), the system may also have a read The margin between the output voltage and the threshold voltage is set to Vr4', Vr9', and Vr14' instead of these, for example. Then, the control unit 22, based on the read results at the threshold voltage of Vr4, the read results at the threshold voltage of Vr9, and the read results at the threshold voltage of Vr14, converts the The value of the read data is determined to be "0" or "1" (step S622). Here, as mentioned above, since the data of the Middle page is different, the interval of the threshold value distribution is narrow, and the read margin of the Middle page is narrowed, so the value of the read data will have a significant reliability. The possibility of ground deterioration, and the Middle page data before the 2nd stage writing can also be defined as invalid. In this case, when the read page is a Middle page, the control unit 22 may perform control to forcibly output all "1" as the output data of the memory cell.

Also, when the read page is an Upper page, since the programming with the Upper page has not been performed in the 1st programming, the control unit 22 forcibly outputs all "1"s as output data. (step S624).

Also, when the read page is the Top page, the control unit 22 reads with four read voltages (steps S626 , S628 , S630 , and S632 ). This voltage is Vr1, Vr4, Vr8, and Vr12 as described above, however, in the case of the word line before writing in the 2nd stage, as shown in FIG. 8 (T2), it can also be There is a margin for the read voltage and the threshold voltage, and instead of these, Vr1', Vr4', Vr8', and Vr12' are set, respectively. Then, the control unit 22 is based on the read results at the threshold voltage of Vr1, the read results at the threshold voltage of Vr4, the read results at the threshold voltage of Vr8, and the read results at the threshold voltage of Vr12. The value of the read data is determined as "0" or "1" according to the read result under the threshold voltage (step S634).

FIG. 16A is a flow chart showing the processing procedure of page read at the word line where the programming until the 2nd stage is completed in the memory system 1 of the first embodiment. When the patterned word line WLi is completed until the 2nd stage, the control unit 22 selects a read page (step S650). When the page to be read is the Lower page, the control unit 22 reads the page using one of the threshold voltages of Vr8 (step S652). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the read result at one threshold voltage of Vr8 (step S654).

Also, when the read page is a Middle page, the control unit 22 reads the page according to the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (steps S656, S658, S660, and S662). Afterwards, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results of the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (step S664) .

Also, when the page to be read is an Upper page, the control unit 22 reads the page according to the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (steps S666, S668, S670, S672, S674 ). Afterwards, the control section 22 determines the value of the read data to be "0" or "1" based on the read results under the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (step S676).

Also, when the page to be read is the Top page, the control unit 22 reads the page according to the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12 (steps S678, S680, S682, S684, S686 ). Afterwards, the control unit 22 determines the value of the read data to be "0" or "1" based on the read results under the threshold voltages of Vr1, Vr3, Vr5, Vr7 and Vr12 (step S688).

In addition, it can be managed and identified by the memory controller 2 as to whether the programming of the word line WLi is before or after the completion of writing in the 2nd stage. In the memory system 1, since the memory controller 2 performs programmed control, as long as the memory controller 2 records the progress status in advance, the memory controller 2 can easily control the non-volatile The address of what in sexual memory 3 is a reference to the stylized state of what. In this case, the memory controller 2, when reading from the non-volatile memory 3, recognizes the programming state of the word line WLi containing the address of the target page, and issues the same The read command corresponding to the identified state. Also, as another method, it is also possible to set a flag cell at each of the word lines WLi, and write to the flag cell when writing in the 2nd stage, and corresponding to the data of the flag cell , to use the non-volatile memory 3 to manage and identify whether it is before or after the end of writing in the 2nd stage.

Hereinafter, one modification example of the page reading process will be described. The page read process by one of the modified examples can be performed only when the programming of the word line WLi including the read target page is performed after the 2nd stage of writing. In the page reading process according to one of the modified examples, when all the data of the word line to be read is read, the reading speed becomes faster, and in this point, it is effective.

The data encoding suitable for the page reading process caused by one of the modified examples is, for example, the same as that shown in FIG. 16B. Hereinafter, the read processing by one of the modified examples in the case of encoding the data will be described. In the page reading process by one of the modified examples, all the pages of the Top/Upper/Middle/Lower pages are read.

FIG. 16C is a flow chart showing the read processing procedure caused by one of the modified examples. Also, FIG. 16D is a voltage waveform diagram of the selected word line, ReadyBusy signal line, and output data line. The control unit 22 sequentially performs readout using all 15 readout voltages Vr15 - Vr1 . First, as shown in FIG. 16D , reading is performed with Vr15 being the highest voltage (step S690 ), and then reading is sequentially continued with a lower reading voltage by decreasing one step at a time. out (steps S691 to S707). When the reading required to determine the read data of each page is completed, the read data of the page can be output.

In the page reading process caused by one of the modified examples, when the reading is performed sequentially from Vr15 until the reading of Vr8 ends (step S697), the data of the Lower page is determined and becomes This data can be output (step S698). In this step S698, based on the read data by the read voltage Vr8, the data of the lower page is determined.

Next, when the reading of Vr4 ends (step S702), the data of the Middle page is determined (step S703). In this step S703, the data of the Middle page is determined based on the read data caused by the read voltages Vr4, Vr9, Vr11 and Vr14.

Next, when the reading of Vr2 ends (step S705), the data of the Upper page is determined (step S706). In this step S706 , based on the read data caused by the read voltages Vr2 , Vr6 , Vr10 , Vr13 and Vr15 , the data of the upper page is determined.

Next, when the reading of Vr1 ends (step S707), the data of the last top page is determined (step S708). In this step S708, the data of the Top page is determined based on the read data caused by the read voltages Vr1, Vr3, Vr5, Vr7 and Vr12.

In the page reading process by one of the modified examples, the delay (latency) until the data of any one page can be output is longer, but the total time for reading all four pages is , it is possible to shorten the total time compared to the case where reading is performed one page at a time as described above. As shown in FIG. 16D, the time for charging the word line from 0 to Vr15, which is a high voltage, as read preparation only needs to be spent once. The amplitude of the voltage change when changing to the next voltage is small, and the voltage becomes stable in a short time. Therefore, the standby time until the read voltage becomes stable can be shortened. Therefore, when reading is performed with all the read voltages Vr15 to Vr1, the total transition time of the selected word lines is shortened, and as a result, the total read time can be increased.

In addition, above, although the data encoding in FIG. 16B is taken as an example for explanation, basically, it can be applied to any data encoding. However, since reading is performed while changing the read voltage sequentially from the maximum voltage to the minimum voltage, the reading of the voltage required to determine the data is performed in the order of the page that is completed first. Data output is possible. Therefore, it should be noted that depending on the form of data encoding, there may be cases where the page order of Lower, Middle, Upper, and Top cannot be read.

In this way, in the first embodiment, when programming the non-volatile memory 3 (4bit/Cell NAND memory with a three-dimensional structure or a two-dimensional structure), the 1-4-5 method is used. -5 data encoding, and set the stylized stage as 2-stage system. Since it is programmed in a two-stage system in this way, the amount of data input when programming data at each stage is reduced, and the necessary writing in the memory controller 2 can be performed. The amount of buffering is suppressed. Also, since the number of threshold boundaries at each page is uniform, the deviation of the bit error rate between pages of the non-volatile memory 3 can be reduced, and the cost spent at the ECC can be reduced. reduce. Also, since data is transferred only once for each page except for one page, it is possible to suppress transfer time and power consumption.

Also, since each programming stage is executed while straddling the word line WLi, the amount of inter-adjacent cell interference with the adjacent word line WLi can be reduced. Also, since 1-4-5-5 data coding is used, the amount of change in the threshold value distribution in the 2nd programming becomes small, so that it is possible to suppress the amount of interference between adjacent cells. Also, by inputting data in one page (specifically, Middle page) in both stages, the IDL margin before the 2nd stage can be expanded, and the reliability of the writing sequence can be improved. Also, since 1-4-5-5 data encoding is used, when programming in the 1st stage, by setting the threshold boundary at the Lower page to 1, and setting the threshold at the Middle page Setting two limit values can speed up the stylization of the 1st stage, that is, the stylization of the Lower page and the Middle page. In addition, the speed-up of programming in the 1st stage can be achieved by, for example, increasing the write voltage step by step when writing and verifying repeatedly Speed up by setting a larger value than the stylization of the 2nd stage. (Second Embodiment)

In the first embodiment, although the 1-4-5-5 data coding was described as an example, various modifications of the data coding can be employed. The hardware constitution of the memory system 1 caused by the second embodiment is common to that of the memory system 1 caused by the first embodiment. Figures 17 to 25 show examples of data encoding of the memory system 1 caused by the second embodiment. The memory system 1 resulting from the second embodiment uses a data encoding other than the 1-4-5-5 data encoding.

Fig. 17 is a diagram showing an example of 1-5-4-5 data encoding. In the example of FIG. 17, the number of transitions in the threshold area at the end of the 2nd programming is a maximum of three. Here, the voltage distribution ranges of the threshold area at the end of programming in the 1st stage and the threshold area at the end of programming in the 2nd stage are not completely consistent with each other. However, in this specification, for the convenience of description, For each threshold area at the end of programming in the 1st stage, the threshold area at the end of programming in the 2nd stage that has the closest voltage distribution range is added, and it will change when the 2nd programming is performed The number of threshold regions of is called transition number. In the case of Figure 17, at the 1st stage, the data of the Lower page, Middle page, and Upper page are input and programmed, and at the 2nd stage, the data of the Top page and Middle page are input and programmed. The data on the Middle page is repeatedly input at the 1st stage and the 2nd stage. The interval between the two threshold areas that can be separated by the data value of the Middle page at the programmed end time point of the 1st stage is set to be narrower than the interval between other threshold areas.

Fig. 18 is a diagram showing an example of 1-5-4-5 data encoding. In the example of FIG. 18, the number of transitions in the threshold area at the end of the 2nd programming is a maximum of three. In the case of Figure 18, at the 1st stage, the data of the Lower page, Middle page, and Upper page are input and programmed, and at the 2nd stage, the data of the Top page and the Upper page are input and programmed. The data on the Upper page is repeatedly input at the 1st stage and the 2nd stage. At the programmed end time point of the 1st stage, the interval between the two threshold areas that can be separated by the value of the data on the Upper page is set to be narrower than the intervals between other threshold areas.

Fig. 19 is a diagram showing an example of 3-5-2-5 data encoding. In the example of FIG. 19, the number of transitions in the threshold area at the end of the 2nd programming is a maximum of three. In the case of Figure 19, at the 1st stage, the data of the Lower page, Middle page, and Upper page are input and programmed, and at the 2nd stage, the data of the Top page and Middle page are input and programmed. The data on the Middle page is repeatedly input at the 1st stage and the 2nd stage. The interval between the two threshold areas that can be separated by the data value of the Middle page at the programmed end time point of the 1st stage is set to be narrower than the interval between other threshold areas.

Fig. 20 is a diagram showing an example of 3-3-4-5 data encoding. In the example of FIG. 20, the number of transitions in the threshold area at the end of the 2nd programming is a maximum of three. In the case of Figure 20, at the 1st stage, the data of the Lower page, Middle page, and Upper page are input and programmed, and at the 2nd stage, the data of the Top page and the Upper page are input and programmed.

Fig. 21 is a diagram showing an example of 2-3-5-5 data encoding. In the example of FIG. 21, the number of transitions in the threshold area at the end of the 2nd programming is a maximum of five. In the case of Figure 21, at the 1st stage, the data of the Lower page, Middle page, and Top page are input and programmed, and at the 2nd stage, the data of the Top page and the Upper page are input and programmed. The data on the Top page is repeatedly input at the 1st stage and the 2nd stage. In the case of Fig. 21, at the time point when the stylization of the 1st stage ends, no matter whether the data on the Top page is 0 or 1, the three threshold value areas are all the same, and the total number of threshold value areas becomes 5. Therefore, it is possible to widen the interval between the respective threshold value regions, and it is possible to accurately perform data reading at the time point when programming in the 1st stage is completed.

Fig. 22 is a diagram showing an example of 3-2-5-5 data encoding. In the example of FIG. 22, the number of transitions in the threshold area at the end of the 2nd programming is a maximum of five. In the case of Figure 22, at the 1st stage, the data of the Lower page, Middle page, and Top page are input and programmed, and at the 2nd stage, the data of the Top page and the Upper page are input and programmed. The data on the Top page is repeatedly input at the 1st stage and the 2nd stage. In the case of Fig. 22, at the time point when the stylization of the 1st stage ends, regardless of whether the data on the Top page is 0 or 1, the two threshold areas are all the same, and the total number of threshold areas becomes 6.

Fig. 23 is a diagram showing an example of 3-4-4-4 data encoding. In the example of FIG. 23, the number of transitions in the threshold area at the end of the 2nd programming is a maximum of seven. In the case of Figure 23, at the 1st stage, the data of the Lower page, Middle page, and Upper page are input and programmed, and at the 2nd stage, the data of the Top page and the Upper page are input and programmed. The data on the Upper page is repeatedly input at the 1st stage and the 2nd stage. At the programmed end time point of the 1st stage, the interval between the two threshold areas that can be separated by the value of the data on the Upper page is set to be narrower than the intervals between other threshold areas.

Fig. 24 is a diagram showing an example of 3-4-4-4 data encoding. In the example of FIG. 24, the number of transitions in the threshold area at the end of the 2nd programming is a maximum of eight. In the case of Figure 24, at the 1st stage, the data of the Lower page, Middle page, and Top page are input and programmed, and at the 2nd stage, the data of the Top page and the Upper page are input and programmed. The data on the Top page is repeatedly input at the 1st stage and the 2nd stage. In the case of Fig. 24, at the point in time when the stylization of the 1st stage ends, regardless of whether the data on the Top page is 0 or 1, the two threshold areas are all the same, and the total number of threshold areas becomes 6.

Figures 17 to 24 are just examples of data coding, and other data coding can also be used.

For example, there are examples in which the number of transitions in the threshold value region at the end of the 2nd programming is a maximum of three, in addition to Figs. 17 to 20, there are also the following Figs. 25 to 27. Fig. 25 is a diagram showing an example of 1-4-5-5 data encoding. In the example of FIG. 25, at the time point when the 1st programming is completed, six different threshold value areas are generated. Among them, the threshold area where the Middle page is 1 and the Lower page is 1, and the threshold area where the Middle page is 0 and the Lower page is 1, are the same threshold regardless of whether the Top page is 0 or 1 area. Therefore, although 8 threshold regions should have been generated, they are aggregated into 6 threshold regions.

Fig. 26 is a diagram showing an example of 2-5-3-5 data encoding. In the example of FIG. 26, seven different threshold value regions are generated at the time when the 1st programming is completed. Among them, the threshold area where the Middle page is 1 and the Lower page is 1, no matter whether the Top page is 0 or 1, it becomes the same threshold area. Therefore, although there should have been 8 threshold regions generated, they were aggregated into 7 threshold regions.

Fig. 27 is a diagram showing an example of 3-4-5-3 data encoding. In the example of FIG. 27, seven different threshold value regions are generated at the time when the 1st programming is completed. Among them, the threshold area where the Middle page is 1 and the Lower page is 1, no matter whether the Top page is 0 or 1, it becomes the same threshold area. Therefore, although there should have been 8 threshold regions generated, they were aggregated into 7 threshold regions.

In addition, other examples of data encoding can also be considered. In the following, the code distribution for each data coding will be shown as a chart. Figure 28 shows one example of 3-2-5-5 data coding, Figure 29 shows one example of 3-2-5-5 data coding, and Figure 30 shows 1-5-5 One example of -4 data encoding is shown. Again, Fig. 31 shows for one example of 1-5-4-5 data coding, and Fig. 32 shows for one example of 1-4-5-5 data coding, and Fig. 33 shows for 1-5 One example of -3-6 data encoding is shown. Again, Fig. 34 shows for one example of 1-3-6-5 data coding, and Fig. 35 shows for one example of 1-2-6-6 data coding, and Fig. 36 shows for 1-2 One of the examples of -6-6 data encoding is shown.

Again, Fig. 37 shows for one example of 1-2-6-6 data coding, and Fig. 38 shows for one example of 1-4-6-4 data coding, and Fig. 39 shows for 1-4 One example of -4-6 data encoding is shown. Again, Fig. 40 shows for one example of 1-4-6-4 data coding, and Fig. 41 shows for one example of 1-4-4-6 data coding, and Fig. 42 shows for 2-5 One example of -2-6 data encoding is shown. Again, Fig. 43 shows for one example of 2-5-2-6 data coding, and Fig. 44 shows for one example of 2-5-2-6 data coding, and Fig. 45 shows for 3-3 One example of -3-6 data encoding is shown. Again, Fig. 46 shows for one example of 3-3-6-3 data coding, and Fig. 47 shows for one example of 2-3-4-6 data coding, and Fig. 48 shows for 3-4 One example of -2-6 data encoding is shown.

Again, Fig. 49 shows for one example of 2-3-4-6 data coding, and Fig. 50 shows for one example of 3-2-6-4 data coding, and Fig. 51 shows for 3-2 One example of -4-6 data encoding is shown. Again, Fig. 52 shows one example of 3-2-6-4 data coding, Fig. 53 shows one example of 3-4-2-6 data coding, Fig. 54 shows 3-2 One example of -4-6 data encoding is shown. Again, Fig. 55 shows for one example of 5-3-2-5 data coding, and Fig. 56 shows for one example of 3-5-2-5 data coding, and Fig. 57 shows for 3-2 One example of -5-5 data encoding is shown. Again, Fig. 58 shows for one example of 2-3-5-5 data coding, and Fig. 59 shows for one example of 2-3-5-5 data coding, and Fig. 60 shows for 2-3 One example of -5-5 data encoding is shown.

Again, Fig. 61 shows for one example of 5-4-2-4 data coding, and Fig. 62 shows for one example of 4-5-2-4 data coding, and Fig. 63 shows for 5-4 One example of -2-4 data encoding is shown. Again, Fig. 64 shows for one example of 2-4-5-4 data coding, and Fig. 65 shows for one example of 2-4-5-4 data coding, and Fig. 66 shows for 2-5 One of the examples of -4-4 data encoding is shown. Again, Fig. 67 shows for one example of 2-5-4-4 data coding, and Fig. 68 shows for one example of 2-5-4-4 data coding, and Fig. 69 shows for 1-5 One of the examples of -4-5 data coding is shown. Again, Fig. 70 shows for one example of 1-4-5-5 data coding, and Fig. 71 shows for one example of 1-5-5-4 data coding, and Fig. 72 shows for 1-4 One example of -5-5 data encoding is shown.

Again, Fig. 73 shows for one example of 1-5-5-4 data coding, and Fig. 74 shows for one example of 1-5-4-5 data coding, and Fig. 75 shows for 1-5 One example of -5-4 data encoding is shown. Again, Fig. 76 shows for one example of 1-5-4-5 data coding, and Fig. 77 shows for one example of 1-4-5-5 data coding, and Fig. 78 shows for 1-4 One example of -5-5 data encoding is shown. Again, Fig. 79 shows for one example of 1-4-5-5 data coding, and Fig. 80 shows for one example of 1-4-5-5 data coding, and Fig. 81 shows for 3-5 One example of -4-3 data encoding is shown. Again, Fig. 82 shows for one example of 3-4-5-3 data coding, and Fig. 83 shows for one example of 3-5-3-4 data coding, and Fig. 84 shows for 3-4 One example of -3-5 data encoding is shown.

Again, Fig. 85 shows for one example of 3-4-5-3 data coding, and Fig. 86 shows for one example of 3-4-3-5 data coding, and Fig. 87 shows for 3-3 One example of -5-4 data encoding is shown. Again, Fig. 88 shows for one example of 3-3-5-4 data coding, and Fig. 89 shows for one example of 4-5-3-3 data coding, and Fig. 90 shows for 3-5 One example of -4-3 data encoding is shown. Again, Fig. 91 shows for one example of 3-4-5-3 data coding, and Fig. 92 shows for one example of 3-3-4-5 data coding, and Fig. 93 shows for 3-3 One of the examples of -4-5 data coding is shown.

Again, Fig. 94 shows for one example of 3-3-4-5 data coding, and Fig. 95 shows for one example of 3-4-5-3 data coding, and Fig. 96 shows for 3-3 One example of -5-4 data encoding is shown. Again, Fig. 97 shows for one example of 3-3-4-5 data coding, and Fig. 98 shows for one example of 4-3-4-4 data coding, and Fig. 99 shows for 3-4 One of the examples of -4-4 data encoding is shown. Again, Fig. 100 shows for one example of 3-4-4-4 data coding, and Fig. 101 shows for one example of 4-3-4-4 data coding, and Fig. 102 shows for 3-4 One of the examples of -4-4 data encoding is shown. Again, Fig. 103 shows one example of 3-4-4-4 data coding, Fig. 104 shows one example of 3-4-4-4 data coding, and Fig. 105 shows 3-4 One of the examples of -4-4 data encoding is shown. Also, Fig. 106 shows one example of 4-4-3-4 data coding, and Fig. 107 shows one example of 4-4-3-4 data coding.

In this way, by repeatedly inputting the data of some pages at the 1st stage and the 2nd stage, and inputting the data of other pages only at one of the 1st stage and the 2nd stage, it is programmed, The system can reduce the mutual interference between cells, and can also reduce the capacity of the write buffer, and can also suppress the deviation of the bit error rate when writing each bit of metadata. In particular, in the case of 1-4-5-5, 1-5-4-5, 3-3-4-5 or 3-5-2-5 data encoding, due to the boundary number system of each page data It is uniform, and the number of transitions in the threshold region during the programming of the 2nd stage is 3 or less, so it can suppress the bias of the bit error rate and reduce the interference between cells. (third embodiment)

In the memory system 1 resulting from the third embodiment, the capacity of the write buffer is further reduced compared with the first and second embodiments.

The hardware configuration of the memory system 1 caused by the third embodiment is common to the memory system 1 caused by the first and second embodiments. In the third embodiment, the data of the page that is repeatedly input in the programming of the 1st stage and also input in the programming of the 2nd stage is kept in the non-volatile memory after the programming of the 1st stage starts. In the page buffer 24 inside the body 3. Thereby, in the programming of the 2nd stage, it becomes possible to omit the process of inputting the data of the page, and it becomes possible to input the data of all the pages only once. By this, the capacity of the write buffer can be reduced.

Furthermore, in this embodiment, the programming of the 2nd stage of the word line WLn-1 and the programming of the 1st stage of the word line WLn are integrated and performed. In this way, the page buffer 24 is the bit that will be repeatedly input when programming in the 1st stage and 2nd stage in the 1st to 4th bits (Lower page, Middle page, Upper page, Top page) The meta data is memorized before the programming of the 1st stage is started, and it can be discarded or invalidated after the programming of the 2nd stage is started. Hereinafter, also in this embodiment, an example using the same 1-4-5-5 data encoding as that described in FIG. 6 of the first embodiment will be described.

In the stylized flow chart shown in Figure 9, the stylization of the 1st stage and the stylization of the 2nd stage make the execution timing offset from each other. When each of the stylization is programmed, it is necessary to carry out each of the stylized instructions and stylized data input. On the other hand, in this embodiment, the programming instruction and programming data input of the programming of the 1st stage and the programming of the 2nd stage are integrated as much as possible.

For example, as shown in FIG. 8B, the stylization of the 1st phase of word line WLn and the 2nd phase of word line WLn-1 is absolutely continuous except for the beginning and end of the block. Therefore, in this embodiment, this part is set as an integrated command input. That is, with one instruction input, the programming data of the Lower page, Middle page, Top page, and Upper page of the word line WLn-1 are input in batches. This is to make the data of the Lower/Middle/Upper/Top pages batched by one programming command when using Foggy-Fine (however, in this case, it is the same character The page in the line WLi) made the input of the amount of 4 pages and the input of the same amount of data.

In this way, by integrating the input of stylized commands and stylized data, the command input and polling in the control performed by the memory controller 2 (regularity of whether the chip busy returns to ready The frequency of checking) is reduced, and the high speed of the memory system 1 and the simplification of control become possible.

Here, an example of the write procedure in accordance with the programming order according to the third embodiment will be described using FIG. 108 and FIG. 109 . In FIG. 108 and FIG. 109, the writing process is shown for the case where the stylized sequence shown in FIG. 8B is followed.

Fig. 108 is a flow chart showing the entire write procedure for one block by the third embodiment. Here, one block is assumed to have n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). As shown in FIG. 108, if writing is started (step S710), then the programming process of the 1st stage of word line WL0 of word strings St0-St3 is performed (step S712). As a result, the control unit 22 executes the programming of the 1st stage of the word line WL0 of the word strings St0 to St3 (step S714 ).

Furthermore, the control unit 22 executes the programming of the 1st stage of the word string St0_word line WL1 and the programming of the 2nd stage of the word string St0_word line WL0 (step S716).

Next, the control unit 22 implements the programming of the 1st stage of the word string St1_word line WL1 and the programming of the 2nd stage of the word string St1_word line WL0 (step S718). Next, the control unit 22 implements the programming of the 1st stage of the word string St2_word line WL1 and the programming of the 2nd stage of the word string St2_word line WL0 (step S720). Thereafter, the control unit 22 repeats the same processing for each word line WLi of each word string.

Next, the programming of the 1st stage of the word string St0_word line WLn and the programming of the 2nd stage of the word string St0_word line WLn-1 are implemented (step S722). Next, the control unit 22 implements the programming of the 1st stage of the word string St1_word line WLn and the programming of the 2nd stage of the word string St1_word line WLn-1 (step S724). Thereafter, the control unit 22 repeats the same processing for each word line WLi of each word string.

Next, the control unit 22 implements the programming of the 1st stage of the word string St3_word line WLn and the programming of the 2nd stage of the word string St3_word line WLn-1 (step S726). Next, the control unit 22 implements programming in the 2nd stage of the word line WLn of the word strings St0-St3 (steps S728, S730, S732).

In this way, at the beginning of the block, only the stylization of the 1st stage is implemented in the same way as in the first embodiment, and at the end of the block, it is implemented in the same way as in the first embodiment. The stylization of the 2nd stage. In this case, only the programming of the 1st stage is carried out following the procedure shown in FIG. 8B, and only the programming of the 2nd stage is carried out following the procedure shown in FIG. 8C. In addition, in the flow chart of FIG. 108, except for the beginning and the end of the block, the programming of the 1st stage of the word line WLn and the programming of the 2nd stage of the word line WLn-1 are integrated and carried out. . As a result, the frequency of command input and polling performed by the memory controller 2 is reduced, and the processing of the memory system 1 can be accelerated.

Fig. 109 is a flow chart showing the writing procedure in the 1st stage and the 2nd stage of the third embodiment. As shown in FIG. 109, in the stylization of the 1st stage and the stylization of the 2nd stage, after the stylization of the 1st stage is carried out, then the stylization of the 2nd stage is carried out. Specifically, firstly, the memory controller 2 starts the input of the data of the Upper page of the word line WLn-1 inputted to the non-volatile memory 3 (step S750). Afterwards, the data of the Upper page of the word line WLn-1 is input to the non-volatile memory 3 from the memory controller 2 (step S752).

Next, an instruction to start inputting the data of the Lower page in which the word line WLn is input from the memory controller 2 to the non-volatile memory 3 (step S754). Afterwards, the data of the Lower page of the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S756).

Next, an instruction to start inputting the data of the Middle page in which the word line WLn is inputted from the memory controller 2 to the non-volatile memory 3 (step S758). After that, the data of the Middle page with the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S760). The data of the Middle page is not only input to the non-volatile memory 3, but also stored in the page buffer 24. After being stored in the page buffer 24, the Middle data written in the buffer can be discarded or invalidated.

Next, an input start instruction is given from the memory controller 2 to the non-volatile memory 3 with respect to the data of the Top page in which the word line WLn is input (step S762). Afterwards, the data of the Top page with the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S764).

Next, the programming execution command of the 1st stage and the 2nd stage is input to the non-volatile memory 3 from the memory controller 2 (step S766), and thus becomes chip_busy (step S768).

Afterwards, one to a plurality of programming voltage pulses are applied to the Lower page, Middle page, and Top page of the word line WLn (step S770 ). Afterwards, in order to confirm whether the memory cell has been moved beyond the threshold boundary level, the data of the Lower page and the Top page with the word line WLn are read (step S772).

Furthermore, it is confirmed whether the number of failed bits of the data in the Lower page and the Top page is smaller than the criterion (step S774). When the number of failed bits of the data in the Lower page and the Top page is above the criterion, the processing of steps S770-S774 is repeated. And, if the number of failed bits of the data becomes smaller than the judgment standard, the data of the Lower page and the Top page of the word line WLn-1 are read (step S776).

Then, based on the data of the Lower and Top pages of the word line WLn-1 and the data of the Middle page read from the page buffer 24, the threshold voltage Vth of the programming target of the Upper page is determined (step S778). Then, using the determined threshold voltage Vth, data writing to the upper page of the word line WLn-1 is performed (step S780).

When writing data on the upper page, one to a plurality of programming voltage pulses are applied to the upper page of the word line WLn-1. Afterwards, in order to confirm whether the memory cell has been moved beyond the threshold boundary level, the data of the Upper page with the word line WLn-1 is read (step S782).

Furthermore, a verification is performed to determine whether the number of failed bits of the data in the Upper page is smaller than the determination criterion (step S784). When the number of failed bits of the data in the upper page is above the judgment standard, the processing of programming voltage pulse application, data readout and verification is repeated. On the other hand, if the number of failed bits of the data is smaller than the criterion, it becomes chip_ready (step S786).

In addition, in the programming of the 1st stage for the same character line, the order of the data input start command on the plural pages and the pages in the data input processing is arbitrary, no matter which page is input first. In addition, in the programming of the 2nd stage for the same word line, the order of the data input start command and the pages in the data input processing on plural pages is also arbitrary. However, the order of the respective word line numbers and the programming process of the two stages is absolutely required to be the order shown in FIG. 109 .

In this way, in FIG. 109, the case where the 1st stage programming of the word line WLn is performed before the 2nd stage programming of the word line WLn-1 will be described. This is to prevent the cell of the word line WLn-1 in which the 16-value threshold voltage Vth is written from being affected by adjacent cells by making the programming of the 1st stage of the word line WLn be performed first. because of the influence.

As mentioned above, in this embodiment, the data of the Upper page of the word line WLn-1 and the data of 4 pages of the data of the Lower page, Middle page and Top page of the word line WLn are continuously obtained. enter.

Also, as another modified example, after the input of the programmed command, as IDL, after the reading of the data of the Lower page, Middle page and Top page of the word line WLn-1 is carried out, the The programming of the Lower page, Middle page and Top page of the word line WLn, then, the threshold voltage Vth of the programming target of the Upper page of the word line WLn-1 is determined, and by the determined Threshold voltage Vth is used to program the upper page of word line WLn-1. If this configuration is adopted, the Lower page, Middle page, and Top page of the word line WLn-1 of the IDL can be performed before being affected by the interference between adjacent cells caused by the writing of the word line WLn. The readout of the data.

In addition, in this embodiment, the programmed actual execution order caused by the integrated commands of the 1st stage of the word line WLn and the 2nd stage of the word line WLn-1 can be modified. That is, the stylization of the Lower page, the Middle page, and the Top page of the word line WLn shown in FIG. No matter which one comes first, it can be exchanged. By reading the data of the Lower page, Middle page, and Top page of word line WLn-1 before programming the Lower page, Middle page, and Top page of word line WLn, it becomes possible and IDL is performed under the influence of the stylization of the Lower page, Middle page, and Top page resulting from the word line WLn.

In this way, in the third embodiment, since the programming of the 2nd stage of the word line WLn-1 and the programming of the 1st stage of the word line WLn are integrated, the command input and polling The frequency is reduced. Therefore, it becomes possible to increase the speed of the memory system 1 and to simplify the control.

Fig. 110 is a diagram for explaining the write buffer amount (buffer data amount) in programming in the third embodiment. In the present embodiment, 1-4-5-5 data encoding is used and programming with two stages is used. In the stylization of this embodiment, in the 1st stage, there are three pages (Lower page, Middle page, and Top page) of data input, and the stylization of these three pages (1st stylization) ). Also, in the case of programming in this embodiment, in the 2nd stage, there is data input for one page (Upper page), and programming for one page of the Upper page (2nd programming ).

However, at each word line WL0, WL1, WL2, ..., it is only necessary to store the data in the write buffer in advance when the data is input at each stage. If programming is started, the data can also be read from Write to buffer and delete. For example, if data is input at the 1st stage, the data is stored in the write buffer. And, if programming is started at the 1st stage, the data of the Lower page, Top page, and Middle page previously stored in the write buffer can also be deleted. However, since the data of the Middle page is also used at the 2nd stage, it is necessary to store it in the page buffer 24 until the programming at the 2nd stage is started. Likewise, if data is input at the 2nd stage, the data is stored in the write buffer. And, if programming is started at the 2nd stage, all the data stored in the write buffer in advance can be deleted. Therefore, in the case of programming in this embodiment, the data that must be kept in the write buffer in advance, even if it is the data of the maximum amount of 3 pages, can be changed more than that of the first embodiment. for reduction.

In the programming of this embodiment, similarly, in order to reduce the interference between adjacent memory cells, the data of 4 pages of Lower/Middle/Upper/Top are not continuously written. For example, after the 1st phase for word line WL0 is performed, before the 2nd phase for word line WL0 is performed, the 1st phase for word line WL1 adjacent to word line WL0 is performed. . Likewise, after the 1st phase for word line WL1 is performed, before the 2nd phase for word line WL1 is performed, the 1st phase for word line WL2 adjacent to word line WL1 is performed. carry out.

In this way, in this embodiment, since all the page data are necessary for programming in only one stage, when the input of the data is completed, it becomes the data that can be written into the buffer delete. Therefore, in this embodiment, the number of pages that need to be simultaneously held in the write buffer in advance is only required to be less than that in the first embodiment.

The page data programmed to the non-volatile memory 3 is temporarily held in the write buffer in the RAM 6, and then the data is input to the non-volatile memory 3 during programming. In this embodiment, since the required capacity of the RAM 6 can be reduced, the cost can be reduced.

Also, in this embodiment, since it is completed by one data transfer of each of the pages, compared with the first embodiment, only less page data transfer time is required, and It becomes possible to reduce power consumption during transmission.

The page read processing in this embodiment is the same as the processing procedure described in the first embodiment, and therefore its description is omitted.

In addition, in this embodiment, the page buffer 24 inside the NAND flash memory needs to be increased for new page data that needs to be kept. In the programming of the NAND flash memory in which there is one character string in the block as shown in FIG. 8A , the amount of page buffer 24 that needs to be added is the amount of data of one page. . In contrast to this, in the programming of the NAND flash memory that generally has 4 strings in the block as shown in FIG. 8B or FIG. 8C, the amount of page buffer 24 that needs to be increased is: The amount of data for 4 pages. This is because, during the period from the 1st stage programming of a certain character string to the 2nd stage programming of the same character string, it is necessary to execute the 1st stage programming of the other three character strings. As a result, it is necessary to hold data corresponding to one page for all four character strings.

In the present embodiment, although the 1-4-5-5 data coding is used as an example to explain, various modifications of the data coding can be adopted, and it is obvious that the above-mentioned embodiment can be realized.

In the above-mentioned first to third embodiments, although the description has been made on the use of the NAND memory 5 to form the non-volatile memory 3, a ReRAM (Resistive Random Access Memory) may also be used. Or MRAM6 (Magneto-Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FeRAM (Ferroeletric Random Access Memory) and other types of non-volatile memory 3 .

In the above-mentioned first to third embodiments, although it is aimed at writing the data of 3 pages in the programming of the 1st stage, the writing of data of 2 pages in the programming of the 2nd stage The writing of data has been described, but it is also possible to change the allocation of the number of pages in programming in the 1st stage and the number of pages in programming in the 2nd stage. For example, the system may be configured such that two pages of data are written in programming at the 1st stage, and data for three pages are written in the programming at the 2nd stage.

Although several embodiments of the present disclosure have been described, these embodiments are only presented as examples and are not intended to limit the scope of the present invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are also included in the scope or gist of the invention, and are also included in the inventions described in the claims and their equivalent scopes.

1: Memory system 2: Memory controller 3: Non-volatile memory 4: Host Processor 5: NAND memory 6: RAM 7:ROM 8: Processor 9: Host interface 10: ECC circuit 11: Memory interface 12:Internal busbar 21:NAND I/O interface 22: Control Department 23: NAND memory cell array 24: Page buffering 31: Oscillator 32: Sequencer 33:Command user interface 34: Voltage supply part 35: column counter 36: Serial access controller 37: row decoder 38: Sense amplifier 41: p-well area 42,43,44: wiring layer 45: memory hole 46: block insulating film 47: Charge storage layer 48: Gate insulating film 49: Conductive film

[FIG. 1] is a block diagram showing a schematic configuration of a memory system according to the first embodiment. [FIG. 2] It is a block diagram showing an example of the internal structure of the non-volatile memory of this embodiment. [FIG. 3] is a circuit diagram showing an example of a 3-dimensional NAND memory cell array. [ Fig. 4 ] is a cross-sectional view of a part of a NAND memory cell array of a NAND memory having a three-dimensional structure. [ Fig. 5 ] is a diagram showing an example of the threshold value region in the first embodiment. [FIG. 6A] is a diagram showing an example of data encoding in the first embodiment. [FIG. 6B] is a diagram showing another example of data encoding in the first embodiment. [ Fig. 7 ] is a diagram showing the stylized threshold value region in the first embodiment. [FIG. 8A] is a diagram showing a first example of the stylized sequence of the first embodiment. [FIG. 8B] is a diagram showing a second example of the stylized sequence of the first embodiment. [FIG. 8C] is a diagram showing a third example of the stylized sequence of the first embodiment. [ Fig. 9 ] is a flow chart showing a first example of the entire write procedure for one block by the first embodiment. [ Fig. 10 ] is a flow chart showing the writing procedure in the 1st stage by the first embodiment. [FIG. 11] is a flow chart showing the first example of the write procedure in the 2nd stage. [FIG. 12] It is a figure for explaining the majority decision processing of the reading result of a plural number of times. [ Fig. 13 ] is a flow chart showing a modified example of the writing procedure in the 2nd stage of the first embodiment. [FIG. 14A] is a diagram for explaining the amount of data in the write buffer in Foggy-Fine programming using 4-3-4-4 data encoding. [FIG. 14B] is a diagram for explaining the amount of data in the write buffer in this embodiment. [FIG. 15] It is a flow chart which shows the processing procedure of the page read at the word line which programmed until the 1st stage was completed. [FIG. 16A] is a flow chart showing a processing procedure for page read at a word line where programming ends until the 2nd stage. [FIG. 16B] is a diagram showing data encoding suitable for the page reading process by one of the modified examples. [FIG. 16C] is a flow chart showing the read processing procedure caused by one of the modified examples. [FIG. 16D] is a voltage waveform diagram for selecting word lines, ReadyBusy signal lines, and output data lines. [Fig. 17] is a diagram showing an example of 1-5-4-5 data coding. [Fig. 18] is a diagram showing an example of 1-5-4-5 data coding. [Fig. 19] is a diagram showing an example of 3-5-2-5 data coding. [Fig. 20] is a diagram showing an example of 3-3-4-5 data coding. [Fig. 21] is a diagram showing an example of 2-3-5-5 data coding. [Fig. 22] is a diagram showing an example of 3-2-5-5 data coding. [Fig. 23] is a diagram showing an example of 3-4-4-4 data coding. [Fig. 24] is a diagram showing an example of 3-4-4-4 data encoding. [Fig. 25] is a diagram showing an example of 1-4-5-5 data coding. [Fig. 26] is a diagram showing an example of 2-5-3-5 data coding. [Fig. 27] is a diagram showing an example of 3-4-5-3 data coding. [Fig. 28] is a diagram showing an example of 3-2-5-5 data coding. [Fig. 29] is a diagram showing an example of 3-2-5-5 data coding. [Fig. 30] is a diagram showing an example of 1-5-5-4 data coding. [Fig. 31] is a diagram showing an example of 1-5-4-5 data coding. [Fig. 32] is a diagram showing an example of 1-4-5-5 data coding. [Fig. 33] is a diagram showing an example of 1-5-3-6 data coding. [Fig. 34] is a diagram showing an example of 1-3-6-5 data coding. [Fig. 35] is a diagram showing an example of 1-2-6-6 data coding. [Fig. 36] is a diagram showing an example of 1-2-6-6 data coding. [Fig. 37] is a diagram showing an example of 1-2-6-6 data coding. [Fig. 38] is a diagram showing an example of 1-4-6-4 data encoding. [Fig. 39] is a diagram showing an example of 1-4-4-6 data coding. [Fig. 40] is a diagram showing an example of 1-4-6-4 data coding. [Fig. 41] is a diagram showing an example of 1-4-4-6 data coding. [Fig. 42] is a diagram showing an example of 2-5-2-6 data coding. [Fig. 43] is a diagram showing an example of 2-5-2-6 data coding. [Fig. 44] is a diagram showing an example of 2-5-2-6 data coding. [Fig. 45] is a diagram showing an example of 3-3-3-6 data coding. [Fig. 46] is a diagram showing an example of 3-3-6-3 data coding. [Fig. 47] is a diagram showing an example of 2-3-4-6 data coding. [Fig. 48] is a diagram showing an example of 3-4-2-6 data coding. [Fig. 49] is a diagram showing an example of 2-3-4-6 data coding. [Fig. 50] is a diagram showing an example of 3-2-6-4 data coding. [Fig. 51] is a diagram showing an example of 3-2-4-6 data coding. [Fig. 52] is a diagram showing an example of 3-2-6-4 data coding. [Fig. 53] is a diagram showing an example of 3-4-2-6 data coding. [Fig. 54] is a diagram showing an example of 3-2-4-6 data coding. [Fig. 55] is a diagram showing an example of 5-3-2-5 data coding. [Fig. 56] is a diagram showing an example of 3-5-2-5 data coding. [Fig. 57] is a diagram showing an example of 3-2-5-5 data coding. [Fig. 58] is a diagram showing an example of 2-3-5-5 data coding. [Fig. 59] is a diagram showing an example of 2-3-5-5 data encoding. [Fig. 60] is a diagram showing an example of 2-3-5-5 data encoding. [Fig. 61] is a diagram showing an example of 5-4-2-4 data encoding. [Fig. 62] is a diagram showing an example of 4-5-2-4 data encoding. [Fig. 63] is a diagram showing an example of 5-4-2-4 data coding. [Fig. 64] is a diagram showing an example of 2-4-5-4 data encoding. [Fig. 65] is a diagram showing an example of 2-4-5-4 data encoding. [Fig. 66] is a diagram showing an example of 2-5-4-4 data encoding. [Fig. 67] is a diagram showing an example of 2-5-4-4 data encoding. [Fig. 68] is a diagram showing an example of 2-5-4-4 data encoding. [Fig. 69] is a diagram showing an example of 1-5-4-5 data coding. [Fig. 70] is a diagram showing an example of 1-4-5-5 data coding. [Fig. 71] is a diagram showing an example of 1-5-5-4 data coding. [Fig. 72] is a diagram showing an example of 1-4-5-5 data coding. [Fig. 73] is a diagram showing an example of 1-5-5-4 data coding. [Fig. 74] is a diagram showing an example of 1-5-4-5 data coding. [Fig. 75] is a diagram showing an example of 1-5-5-4 data coding. [Fig. 76] is a diagram showing an example of 1-5-4-5 data coding. [Fig. 77] is a diagram showing an example of 1-4-5-5 data coding. [Fig. 78] is a diagram showing an example of 1-4-5-5 data coding. [Fig. 79] is a diagram showing an example of 1-4-5-5 data coding. [Fig. 80] is a diagram showing an example of 1-4-5-5 data coding. [Fig. 81] is a diagram showing an example of 3-5-4-3 data coding. [Fig. 82] is a diagram showing an example of 3-4-5-3 data coding. [Fig. 83] is a diagram showing an example of 3-5-3-4 data encoding. [Fig. 84] is a diagram showing an example of 3-4-3-5 data coding. [Fig. 85] is a diagram showing an example of 3-4-5-3 data encoding. [Fig. 86] is a diagram showing an example of 3-4-3-5 data coding. [Fig. 87] is a diagram showing an example of 3-3-5-4 data encoding. [Fig. 88] is a diagram showing an example of 3-3-5-4 data coding. [Fig. 89] is a diagram showing an example of 4-5-3-3 data coding. [Fig. 90] is a diagram showing an example of 3-5-4-3 data coding. [Fig. 91] is a diagram showing an example of 3-4-5-3 data coding. [Fig. 92] is a diagram showing an example of 3-3-4-5 data coding. [Fig. 93] is a diagram showing an example of 3-3-4-5 data coding. [Fig. 94] is a diagram showing an example of 3-3-4-5 data encoding. [Fig. 95] is a diagram showing an example of 3-4-5-3 data coding. [Fig. 96] is a diagram showing an example of 3-3-5-4 data encoding. [Fig. 97] is a diagram showing an example of 3-3-4-5 data coding. [Fig. 98] is a diagram showing an example of 4-3-4-4 data encoding. [Fig. 99] is a diagram showing an example of 3-4-4-4 data coding. [Fig. 100] is a diagram showing an example of 3-4-4-4 data coding. [Fig. 101] is a diagram showing an example of 4-3-4-4 data coding. [Fig. 102] is a diagram showing an example of 3-4-4-4 data coding. [Fig. 103] is a diagram showing an example of 3-4-4-4 data coding. [Fig. 104] is a diagram showing an example of 3-4-4-4 data encoding. [Fig. 105] is a diagram showing an example of 3-4-4-4 data coding. [Fig. 106] is a diagram showing an example of 4-4-3-4 data encoding. [Fig. 107] is a diagram showing an example of 4-4-3-4 data coding. [FIG. 108] is a flow chart showing the entire write procedure for one block in the third embodiment. [FIG. 109] is a flow chart showing the writing procedure in the 1st stage and the 2nd stage of the third embodiment. [ Fig. 110 ] is a diagram for explaining the amount of write buffer in programming in the third embodiment.

2: Memory controller

3: Non-volatile memory

4: Host Processor

5: NAND memory

6: RAM

7:ROM

8: Processor

9: Host interface

10: ECC circuit

11: Memory interface

12:Internal busbar

Claims (16)

A memory system comprising a non-volatile semiconductor memory device and a memory controller, The non-volatile semiconductor memory device includes: The first to nth character strings respectively have a plurality of memory cells and selection transistors connected in series with the plurality of memory cells, the plurality of memory cells are connected in series, and Respectively by writing to the first threshold value area including the deletion state that will represent the data to be deleted and the voltage level is higher than the first threshold value area. The 16th threshold value area of the 2nd to the 16th threshold value of the entry state is added to correspond to the 1st to 4th bits, so that 4-bit data can be stored. In the aforementioned plural memory cells, it is Contains the first to third memory cells; and A bit line is connected with the aforementioned 1st to nth word strings; and The first to nth selection gate lines are such that the kth selection gate line is connected to the gate of the kth selection transistor of the kth word string; and The first word line is connected to the gate of the first memory cell of the first to nth word strings; and The second word line is connected to the gate electrode of the aforementioned second memory cell of the aforementioned 1st to nth word strings; and The 3rd word line is connected with the gate electrode of the aforementioned 3rd memory cell of the aforementioned 1st to nth word strings, The aforementioned memory controller is configured to execute the first to nth writing processes, and after the execution of the first to nth writing processes, to execute the (n+1)th to 2nth writing processes, and After execution of the aforementioned (n+1)th to 2nth write processing, execute the (2n+1)th to 3nth write processing, and after execution of the aforementioned (2n+1)th to 3nth write processing, Execute the (3n+1)th to 4nth write processing, and perform the (4n+1) to 5nth write processing after the execution of the aforementioned (3n+1) to 4nth write processing, The aforementioned (e+1)th writing process is performed after the aforementioned e-th writing process, The aforementioned (f+1)th writing process is performed after the aforementioned fth writing process, The aforementioned (g+1)th writing process is performed after the aforementioned gth writing process, The aforementioned (h+1)th writing process is performed after the aforementioned hth writing process, The aforementioned (i+1)th writing process is performed after the aforementioned i-th writing process, The aforementioned kth writing process includes the process of writing data corresponding to the aforementioned 1st, 2nd, and 4th bits to the aforementioned first memory cell of the aforementioned kth character string, The aforementioned (n+k) writing process includes the process of writing data corresponding to the aforementioned 1st, 2nd, and 4th bits to the aforementioned second memory cell of the aforementioned kth character string, The aforementioned (2n+k) writing process includes the process of writing data corresponding to the aforementioned 3rd bit to the aforementioned 1st memory cell of the aforementioned kth word string, The aforementioned (3n+k) writing process includes the process of writing the data corresponding to the aforementioned 1st, 2nd, and 4th bits to the aforementioned 3rd memory cell of the aforementioned kth character string, The aforementioned (4n+k) writing process includes the process of writing the data corresponding to the aforementioned 3rd bit to the aforementioned 2nd memory cell of the aforementioned kth character string, The aforementioned memory controller is to make the threshold value area in the aforementioned memory cell become representative data corresponding to the data of the aforementioned 1st bit, the aforementioned 2nd bit, and the aforementioned 4th bit. The 17th threshold value area and the voltage level of the erased state are higher than the aforementioned 17th threshold value area and represent the 18th to 24th threshold value areas of the writing state where data has been written. One of the threshold value areas is used to implement the aforementioned writing of the data corresponding to the aforementioned 1st, 2nd, and 4th bits for the aforementioned memory cell, The aforementioned memory controller is such that the threshold area in the aforementioned memory cell will be changed from any one of the aforementioned 17th to 24th threshold areas in response to the data of the aforementioned 3rd bit. The limit value area becomes the threshold value area of any one of the two threshold value areas in the aforementioned 1st to 16th threshold area areas, so that the aforementioned memory cells corresponding to the aforementioned 3rd The aforementioned writing of bit data, Among them, n is an integer not less than 2, k is an integer not less than 1 and not more than n, e is an integer not less than 1 (n-1), and f is an integer not less than (n+1) and not more than (2n-1). Integer, g is an integer from (2n+1) to (3n-1), h is an integer from (3n+1) to (4n-1), and i is an integer from (4n+1) to (5n- 1) The following integers. As the memory system described in claim 1, wherein, the first memory cell of the aforementioned k-th word string and the second memory cell of the aforementioned k-th word string are connected in series, and the aforementioned k-th word string is connected in series. The 2nd memory cell of the word string and the 3rd memory cell of the aforementioned k-th word string are connected in series. The memory system as described in claim 1, wherein the aforementioned memory controller is configured such that when the data corresponding to the aforementioned third bit is written to the aforementioned memory cell, it will correspond to the aforementioned second bit The bit data and the data corresponding to the aforementioned third bit are input to the aforementioned non-volatile memory. The memory system as described in Claim 1, wherein, among the 15 borders between the adjacent threshold areas existing in the aforementioned 1st to 16th threshold areas, they are used in the aforementioned 1st The number of the first boundary used in the determination of the value of the bit, the number of the second boundary used in the determination of the value of the second bit, the number of the third used in the determination of the value of the third bit Among the number of borders and the number of fourth borders used in determining the value of the fourth bit, the largest value among them is 5, and the second largest value is 4. The memory system as described in Claim 1, wherein, the area between the threshold area with the lowest voltage level and the threshold area with the highest voltage level in the aforementioned two threshold areas The number of threshold value regions is within 2. The memory system as described in Claim 1, wherein, It is the number of the aforementioned borders whose value of the first bit is different among the 15 borders between the adjacent threshold value areas existing in the aforementioned 1st to 16th threshold value areas , the number of the aforementioned borders whose values of the aforementioned second bit are different, the number of the aforementioned borders whose values of the aforementioned third bit are different, and the number of the aforementioned borders whose values of the aforementioned fourth bit are different, Become (1, 4, 5, 5), (1, 5, 4, 5) or (3, 3, 4, 5) in order to implement the first memory for the k-th word string The writing of the data corresponding to the aforementioned 1st, 2nd, and 4th bits of the cell and the writing of the data corresponding to the aforementioned 3rd bit of the first memory cell of the kth character string. The memory system as described in Claim 1, wherein, In this way, the voltage level difference between the two threshold areas with different values of the aforementioned 2nd bit data in the aforementioned 17th to 24th threshold areas will be higher than that of the aforementioned 17th threshold area. In the 24th threshold area, the voltage level difference between the 2 threshold areas having different values of the data of the aforementioned first bit is smaller and becomes smaller than that of the aforementioned 17th to 1st threshold areas. In the 24th threshold value area, the voltage level difference between the two threshold value areas having different values of the data of the aforementioned 4th bit is smaller, so as to implement the aforementioned kth word Writing of data corresponding to the aforementioned 1st, 2nd, and 4th bits of the first memory cell of the string. The memory system as described in Claim 7, wherein, The aforementioned memory controller is compared with the aforementioned 2nd bit when the data corresponding to the aforementioned 1st, 2nd, and 4th bits are written into the first memory cell of the aforementioned k-th word string The value of the data is the interval between two different threshold value areas, and the second programming is obtained by using the aforementioned third bit data for the aforementioned two threshold value areas. The aforementioned (2n+k)-th writing process is performed so that the intervals between adjacent threshold value regions among the four threshold value regions become wider. The memory system as described in Claim 1, wherein, The aforementioned 1st bit is the lower bit, the aforementioned 2nd bit is the second smallest Middle bit, and the aforementioned 3rd bit is the second largest Upper bit. The aforementioned 4th bit is the top bit of the body. As the memory system recorded in claim 1, it further has: The volatile first memory unit is used to memorize the aforementioned first to fourth bits of data, Among the 1st to 4th bits stored in the volatile first memory unit, the bits that are repeatedly input in the k-th write process and the (2n+k)-th write process The data of the bit can be discarded or invalidated after starting the aforementioned (2n+k)th writing process, and the data of other bits can be discarded or invalidated after starting the aforementioned kth writing process change. As the memory system recorded in claim 1, it further has: The volatile first memory part is used to memorize the aforementioned 1st to 4th bit data; and The volatile second memory unit is used to memorize the bits repeatedly input in the kth writing process and the (2n+k) writing process among the aforementioned 1st to 4th bit data the information, The aforementioned memory controller sets the aforementioned 1st to 4th bit data stored in the aforementioned volatile first memory unit to be discardable or invalid after starting the aforementioned kth writing process , and will be memorized in the aforementioned 1st to 4th bits in the aforementioned volatile second memory unit in the aforementioned kth writing process and the aforementioned (2n+k)th writing process and be repeatedly performed The input bit data is memorized before the start of the k-th write process, and can be discarded or invalidated after the start of the (2n+k)-th write process. The memory system as described in Claim 11, wherein, The aforementioned volatile second memory unit is set in units of word lines. The memory system as described in Claim 1, wherein, The above-mentioned memory controller is for the above-mentioned non-volatile memory, and through continuous instruction and data input, the data corresponding to the above-mentioned 1st, 2nd, and 4th bits are written into the above-mentioned k-th string. An instruction to write the data corresponding to the aforementioned 3rd bit into the aforementioned first memory cell of the kth word string in the aforementioned first memory cell. The memory system as described in Claim 1, wherein, The aforementioned non-volatile memory has: The control section is based on the data written by writing the data corresponding to the aforementioned 1st, 2nd, and 4th bits into the aforementioned 1st memory cell of the aforementioned k-th word string. The data obtained, and the writing of the data corresponding to the aforementioned 1, 2, and 4 bits in the aforementioned first memory cell of the aforementioned k-th word string and the writing of the aforementioned first memory cell of the aforementioned k-th word string The data corresponding to the aforementioned 2nd bit that is repeatedly input during the writing of the data corresponding to the aforementioned 3rd bit, and the aforementioned 3rd bit corresponding to the aforementioned 1st memory cell corresponding to the aforementioned k-th word string The input data corresponding to the aforementioned 3rd bit of the data of the bit is entered to determine the threshold voltage corresponding to the aforementioned 3rd bit of data at the aforementioned 1st memory cell of the aforementioned k-th word string. The memory system as described in Claim 14, wherein, The aforementioned memory controller is to write the data corresponding to the aforementioned 1st, 2nd, and 4th bits into the aforementioned 1st memory cell of the aforementioned k-th word string as the written data. read out, and implement error correction for the aforementioned data read out, The above-mentioned control unit is based on the above-mentioned read data that has been subjected to the above-mentioned error correction, and the data corresponding to the above-mentioned 2nd bit, and the data corresponding to the aforementioned 3rd bit, to determine and pass the k-th word The above-mentioned threshold voltage of the data corresponding to the data corresponding to the written bit is written into the data corresponding to the above-mentioned third bit in the aforementioned first memory cell. The memory system as described in Claim 1, wherein, Among the 15 boundaries existing between the adjacent threshold value areas in the aforementioned 1st to 16th threshold value areas, the first boundary used to determine the value of the aforementioned 1st bit data Quantity, the number of the second boundary used to determine the value of the aforementioned second bit data, the number of the third boundary used to determine the value of the aforementioned third bit data, and the number of the aforementioned fourth bit The number of the fourth boundary used by the value of the element data is (3, 5, 2, 5), In the writing of the data corresponding to the aforementioned third bit, the difference between the threshold area with the minimum voltage level and the threshold area with the maximum voltage level among the aforementioned two threshold areas The number of threshold value regions between is within 2.

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