TW202121426A - Memory system capable of avoiding the mutual interference between cells to reducing the capacity of writing in a buffer, and suppressing bias of a bit error rate - Google Patents

Abstract

An embodiment of the invention provides a memory system capable of avoiding the mutual interference between cells to reduce the capacity of writing in a buffer, and suppressing bias of a bit error rate. In the memory system of the embodiment, a memory controller in the memory system is configured to enable a nonvolatile memory to execute a first programming such that a threshold region in the memory cell becomes any threshold region of a seventeenth threshold region indicating an erased state in which data is erased and eighteenth to twenty-fourth threshold regions having a higher voltage level than that of the seventeenth threshold region and indicating a written state in which data is written according to the data of the first bit, the second bit, and the fourth bit, and configured to allow the nonvolatile memory to execute a second programming such that the threshold region in the memory cell becomes any threshold region in two threshold regions among the first to sixteenth threshold regions from any threshold region of the seventeenth to twenty-fourth threshold regions according to the data of the third bit. When driving the nonvolatile memory to execute the second programing, the memory controller is configured to input the data of the second bit and the data of the third bit to the nonvolatile memory.

Description

Memory system

The implementation form of this disclosure is related to a memory system. [Related Application Case] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2019-210823 (application date: November 21, 2019) and Japanese Patent Application No. 2020-113206 (application date: June 30, 2020) . This application contains all the contents of the basic application by referring to these basic applications.

In NAND-type flash memory, generally speaking, multi-value data composed of multiple bits is written to the memory cell, and multi-value data composed of 3 bits is written to the memory cell. (Triple Level Cell) technology department was put into practical use. In the future, it can be expected that the QLC (Quadruple Level Cell) technology system that writes multi-value data composed of 4 bits will become the mainstream. In QLC, in order to avoid mutual interference between cells, it is reviewed that "after writing 4-bit data into the first memory cell at the same time, the same applies to adjacent cells and writing 4-bit data at the same time. , After that, rewrite the 4-bit data to the first memory cell at the same time" again. However, in this method, it is necessary to keep the 4-bit data in the write buffer in the memory controller in advance until the rewriting is completed. In recent years, the NAND memory system has been three-dimensional, and the memory capacity of the necessary write buffer has been increased, and there has been a problem that the cost of the built-in memory controller in the write buffer has increased. Therefore, in a 3-dimensional non-volatile memory, the same is true, and it is necessary to review the countermeasures to reduce the write buffer capacity of the memory controller. As a countermeasure to avoid mutual interference between cells and reduce the amount of write buffer of the memory controller at the same time, it is well known: When writing the data of each bit to the memory cell, divide it into two The writing is done in stages, and it becomes a method that does not need to rewrite all the bit data. However, in this technique, there is a problem that the bit error rate when writing bit data to the memory cell is quite large. In order to increase the reliability of the QLC technology, it is necessary to avoid mutual interference between cells and reduce the capacity of the write buffer in the memory controller. It is also biased towards the bit error rate when writing bit data. Used as a suppressed memory system.

In one aspect of the present disclosure, a method is provided that can avoid mutual interference between cells and reduce the capacity of the write buffer in the memory controller, and is also suitable for bit errors when writing bit data The rate of bias is suppressed by the memory system. According to this embodiment, a memory system is provided, which is equipped with: non-volatile memory, which has a plurality of memory cells, and each of the plurality of memory cells has 16 thresholds Area, and can memorize 4-bit data represented by the first to fourth bits. The 16 threshold areas include the first threshold that represents the deleted state of the data being deleted The value area and the voltage level are higher than the aforementioned first threshold area and represent the 2nd to 16th threshold area of the writing state in which the data is written; and The memory controller causes the non-volatile memory to perform the first programming of writing the data of the first bit, the second bit, and the fourth bit to make the non-volatile memory The sexual memory performs the second programming of writing the data of the third bit mentioned above, Among the 15 boundaries between adjacent threshold regions existing in the first to 16th threshold regions, the first boundary used in the determination of the value of the first bit data The number of the second boundary used in the determination of the value of the second bit data, the number of the third boundary used in the determination of the value of the third bit data, is used in For the number of the fourth boundary in the determination of the value of the fourth bit of the data, the largest value among these numbers is 5, and the second largest value is 4. The aforementioned memory controller is configured so that the threshold area in the aforementioned memory cell becomes representative data in response to the data of the aforementioned first bit, the aforementioned second bit, and the aforementioned fourth bit. The 17th threshold area and voltage level of the deleted state with deletion are higher than the above-mentioned 17th threshold area and represent the 18th to 24th thresholds of the write state with data being written The threshold area of one of the areas is used to make the aforementioned non-volatile memory perform the aforementioned first programming, The aforementioned memory controller is configured so that the threshold area in the aforementioned memory cell changes from any one of the aforementioned 17th to 24th threshold areas in accordance with the data of the aforementioned 3rd bit. The threshold area becomes the threshold area of any one of the threshold areas of the first to 16th threshold areas, so that the non-volatile memory performs the second Stylized, The number of threshold areas between the threshold area where the voltage level is the lowest and the threshold area where the voltage level is the highest in the aforementioned two threshold areas is within two. The aforementioned memory controller, when the aforementioned non-volatile memory is subjected to the aforementioned second programming, is configured to combine the aforementioned second bit data and the aforementioned third bit data with respect to the aforementioned non-volatile memory For input.

FIG. 1 is a block diagram showing the schematic configuration of the memory system 1 according to the first embodiment. The memory system 1 in FIG. 1 has a memory controller 2 and a non-volatile memory 3. The memory system 1 in FIG. 1 can be connected to a host processor (hereinafter, simply referred to as a host) 4. The host 4 is, for example, an electronic device such as a personal computer or a portable terminal. The non-volatile memory 3 is a memory that stores data non-volatilely. For example, it is equipped with a NAND flash memory (hereinafter, it is also referred to as a NAND memory) 5. In this embodiment, the non-volatile memory 3 is a 4bit/Cell (QLC: Quad Level Cell) NAND with a memory cell capable of storing 4 bits of data at each memory cell. An example of memory 5 will be explained. The non-volatile memory 3 according to this embodiment has a three-dimensional structure in which memory cells are stacked three-dimensionally. Non-volatile memory 3 is a memory cell with a plurality of memory cells, each of which has 16 threshold areas, and can memorize what is represented by the first to fourth bits 4-bit data. The 16 threshold areas include the first threshold area that represents the deleted state and the voltage level is higher than the first threshold area. It also represents the 2nd to 16th threshold area of the writing state where the data has been written. For example, the first bit is the lower bit of the lowest bit, the second bit is the middle bit of the second smallest, and the third bit is the upper bit of the second largest. , The 4th bit mentioned above is the Top bit which is the highest. The memory controller 2 controls the writing of data in the non-volatile memory 3 in accordance with the write command from the host 4. In addition, the memory controller 2 controls the reading of data from the non-volatile memory 3 in accordance with the read command from the host 4. The memory controller 2 has a RAM (Random Access Memory) 6, a ROM (Read Only Memory) 7, a processor 8, a host interface 9, an ECC (Error Check and Correct) circuit 10, and a memory interface 11. The RAM 6, the processor 8, the host interface 9, the ECC circuit 10, and the memory interface 11 are connected by a common internal bus 12. As will be described later, the memory controller 2 of this embodiment uses the non-volatile memory 3 to perform the first programming of writing the data of the first bit, the second bit, and the fourth bit. After that, the non-volatile memory 3 is subjected to the second programming of writing the data of the third bit. Among the 15 boundaries between adjacent threshold regions existing in the first to 16th threshold regions, the number of first boundaries used in the determination of the value of the first bit data , The number of the second boundary used in the determination of the value of the data of the second bit, the number of the third boundary used in the determination of the value of the third bit of data, is used in the fourth bit For the number of the fourth boundary in the determination of the value of the data, the largest value among these numbers is 5, and the second largest value is 4. The memory controller 2 is configured so that the threshold area in the memory cell will correspond to the data in the first, second, and fourth bits and become the representative data that has been deleted The 17th threshold area and voltage level of the deleted state are higher than the 17th threshold area and represent one of the 18th to 24th threshold areas of the write state where the data is written The threshold area is used to make the non-volatile memory 3 perform the first programming. The memory controller 2 is configured so that the threshold value area in the memory cell will be from the threshold value of any one of the 17th to the 24th threshold value area in response to the data of the third bit The non-volatile memory 3 is programmed for the second time by making the area become the threshold area of any one of the threshold areas of the first to 16th threshold areas. The number of threshold regions between the two threshold regions where the voltage level is the lowest and the threshold region where the voltage level is the highest is within two. The memory controller 2 is configured to input the data of the second bit and the data of the third bit into the non-volatile memory 3 when the non-volatile memory 3 is programmed in the second. In more detail, the memory controller 2 is designed to make adjacent threshold regions in the boundary of 15 among 16 threshold regions (the first to 16th threshold regions) The value of the first bit is the number of different boundaries, the value of the second bit is the number of different boundaries, the value of the third bit is the number of different boundaries, and the fourth bit The value is the number of different boundaries, in order of (1, 4, 5, 5), (1, 5, 4, 5) or (3, 3, 4, 5) to make non-volatile The sexual memory performs the first programming and the second programming. Or, the memory controller 2 of this embodiment is after the non-volatile memory 3 is programmed to write the data of the first bit, the second bit, and the fourth bit. , Make the non-volatile memory 3 perform the second programming of writing the data of the third bit. Among the 15 boundaries between adjacent threshold regions existing in the first to 16th threshold regions, the number of first boundaries used in the determination of the value of the first bit data , The number of the second boundary used in the determination of the value of the data of the second bit, the number of the third boundary used in the determination of the value of the third bit of data, is used in the fourth bit The number of the fourth boundary in the judgment of the value of the data is (3, 5, 2, 5) in order. The memory controller 2 is configured so that the threshold area in the memory cell will correspond to the data in the first, second, and fourth bits and become the representative data that has been deleted The 17th threshold area and voltage level of the deleted state are higher than the 17th threshold area and represent one of the 18th to 24th threshold areas of the write state where the data is written The threshold area is used to make the non-volatile memory 3 perform the first programming. The memory controller 2 is configured so that the threshold value area in the memory cell will be from the threshold value of any one of the 17th to the 24th threshold value area in response to the data of the third bit The non-volatile memory 3 is programmed for the second time by making the area become the threshold area of any one of the threshold areas of the first to 16th threshold areas. The number of threshold regions between the two threshold regions where the voltage level is the lowest and the threshold region where the voltage level is the highest is within two. The memory controller 2 is configured to input the data of the second bit and the data of the third bit into the non-volatile memory 3 when the non-volatile memory 3 is programmed in the second. The memory controller 2 can also calculate the voltage level difference between the two threshold regions that will make the data value of the second bit in the 17th ~ 24th threshold region different The voltage level difference between the two threshold regions that are different from the data value of the first bit becomes smaller and becomes the two that are different from the data value of the fourth bit. The voltage level difference between the threshold areas is smaller to make the non-volatile memory the first programming. Alternatively, the memory controller 2 can also use the interval between the two threshold regions at the time of the first programming that are different from the data value of the second bit, so that the Two threshold areas, and the second programming is performed with the data of the third bit, the interval between adjacent threshold areas among the four threshold areas becomes wider. , To make the non-volatile memory the second programming. The host interface 9 outputs the commands received from the host 4 and user data (write data) to the internal bus 12. In addition, the host interface 9 sends the user data read from the non-volatile memory 3 or the response from the processor 8 to the host 4. The memory interface 11 is based on the instructions of the processor 8, and for the processing of writing user data into the non-volatile memory 3 and the processing of reading user data from the non-volatile memory 3 control. The processor 8 is for overall control of the memory controller 2. The processor 8 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), etc. When the processor 8 receives a command from the host 4 via the host interface 9, it performs control following the command. For example, the processor 8 follows the instructions from the host 4 and issues instructions to the memory interface 11 to write user data and parity check codes in the non-volatile memory 3. In addition, the processor 8 follows the instructions from the host 4, and gives the memory interface 11 instructions for reading the user data from the non-volatile memory 3 and the parity check code. The user data is stored in the RAM 6 via the internal bus 12. The processor 8 determines the storage area (memory area) on the non-volatile memory 3 for the user data stored in the RAM 6. The processor 8 determines the memory area on the non-volatile memory 3 for the data (page data) of the page unit as the writing unit. In this manual, user data stored in one page of non-volatile memory 3 is defined as unit data. The unit data is generally encoded and stored in the non-volatile memory 3 as a code word, but the encoding system is not necessary. The memory controller 2 can also store the unit data in the non-volatile memory 3 without encoding. However, in FIG. 1, as one of the configuration examples, the encoding configuration is shown. When the memory controller 2 does not perform encoding, the page data is consistent with the unit data. In addition, one codeword can be generated based on one unit data, or one codeword can be generated based on segmentation data after the unit data is divided. In addition, it is also possible to use plural unit data to generate one codeword. The processor 8 determines the memory area of the non-volatile memory 3 of the write target for each of the unit data. The memory area of the non-volatile memory 3 is assigned a physical address. The processor 8 uses the physical address to manage the memory area of the writing target of the unit data. The processor 8 gives instructions to the memory interface 11 by designating the determined memory area (physical address) and writing user data to the non-volatile memory 3. On the other hand, the host 4 manages data through logical addresses. Therefore, the processor 8 manages the correspondence between the logical address and the physical address of the user data. When the processor 8 receives a read command containing a logical address from the host 4, it specifies the physical address corresponding to the logical address, and specifies the physical address. The memory interface 11 gives instructions to read the user data. In this specification, a plurality of memory cells that are commonly connected with one character line is defined as a memory cell group MG. One memory cell group MG becomes the unit of writing (programming). In this embodiment, the non-volatile memory 3 is a 4bit/Cell NAND memory 5, and one memory cell group MG has a data amount of 4 bits×number of bits. The bits written into each memory cell correspond to pages that are different from each other. In this embodiment, the four pages of a memory cell group MG are called Lower page (first page), Middle page (second page), Upper page (third page), and Top page (first page). 4 pages). The ECC circuit 10 encodes the user data stored in the RAM 6 and generates code words. In addition, the ECC circuit 10 decodes the code word read from the non-volatile memory 3. The ECC circuit 10 corrects the bit error contained in the code word read from the non-volatile memory 3 and decodes it into user data. RAM6 is to temporarily store the user data received from the host 4 until it is stored in the non-volatile memory 3, or is read from the non-volatile memory 3. The data is temporarily stored until the host 4 is sent. RAM6, for example, is a general purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). In FIG. 1, the memory controller 2 is shown as an example of a configuration in which the ECC circuit 10 and the memory interface 11 are respectively provided. However, the ECC circuit 10 can also be embedded in the memory interface 11. In addition, the ECC circuit 10 can also be embedded in the non-volatile memory 3. When a write request is received from the host 4, the memory system 1 operates as follows. The processor 8 temporarily stores the written data in the RAM 6. The processor 8 reads the data stored in the RAM 6 and inputs it to the ECC circuit 10. The ECC circuit 10 encodes the input data and inputs the code word into the memory interface 11. The memory interface 11 is used to write the entered codeword into the non-volatile memory 3. When a read request is received from the host 4, the memory system 1 operates as follows. The memory interface 11 inputs the code words read from the non-volatile memory 3 to the ECC circuit 10. The ECC circuit 10 decodes the code word that has been input, and temporarily stores the decoded data in the RAM 6. The processor 8 sends the data stored in the RAM 6 to the host 4 via the host interface 9. In addition, the non-volatile memory 3 may also be formed by a plurality of chips. The non-volatile memory 3 and the memory interface 11 can also be formed through through holes (TSV: Through Silicon Via) To make connections. In addition, the structure of the memory controller 2 shown in FIG. 1 is only one example, and the internal bus 12 may be a divided structure or a hierarchical structure, or be connected with additional functional blocks, etc. The other various derivative forms. FIG. 2 is a block diagram showing an example of the internal structure of the non-volatile memory 3 of this embodiment. The non-volatile memory 3 includes a NAND I/O interface 21, a control unit 22, a NAND memory cell array (memory cell unit) 23, and a page buffer (second memory unit) 24. The non-volatile memory 3 is, for example, formed on a semiconductor substrate (such as a silicon substrate) and is chipped. The control unit 22 controls the operation of the non-volatile memory 3 based on commands from the memory controller 2 via the NAND I/O interface 21 and the like. Specifically, when a write request is input, the control unit 22 writes the data requested to be written to the specified address on the NAND memory cell array 23. And to control. In addition, when a read request is input, the control unit 22 reads the data requested to be read from the NAND memory cell array 23 and controls the memory through the NAND I/O interface 21. The output mode of the device 2 is used for control. The page buffer 24 temporarily stores the data input from the memory controller 2 during the writing of the NAND memory cell array 23 and reads the data from the NAND memory cell array 23 Temporarily serve as a buffer for storage. As described later, the control unit 22 is based on the data obtained by reading out the data programmed by the 1st stage programming, and the bits that are repeatedly input during the programming of the 1st stage and the 2nd stage. The data of the element and the input data of the bit programmed by the programming of the 2nd stage determine the threshold voltage of the data of the bit programmed by the programming of the 2nd stage. The control unit 22 includes an oscillator 31, a sequencer 32, a command user interface 33, a voltage supply unit 34, a column counter 35, and a serial access controller 36. In addition, the NAND memory cell array 23 includes a row decoder 37 and a sense amplifier 38. The NAND I/O interface 21 is a circuit for transmitting and receiving IO signals and control signals between the memory controller 2 and the memory controller 2. The command user interface 33 is obtained from the command and address received from the memory controller 2 via the IO signal line and the command and address in the data based on the control signal. The command user interface 33 delivers the obtained command and address to the serializer 32. The oscillator 31 is a circuit that generates a clock pulse. The clock generated by the oscillator 31 is supplied to each component including the sequencer 32. The sequencer 32 is a state machine (State Machine) driven by the clock supplied from the oscillator 31. The sequencer 32 performs control of access to the NAND memory cell array 23, etc. For example, the sequencer 32 responds to commands received from the command user interface 33 to issue various commands for controlling internal voltages or operating timing. In addition, the serializer 32 supplies the block address and page address contained in the address received from the command user interface 33 to the row decoder 37. Furthermore, the sequencer 32 supplies the column address contained in the address received from the command user interface 33 to the column counter 35. The voltage supply unit 34 generates various internal voltages supplied to the word lines and various internal voltages supplied to the bit lines, and supplies them to the row decoder 37 and the sense amplifier 38. The row counter 35 starts with the row address supplied from the serializer 32 during programming or reading, and follows the control signal supplied from the serial access controller 36 to set the row address Go forward in order. When the page buffer 24 is programmed, the data received from the serial access controller 36 is sequentially stored in the row address area designated by the row counter 35. In addition, the page buffer 24 sequentially sends the data of the column address specified by the above-mentioned column address among the stored data to the serial access controller 36 during the read operation. The serial access controller 36 stores the data sequentially received from the NAND I/O interface 21 at the bit width of the IO signal line in the page buffer 24 when it is programmed. In addition, the serial access controller 36 sends the data sequentially received from the page buffer 24 at the bit width of the IO signal line to the NAND I/O interface 21 during the read operation. The row decoder 37 decodes the block address and the page address during programming and reading operations, and selects the corresponding page to be accessed in the block BLK of the access target. The corresponding character line. After that, each row decoder 37 applies an appropriate voltage to the selected word line and the non-selected word line. The sense amplifier 38 transmits the corresponding data stored in the page buffer 24 to the memory cell transistor during programming operation. In addition, the sense amplifier 38 senses the data read from the selected word line to the bit line during the reading operation, and stores the obtained data in the page buffer 24. The data stored in the page buffer 24 is sent to the memory controller 2 through the serial access controller 36 and the NAND I/O interface 21. FIG. 3 is a circuit diagram showing an example of the NAND memory cell array 23 with a three-dimensional structure. FIG. 3 shows the circuit configuration of the block BLK of one of the plural blocks in the NAND memory cell array 23 with a three-dimensional structure. The other blocks of the NAND memory cell array 23 also have the same circuit configuration as in FIG. 3. In addition, this embodiment can also be applied to a memory cell with a two-dimensional structure. As shown in FIG. 3, the block BLK, for example, has four fingers FNG (FNG0-FNG3). In addition, each refers to FNG, which includes plural NAND strings NS. Each of the NAND string NS includes, for example, 8 memory cell transistors MT (MT0 to MT7) connected in series, and selection transistors ST1 and ST2. In this specification, there may be cases where each finger FNG is referred to as a string St. In addition, the number of memory cell transistors MT in the NAND string NS is not limited to 8. The memory cell transistor MT is arranged between the selection transistors ST1 and ST2 so that the current paths are connected in series. The current path of the memory cell transistor MT7 on one end side of the series connection is connected with one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 on the other end side is connected by Connect with one end of the current path of the selective transistor ST2. The gates of the selection transistor ST1 of each of FNG0～FNG3 are respectively connected to the selection gate lines SGD0～SGD3 in common. On the other hand, the gate of the selection transistor ST2 is commonly connected to the same selection gate line SGS between the plural fingers FNG. In addition, the control gates of the memory cell transistors MT0 to MT7 located in the same block BLK are respectively connected to the word lines WL0 to WL7 in common. That is, the word lines WL0 to WL7 and the select gate line SGS are commonly connected between the plural fingers FNG0 to FNG3 in the same block BLK. In contrast, the select gate line SGD, Even if it is in the same block BLK, it also refers to each of FNG0~FNG3 and is independent of each other. The control gate electrodes of the memory cell transistors MT0 to MT7 constituting the NAND string NS are respectively connected to the word lines WL0 to WL7, and the same refers to the first in each NAND string NS in the FNG. The i memory cell transistors MTi (i=0 to n) are connected in common through the same character line WLi (i=0 to n). That is, the control gate electrode of the memory cell transistor MTi in the same row in the block BLK is connected to the same word line WLi. Each NAND string NS is connected to the word line WLi and is also connected to the bit line. Each memory cell in each NAND string NS can be identified by the address for identifying the word line WLi and the select gate lines SGD0 to SGD3, and the address for identifying the bit line. As mentioned above, the data of the memory cells (memory cell transistors MT) located in the same block BLK are deleted in batches. On the other hand, data reading and writing are performed in units of physical sectors MS. One physical sector MS is connected with one character line WLi, and contains a plurality of memory cells belonging to one FNG. The memory controller 2 writes (programs) all the NAND strings NS connected to one character line in one finger as a unit. Therefore, the unit of the amount of data programmed by the memory controller 2 is 4 bits×the number of bit lines. In the read operation and programming operation, according to the physical address, one word line WLi and one selection gate line SGD are selected, and the physical sector MS is selected. In addition, in this specification, the writing of data to a memory cell is referred to as a program as needed. FIG. 4 is a cross-sectional view of a partial area of the NAND memory cell array 23 of the NAND memory 5 with a three-dimensional structure. As shown in FIG. 4, a plurality of NAND strings NS are formed on the p-well region (P-well) 41 of the semiconductor substrate in the vertical direction. That is, on the p-type well region 41, a plurality of wiring layers 42 functioning as a selective gate line SGS and a plurality of wiring layers functioning as a word line WLi are formed in the vertical direction. 43. And a plurality of wiring layers 44 functioning as a selective gate line SGD. In addition, a memory hole 45 that penetrates through these wiring layers 42, 43, and 44 and reaches the p-type well region 41 is formed. On the side surface of the memory cavity 45, a block insulating film 46, a charge storage layer 47, and a gate insulating film 48 are sequentially formed. Furthermore, a conductive film 49 is buried in the memory cavity 45. The conductive film 49 functions as a current path of the NAND string NS, and is a region where channels are formed during the operation of the memory cell transistor MT and the selection transistors ST1 and ST2. At each NAND string NS, a selection transistor ST2, a plurality of memory cell transistors MT, and a selection transistor ST1 are sequentially stacked on the p-well region 41. At the upper end of the conductive film 49, a wiring layer that functions as a bit line BL is formed. Furthermore, in the surface of the p-type well region 41, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed. On the n+ type impurity diffusion layer, a contact plug 50 is formed, and on the contact plug 50, a wiring layer that functions as a source line SL is formed. In addition, on the p+ type impurity diffusion layer, contact pins 51 are formed, and on the contact pins 51, a wiring layer that functions as a well wiring CPWELL is formed. The well wiring CPWELL is used to apply a delete voltage. The NAND memory cell array 23 shown in FIG. 4 is arranged in plural in the depth direction of the paper of FIG. 4, and a collection of plural NAND strings NS arranged in a row in the depth direction, 1 One of the FNG lines is formed. The other means FNG, for example, is formed in the left-right direction in FIG. 4. In FIG. 3, although there are four fingers FNG0 to 3 in the figure, in FIG. 4, an example in which three fingers are arranged between the contact pins 50 and 51 is shown. Fig. 5 is a diagram showing an example of the threshold value area of the first embodiment. FIG. 5 shows an example of the distribution of the threshold area of the non-volatile memory 3 of 4 bits/Cell. In the non-volatile memory 3, information is stored by the charge amount of electrons accumulated in the charge accumulation layer 47 of the memory cell. Each memory cell has a threshold voltage corresponding to the amount of charge of the electron. In addition, the plural data values stored in the memory cell correspond to the plural areas (threshold area) where the threshold voltage is different. S0～S15 in Figure 5 show the distribution of threshold values in 16 threshold regions. The horizontal axis of Fig. 5 represents the threshold voltage, and the vertical axis represents the number of memory cells (cell number). The threshold value distribution is the range of the threshold value change. In this way, each memory cell has 16 threshold regions divided by 15 boundaries, and each threshold region has an inherent threshold distribution. In this embodiment, the area where the threshold voltage becomes below Vr1 is called area S0, and the area where the threshold voltage becomes greater than Vr1 and below Vr2 is called area S1, and the area where the threshold voltage is below Vr2 is called area S1. The region where the limit voltage becomes larger than Vr2 and below Vr3 is called region S2, and the region where the threshold voltage becomes larger than Vr3 and below Vr4 is called region S3. In addition, in this embodiment, the threshold voltage is larger than Vr4 and the region below Vr5, called region S4, and the threshold voltage is larger than Vr5 and below Vr6 region, called region S4 The area where the threshold voltage is greater than Vr6 and less than Vr7 is referred to as area S6, and the area where the threshold voltage is greater than Vr7 and less than Vr8 is referred to as area S7. In addition, in this embodiment, the area where the threshold voltage is greater than Vr8 and less than Vr9 is called area S8, and the area where the threshold voltage is greater than Vr9 and less than Vr10 is called area S8. The area where the threshold voltage is greater than Vr10 and less than Vr11 is referred to as area S10, and the area where the threshold voltage is greater than Vr11 and less than Vr12 is referred to as area S11. In addition, in this embodiment, the area where the threshold voltage is greater than Vr12 and less than Vr13 is called area S12, and the area where the threshold voltage is greater than Vr13 and less than Vr14 is called area S12. The area where the threshold voltage is greater than Vr14 and below Vr15 is referred to as area S13, and the area where the threshold voltage is greater than Vr15 is referred to as area S15. In addition, the threshold value distributions corresponding to the regions S0 to S15 are referred to as the 1st to 16th distributions. Vr1～Vr15 are the threshold voltages that become the boundary of each threshold area. In the non-volatile memory 3, the data values of the plural numbers correspond to the threshold regions of the plural numbers of the memory cells respectively. This correspondence is called data encoding. This data code is formulated in advance. When the data is written (programmed), the data code is followed to become the threshold area corresponding to the memorized data value for the memory cell The charge accumulation layer 47 injects charge. However, when reading, a read voltage is applied to the memory cell, and the data logic is determined according to the threshold value of the memory cell being lower or higher than the read voltage. When the data is read, the logic system of the data is determined according to the fact that the threshold value is lower or higher than the read level of the boundary of the read object. When the threshold is the lowest, the system is in the "deleted" state, and all bit data is defined as "1". When the threshold value is higher than the "deleted" state, it is in the state of "programmed", following the code, the data is defined as "1" or "0". Fig. 6A is a diagram showing one example of the data encoding of the first embodiment, and showing one example of the 1-4-5-5 data encoding. In this embodiment, the 16 threshold value regions shown in FIG. 5 correspond to 16 data values of 4 bits, respectively. The relationship between the threshold voltage in FIG. 6A and the data value of the bits corresponding to the Top, Upper, Middle, and Lower pages is as follows. ・The threshold voltage is the memory cell located in the S0 area, which is in the state of memory "1111". ・The threshold voltage is the memory cell located in the S1 area, which has a state of "0111" in its memory. ・The threshold voltage is the memory cell located in the S2 area, which is a state with "0011" in its memory. ・The threshold voltage is the memory cell located in the S3 area, and the memory cell has a state of "1011". ・The threshold voltage is the memory cell located in the S4 area, which is a state of memory with "1001". ・The threshold voltage is the memory cell located in the S5 area, and the memory cell has a state of "0001". ・The threshold voltage is the memory cell located in the S6 area, which is in the state of memory "0101". ・The threshold voltage is the memory cell located in the S7 area, which is in the state of memory "1101". ・The threshold voltage is the memory cell located in the S8 area, and the memory cell is in the state of "1100". ・The threshold voltage is the memory cell located in the S9 area, which is in the state of memory "1110". ・The threshold voltage is the memory cell located in the S10 area, which is a state of memory with "1010". ・The threshold voltage is the memory cell located in the S11 area, which means it has a memory state of "1000". ・The threshold voltage is the memory cell located in the S12 area, and the memory cell has a state of "0000". ・The threshold voltage is the memory cell located in the S13 area, and the memory cell has a state of "0100". ・The threshold voltage is the memory cell located in the S14 area, which is in a state of memory with "0110". ・The threshold voltage is the memory cell located in the S15 area, which is in a state of memory with "0010". Fig. 6B is a diagram showing another example of data encoding in the first embodiment, and showing one example of 4-3-4-4 data encoding. The relationship between the threshold voltage in Figure 6B and the data values corresponding to the bits on the Top, Upper, Middle, and Lower pages is as follows. ・The threshold voltage is the memory cell located in the S0 area, which is in the state of memory "1111". ・The threshold voltage is the memory cell located in the S1 area, which has a state of "0111" in its memory. ・The threshold voltage is the memory cell located in the S2 area, which is a state with "0011" in its memory. ・The threshold voltage is the memory cell located in the S3 area, and the memory cell has a state of "1011". ・The threshold voltage is the memory cell located in the S4 area, which is in the state of memory "1010". ・The threshold voltage is the memory cell located in the S5 area, which is in the state of memory "1110". ・The threshold voltage is the memory cell located in the S6 area, and the memory cell has a state of "1100". ・The threshold voltage is the memory cell located in the S7 area, and the memory cell has a state of "1000". ・The threshold voltage is the memory cell located in the S8 area, which is in a state of memory with "1001". ・The threshold voltage is the memory cell located in the S9 area, and the memory cell has a state of "0001". ・The threshold voltage is the memory cell located in the S10 area, which is in the state of memory with "0000". ・The threshold voltage is the memory cell located in the S11 area, which is a state with "0010" in its memory. ・The threshold voltage is the memory cell located in the S12 area, which is in a state of memory with "0110". ・The threshold voltage is the memory cell located in the S13 area, and the memory cell has a state of "0100". ・The threshold voltage is the memory cell located in the S14 area, which is in the state of memory "0101". ・The threshold voltage is the memory cell located in the S15 area, which is in the state of memory "1101". As shown in FIGS. 6A and 6B, it is a logic capable of distributing 4-bit data of each memory cell at each area of the threshold voltage. In addition, when the memory cell is in an unwritten state ("deleted" state), the threshold voltage of the memory cell is located in the S0 area. In addition, in the symbols shown here, it is the same as "in the S0 (deleted) state, the data of "1111" is memorized, and in the state of S1, the data "0111" is memorized." The data is changed by only 1 bit between adjacent areas. In this way, the data code shown in FIG. 6A and FIG. 6B is a Gray code that only changes the data by one bit between any two adjacent regions. In the coding of this embodiment shown in FIG. 6A, the threshold voltage used to determine the boundary of the bit value of each page is as follows. ・The threshold voltage used to determine the boundary of the bit value of the Top page is Vr1, Vr3, Vr5, Vr7, Vr12. ・The threshold voltage used to determine the boundary of the upper page bit value is Vr2, Vr6, Vr10, Vr13, Vr15. ・The threshold voltage used to determine the boundary of the bit value of the middle page is Vr4, Vr9, Vr11, and Vr14. ・The threshold voltage used to determine the boundary of the bit value of the lower page is Vr8. In this way, the number of threshold voltages used to determine the boundary of the bit value (hereinafter referred to as the boundary number) is 1, 4, and 5 for the Lower page, Middle page, Upper page, and Top page, respectively. , 5. Hereinafter, this kind of encoding is referred to as 1-4-5-5 encoding using the number of boundaries of each of the Lower page, Middle page, Upper page, and Top page. The first feature of this embodiment is that the maximum number of boundaries by which the bit value of each page changes is 5. When the 16 states are represented by 4 bits, the minimum value of the maximum number of boundaries is 4, and the code in Fig. 6 is only more than this, and the bit error bias is reduced. . In this way, the memory system 1 of the present embodiment has the first feature, which can suppress the bit error rate, and can also perform bit error bias for each page. inhibition. The second feature of this embodiment is that the number of borders on the lower page is one, and the number of borders on the middle page is four. This makes it possible to integrate the lower page and the middle page into one. The programming is carried out in the two stages of "programming" and "the second stage of programming that unifies the Upper page and the Top page". The third feature of this embodiment is that the range of change from the threshold area generated by the programming of the first stage to the threshold area generated by the programming of the second stage is less. That is, this means that the change range of the threshold area is small. If the change range of the threshold area is smaller, the system becomes more difficult to be affected by interference between neighboring cells. The first to third features mentioned above will be described in detail later. The control unit 22 of the non-volatile memory 3 controls the programming of the NAND memory cell array 23 and the reading from the NAND memory cell array 23 based on the code shown in FIG. 6A or FIG. 6B. In a 3-dimensional memory cell, the miniaturization of the memory cell has not progressed as well as that of a 2-dimensional memory cell. Therefore, in a three-dimensional memory cell, if it is a generation in which the interval between adjacent memory cells is wide, the mutual interference between the cells is small. In this case, generally speaking, a programming technique is adopted to program all the bits of each memory cell simultaneously (for example, if the bits are allocated to different pages, all the pages are simultaneously). When programming all the bits of each memory cell at the same time, as data coding, it is not particularly limited to group cooperation. Just based on the data of all the bits, decide which of the 16 threshold areas to be located, and make it the determined threshold area from the area of S0 that is in the deleted state. Just program it. In this case, generally speaking, a data encoding such as 4-4-3-4 data encoding is used to make the maximum boundary number take the minimum value. In the 4-4-3-4 data encoding, when the 15 boundaries between the 16 threshold areas are allocated to the 4 pages, 4 boundaries are allocated to the Lower page, and 4 boundaries are allocated to the Middle page 4 boundaries, and 3 boundaries are allocated for the Upper page, and 4 boundaries are allocated for the Top page. In the case of data encoding, since the deviation of the number of boundaries between pages is small, as a result, the deviation of the bit error rate between pages is reduced. This is because the vast majority of the causes of bit errors are caused by the shift of the threshold value to the adjacent threshold area, and if it is a page with a larger number of boundaries, the bit The number of meta errors will become larger. This is because "even if the error rate of the memory cell is the same, the correction capability of the ECC circuit 10, which is necessary for correcting page data errors, must be strengthened." Therefore, in order to It is also effective in suppressing the deterioration of the response performance, cost, and power consumption of the memory system 1 in response to the write request from the host 4. In addition, the bias in the readout speed caused by the bias in the number of borders is also reduced. In addition, in the 4-bit/Cell NAND memory 5, since the interval between adjacent threshold regions is narrow, the influence caused by mutual interference between cells is compared to 1 bit/ Cell or 2-bit/Cell NAND memory 5 series becomes larger. Therefore, in the NAND memory 5 of the generation where the miniaturization has progressed in recent years, generally speaking, in order to suppress the mutual interference between cells, a programming stage using plural numbers, such as two programming phases, is adopted. The stage (hereinafter referred to simply as a stage) is a stylized method (Foggy-Fine stylization) that sequentially injects a small amount of charge into the charge accumulation layer 47 of the memory cell. In this Foggy-Fine programming, after writing to the memory cell in the first stage (Foggy stage), writing to the neighboring cell is performed, and then back to the original memory cell , And write in the second stage (Fine stage). In this case, each stage is the implementation unit of programming, and the programming of the memory cell corresponding to one character line WLi is completed by implementing two programming stages. Regardless of whether it is in the programming of the first stage or in the programming of the second stage, 16 threshold regions are used for programming. The threshold value distribution of the threshold value area at the end of the programming of the first stage has a wider width than the threshold value distribution of the threshold value area in the final data encoding. That is, in the Foggy stage, Foggy (rough) writing is performed. In the programming of this Foggy stage, all 4 pages of input data are necessary. The programmed threshold distribution in the Foggy stage is in an intermediate state where adjacent distributions overlap each other, so data cannot be read out. In the programming of the Fine stage, which is the second stage, the programmed threshold area of the Foggy stage is moved to the threshold area in the final data encoding. That is, in the Fine stage, Fine writing is performed. The stylization of this Fine stage is also the same. All 4 pages of input data are necessary. The programmed threshold distribution in the Fine stage is a final state separated from each other because the adjacent distributions are separated from each other. Therefore, the data can be read out after the programming in the Fine stage. In the case of 4-4-3-4 data coding, although the bias of the number of boundaries is small, in Foggy-Fine stylized data input, 4 pages of data are required at each stage enter. This system will increase the time spent in data input and degrade the response performance of the memory system 1 with respect to the write request from the host 4. In addition, in the memory system 1, the amount of buffer (the amount of write buffer) used for the write buffer (first memory portion) for holding data input to the NAND memory 5 in advance is increased. Generally speaking, this write buffer is allocated to a part of the RAM 6 in the memory system 1. As a countermeasure to these problems, in this embodiment, the memory system 1 uses 1-4-5-5 data coding for the non-volatile memory 3 with a three-dimensional structure, and further uses two To implement page by page writing. As a result, in this embodiment, even in the non-volatile memory 3 with a three-dimensional structure, it is possible to suppress the mutual interference between cells and the bias of the bit error rate between the pages, and at the same time Reduce the write buffer capacity of the memory controller 2. In the write buffer of this embodiment, the first to fourth bits (the data of the lower page, the middle page, the upper page and the top page) will be repeatedly entered during the first programming and the second programming The bit data of is set to be able to be discarded or invalidated after the start of the second programming, and the data of other bits are set to be able to be discarded or invalidated after the first programming is started. Here, the interference between adjacent memory cells will be explained. The electric charge accumulated in the charge accumulation layer 47 of a certain memory cell will disturb the electric field of the adjacent memory cell. As a result, it will be given to the adjacent memory cell. The threshold voltage at the time of output produces noise that fluctuates. It is caused by the fact that "program and verify are implemented under certain electric field conditions, and after the programming is completed, adjacent memory cells are programmed into different charges", read Out of the accuracy system will become somewhat degraded. This interference between adjacent memory cells has become more pronounced with the miniaturization of the manufacturing technology of memory devices and the shrinking of the interval between memory cells. Moreover, if the interference between adjacent memory cells is enlarged, it will occur between adjacent memory cells connected by different bit lines on the same character line WLi. Interference between adjacent memory cells can be achieved by adjusting the electric field conditions of the memory cells between "programming and verification" and "reading after the adjacent memory cell is programmed" The difference has been reduced, and has been eased. As one of the methods to reduce the interference between adjacent memory cells connected by different bit lines on the same character line WLi, there is a method of dividing the programming into plural numbers. The phases are also programmed in a way that does not produce large changes in the amount of charge in the charge accumulation layer 47 between phases. In the programming sequence of this embodiment, the 4 bits on one character line WLi are programmed by two programming stages, that is, the 1st stage and the 2nd stage. Each programming stage is the execution unit of programming. The memory system 1 of this embodiment is to write 4-bit data to the memory cell by executing two programming stages. In addition, in this embodiment, in each of the two programming stages, data of some pages with 4 bits are used. Specifically, in the programming of the 1st stage, the data of the Lower page, Middle page, and Top page are used, and in the programming of the 2nd stage, the data of the Middle page, Upper page, and Top page are used. Fig. 7 is a diagram showing the programmed threshold area in the first embodiment. In FIG. 7, there are shown the threshold region after the 1st stage and the 2nd stage are programmed for the memory cell. Fig. 7 (T1) shows the threshold area of the deleted state which is the initial state before programming. Fig. 7 (T2) shows the threshold area after the programming of the 1st stage (the first programming). Fig. 7 (T3) shows the threshold area after the 2nd stage programming (second programming). As shown in (T1) of FIG. 7, all memory cells of the NAND memory cell array 23 are in the state of distribution S0 in the unwritten state (the "deleted" state). The control unit 22 of the non-volatile memory 3 is as shown in (T2) of FIG. 7. In the programming of the 1st stage, it corresponds to writing (memory) to the Lower page, Middle page and Top page The bit value for each memory cell is maintained at the state of the distribution S0, or the charge is injected to move it to a distribution higher than the distribution S0. Specifically, the control unit 22 uses "when the bit values written in the lower page, the middle page, and the top page are all "1", no charge is injected, and when written to the lower page As long as any one of the bit values on the Middle page and the Top page is "0", it is programmed by injecting charge and moving the threshold voltage to a higher position. That is, when the bit value written to the Lower page, Middle page, and Top page is "011", it is moved to distribution S1, and when written to the Lower page and Middle page And when the bit value at the top page is "101", it is moved to distribution S4, and when the bit value written to the lower page, the middle page, and the top page is "001" In the case of ", it is moved to distribution S5, and when the bit value written to the Lower page, Middle page, and Top page is "100", it is moved to distribution S8, Also, when the bit value written to the Lower page, Middle page, and Top page is “110”, it is moved to distribution S9, and when written to the Lower page, Middle page, and Top page. When the bit value on the page is "000", it is moved to distribution S12, and when the bit value written to the Lower page, Middle page and Top page is "010" In this case, it is moved to distribution S14. Here, it is ideal that distribution S1, distribution S4, distribution S5, distribution S8, distribution S9, distribution S12, and distribution S14 are used to reduce the threshold voltage in a way that reduces the width of the threshold area. Expand and roughly program. That is, the rising amplitude of the programmed voltage pulse described later is increased. By this, the time required for writing can be shortened. In addition, by programming in a way that the threshold voltage will be somewhat reduced, the threshold can be distributed in a way that will eventually become a specific width in the 2nd stage of programming The width of the area is for writing. Furthermore, ideally, the adjacent distribution S8 and the distribution S9, and the adjacent threshold distribution S12 and the distribution S14, the interval between each of these is set to be smaller than the adjacent distribution The interval between them is narrower. These adjacent threshold distributions with narrowed intervals have different write bit values from each other because the data on the Middle page are different. That is, the data after the programming of the 1st stage looks like a binary value (binary). Therefore, it is possible to read the data of the Lower page, the Middle page, and the Top page. However, by combining The data on the Middle page has different threshold distributions. The interval between the different threshold distributions is narrowed to ensure that the interval between the data on the Lower page and the top page is different from the threshold distribution, and to enable the reading of the Lower page and the Top page. The time margin (margin) increases. The threshold value distributions S0 to S14 shown in (T2) of Fig. 7 correspond to the 17th to 24th threshold value regions. Then, as shown in (T3) of FIG. 7, in the programming of the 2nd stage, two pages of the Middle page and the Upper page are required for data writing. In addition, the control unit 22 of the non-volatile memory 3 adopts a method in which the threshold value distribution after programming at the 2nd stage will be a final state where the adjacent distributions are separated and become a 16-value level. For stylization. After programming in the 2nd stage, it is able to read out all page data. In the programming of the 2nd stage, if the threshold value of the memory cell changes from the end of the programming of the 1st stage, the larger the interference system between adjacent cells becomes. Therefore, it is ideal to minimize the change in the threshold distribution of the memory cell with the maximum change in the threshold distribution. According to this embodiment, the maximum threshold distribution change is the amount of three threshold distributions, and the case where S0 changes to S3, the case where S4 changes to S7, and the case where S8 changes are The case of S11. The threshold value distributions S0 to S15 shown in (T3) of Fig. 7 correspond to the first to sixteenth threshold value regions. In addition, typically, programming is performed by applying a programming voltage pulse one or more times. In a plurality of programmed pulses, the voltage value is gradually increased. After each programmed voltage pulse, in order to confirm whether the memory cell has moved beyond the threshold level, a readout called verify is performed. By performing this application and reading repeatedly, it becomes possible to move the threshold value of the memory cell to a specific threshold value distribution range. In addition, although the control unit 22 can continuously perform the programming of the 1st stage and the programming of the 2nd stage for one character line WLi, in order to reduce the influence of the interference between adjacent memory cells, it is also acceptable. Across the plural character lines WLi ground to implement stylization in a non-continuous order. Fig. 8A is a diagram showing the first example of the stylized sequence of the first embodiment. Fig. 8B is a diagram showing a second example of the stylized sequence of the first embodiment. Fig. 8C is a diagram showing a third example of the stylized sequence of the first embodiment. In FIGS. 8A to 8C, in order to reduce the influence of interference between adjacent memory cells, the programming is performed in two programming stages. FIG. 8A shows an example of the programming sequence in the NAND memory 5 in which one string St is connected to each character line in each block. In addition, FIGS. 8B and 8C show an example of the programming sequence in the NAND memory 5 in which four character strings St are connected to each character line in each block. In addition, in FIG. 8B and FIG. 8C, the four character strings St connected to each character line are marked as String0~3. If it is to start writing, the control unit 22 performs various programming stages across the character line WLi in a specific non-continuous sequence. That is, the 1st stage and the 2nd stage for the same character line are not implemented continuously, but after the 1st stage is programmed for a character line, the different characters The 2nd stage of programming is performed on the element line. If after finishing programming for a certain character line up to the 2nd stage, the 1st and 2nd stages of programming are continuously performed for adjacent character lines, the variation of the threshold voltage is Will become bigger. However, if the variation of the threshold voltage of adjacent word lines is large, the intercellular interference of adjacent memory cells between the word lines will become larger. Therefore, in order to reduce the interference between adjacent memory cells between the word lines, after the word line is programmed until the 2nd stage, the variation of the threshold voltage of the adjacent word lines is reduced. Is effective. If it is the sequence of FIG. 8A, the programming phase of the adjacent character line after programming is completed until the 2nd phase for a certain character line, and it becomes only the 2nd phase. In the case of programming the NAND memory 5 with a three-dimensional structure in the programming sequence of FIG. 8A, if writing is started, the control unit 22 is based on the instruction from the processor 8, and by Perform programming in the order shown in (1) ~ (9) below. The control unit 22 programs the NAND memory 5 based on instructions from the processor 8. However, in the following, description of the content based on instructions from the processor 8 is omitted. (1) First, the control unit 22 implements the stylization ST11 of the 1st stage of the word line WL0. (2) Next, the control unit 22 implements the stylized ST12 of the 1st stage of the character line WL1. (3) Next, the control unit 22 implements the stylization ST13 of the 2nd stage of the character line WL0. (4) Next, the control unit 22 implements the stylized ST14 of the 1st stage of the character line WL2. (5) Next, the control unit 22 implements the stylization ST15 of the 2nd stage of the character line WL1. (6) Next, the control unit 22 implements the stylized ST16 of the 1st stage of the character line WL3. (7) Next, the control unit 22 implements the stylization ST17 of the 2nd stage of the character line WL2. (8) Next, the control unit 22 implements the stylized ST18 of the 1st stage of the character line WL4. (9) Next, the control unit 22 implements the stylization ST19 of the 2nd stage of the character line WL3. Hereinafter, in the same manner, the control unit 22 performs the processing from the lower left to the upper right in FIG. 8A and diagonally upward. In this way, in FIG. 8A, the plurality of memory cells in the non-volatile memory 3 are provided with the first memory cell having the plural numbers connected to the first character line, and the first memory cell is connected to the first character line. A plurality of second memory cells connected by a second character line adjacent to the character line, the memory controller 2, after performing the first programming on the plural first memory cells, Perform the first programming for the plurality of second memory cells, and then, after the first programming for the plurality of second memory cells, perform the first programming for the plurality of first memory cells Proceed to the second stylization. In the case of programming the NAND memory 5 with a three-dimensional structure in the programming sequence of FIG. 8B, if the writing is started, the control unit 22 is shown in (11) to (24) below To implement stylization. (11) First, the control unit 22 implements the stylized ST21 of the 1st stage of the character string St0_character line WL0. (12) Next, the control unit 22 implements the stylized ST22 of the 1st stage of the character string St1_character line WL0. (13) Next, the control unit 22 implements the stylized ST23 of the 1st stage of the word string St2_character line WL0. (14) Next, the control unit 22 implements the stylized ST24 of the 1st stage of the character string St3_character line WL0. (15) Next, the control unit 22 implements the stylized ST25 of the 1st stage of the word string St0_character line WL1. (16) Next, the control unit 22 implements the 2nd stage stylization ST26 of the word string St0_character line WL0. (17) Next, the control unit 22 implements the stylized ST27 of the 1st stage of the word string St1_character line WL1. (18) Next, the control unit 22 implements the 2nd stage stylization ST28 of the word string St1_character line WL0. (19) Next, the control unit 22 implements the stylized ST29 of the 1st stage of the word string St2_character line WL1. (20) Next, the control unit 22 implements the 2nd stage stylization ST210 of the word string St2_character line WL0. (21) Next, the control unit 22 implements the stylized ST211 of the 1st stage of the character string St3_character line WL1. (22) Next, the control unit 22 implements the 2nd stage stylization ST212 of the word string St3_character line WL0. (23) Next, the control unit 22 implements the stylized ST213 of the 1st stage of the word string St0_character line WL2. (24) Next, the control unit 22 implements the 2nd stage stylized ST214 of the word string St0_character line WL1. Hereinafter, in the same manner, the control unit 22 proceeds from the lower left to the upper right in FIG. 8B and obliquely upwards to perform the processing. In addition, in FIG. 8B, although the description is made for the case where there are four character strings St in the block, the number of character strings St in the block may be three or less, or five. the above. In the case of programming the NAND memory 5 with a three-dimensional structure in the programming sequence shown in FIG. 8C, if writing is started, the control unit 22 is shown by the following (31) to (50) To implement stylization. (31) First, the control unit 22 implements the stylized ST31 of the 1st stage of the word string St0_character line WL0. (32) Next, the control unit 22 implements the stylized ST32 of the 1st stage of the word string St1_character line WL0. (33) Next, the control unit 22 implements the stylized ST33 of the 1st stage of the character string St2_character line WL0. (34) Next, the control unit 22 implements the stylized ST34 of the 1st stage of the character string St3_character line WL0. (35) First, the control unit 22 implements the stylized ST35 of the 1st stage of the word string St0_character line WL1. (36) Next, the control unit 22 implements the stylized ST36 of the 1st stage of the character string St1_character line WL1. (37) Next, the control unit 22 implements the stylization ST37 of the 1st stage of the character string St2_character line WL1. (38) Next, the control unit 22 implements the stylized ST38 of the 1st stage of the character string St3_character line WL1. (39) Next, the control unit 22 implements the 2nd stage stylization ST39 of the word string St0_character line WL0. (40) Next, the control unit 22 implements the 2nd stage stylized ST310 of the word string St1_character line WL0. (41) Next, the control unit 22 implements the 2nd stage stylization ST311 of the word string St2_character line WL0. (42) Next, the control unit 22 implements the 2nd stage stylization ST312 of the word string St3_character line WL0. (43) Next, the control unit 22 implements the stylization ST313 of the 1st stage of the word string St0_character line WL2. (44) Next, the control unit 22 implements the stylized ST314 of the 1st stage of the character string St1_character line WL2. (45) Next, the control unit 22 implements the stylized ST315 of the 1st stage of the character string St2_character line WL2. (46) Next, the control unit 22 implements the stylized ST316 of the 1st stage of the character string St3_character line WL2. (47) Next, the control unit 22 implements the 2nd stage stylized ST317 of the word string St0_character line WL1. (48) Next, the control unit 22 implements the 2nd stage stylized ST318 of the word string St1_character line WL1. (49) Next, the control unit 22 implements the 2nd stage stylization ST319 of the word string St2_character line WL1. (50) Next, the control unit 22 implements the 2nd stage stylization ST320 of the word string St3_character line WL1. In addition, in FIG. 8C, although the description is made for the case where there are four character strings St in the block, the number of character strings St in the block may be three or less, or five. the above. In this way, even if the string St becomes a plural number, the programming sequence of each programming stage of the character line WLi in one string St is the same as when the string St is one. When there is a non-volatile memory 3 with a three-dimensional structure of plural strings St in the block, the programming of the combination position of the character line WLi and the string St is generally based on the relative The same character line number in the different string St is programmed, and then it advances to the next character line number. In the case of following this sequence, if FIG. 8A is combined with the quantity of the word string St, for example, the sequence will be the same as that of FIG. 8B or FIG. 8C. Here, an example of the writing procedure following the programming sequence of the first embodiment will be described with reference to FIGS. 9 to 11. In Figs. 9-11, the writing procedure is shown when following the programming sequence shown in Fig. 8B or Fig. 8C. As mentioned above, the memory controller 2 advances the programming stage while traversing the character line WLi in a non-continuous sequence. Therefore, the entire batch of certain character lines WLi (here, It is a block) as a whole of the programming sequence to be programmed. Fig. 9 is a flow chart showing the first example of the write procedure for the total amount of 1 block caused by the first embodiment. One block here is assumed to have n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). Fig. 10 is a flow chart showing the writing procedure in the 1st stage caused by the first embodiment, and Fig. 11 is a flowchart showing the writing procedure in the 2nd stage caused by the first embodiment The flow chart. As shown in FIG. 9, if writing is started, the control unit 22 executes the programming of the 1st stage of the string St0_character line WL0 (step S10). Next, the control unit 22 implements the programming of the 1st stage of the character string St1_character line WL0 (step S20). After that, the control unit 22 executes the same processing as steps S10 and S20 for each character string St. Next, the control unit 22 implements the programming of the 1st stage of the character string St3_character line WL0 (step S30). Furthermore, the control unit 22 implements the programming of the 1st stage of the character string St0_character line WL1 (step S40). Next, the control unit 22 implements the 2nd stage programming of the word string St0_character line WL0 (step S50). Next, the control unit 22 implements the programming of the 1st stage of the character string St1_character line WL1 (step S60). After that, the control unit 22 repeatedly performs the same processing as steps S40, S50, and S60 for each character line WLi of each character string St. Next, the control unit 22 implements the programming of the 1st stage of the word string St0_character line WLn (step S70). Next, the control unit 22 implements the 2nd stage programming of the word string St0_character line WLn-1 (step S80). After that, the control unit 22 repeatedly performs the same processing as steps S70 and S80 for each character line WLi of each character string St. Next, the control unit 22 implements the 2nd stage programming of the word string St3_character line WLn-1 (step S90). Next, the control unit 22 implements the 2nd stage programming of the word string St0_character line WLn (step S100). Next, the control unit 22 implements the 2nd stage programming of the word string St1_character line WLn (step S110). After that, the control unit 22 executes the same processing as steps S100 and S110 for each character string St. Next, the control unit 22 implements the 2nd stage programming of the word string St3_character line WLn (step S120). Fig. 10 is a flow chart showing the first example of the write procedure in the 1st stage. In the programming of the 1st stage, first, an input start command is input from the memory controller 2 to the non-volatile memory 3 with Lower page data (step S210). After that, the lower page data is input to the non-volatile memory 3 from the memory controller 2 (step S215). Next, the input start instruction of Middle page data is inputted from the memory controller 2 to the non-volatile memory 3 (step S220). After that, the middle page data is input to the non-volatile memory 3 from the memory controller 2 (step S225). Next, it is an input start instruction of the data of the Top page inputted from the memory controller 2 to the non-volatile memory 3 (step S230). After that, the top page data is input to the non-volatile memory 3 from the memory controller 2 (step S235). Furthermore, the 1st-stage programmed execution command is input to the non-volatile memory 3 from the memory controller 2 (step S240), and thereby becomes chip_busy (step S245). When data is written, the threshold voltage Vth is determined (step S250), and a programmed voltage pulse is applied from 1 to multiple times (step S255). After that, in order to confirm whether the memory cell has moved beyond the threshold level, data reading (verification) is performed (step S260). Furthermore, it is determined whether the number of fail-bits of the data in the Lower page, Middle page, and Top page is smaller than the criterion (step S265). When the number of failed bits of the data is greater than the criterion, the processing (steps S255 to S265) from the application of the programmed pulse to the criterion determination is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the judgment criterion, it becomes chip_ready (step S270). In this way, by repeatedly applying, reading and confirming, it becomes possible to move the threshold value of the memory cell to the specific threshold value distribution range. In addition, as mentioned above, the read level after the programming voltage pulse is applied in the 1st stage of writing can also be slightly different from the read level after the 2nd stage of writing. Ideally, it is better. The reading level after the 2nd stage writing is lower. That is, the system itself is Vr1'≦Vr1, Vr4'≦Vr4, Vr5'≦Vr5, Vr8'≦Vr8, Vr9'≦Vr9, Vr12'≦Vr12, Vr14'≦Vr14. In addition, in the reading after the programming voltage pulse is applied in the 1st stage writing, the reading caused by Vr9' and the reading caused by Vr14' can also be omitted. Vr9' is after passing Vr8. After'reading, after applying a certain number of programmed voltage pulses, it is set as the end of writing. Vr14' is after the reading of Vr13' is passed, after a certain number of programmed voltage pulses are applied After that, it is set as the end of writing. This is because, as mentioned above, by narrowing the interval between the data in the middle page of the programmed data in the 1st stage as different threshold areas, it is possible to perform writing in the 2nd stage. The data of the lower page and the top page that are read out are different in the interval of the threshold area, even if it is simply controlled by "applying a certain number of programmed voltage pulses", it can be sufficiently wide. Furthermore, it is also possible to omit the reading after the application of the programmed voltage pulses of Vr8' and Vr9', Vr12' and Vr14', and after passing the reading of Vr5', after applying a certain number of times respectively. After programming the voltage pulse, set the end of writing. In addition, furthermore, it is also possible to omit the reading after applying the programmed voltage pulses of Vr4', Vr5', Vr8', Vr9', Vr12', and Vr14', and after passing the reading of Vr1' , After applying the programmed voltage pulses of a certain number of times respectively, it is set as the end of writing. Fig. 11 is a flow chart showing the first example of the 2nd stage writing procedure. In the programming of the 2nd stage, first, the input start instruction of the data of the Middle page inputted from the memory controller 2 to the non-volatile memory 3 (step S310). After that, the data of the Middle page is input to the non-volatile memory 3 from the memory controller 2 (step S320). Next, it is an input start instruction of the data of the upper page inputted from the memory controller 2 to the non-volatile memory 3 (step S330). After that, the data of the Upper page is input to the non-volatile memory 3 from the memory controller 2 (step S340). Next, a 2nd-stage programmed execution command is input from the memory controller 2 to the non-volatile memory 3 (step S350), and thereby becomes chip_busy (step S360). After that, the control unit 22 reads the Lower page and Top page data, which are IDL (Internal Data Load) (step S370). After that, based on the previously input Middle page data and the Lower page and Top page data caused by IDL, the Vth (threshold voltage) of the programming target of the Upper page is determined (step S380). After that, using the determined Vth, the data writing system for the Upper page is performed. More specifically, the voltage values of the plural programming pulses are gradually increased and written so as to become the determined threshold voltage (step S390). The memory cell that has reached the target threshold voltage is removed from the writing target. After that, the written data is read (step S400), and it is determined whether the number of failed bits is smaller than the criterion (step S410). When the number of failed bits of the data is greater than the judgment criterion, the processing from the application of the programmed pulse to the criterion judgment (steps S390 to S410) is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the judgment criterion, it becomes chip_ready (step S420). Here, in this embodiment, there are two characteristics. The first feature is that the data of the Middle page has been entered in the 1st stage of programming, and the threshold area after the 1st programming is the writing state that also contains the data of the Middle page. However, In the programming of the 2nd stage, the data of the middle page is still entered again. The second feature is that in the programming of the 1st stage, the interval between the adjacent threshold areas for switching the data of the Middle page is narrowed. On the contrary, the data of the Lower page and the data of the Top page are switched. The adjacent threshold values are distributed with each other, and the interval system becomes wider. With this, the reliability of the Lower page and Top page data read by IDL can be improved. On the other hand, if the data of the Middle page is read by IDL, the reliability may be reduced. However, in this embodiment, it will be used in the 1st stage programming. The data of the middle page that has been added is entered again, so there will be no problem of reduced reliability. Furthermore, the control unit 22 can also read multiple times in order to improve the reliability of the read data of the IDL, and use the majority of the read results in the page buffer within the chip as the interface Write down the data for use. Of course, the control unit 22 can also perform multiple readings during normal reading operations and use the majority of the reading results in the chip for use as external reading data. FIG. 12 is a diagram for explaining the majority decision processing of the read result of the plural number of times. In Figure 12, as the result of reading the data of a specific page, the correct bit is marked with a circle mark (○), and the wrong bit is marked with a cross mark (×) Make the mark. In addition, in FIG. 12, the result of the majority decision when the reading is performed three times is shown. At each position, the result of the majority decision is judged to be wrong, which is (a) the case where all 3 times are wrong, and (b) the case where 2 times are wrong. If the probability of each bit being wrong is set to p, then p=0. In the case of 2, (a) the probability of 3 errors is p×p×p=0. 2×0. 2×0. 2. (b) The probability of 2 errors is (1-p)×p×p=(1-0. 2)×0. 2×0. 2. Therefore, the probability that the result of the 3rd majority decision is judged to be wrong is (p×p×p) + 3×(1-p)×p×p=0. 104. In this way, the control unit 22 can improve the reliability of the read data by performing the majority processing of the read results of a plurality of times at the page buffer 24 in the chip. Furthermore, the control unit 22 may also perform writing in response to writing in the 1st stage of WLn+1 in order to improve the reliability of the IDL read data in the 2nd stage writing of the word line WLn. The data or the threshold voltage is used to change the reading voltage of the word line WLn at the IDL and perform reading. Furthermore, the control unit 22 can also improve the reliability of the IDL read data in the 2nd stage writing of the word line WLn, and respond to the writing in the 1st stage of the word line WLn+1. The written data or the threshold voltage is used to change the non-select voltage of the word line WLn+1 at the IDL and read. At this time, it is also possible to simultaneously change the read voltage of the word line WLn and perform read. When writing data to the Upper page, a programmed voltage pulse is applied from 1 to multiple times. After that, in order to confirm whether the memory cell has moved beyond the threshold level, the data read (verification) with the upper page is performed. The reading level at this time is a specific level. Furthermore, it is determined whether the number of failed bits of the data in the Upper page is smaller than the determination criterion. When the number of failed bits of the data in the Upper page is above the judgment criterion, the processing from the application of the programmed voltage pulse to the verification is repeated. However, if the number of failed bits of the data becomes smaller than the judgment criterion, it becomes chip_ready. Here, a modification of the writing program shown in FIG. 11 will be described. FIG. 13 is a flowchart showing a modification example of the writing procedure in the 2nd stage of the first embodiment. In addition, in the flowchart in Fig. 13, there is added "The IDL data read out of the data programmed in the 1st stage is corrected, and the error is sent back to the non-volatile memory 3." The procedure. Specifically, first, a read command of the lower page is input to the non-volatile memory 3 from the memory controller 2 (step S510). With this, the system becomes chip_ready (step S512). Next, the control unit 22 reads the lower page data using the threshold voltage of Vr8'. After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the reading result at the threshold voltage of Vr8' (step S514). After that, the system becomes chip_ready (step S516). If the lower page data read by the control unit 22 is output (step S518), the lower page data is sent to the ECC circuit 10 (step S520). With this, the ECC circuit 10 performs ECC correction on the lower page data (step S522). Next, it is an input start instruction of the data of the lower page inputted from the memory controller 2 to the non-volatile memory 3 (step S524). With this, the ECC circuit 10 inputs the data of the lower page to the non-volatile memory 3 (step S526). Next, a read command of the Top page is inputted from the memory controller 2 to the non-volatile memory 3 (step S528), and thereby becomes chip_busy (step S530). After that, the control unit 22 reads the Top page data using the threshold voltages of Vr2' and Vr10'. After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the reading results at the threshold voltages of Vr1', Vr4', Vr8', and Vr12' (Step S532). After that, the system becomes chip_ready (step S534). If the top page data read by the control unit 22 is output (step S536), the top page data is sent to the ECC circuit 10 (step S538). With this, the ECC circuit 10 performs ECC correction on the Top page data (step S540). Next, it is an input start command for the data of the Top page inputted from the memory controller 2 to the non-volatile memory 3 (step S542). With this, the ECC circuit 10 inputs the top page data to the non-volatile memory 3 (step S544). After that, it is the input start command that the middle page data is input from the memory controller 2 to the non-volatile memory 3. (Step S546). The subsequent steps are the same as the procedure in Figure 11. The threshold voltage Vth of the programmed target is based on the Lower page data and Top page data from the ECC circuit 10, the data of the Middle page that has been input again, and the data of the newly input Upper page. Determine the threshold voltage Vth of the programmed target. In the above-mentioned 2nd stage programming, the data input of non-volatile memory 3 is only two pages of Middle page and Upper page. However, in this 2nd stage, at the threshold voltage Vth which is the programmed destination of the memory cell, it is necessary to also include the Lower page and Top page (the threshold voltage Vth before the start of the 2nd stage). ) Of 4 pages of data. Therefore, in the programming at this stage, as a pre-processing, the control unit 22 performs "first read the lower page data and the top page data, and then use the inputted middle page and the middle page with the data. The Upper page is used to synthesize and determine the action of the threshold voltage Vth of the programmed target. In addition, the read level during the 2nd stage verification may be slightly different from the read level after the 2nd stage write. Here, a comparison between the Foggy-Fine stylized processing procedure using 4-3-4-4 data coding and the stylized processing procedure of this embodiment will be explained. FIG. 14A is a diagram for explaining the amount of data written in the buffer in the Foggy-Fine programming using 4-3-4-4 data encoding. Fig. 14B is a diagram for explaining the amount of data written in the buffer in this embodiment. Figure 14B shows an example of using 1-4-5-5 data coding. In Fig. 14A and Fig. 14B, on the upper stage side, the timing chart for data input and programming execution of block writing is shown, and on the lower stage side, it’s for data retention in the write buffer. The timing chart of the required period is displayed. In addition, in FIG. 14A and FIG. 14B, in order to simplify the description, the case where the number of the string St in one block is one is shown. When the string St is a plural number, the amount of data written into the buffer is a multiple of the number of the string St. In the case of Foggy-Fine programming of 4-3-4-4 data coding, in the Foggy stage, which is the first stage, 4 pages of data input and these 4 pages are performed The stylization of the quantity (the stylization of the Foggy stage). In addition, in the case of Foggy-Fine programming of 4-3-4-4 data coding, in the Fine stage, which is the second stage, data input for 4 pages is also performed, and this The stylization of the amount of 4 pages (the stylization of the Fine stage). However, at each word line WL0, WL1, WL2,..., until the programming is started at the Fine stage, it is necessary to write the data in the amount of 4 pages written in the Foggy stage , Pre-stored in the write buffer. In Foggy-Fine programming, in the same way, in order to reduce the interference between adjacent memory cells, the data of the 4 pages of Lower/Middle/Upper/Top are not written continuously. For example, after the Foggy phase for the word line WL0 is executed, before the Fine phase for the word line WL0 is executed, the Foggy phase for the word line WL1 adjacent to the word line WL0 is executed. . Furthermore, after the Foggy phase for the word line WL0 is executed, before the Fine phase for the word line WL1 is executed, the Foggy phase for the word line WL2 adjacent to the word line WL1 is executed. . In the case of this method, it is necessary to keep the data of 4 pages of Lower/Middle/Upper/Top in the write buffer in advance until the end of the data input of the second Fine stage. Inside. In addition, in order to reduce the interference between adjacent memory cells, it is necessary to hold the data at the plural character lines WLi in the write buffer in advance. For example, when the Foggy stage is implemented for the word line WL2, it is necessary to keep the data for the 3 pages of the word line WL1 and the data for the 3 pages of the word line WL2 in writing. Into the buffer. In this way, in the case of Foggy-Fine programming of 4-3-4-4 data encoding, it is necessary to keep a maximum of 8 pages of data in the write buffer. As shown in FIG. 14B, in the stylization of this embodiment, for example, a 2-stage stylization is used with 1-4-5-5 data encoding. In the programming of this embodiment, in the 1st stage, data input for the amount of three pages (Lower page, Middle page and Top page) and the programming of the amount of these three pages (1st stylization) are performed. ). In the case of the programming of this embodiment, in the 2nd stage, data input for two pages (Middle page and Upper page) and programming for one page of the Upper page are performed ( 2nd stylized). However, at each character line WL0, WL1, WL2,..., except for the Middle page that is input in both stages, as long as the data is pre-stored in the write buffer during the data input of each stage. However, if programming is started, the data can also be deleted from the write buffer. For example, if data is input at the 1st stage, the data is stored in the write buffer. However, if the programming is started at the 1st stage, the data of the Lower page and the Top page previously stored in the write buffer can also be deleted. Similarly, if data is input at the 2nd stage, the data is stored in the write buffer. However, if programming is started at the 2nd stage, all the data previously stored in the write buffer can also be deleted. Therefore, in the case of programming in this embodiment, it is necessary to hold the data in the write buffer in advance, even if it is a maximum of 4 pages of data. In the programming of this embodiment, in the same way, in order to reduce the interference between adjacent memory cells, the data of the 4 pages of Lower/Middle/Upper/Top are not written continuously. For example, after the 1st stage for the word line WL0 is executed, before the 2nd stage for the word line WL0 is executed, the 1st stage for the word line WL1 adjacent to the word line WL0 is executed. . Similarly, after the 1st stage for the word line WL1 is executed, before the 2nd stage for the word line WL1 is executed, the 1st stage for the word line WL2 adjacent to the word line WL1 is Implement. In this way, in this embodiment, the page data other than the middle page is only necessary for programming in one stage. Therefore, if the data input is completed, it becomes possible to write to the buffer. The data inside is deleted. Therefore, in this embodiment, it is necessary to keep the number of pages in the write buffer at the same time in advance at a small amount. The page data programmed for the non-volatile memory 3 is temporarily held in the write buffer in the RAM 6 and then the data is input into the non-volatile memory 3 during programming. In this embodiment, since the necessary capacity of the RAM 6 can be reduced, the cost can be reduced. In addition, when using Foggy-Fine programming, because it is necessary to transfer all the page data twice, it will take time for the transfer and it will also consume more power when the transfer is required. In this embodiment, the page data other than the middle page is individually completed by one data transmission for each page, so the transmission time and power consumption can be suppressed to about 1/2. Here, the page reading process will be described. The method of page reading differs based on whether the programming of the character line WLi containing the read target page is a 2nd stage before writing or after writing. In the situation before writing in the 2nd stage, only the lower page, middle page and top page are valid for the data to be recorded. Therefore, the control unit 22 reads the data from the memory cell when the read page is the Lower page, Middle page, and Top page, but in other pages (specifically, Upper page) In the case of, the system does not perform the memory cell read operation, and performs the control of forcibly outputting all "1" as the read data. On the other hand, in the case of the character line WLi that has ended up to the 2nd stage, the control unit 22 reads the memory cell regardless of whether the read page is Top/Upper/Middle/Lower page Out. In this case, the required read voltage is different because it depends on which page is the page to be read. Therefore, the control unit 22 performs only necessary reading according to the selected page. Out. The following describes the specific processing procedures for page reading. Figure 15 shows the page read at the character line where the programming up to the 1st stage in the memory system 1 caused by the first embodiment is finished (the programming system of the 2nd stage has not yet ended) The processing procedure is shown as a flow chart. According to the 1-4-5-5 data encoding shown in Fig. 6, the boundary between the threshold states changed by the Lower page data is one, so the control unit 22 is based on the threshold value as The location is determined by which of the two areas separated by the boundary is the data. For example, when the threshold voltage is smaller than Vr8', the control unit 22 performs control to output "1" as the data of the memory cell. On the other hand, when the threshold voltage is larger than Vr8', the control unit 22 performs control to output "0" as the data of the memory cell. In addition, since the boundary between the threshold states where the Middle page data changes is three, the control unit 22 is based on the threshold as the position in the four separated by these boundaries. Which one of the scopes determines the data. In addition, since the boundaries between the threshold states where the Top page data changes are four, the control unit 22 is based on the threshold as the position in the five separated by these boundaries. Which one of the scopes determines the data. As shown in FIG. 15, in the case of the word line WLi before writing in the 2nd stage, the control unit 22 selects the read page (step S610). When the read page is a lower page, the control unit 22 performs reading with one read voltage (step S612). This voltage is Vr8, but, as mentioned above, in the case of the character line before the 2nd stage writing, as shown in Figure 8 (T2), it can also have a read voltage and threshold The margin of the value voltage is, for example, Vr8'. After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the reading result at the threshold voltage of Vr8 (step S614). In addition, when the read page is a middle page, the control unit 22 performs reading using three read voltages (steps S616, S618, and S620). This voltage is Vr4 and Vr9 and Vr14 as mentioned above. However, when it is a character line before the 2nd stage writing, as shown in Figure 8 (T2), the system can also have read The margin between the output voltage and the threshold voltage is set to Vr4', Vr9' and Vr14' instead of these, for example. After that, the control unit 22 compares the results based on the reading result under the threshold voltage of Vr4, the reading result under the threshold voltage of Vr9, and the reading result under the threshold voltage of Vr14. The value of the read data is determined to be "0" or "1" (step S622). Here, as mentioned above, since the interval of the different threshold distributions for the data of the Middle page is narrow, and the reading margin of the Middle page is narrowed, the value of the read data will have significant reliability. The possibility of ground deterioration, and the middle page data before the 2nd stage writing can be defined as invalid. In this case, when the read page is a middle page, the control unit 22 can also perform the control of forcibly outputting all "1"s as the output data of the memory cell. Also, when the read page is an Upper page, since the programming of the Upper page is not performed in the 1st programming, the control unit 22 compulsorily outputs all "1" as output data. (Step S624). In addition, when the read page is the Top page, the control unit 22 performs reading with four read voltages (steps S626, S628, S630, and S632). This voltage is the same as described above, but Vr1 and Vr4, Vr8 and Vr12. However, in the case of the character line before the 2nd stage writing, it is as shown in Figure 8 (T2). There is a margin for the readout voltage and the threshold voltage, and for example, instead of these, set Vr1' and Vr4', Vr8' and Vr12', respectively. After that, the control unit 22 is based on the reading result under the threshold voltage of Vr1 and the reading result under the threshold voltage of Vr4, the reading result under the threshold voltage of Vr8 and the reading result under the threshold voltage of Vr12. As a result of the reading under the threshold voltage, the value of the read data is determined to be "0" or "1" (step S634). FIG. 16A is a flowchart showing the processing procedure of page reading at the character line programmed to end up to the 2nd stage in the memory system 1 of the first embodiment. When the stylized character line WLi is ended until the 2nd stage, the control unit 22 selects the read page (step S650). When the read page is a lower page, the control unit 22 performs the read based on the threshold voltage of one of Vr8 (step S652). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the reading result at the threshold voltage of one of Vr8 (step S654). In addition, when the read page is a middle page, the control unit 22 reads using the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (steps S656, S658, S660, and S662). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the reading results under the threshold voltages of Vr4, Vr9, Vr11, and Vr14 (step S664) . In addition, when the read page is the upper page, the control unit 22 performs the read based on the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (steps S666, S668, S670, S672, S674 ). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the reading results at the threshold voltages of Vr2, Vr6, Vr10, Vr13, and Vr15 (step S676). In addition, when the read page is the Top page, the control unit 22 performs the reading based on the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12 (steps S678, S680, S682, S684, S686). ). After that, the control unit 22 determines the value of the read data to be "0" or "1" based on the reading results under the threshold voltages of Vr1, Vr3, Vr5, Vr7, and Vr12 (step S688). In addition, whether the programming of the word line WLi is before or after the completion of the writing in the 2nd stage can be managed and identified by the memory controller 2. In the memory system 1, since the memory controller 2 performs programmed control, as long as the memory controller 2 records the progress in advance, the memory controller 2 can easily control the non-volatile The address of the sexual memory 3 is based on what kind of programmatic state it is. In this case, when the memory controller 2 reads from the non-volatile memory 3, it recognizes the programmed state of the character line WLi containing the address of the target page, and issues and The read command corresponding to the identified state. In addition, as another method, it is also possible to separately set a flag cell at each of the character lines WLi, and write to the flag cell during the 2nd stage of writing, and respond to the data of the flag cell , To use the non-volatile memory 3 to manage and identify whether it is before or after the end of the 2nd stage of writing. Hereinafter, a modification example of the page reading process will be described. The page reading process caused by one of the modified examples can be executed only when the programming of the character line WLi containing the read target page is performed after the 2nd stage of writing has been performed. In the page reading process due to one of the modified examples, when all the data of the character line of the reading target is read, the reading speed becomes faster, and at this point, it is effective. The data encoding suitable for the page reading process caused by one of the modifications is, for example, the one shown in FIG. 16B. Hereinafter, the reading process caused by one of the modified examples in the case of data encoding will be explained. In the page reading process caused by one of the modified examples, all the pages of the Top/Upper/Middle/Lower pages are read. FIG. 16C is a flowchart showing the read processing procedure caused by one of the modified examples. In addition, FIG. 16D is a voltage waveform diagram of the selected word line, the ReadyBusy signal line, and the output data line. The control unit 22 reads sequentially using all 15 read voltages Vr15 to Vr1. First, as shown in FIG. 16D, the reading is performed with Vr15, which is the highest voltage (step S690), and then, the ground is lowered one step at a time to sequentially continue reading with a low reading voltage. Out (steps S691 to S707). When the reading required to determine the reading data of each page is finished, the reading data of the page becomes able to be output. In the page reading process caused by one of the modified examples, when the reading from Vr15 is performed in sequence and the reading of Vr8 ends (step S699), the data of the lower page is determined and becomes This data can be output (step S700). In this step S700, based on the read data caused by the read voltage Vr8, the data of the lower page is determined. Then, when the reading of Vr4 ends (step S702), the data of the middle page is determined (step S703). In this step S703, based on the read data caused by the read voltages Vr4, Vr9, Vr11, and Vr14, the data of the middle page is determined. Then, when the reading of Vr2 ends (step S705), the data of the upper page is determined (step S706). In this step S706, based on the read data caused by the read voltages Vr2, Vr6, Vr10, Vr13, and Vr15, the data of the Upper page is determined. Then, until the reading of Vr1 ends (step S707), the data of the final Top page is determined (step S708). In this step S708, based on the read data caused by the read voltages Vr1, Vr3, Vr5, Vr7, and Vr12, the data of the Top page is determined. In the page reading process caused by one of the modified examples, the latency until the data of any one page can be output is increased, but the total time for reading all 4 pages , The total time can be shortened compared to the case of reading one page at a time as described above. As shown in FIG. 16D, the time required to charge the word line from 0 to Vr15, which is a high voltage, as a read preparation, only needs to be done once. The amplitude of the voltage change when changing to the next voltage is small, and the voltage becomes stable in a short time. Therefore, the standby time until the read voltage becomes stable can be shortened. Therefore, when reading is performed with all the reading voltages Vr15 to Vr1, the total of the transition time of the selected word line is shortened, and as a result, the total reading time can be increased. In addition, although the data encoding in FIG. 16B is used as an example for the above description, basically, it can be applied to any data encoding. However, since the read voltage is sequentially changed from the maximum voltage to the minimum voltage and read is performed, the reading of the voltage required to determine the data is in the order of the page that ends first. Ability to export data. Therefore, it should be noted that depending on the form of data encoding, there may be situations where it is impossible to read in the order of Lower, Middle, Upper, and Top pages. In this way, in the first embodiment, when programming the non-volatile memory 3 (a 4bit/Cell NAND memory with a 3-dimensional structure or a 2-dimensional structure), 1-4-5 is used. -5 Data coding, and set the programming stage to a 2-stage system. Since it is programmed in a two-stage system in this way, the amount of input data in the data programming at each stage is reduced, and it can be used for writing necessary in the memory controller 2. The amount of buffer is suppressed. In addition, since the number of threshold boundaries at each page is uniform, the bias of the bit error rate between pages of the non-volatile memory 3 can be reduced, and the cost of ECC can be reduced. reduce. In addition, since the data transmission is performed only once for each page except for one page, the transmission time and power consumption can be suppressed. In addition, since each programming stage is performed while straddling the character line WLi, it is possible to reduce the amount of adjacent cell interference with the adjacent character line WLi. In addition, since the 1-4-5-5 data encoding is used, the amount of change in the threshold distribution in the 2nd stylization is reduced, so that the amount of interference between adjacent cells can be suppressed. In addition, by inputting data in one page (specifically, the middle page) in both stages, the IDL margin before the 2nd stage can be enlarged, and the reliability of the writing sequence can be improved. In addition, since the 1-4-5-5 data encoding is used, in the programming of the 1st stage, by setting the threshold boundary at the Lower page to one, the threshold at the Middle page is set The limit value is set to two, which can make the programming of the 1st stage, that is, the programming of the Lower page and the Middle page faster. In addition, the programming speed of the 1st stage can be used to step up the writing voltage step by step and to step up the writing voltage step by step during repeated writing and writing verification. Set a larger value than the programming of the 2nd stage to increase the speed. (Second Embodiment) In the first embodiment, although 1-4-5-5 data encoding is used as an example, various data encoding modifications can be used. The hardware configuration of the memory system 1 according to the second embodiment is the same as that of the memory system 1 according to the first embodiment. Figures 17-25 show examples of data encoding in the memory system 1 caused by the second embodiment. The memory system 1 resulting from the second embodiment uses a data code other than the data code of 1-4-5-5. Figure 17 is a diagram showing an example of coding 1-5-4-5 data. In the example of FIG. 17, the number of transitions in the threshold area at the end of the 2nd stylization is 3 at most. Here, the voltage distribution ranges of the threshold area at the end of the programming of the 1st stage and the threshold area at the end of the programming of the 2nd stage are not completely consistent with each other. However, in this manual, for the convenience of explanation, For each threshold area at the end of the programming of the 1st stage, the threshold area at the end of the programming of the 2nd stage with the closest voltage distribution range is added to correspond, and it will change when the 2nd programming is performed. The number of threshold areas is called the number of transitions. In the case of Figure 17, at the 1st stage, the data of the Lower page, Middle page, and Upper page are input for programming, and at the 2nd stage, the data of the Top page and Middle page are input and programmed. The data on the Middle page is repeatedly entered at the 1st stage and the 2nd stage. The interval between the two threshold areas that can be separated by the value of the data on the Middle page at the end of the programming of the 1st stage is set to be narrower than the interval between other threshold areas. Figure 18 is a diagram showing an example of 1-5-4-5 data encoding. In the example of FIG. 18, the number of transitions in the threshold area at the end of the 2nd stylization is 3 at most. In the case of Figure 18, at the 1st stage, the data of the Lower page, the Middle page, and the Upper page are input for programming, and at the 2nd stage, the data of the Top page and the Upper page are input and programmed. The information on the Upper page is repeatedly entered at the 1st and 2nd stages. The interval between the two threshold regions that can be separated by the value of the upper page data at the end of the programming of the 1st stage is set to be narrower than the interval between other threshold regions. Figure 19 is a diagram showing an example of 3-5-2-5 data coding. In the example of FIG. 19, the number of transitions in the threshold area at the end of the 2nd stylization is 3 at most. In the case of Figure 19, at the 1st stage, the data of the Lower page, Middle page, and Upper page are input for programming, and at the 2nd stage, the data of the Top page and Middle page are input and programmed. The data on the Middle page is repeatedly entered at the 1st stage and the 2nd stage. The interval between the two threshold areas that can be separated by the value of the data on the Middle page at the end of the programming of the 1st stage is set to be narrower than the interval between other threshold areas. Figure 20 is a diagram showing an example of 3-3-4-5 data encoding. In the example of FIG. 20, the number of transitions in the threshold area at the end of the 2nd stylization is 3 at most. In the case of Figure 20, at the 1st stage, the data of the Lower page, the Middle page, and the Upper page are input for programming, and at the 2nd stage, the data of the Top page and the Upper page are input and programmed. Figure 21 is a diagram showing an example of 2-3-5-5 data coding. In the example of FIG. 21, the number of transitions in the threshold area at the end of the 2nd stylization is 5 at most. In the case of Figure 21, at the 1st stage, the data of the Lower page, Middle page, and Top page are input for programming, and at the 2nd stage, the data of the Top page and Upper page are input and programmed. The information on the Top page is repeatedly entered at the 1st stage and the 2nd stage. In the case of Figure 21, at the time point when the programming of the 1st stage ends, regardless of whether the data of the Top page is 0 or 1, the three threshold areas become the same, and the total number of threshold areas becomes 5 pcs. Therefore, the interval between each threshold area can be expanded, and the data at the time point when the programming of the 1st stage ends can be accurately read. Figure 22 is a diagram showing an example of 3-2-5-5 data coding. In the example of FIG. 22, the number of transitions in the threshold area at the end of the 2nd stylization is 5 at most. In the case of Fig. 22, at the 1st stage, the data of the Lower page, Middle page, and Top page are input for programming, and at the 2nd stage, the data of the Top page and Upper page are input and programmed. The information on the Top page is repeatedly entered at the 1st stage and the 2nd stage. In the case of Figure 22, at the time point when the programming of the 1st stage ends, regardless of whether the data of the Top page is 0 or 1, the threshold area of both becomes the same, and the total number of threshold areas becomes 6 pcs. Figure 23 is a diagram showing an example of 3-4-4-4 data encoding. In the example of FIG. 23, the number of transitions in the threshold area at the end of the 2nd stylization is 7 at most. In the case of Figure 23, at the 1st stage, the data of the Lower page, Middle page, and Upper page are input for programming, and at the 2nd stage, the data of the Top page and Upper page are input and programmed. The information on the Upper page is repeatedly entered at the 1st and 2nd stages. The interval between the two threshold regions that can be separated by the value of the upper page data at the end of the programming of the 1st stage is set to be narrower than the interval between other threshold regions. Figure 24 is a diagram showing an example of 3-4-4-4 data encoding. In the example of FIG. 24, the number of transitions in the threshold area at the end of the 2nd stylization is 8 at most. In the case of Figure 24, at the 1st stage, the data of the Lower page, Middle page, and Top page are input for programming, and at the 2nd stage, the data of the Top page and Upper page are input and programmed. The information on the Top page is repeatedly entered at the 1st stage and the 2nd stage. In the case of Fig. 24, at the time point when the programming of the 1st stage ends, no matter whether the data of the Top page is 0 or 1, the threshold area of both becomes the same, and the total number of threshold areas becomes 6 pcs. Figures 17-24 are only examples of data encoding, and other data encodings can also be used. For example, at the end of the 2nd stylization, the transition number system of the threshold value area becomes a maximum of three. In addition to Figs. 17 to 20, the following Figs. 25 to 27 also exist. Figure 25 is a diagram showing an example of coding 1-4-5-5. In the example of FIG. 25, at the time point when the 1st stylization ends, 6 different threshold regions are generated. Among them, the threshold area where the Middle page is 1 and the Lower page is 1, and the threshold area where the Middle page is 0 and the Lower page is 1, become the same threshold regardless of whether the Top page is 0 or 1. area. Therefore, although 8 threshold areas should have been generated originally, they are collected into 6 threshold areas. Figure 26 is a diagram showing an example of 2-5-3-5 data encoding. In the example of FIG. 26, at the point in time when the 1st stylization ends, 7 different threshold regions are generated. Among them, the threshold area where the Middle page is 1 and the Lower page is 1, regardless of whether the Top page is 0 or 1, all become the same threshold area. Therefore, although there should be 8 threshold regions originally generated, they are collected into 7 threshold regions. Figure 27 is a diagram showing an example of 3-4-5-3 data coding. In the example of FIG. 27, at the point in time when the 1st stylization ends, 7 different threshold regions are generated. Among them, the threshold area where the Middle page is 1 and the Lower page is 1, regardless of whether the Top page is 0 or 1, all become the same threshold area. Therefore, although there should be 8 threshold regions originally generated, they are collected into 7 threshold regions. In addition, other data coding examples can also be considered. Below, the code allocation for each data code will be shown as a list. Figure 28 shows an example of 3-2-5-5 data encoding, Figure 29 shows an example of 3-2-5-5 data encoding, and Figure 30 shows an example of 1-5-5 -4 One example of data coding will be displayed. In addition, Figure 31 shows one example of 1--5-4-5 data encoding, Figure 32 shows one example of 1-4-5-5 data encoding, and Figure 33 shows one example of data encoding 1-5 -3-6 An example of data coding is displayed. In addition, Figure 34 shows an example of 1-3-6-5 data encoding, Figure 35 shows an example of 1-2-6-6 data encoding, and Figure 36 shows an example of 1-2 -6-6 One example of data coding is displayed. Also, Figure 37 shows an example of 1-2-6-6 data encoding, Figure 38 shows an example of 1-4-6-4 data encoding, and Figure 39 shows an example of data encoding 1-4 -4-6 One example of data coding is shown. Also, Figure 40 shows an example of 1-4-6-4 data encoding, Figure 41 shows an example of 1-4-4-6 data encoding, and Figure 42 shows an example of 2-5 -2-6 One example of data coding is displayed. In addition, Figure 43 shows an example of 2-5-2-6 data encoding, Figure 44 shows an example of 2-5-2-6 data encoding, and Figure 45 shows an example of 3-3. -3-6 An example of data coding is displayed. In addition, Figure 46 shows an example of 3-3-6-3 data encoding, Figure 47 shows an example of 2-3-4-6 data encoding, and Figure 48 shows an example of 3-4 -2-6 One example of data coding is displayed. Also, Figure 49 shows an example of 2-3-4-6 data encoding, Figure 50 shows an example of 3-2-6-4 data encoding, and Figure 51 shows an example of 3-2 -4-6 One example of data coding is shown. In addition, Figure 52 shows an example of 3-2-6-4 data encoding, Figure 53 shows an example of 3-4-2-6 data encoding, and Figure 54 shows an example of 3-2 -4-6 One example of data coding is shown. In addition, Figure 55 shows an example of 5-3-2-5 data encoding, Figure 56 shows an example of 3-5-2-5 data encoding, and Figure 57 shows an example of 3-2 -5-5 One example of data coding is displayed. In addition, Figure 58 shows one example of 2-3-5-5 data encoding, Figure 59 shows one example of 2-3-5-5 data encoding, and Figure 60 shows one example of 2-3-5-5 data encoding. -5-5 One example of data coding is displayed. Also, Figure 61 shows one example of 5-4-2-4 data encoding, Figure 62 shows one example of 4-5-2-4 data encoding, and Figure 63 shows one example of 5-4 -An example of 2-4 data encoding is displayed. Also, Figure 64 shows one example of 2-4-5-4 data encoding, Figure 65 shows one example of 2-4-5-4 data encoding, and Figure 66 shows one example of 2-5. -4-4 One example of data coding is shown. In addition, Figure 67 shows one example of 2-5-4-4 data encoding, Figure 68 shows one example of 2-5-4-4 data encoding, and Figure 69 shows one example of 2-5-4-4 data encoding. -An example of 4-5 data coding for display. In addition, Figure 70 shows an example of 1-4-5-5 data encoding, Figure 71 shows an example of 1-5-5-4 data encoding, and Figure 72 shows an example of 1-4-5-5 data encoding. -5-5 One example of data coding is displayed. In addition, Figure 73 shows an example of the data encoding 1-5-4, Figure 74 shows an example of the data encoding 1-5-4-5, and Figure 75 shows an example of the data encoding 1-5. -5-4 One example of data coding is displayed. In addition, Figure 76 shows one example of 1--5-4-5 data encoding, Figure 77 shows one example of 1-4-5-5 data encoding, and Figure 78 shows one example of data encoding 1-4 -5-5 One example of data coding is displayed. In addition, Figure 79 shows an example of 1-4-5-5 data encoding, Figure 80 shows an example of 1-4-5-5 data encoding, and Figure 81 shows an example of 3-5 -4-3 One example of data coding is shown. In addition, Figure 82 shows an example of 3-4-5-3 data encoding, Figure 83 shows an example of 3--5-3-4 data encoding, and Figure 84 shows an example of 3-4 -One example of 3-5 data coding for display. In addition, Figure 85 shows an example of 3-4-5-3 data encoding, Figure 86 shows an example of 3--4-3-5 data encoding, and Figure 87 shows an example of 3-3. -5-4 One example of data coding is displayed. In addition, Figure 88 shows an example of 3-3-5-4 data encoding, Figure 89 shows an example of 4-5-3-3 data encoding, and Figure 90 shows an example of 3-5-4 data encoding. -4-3 One example of data coding is shown. In addition, Figure 91 shows an example of 3-4-5-3 data encoding, Figure 92 shows an example of 3-3-4-5 data encoding, and Figure 93 shows an example of 3-3. -An example of 4-5 data coding for display. In addition, Figure 94 shows an example of 3-3-4-5 data encoding, Figure 95 shows an example of 3-4-5-3 data encoding, and Figure 96 shows an example of 3-3. -5-4 One example of data coding is displayed. In addition, Figure 97 shows an example of 3-3-4-5 data encoding, Figure 98 shows an example of 4-3-4-4 data encoding, and Figure 99 shows an example of 3-4 -4-4 One example of data coding is shown. In addition, Figure 100 shows one example of 3-4-4-4 data encoding, Figure 101 shows one example of 4-3-4-4 data encoding, and Figure 102 shows one example of 3-4-4 data encoding. -4-4 One example of data coding is shown. In addition, Fig. 103 shows an example of 3-4-4-4 data encoding, Fig. 104 shows an example of 3-4-4-4 data encoding, and Fig. 105 shows an example of 3-4-4-4 data encoding. -4-4 One example of data coding is shown. In addition, Fig. 106 shows an example of 4-4-3-4 data encoding, and Fig. 107 shows an example of 4-4-3-4 data encoding. In this way, by repeatedly inputting the data of a part of the pages at the 1st and 2nd stages, and inputting the data of the other pages only at one of the 1st and 2nd stages, it is programmed. The system can reduce the mutual interference between cells, and can also reduce the capacity of the write buffer, and can also suppress the bias of the bit error rate when writing each bit data. Especially, in the case of 1-4-5-5, 1-5-4-5, 3-3-4-5 or 3-5-2-5 data encoding, due to the boundary number system of each page data It is uniform, and the transition number of the threshold region at the 2nd stage of programming is 3 or less. Therefore, the deviation of the bit error rate can be suppressed, and the mutual interference between cells can be reduced. (Third Embodiment) The memory system 1 resulting from the third embodiment is a further reduction in the capacity of the write buffer compared to the first and second embodiments. The hardware configuration of the memory system 1 according to the third embodiment is common to the memory system 1 according to the first and second embodiments. In the third embodiment, the data of the page entered in the programming of the 1st stage, which is repeated in the programming of the 2nd stage, is kept in the non-volatile memory after the programming of the 1st stage is started. In the page buffer 24 inside the body 3. By this, in the 2nd stage of programming, the process of data input for this page can be omitted, and the data input for all pages can be set to only one time. With this, the capacity of the write buffer can be reduced. Furthermore, in this embodiment, the 2nd stage programming of the word line WLn-1 and the 1st stage programming of the word line WLn are integrated and performed. In this way, the page buffer 24 is the bit that will be input repeatedly during the programming of the 1st stage and the 2nd stage in the first to fourth bits (Lower page, Middle page, Upper page, Top page). The meta data is memorized before the beginning of the 1st stage of programming, and after the beginning of the 2nd stage of programming, it can be discarded or invalidated. Hereinafter, in this embodiment, the same applies, and an example of using the same 1-4-5-5 data encoding as that described in FIG. 6 of the first embodiment will be described. In the stylized flow chart shown in Fig. 9, the programming of the 1st stage and the programming of the 2nd stage shift the execution timing to each other. When each is programmed, it is necessary to perform the programming instructions of each. And the input of stylized data. In contrast, in this embodiment, the programming of the 1st stage and the programming of the 2nd stage are integrated as much as possible with the input of programmatic data. For example, as shown in FIG. 8B, except for the beginning and the end of the block, the programming of the 1st stage of the word line WLn and the 2nd stage of the word line WLn-1 is absolutely continuous. Therefore, in this embodiment, this part is set as an integrated command input. That is, with one command input, the programming data of the Lower page, Middle page, Top page and Upper page of the character line WLn-1 of the character line WLn are input in batches. This system is the same as when Foggy-Fine is used, the data of the Lower/Middle/Upper/Top page is batched by one programming command (However, in this case, it is the same character The page within the line WLi) has made the input of the same amount of data as the input of 4 pages. In this way, by integrating the input of programmatic commands and programmatic data, the command input and polling in the control performed by the memory controller 2 (regularity of whether the chip busy is returned to the ready) The frequency of inspection) is reduced, and the speed of the memory system 1 and the simplification of control become possible. Here, one example of the writing procedure following the programming sequence of the third embodiment will be described using FIG. 108 and FIG. 109. In FIG. 108 and FIG. 109, the writing procedure when following the programming sequence shown in FIG. 8B is shown. Fig. 108 is a flowchart showing the writing procedure for the entire amount of 1 block by the third embodiment. One block here is assumed to have n+1 word lines WLi of word lines WL0 to WLn (n is a natural number). As shown in FIG. 108, if writing is started (step S710), the 1st-stage programming process of the character line WL0 of the string St0 to St3 is performed (step S712). With this, the control unit 22 implements the 1st stage programming of the character line WL0 of the character string St0 to St3 (step S714). In addition, the control unit 22 implements the 1st stage programming of the string St0_character line WL1 and the 2nd stage programming of the string St0_character line WL0 (step S716). Next, the control unit 22 implements the 1st stage programming of the string St1_character line WL1 and the 2nd stage programming of the string St1_character line WL0 (step S718). Next, the control unit 22 implements the 1st stage programming of the string St2_character line WL1 and the 2nd stage programming of the string St2_character line WL0 (step S720). After that, the control unit 22 repeatedly performs the same processing for each character line WLi of each character string. Then, the 1st stage programming of the string St0_character line WLn and the 2nd stage programming of the string St0_character line WLn-1 are implemented (step S722). Next, the control unit 22 implements the 1st stage programming of the string St1_character line WLn and the 2nd stage programming of the string St1_character line WLn-1 (step S724). After that, the control unit 22 repeatedly performs the same processing for each character line WLi of each character string. Next, the control unit 22 implements the 1st stage programming of the string St3_character line WLn and the 2nd stage programming of the string St3_character line WLn-1 (step S726). Next, the control unit 22 implements the 2nd stage programming of the character line WLn of the character string St0 to St3 (steps S728, S730, and S732). In this way, at the beginning of the block, it is implemented in the same way as the first embodiment, with only the 1st stage of programming, and at the end of the block, it is implemented in the same way as in the first embodiment. Stylization of the 2nd stage. In this case, only the 1st stage of programming is implemented according to the procedure shown in FIG. 8B, and only the 2nd stage of programming is implemented according to the procedure shown in FIG. 8C. Moreover, in the flowchart of FIG. 108, except for the beginning and the end of the block, the programming of the 1st stage of the character line WLn and the programming of the 2nd stage of the character line WLn-1 are integrated and performed. . With this, the frequency of command input and polling performed by the memory controller 2 is reduced, and the processing of the memory system 1 can be speeded up. Fig. 109 is a flowchart showing the writing procedure in the 1st stage and the 2nd stage of the third embodiment. As shown in FIG. 109, in the programming of the 1st stage and the 2nd stage, after the programming of the 1st stage is carried out, the programming of the 2nd stage is carried out. Specifically, first, it is an input start command of the upper page data inputted with the character line WLn-1 to the non-volatile memory 3 from the memory controller 2 (step S750). After that, the data of the Upper page of the word line WLn-1 is input to the non-volatile memory 3 from the memory controller 2 (step S752). Next, it is an input start command of the data of the Lower page with the word line WLn inputted from the memory controller 2 to the non-volatile memory 3 (step S754). After that, the data of the Lower page with the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S756). Next, the input start command of the data of the Middle page with the word line WLn inputted from the memory controller 2 to the non-volatile memory 3 (step S758). After that, the data of the Middle page with the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S760). The data of the Middle page is not only input to the non-volatile memory 3, but also stored in the page buffer 24. After being stored in the page buffer 24, the middle data written in the buffer can be discarded or invalidated. Next, an input start command for the data of the Top page with the word line WLn inputted from the memory controller 2 to the non-volatile memory 3 (step S762). After that, the data of the top page of the word line WLn is input to the non-volatile memory 3 from the memory controller 2 (step S764). Next, the 1st stage and the 2nd stage programmed execution commands are input from the memory controller 2 to the non-volatile memory 3 (step S766), and thereby become chip_busy (step S768). After that, for the Lower page, Middle page, and Top page of the word line WLn, a stylized voltage pulse is applied 1 to multiple times (step S770). After that, in order to confirm whether the memory cell has moved beyond the threshold level, the data of the lower page and the top page with the word line WLn are read (step S772). Furthermore, it is confirmed whether the number of failed bits of the data in the lower page and the top page is smaller than the determination criterion (step S774). When the number of failed bits of the data in the lower page and the top page is greater than the judgment criterion, the processing of steps S770 to S774 is repeated. However, if the number of failed bits of the data becomes smaller than the judgment criterion, the lower page and top page data of the word line WLn-1 are read (step S776). After that, based on the Lower and Top page data of the word line WLn-1 and the Middle page data read from the page buffer 24, the threshold voltage Vth of the programming target of the Upper page is determined (step S778). After that, using the determined threshold voltage Vth, data writing to the upper page of the word line WLn-1 is performed (step S780). When writing data to the upper page, the upper page of the word line WLn-1 is applied with a programming voltage pulse of 1 to multiple times. After that, in order to confirm whether the memory cell has moved beyond the threshold level, the data of the Upper page with the word line WLn-1 is read (step S782). Furthermore, a verification is performed to determine whether the number of failed bits of the data in the upper page is smaller than the determination criterion (step S784). When the number of failed bits of the data in the Upper page is above the judgment criterion, the process of applying the programmed voltage pulse and reading and verifying the data is repeated. On the other hand, if the number of failed bits of the data becomes smaller than the judgment criterion, it becomes chip_ready (step S786). In addition, in the 1st stage programming for the same character line, the order of the data input start command on the plural pages and the pages in the data input process is arbitrary, no matter which page is input first. In addition, in the 2nd stage programming for the same character line, the order of the data input start command on the plural pages and the pages in the data input process is also arbitrary. However, the sequence of each character line number and the two-stage stylized processing absolutely needs to be the sequence shown in FIG. 109. In this way, in FIG. 109, an explanation is given for the case where the programming of the 1st stage of the word line WLn is performed before the programming of the 2nd stage of the word line WLn-1. This is to prevent the cell of the word line WLn-1 written by the threshold voltage Vth of 16 values from being contiguous by the programming of the 1st stage of the word line WLn. Because of the impact. As described above, in this embodiment, the data of the upper page of the character line WLn-1 and the data of the 4 pages of the lower page, the middle page and the top page of the character line WLn are continuously enter. In addition, as another modification, it is also possible to use the input of the programmed command as an IDL, and then perform the reading of the Lower page, Middle page, and Top page of the character line WLn-1. The programming of the Lower page, Middle page, and Top page of the character line WLn. Then, the threshold voltage Vth of the programming target of the Upper page of the character line WLn-1 is determined, and by the determined The threshold voltage Vth is used to program the Upper page of the word line WLn-1. With this configuration, it is possible to perform the Lower, Middle, and Top pages of the IDL character line WLn-1 before being affected by the interference between adjacent cells caused by the writing of the character line WLn The reading of the data. In addition, in the present embodiment, the actual execution sequence of the programming caused by the unifying command of the 1st stage of the word line WLn and the 2nd stage of the word line WLn-1 can be modified. That is, the programming of the Lower page, Middle page, and Top page of the character line WLn shown in Figure 109, and the reading of the data of the Lower page, Middle page, and Top page as the IDL character line WLn-1 Out, no matter which one comes first, it can be exchanged. By reading the data of the Lower page, Middle page and Top page of the character line WLn-1 before programming the Lower page, Middle page and Top page of the character line WLn, it becomes possible to IDL is performed under the influence caused by the programming of the Lower page, Middle page, and Top page of the character line WLn. In this way, in the third embodiment, since the 2nd stage programming of the word line WLn-1 and the 1st stage programming of the character line WLn are integrated, command input and polling are performed. The frequency is reduced. Therefore, it becomes possible to achieve speed-up of the memory system 1 and simplification of control. FIG. 110 is a diagram for explaining the write buffer amount (buffer data amount) in the programming of the third embodiment. In this embodiment, a two-stage stylization is used with 1-4-5-5 data encoding. In the programming of this embodiment, in the 1st stage, data input for the amount of three pages (Lower page, Middle page and Top page) and the programming of the amount of these three pages (1st stylization) are performed. ). In the case of the programming of the present embodiment, in the 2nd stage, data input for one page (Upper page) and programming for one page of the Upper page (2nd stylization) are performed. ). However, at each character line WL0, WL1, WL2,..., it is sufficient to pre-store the data in the write buffer during the data input of each stage. If the programming is started, the data can also be changed from Write to the buffer and delete. For example, if data is input at the 1st stage, the data is stored in the write buffer. However, if the programming is started at the 1st stage, the data of the Lower page, Top page and Middle page stored in the write buffer in advance can also be deleted. However, the data of the middle page is also used at the 2nd stage. Therefore, it is necessary to store it in the page buffer 24 in advance until the programming at the 2nd stage is started. Similarly, if data is input at the 2nd stage, the data is stored in the write buffer. However, if programming is started at the 2nd stage, all the data previously stored in the write buffer can also be deleted. Therefore, in the case of programming in this embodiment, it is necessary to hold the data in the write buffer in advance. Even the largest data is only 3 pages of data, which can be more than that of the first embodiment. To reduce. In the programming of this embodiment, in the same way, in order to reduce the interference between adjacent memory cells, the data of the 4 pages of Lower/Middle/Upper/Top are not written continuously. For example, after the 1st stage for the word line WL0 is executed, before the 2nd stage for the word line WL0 is executed, the 1st stage for the word line WL1 adjacent to the word line WL0 is executed. . Similarly, after the 1st stage for the word line WL1 is executed, before the 2nd stage for the word line WL1 is executed, the 1st stage for the word line WL2 adjacent to the word line WL1 is Implement. In this way, in this embodiment, all page data is only necessary for programming in one stage. Therefore, if the data input is completed, the data can be written into the buffer. delete. Therefore, in this embodiment, it is necessary to keep the number of pages in the write buffer at the same time in advance, and it only needs to be smaller than that in the first embodiment. The page data programmed for the non-volatile memory 3 is temporarily held in the write buffer in the RAM 6 and then the data is input into the non-volatile memory 3 during programming. In this embodiment, since the necessary capacity of the RAM 6 can be reduced, the cost can be reduced. In addition, in the present embodiment, since the data transmission of each page is completed once, compared with the first embodiment, the transmission time of the page data is less than that of the first embodiment. It becomes possible to reduce the power consumption during transmission. The page reading processing in this embodiment is the same as the processing procedure described in the first embodiment, so its description is omitted. In addition, in this embodiment, for new page data that needs to be maintained, it is necessary to increase the page buffer 24 inside the NAND flash memory. In the programming of NAND flash memory with 1 string in the block as shown in Figure 8A, the amount of page buffer 24 that needs to be increased is the amount of data for 1 page. . In contrast, in the programming of NAND flash memory with 4 strings in the block as shown in FIG. 8B or FIG. 8C, the amount of page buffer 24 that needs to be increased is The amount of data on 4 pages. This is because, during the period from the implementation of the 1st stage programming of a certain string to the implementation of the 2nd stage programming of the same string, it is necessary to execute the 1st stage programming of the other 3 strings. As a result, it is necessary to maintain the data of one page for all of the four strings. In this embodiment, although 1-4-5-5 data encoding is used as an example, various data encoding modifications can be used, and it is obvious that the above-mentioned embodiment can be realized. In the above-mentioned first to third embodiments, although the NAND memory 5 is used to form the non-volatile memory 3, the description has been made, but it can also be used such as ReRAM (Resistive Random Access Memory). Or MRAM6 (Magneto-Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FeRAM (Ferroeletric Random Access Memory) and other types of non-volatile memory3. In the above-mentioned first to third embodiments, although the data is written for 3 pages in the 1st stage of programming, the 2nd stage of programming is written for 2 pages. The situation of data writing is explained, but it is also possible to change the allocation of the number of pages in the programming of the 1st stage and the number of pages in the programming of the 2nd stage. For example, it can also be configured to write data for 2 pages in the programming of the 1st stage, and write data for 3 pages in the programming of the 2nd stage. Although several embodiments of the present disclosure have been described, these embodiments are merely presented as examples, and are not intended to limit the scope of the present invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments or their modifications are also included in the scope or gist of the invention, and are also included in the invention described in the scope of the patent application and its equivalent scope.

1: Memory system 2: Memory controller 3: Non-volatile memory 4: Host processor 5: NAND memory 6: RAM 7: ROM 8: processor 9: Host interface 10: ECC circuit 11: Memory interface 12: Internal bus 21: NAND I/O interface 22: Control Department 23: NAND memory cell array 24: page buffering 31: Oscillator 32: Sequencer 33: Command user interface 34: Voltage Supply Department 35: column counter 36: Serial access controller 37: Line decoder 38: Sense amplifier 41: P-well area 42, 43, 44: Wiring layer 45: memory hole 46: Block insulation film 47: charge accumulation layer 48: Gate insulating film 49: conductive film

[Fig. 1] is a block diagram showing the schematic configuration of the memory system according to the first embodiment. [Fig. 2] is a block diagram showing an example of the internal structure of the non-volatile memory of this embodiment. [Fig. 3] is a circuit diagram showing an example of a NAND memory cell array with a three-dimensional structure. [Figure 4] is a cross-sectional view of a partial area of a NAND memory cell array of a 3-dimensional NAND memory. [Fig. 5] is a diagram showing an example of the threshold value area of the first embodiment. [Fig. 6A] is a diagram showing an example of data coding in the first embodiment. [Fig. 6B] is a diagram showing another example of data encoding in the first embodiment. [Figure 7] is a diagram showing the programmed threshold area in the first embodiment. [Fig. 8A] is a diagram showing the first example of the stylized sequence of the first embodiment. [Fig. 8B] is a diagram showing the second example of the stylized sequence of the first embodiment. [Fig. 8C] is a diagram showing the third example of the stylized sequence of the first embodiment. [Fig. 9] is a flowchart showing the first example of the writing procedure for the entire amount of 1 block caused by the first embodiment. [Fig. 10] is a flowchart showing the writing procedure in the 1st stage caused by the first embodiment. [Figure 11] is a flow chart showing the first example of the 2nd stage write process. [Fig. 12] is a diagram for explaining the majority decision processing of the reading result of the plural number of times. [Fig. 13] is a flowchart showing a modification example of the writing procedure in the 2nd stage of the first embodiment. [Figure 14A] is a diagram for explaining the amount of data written in the buffer in the Foggy-Fine programming using 4-3-4-4 data encoding. [Fig. 14B] is a diagram for explaining the amount of data in the write buffer in this embodiment. [Fig. 15] is a flowchart showing the processing procedure of page reading at the character line where the programming is completed until the 1st stage. [FIG. 16A] is a flowchart showing the processing procedure of page reading at the character line where the programming is completed until the 2nd stage. [FIG. 16B] is a diagram showing data encoding suitable for page read processing caused by one of the modified examples. [FIG. 16C] is a flowchart showing the read processing procedure caused by one of the modified examples. [Figure 16D] is the voltage waveform diagram of the selected word line, ReadyBusy signal line, and output data line. [Figure 17] is a diagram showing an example of coding 1-5-4-5 data. [Figure 18] is a diagram showing one example of coding 1-5-4-5 data. [Figure 19] is a diagram showing an example of 3-5-2-5 data coding. [Figure 20] is a diagram showing an example of 3-3-4-5 data coding. [Figure 21] is a diagram showing an example of 2-3-5-5 data coding. [Figure 22] is a diagram showing an example of 3-2-5-5 data coding. [Figure 23] is a diagram showing an example of 3-4-4-4 data coding. [Figure 24] is a diagram showing an example of 3-4-4-4 data coding. [Figure 25] is a diagram showing an example of coding 1-4-5-5. [Figure 26] is a diagram showing an example of 2-5-3-5 data coding. [Figure 27] is a diagram showing an example of 3-4-5-3 data coding. [Figure 28] is a diagram showing an example of 3-2-5-5 data coding. [Figure 29] is a diagram showing an example of 3-2-5-5 data coding. [Figure 30] is a diagram showing an example of coding 1-5-5-4. [Figure 31] is a diagram showing an example of the coding of 1-5-4-5 data. [Figure 32] is a diagram showing an example of coding 1-4-5-5. [Figure 33] is a diagram showing an example of 1-5-3-6 data coding. [Figure 34] is a diagram showing one of the examples of 1-3-6-5 data coding. [Figure 35] is a diagram showing an example of 1-2-6-6 data coding. [Figure 36] is a diagram showing an example of 1-2-6-6 data coding. [Figure 37] is a diagram showing an example of 1-2-6-6 data coding. [Figure 38] is a diagram showing an example of 1-4-6-4 data coding. [Figure 39] is a diagram showing an example of 1-4-4-6 data coding. [Figure 40] is a diagram showing an example of 1-4-6-4 data coding. [Figure 41] is a diagram showing an example of 1-4-4-6 data coding. [Figure 42] is a diagram showing an example of 2-5-2-6 data coding. [Figure 43] is a diagram showing an example of 2-5-2-6 data coding. [Figure 44] is a diagram showing an example of 2-5-2-6 data coding. [Figure 45] is a diagram showing an example of 3-3-3-6 data coding. [Figure 46] is a diagram showing an example of 3-3-6-3 data coding. [Figure 47] is a diagram showing an example of 2-3-4-6 data encoding. [Figure 48] is a diagram showing an example of 3-4-2-6 data coding. [Figure 49] is a diagram showing an example of 2-3-4-6 data encoding. [Figure 50] is a diagram showing an example of 3-2-6-4 data coding. [Figure 51] is a diagram showing an example of 3-2-4-6 data coding. [Figure 52] is a diagram showing an example of 3-2-6-4 data coding. [Figure 53] is a diagram showing an example of 3-4-2-6 data coding. [Figure 54] is a diagram showing an example of 3-2-4-6 data coding. [Figure 55] is a diagram showing an example of 5-3-2-5 data coding. [Figure 56] is a diagram showing an example of 3-5-2-5 data coding. [Figure 57] is a diagram showing an example of 3-2-5-5 data coding. [Figure 58] is a diagram showing an example of 2-3-5-5 data coding. [Figure 59] is a diagram showing an example of 2-3-5-5 data coding. [Figure 60] is a diagram showing an example of 2-3-5-5 data coding. [Figure 61] is a diagram showing an example of 5-4-2-4 data coding. [Figure 62] is a diagram showing an example of 4-5-2-4 data coding. [Figure 63] is a diagram showing an example of 5-4-2-4 data coding. [Figure 64] is a diagram showing an example of 2-4-5-4 data encoding. [Figure 65] is a diagram showing an example of 2-4-5-4 data coding. [Figure 66] is a diagram showing an example of 2-5-4-4 data encoding. [Figure 67] is a diagram showing an example of 2-5-4-4 data coding. [Figure 68] is a diagram showing an example of 2-5-4-4 data coding. [Figure 69] is a diagram showing an example of coding 1-5-4-5 data. [Figure 70] is a diagram showing an example of the 1-4-5-5 data coding. [Figure 71] is a diagram showing an example of the 1-5-5-4 data coding. [Figure 72] is a diagram showing an example of coding 1-4-5-5. [Figure 73] is a diagram showing an example of the coding of 1-5-5-4 data. [Figure 74] is a diagram showing one example of coding 1-5-4-5 data. [Figure 75] is a diagram showing an example of the 1-5-5-4 data coding. [Figure 76] is a diagram showing one example of coding 1-5-4-5 data. [Figure 77] is a diagram showing an example of coding 1-4-5-5. [Figure 78] is a diagram showing an example of the 1-4-5-5 data encoding. [Figure 79] is a diagram showing an example of the 1-4-5-5 data encoding. [Figure 80] is a diagram showing an example of coding 1-4-5-5. [Figure 81] is a diagram showing an example of 3-5-4-3 data coding. [Figure 82] is a diagram showing an example of 3-4-5-3 data coding. [Figure 83] is a diagram showing an example of 3-5-3-4 data coding. [Figure 84] is a diagram showing an example of 3-4-3-5 data coding. [Figure 85] is a diagram showing an example of 3-4-5-3 data coding. [Figure 86] is a diagram showing an example of 3-4-3-5 data coding. [Figure 87] is a diagram showing an example of 3-3-5-4 data coding. [Figure 88] is a diagram showing an example of 3-3-5-4 data coding. [Figure 89] is a diagram showing an example of 4-5-3-3 data coding. [Figure 90] is a diagram showing an example of 3-5-4-3 data coding. [Figure 91] is a diagram showing an example of 3-4-5-3 data coding. [Figure 92] is a diagram showing an example of 3-3-4-5 data coding. [Figure 93] is a diagram showing an example of 3-3-4-5 data coding. [Figure 94] is a diagram showing an example of 3-3-4-5 data coding. [Figure 95] is a diagram showing an example of 3-4-5-3 data coding. [Figure 96] is a diagram showing an example of 3-3-5-4 data coding. [Figure 97] is a diagram showing an example of 3-3-4-5 data coding. [Figure 98] is a diagram showing an example of 4-3-4-4 data coding. [Figure 99] is a diagram showing an example of 3-4-4-4 data coding. [Figure 100] is a diagram showing an example of 3-4-4-4 data coding. [Figure 101] is a diagram showing an example of 4-3-4-4 data coding. [Figure 102] is a diagram showing an example of 3-4-4-4 data encoding. [Figure 103] is a diagram showing an example of 3-4-4-4 data encoding. [Figure 104] is a diagram showing an example of 3-4-4-4 data encoding. [Figure 105] is a diagram showing an example of 3-4-4-4 data encoding. [Figure 106] is a diagram showing an example of 4-4-3-4 data coding. [Figure 107] is a diagram showing an example of 4-4-3-4 data coding. [Fig. 108] is a flowchart showing the writing procedure for the entire amount of 1 block in the third embodiment. [Fig. 109] is a flowchart showing the writing procedure in the 1st stage and the 2nd stage of the third embodiment. [Fig. 110] is a diagram for explaining the amount of write buffer in the programming of the third embodiment.

2: Memory controller

3: Non-volatile memory

4: Host processor

5: NAND memory

6: RAM

7: ROM

8: processor

9: Host interface

10: ECC circuit

11: Memory interface

12: Internal bus

Claims (13)

A memory system that has: Non-volatile memory is a memory cell with a plurality of memory cells, each of which has 16 threshold areas, and can memorize 4 expressed by the first to fourth bits. For bit data, the 16 threshold areas include the first threshold area that represents the deleted state where the data is deleted, and the voltage level is higher than the first threshold area mentioned above It also represents the 2nd to 16th threshold area of the writing state where the data has been written; and The memory controller causes the non-volatile memory to perform the first programming of writing the data of the first bit, the second bit, and the fourth bit to make the non-volatile memory The sexual memory performs the second programming of writing the data of the third bit mentioned above, Among the 15 boundaries between adjacent threshold regions existing in the first to 16th threshold regions, the first boundary used in the determination of the value of the first bit data The number of the second boundary used in the determination of the value of the second bit data, the number of the third boundary used in the determination of the value of the third bit data, is used in For the number of the fourth boundary in the determination of the value of the fourth bit of the data, the largest value among these numbers is 5, and the second largest value is 4. The aforementioned memory controller is configured so that the threshold area in the aforementioned memory cell becomes representative data in response to the data of the aforementioned first bit, the aforementioned second bit, and the aforementioned fourth bit. The 17th threshold area and voltage level of the deleted state with deletion are higher than the above-mentioned 17th threshold area and represent the 18th to 24th thresholds of the write state with data being written The threshold area of one of the areas is used to make the aforementioned non-volatile memory perform the aforementioned first programming, The aforementioned memory controller is configured so that the threshold area in the aforementioned memory cell changes from any one of the aforementioned 17th to 24th threshold areas in accordance with the data of the aforementioned 3rd bit. The threshold area becomes the threshold area of any one of the threshold areas of the first to 16th threshold areas, so that the non-volatile memory performs the second Stylized, The number of threshold areas between the threshold area where the voltage level is the lowest and the threshold area where the voltage level is the highest in the aforementioned two threshold areas is within two. The aforementioned memory controller, when the aforementioned non-volatile memory is subjected to the aforementioned second programming, is configured to combine the aforementioned second bit data and the aforementioned third bit data with respect to the aforementioned non-volatile memory For input. Such as the memory system described in claim 1, in which: The aforementioned memory controller is such that the value of the aforementioned first bit is the same in the 15 boundaries between adjacent threshold areas existing in the aforementioned first to 16th threshold areas. The number of the aforementioned boundaries that are different, the number of the aforementioned boundaries that have a different value in the second bit, the number of the aforementioned boundaries that have a different value in the third bit, and the number of the aforementioned boundaries that have a different value in the fourth bit are different The number of the aforementioned borders in sequence becomes (1, 4, 5, 5), (1, 5, 4, 5) or (3, 3, 4, 5) in order to make the aforementioned non-volatile memory Perform the aforementioned first stylization and the aforementioned second stylization. A memory system that has: Non-volatile memory is a memory cell with a plurality of memory cells, each of which has 16 threshold areas, and can memorize 4 expressed by the first to fourth bits. For bit data, the 16 threshold areas include the first threshold area that represents the deleted state where the data is deleted, and the voltage level is higher than the first threshold area mentioned above It also represents the 2nd to 16th threshold area of the writing state where the data has been written; and The memory controller causes the non-volatile memory to perform the first programming of writing the data of the first bit, the second bit, and the fourth bit to make the non-volatile memory The sexual memory performs the second programming of writing the data of the third bit mentioned above, Among the 15 boundaries between adjacent threshold regions existing in the first to 16th threshold regions, the first boundary used in the determination of the value of the first bit data The number of the second boundary used in the determination of the value of the second bit data, the number of the third boundary used in the determination of the value of the third bit data, is used in The number of the fourth boundary in the determination of the value of the data of the fourth bit mentioned above is (3, 5, 2, 5) in order, The aforementioned memory controller is configured so that the threshold area in the aforementioned memory cell becomes representative data in response to the data of the aforementioned first bit, the aforementioned second bit, and the aforementioned fourth bit. The 17th threshold area and voltage level of the deleted state with deletion are higher than the above-mentioned 17th threshold area and represent the 18th to 24th thresholds of the write state with data being written The threshold area of one of the areas is used to make the aforementioned non-volatile memory perform the aforementioned first programming, The aforementioned memory controller is configured so that the threshold area in the aforementioned memory cell changes from any one of the aforementioned 17th to 24th threshold areas in accordance with the data of the aforementioned 3rd bit. The threshold area becomes the threshold area of any one of the threshold areas of the first to 16th threshold areas, so that the non-volatile memory performs the second Stylized, The number of threshold areas between the threshold area where the voltage level is the lowest and the threshold area where the voltage level is the highest in the aforementioned two threshold areas is within two. The aforementioned memory controller, when the aforementioned non-volatile memory is subjected to the aforementioned second programming, is configured to combine the aforementioned second bit data and the aforementioned third bit data with respect to the aforementioned non-volatile memory For input. Such as the memory system described in any one of claims 1 to 3, wherein: The aforementioned memory controller is based on the voltage level difference between the two different threshold areas that will cause the value of the second bit in the 17th to 24th threshold areas to be different It becomes smaller than the voltage level difference between the two threshold regions that are different from the value of the data of the aforementioned first bit, and becomes 2 that is different from the value of the data of the aforementioned fourth bit. The voltage level difference between the two threshold regions is smaller, so that the non-volatile memory is subjected to the first programming. Such as the memory system described in claim 4, in which: The aforementioned memory controller is based on the interval between the two threshold regions at the time of the aforementioned first programming that are different from the value of the aforementioned second bit data, so that for the aforementioned two The threshold value area of the above-mentioned third bit data is used to carry out the above-mentioned second programming to obtain a way that the interval between adjacent threshold value areas of the four threshold value areas becomes wider , To make the aforementioned non-volatile memory carry out the aforementioned second programming. Such as the memory system described in any one of claims 1 to 3, wherein: The aforementioned first bit is the lowest bit, the aforementioned second bit is the second smallest Middle bit, and the aforementioned third bit is the second largest Upper bit. The fourth bit mentioned above is the top bit. Such as the memory system described in any one of claims 1 to 3, wherein: It is the first memory section with volatility that memorizes the data of the first to fourth bits mentioned above, Among the first to fourth bits stored in the first memory section, the data of the bits that will be repeatedly input in the first programming and the second programming are the data of the bits that are repeatedly input when the first to the fourth bit is started. 2 After programming, it becomes discardable or invalidated, and the data of other bits becomes discardable or invalidated after the first programming is started. Such as the memory system described in any one of claims 1 to 3, wherein: It is equipped with a volatile first memory section that stores the data of the first to fourth bits mentioned above; and The non-volatile second memory part that stores the data of the bits that will be repeatedly input in the first programming and the second programming in the first to fourth bits mentioned above, The data of the first to fourth bits stored in the first memory section can be discarded or invalidated after the first programming is started, Among the first to fourth bits stored in the second memory section, the data of the bits that will be repeatedly input during the first programming and the second programming are the data at the beginning of the first The programming is stored in the second storage section before the programming, and becomes discardable or invalidated after the programming of the second programming is started. Such as the memory system described in claim 8, in which: The aforementioned second memory portion is provided in units of character lines. Such as the memory system described in any one of claims 1 to 3, wherein: The plurality of memory cells in the non-volatile memory are provided with a plurality of first memory cells connected to the first character line, and a first memory cell adjacent to the first character line The second memory cell of the plural number connected by a 2-character line, The memory controller performs the first programming for the plurality of first memory cells, and then performs the first programming for the plurality of second memory cells, and then, The aforementioned plural number of first memory cells are subjected to the aforementioned second programming. Such as the memory system described in any one of claims 1 to 3, wherein: The aforementioned non-volatile memory is provided with at least a first character line and a second character line connecting the two or more memory cells, respectively, The aforementioned memory controller is to convert the aforementioned first programming for the memory cell connected with the aforementioned first character line and the aforementioned second programming for the aforementioned memory cell connected with the aforementioned second character line The continuous implementation of transformation is to issue instructions to the aforementioned non-volatile memory through successive commands and data input. Such as the memory system described in any one of claims 1 to 3, wherein: The aforementioned non-volatile memory has: The control unit is based on the data obtained by reading out the data programmed by the first programming, and the second data repeatedly input during the first programming and the second programming. The bit data and the input data of the third bit programmed by the second programming described above determine the prominence of the bit data programmed by the second programming described above. Limit voltage. For example, the memory system described in claim 12, which includes: The error correction department reads out the data that has been programmed through the above-mentioned first stylization and corrects errors. The aforementioned control unit is based on the data after the error correction by the aforementioned error correction unit, the aforementioned data of the second bit, and the aforementioned input data of the third bit, to determine the result by the aforementioned second stylization The aforementioned threshold voltage of the programmed bit data.

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