JP2009295232A - Semiconductor memory device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can suppress degradation of reliability of read out data, speed up writing, and store multilevel data. <P>SOLUTION: The semiconductor memory device comprises a plurality of word lines WL extended in a first direction, a plurality of bit lines BL extended in a second direction crossing the first direction, a plurality of memory cells MC set at lattice shaped intersections formed by the word lines and bit lines for storing N bits data (N≥2), and sense amps 40 set for the plurality of bit lines to detect the data stored in the memory cells or write the data into the memory cells. It also writes data at a plurality of levels out of the N bit data into the memory cells as data with a first threshold voltage data and reads data by using error correcting codes when reading the data written as data with the first threshold voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a driving method thereof.

  In the EEPROM type NAND flash memory which is a nonvolatile semiconductor memory device, a memory capable of storing multi-value data has been proposed.

  Nonvolatile semiconductor memory devices such as EEPROM type NAND flash memories are remarkably miniaturized. For this reason, the mutual interval between adjacent memory cells is very narrow. When the interval between adjacent memory cells is narrowed, the capacitance between floating gates between adjacent cells (FG-FG capacitance) increases. Therefore, there arises a problem that the threshold voltage Vth of the memory cell written earlier varies according to the data of the adjacent cell written later due to the capacitance between FG and FG. This is called the proximity effect. In particular, a multilevel memory that stores N-bit data (N ≧ 2) in one memory cell needs to have a very narrow threshold voltage distribution per data. Therefore, the problem of the proximity effect becomes significant in the multilevel memory.

Further, as the miniaturization progresses, not only the proximity effect increases but also the data retention characteristics deteriorate. This is because as the miniaturization progresses, the floating gate becomes smaller and the number of accumulated electrons decreases. The increase in the proximity effect and the deterioration of the data retention characteristic widen the threshold distribution of the memory cells. In particular, in a multi-level memory, widening of the threshold distribution leads to a decrease in read margin, thereby reducing data reliability. In order to cope with this, if an attempt is made to narrow the threshold distribution at the time of writing, the writing speed is lowered. That is, the reliability of read data and the write speed are in a trade-off relationship.
JP 2004-192789 A

  Provided is a semiconductor memory device capable of suppressing a decrease in reliability of read data, having a high writing speed, and storing multi-value data.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and the word A plurality of memory cells that are provided corresponding to intersections of a lattice shape constituted by a line and the bit line, and store N bit data (N ≧ 2), and are provided corresponding to the plurality of bit lines, A sense amplifier that detects data stored in the memory cell or writes data to the memory cell;
When data of a plurality of levels among the N-bit data is written to the memory cell as data of a first threshold voltage, and the data written as the first threshold voltage is read, the data is stored using an error correction code. It is characterized by reading.

A write controller according to an embodiment of the present invention includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction crossing the first direction, and the word lines And a plurality of memory cells that store N-bit data (N ≧ 2), and are provided corresponding to the plurality of bit lines. A write controller that detects data stored in the memory cell or writes data to a memory unit including a sense amplifier that writes data to the memory cell;
The memory unit is controlled to write a plurality of levels of N-bit data to the memory cell as first threshold voltage data.

A read controller according to an embodiment of the present invention includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and the word lines And a plurality of memory cells that store N-bit data (N ≧ 2), and are provided corresponding to the plurality of bit lines. A read controller that detects data stored in the memory cell or reads data from a memory unit including a sense amplifier that writes data to the memory cell;
Controlling the memory unit to read out the data using an error correction code when reading out the data from the memory cell storing a plurality of levels of the N-bit data as data of a first threshold voltage To do.

A method for driving a semiconductor memory device according to an embodiment of the present invention includes a plurality of word lines extending in a first direction, and a plurality of bit lines extending in a second direction intersecting the first direction. A plurality of memory cells that are provided in the vicinity of the intersection of the lattice shape constituted by the word lines and the bit lines and store N-bit data (N ≧ 2), and correspond to the plurality of bit lines. A method for driving a semiconductor memory device, comprising: a sense amplifier that detects data stored in the memory cell or writes data to the memory cell;
A plurality of levels of data among the N-bit data are written to the memory cell as first threshold voltage data,
When the data written as the first threshold voltage is read, the data is read using an error correction code.

  The semiconductor memory device according to the present invention can store multi-value data, suppress a decrease in reliability of read data, and increase a writing speed.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram showing an example of the configuration of a NAND flash memory 10 (hereinafter simply referred to as a memory 10) according to the first embodiment of the present invention. The memory 10 includes a memory cell array 100, a row decoder 20, a column decoder 30, a sense amplifier group 40 (including a bit line driving circuit), an input / output buffer 50, an address buffer 60, a voltage generation circuit 70, and a power-on reset circuit. 80, a control circuit 90, a latch circuit 200, an external I / O pad 210, and a NAND controller 220. Furthermore, although a state machine, a command interface, and the like are provided, they are omitted in FIG.

  The NAND controller 220 outputs data and a control signal (command). The NAND controller 220 may be incorporated in the card together with the memory 10. Data and control signals are input to the input / output buffer 50 via an external I / O pad. The input / output buffer 50 sends data and control signals to the command interface and column decoder 30. The state machine controls the column decoder 30 and the row decoder 20 based on the data and the control signal. The row decoder 20 decodes the control signal and selects a certain word line based on the address signal. The column decoder 30 is provided between the sense amplifier group 40 and the data bus. The column decoder 30 selects a sense amplifier in the sense amplifier group 40, transfers read data latched by the selected sense amplifier to the data bus, or transfers data received from the outside to the selected sense amplifier. The sense amplifier group 40 includes a plurality of sense amplifiers provided corresponding to the bit lines. The configuration of each sense amplifier may be a known one.

  At the time of data writing, the sense amplifier once latches the data and writes this data to the memory cell connected to the selected word line via the bit line of the column. At the time of data reading, the sense amplifier detects data in the memory cell connected to the selected word line. The sense amplifier outputs the read data to the outside of the memory 10 via the input / output buffer 50 and the external I / O pad 210. For example, the sense amplifier writes or reads data in units of pages composed of 8-bit data or 16-bit data.

  The address buffer 60 encodes address information received from the outside and sends it to the row decoder 20 and the column decoder 30.

  The voltage generation circuit 70 receives the mode signal, the voltage generation timing control signal, and the voltage level setting signal from the control circuit 90, and uses the power supply voltage VCC supplied from the outside as a reference voltage Vref for reference or a program voltage. An internal voltage such as Vpgm is generated. The voltage generation circuit 70 supplies the internal voltage to the row decoder 20, the column decoder 30, the sense amplifier group 40, and the like.

  The power-on reset circuit 80 detects that power is turned on, resets the register of the control circuit 90, and outputs a signal for performing an initialization operation. The power-on reset circuit 80 outputs a power-on reset signal that is low after the power is turned on until the power supply voltage reaches a predetermined voltage level, and goes high when the power supply voltage reaches the predetermined voltage level. Output.

  The control circuit 90 generates a mode signal indicating a data read operation, a data write operation, a data erase operation, or the like according to a command received from the outside. The control circuit 90 also outputs a timing control signal indicating timing for generating a voltage required in each mode, a voltage setting signal indicating a setting voltage stored in a register, an address control signal, and an access control signal for a memory cell. To do. In response to the power-on reset signal, the initialization control circuit 91 outputs a control signal for initializing the address buffer 60, the row decoder 20, the column decoder 30, the sense amplifier group 40, the latch circuit 200, and the voltage generation circuit 70. The ROM read control circuit 92 receives a power-on reset signal and outputs a control signal for starting a ROM read operation.

  ROM 120 is trimming data for timer adjustment, various voltage adjustments, various data (fuse data) that needs to be read after power-on, and replacement address data for replacing defective cells existing in memory cell array 100 with other redundant cells. (Redundancy data) and the like are stored. Data stored in the ROM 120 is sent to the latch circuit 200 via the sense amplifier group 40 and the column decoder 30 and held therein. This is called a ROM read operation.

  The sense amplifier group 40 includes a plurality of sense amplifiers provided corresponding to the bit lines BL. Each sense amplifier reads data stored in the memory cell MC via the bit line BL or writes data to the memory cell MC. Each sense amplifier has a latch function and is configured to temporarily hold read data or data to be written.

  On the other hand, ECC (Error Correction Code) information is held in a part of the memory cell array 100. Alternatively, ECC information may be held exclusively in the same location as the memory cell array 100. In either case, the ECC information is read and written using the sense amplifier group 40.

  In the present embodiment, the ECC is used when there is an error bit in the read data, and also when reading data of a plurality of levels overlapping with a single threshold voltage.

  FIG. 2 is a diagram illustrating an example of the configuration of the memory cell array 100. The memory cell array 100 is divided into memory cell blocks (hereinafter also referred to as blocks) BLOCK0 to BLOCKm. In this example, the blocks BLOCK0 to BLOCKm are the minimum units for data erasure. In addition, a block can be configured with an arbitrary number of memory cells. Each block BLOCK0 to BLOCKm is composed of a plurality of pages. A page is a unit of data read / data write. Each page corresponds to a word line and is constituted by data of a plurality of memory cells specified by a certain row address.

  FIG. 3 is a diagram illustrating an example of the configuration of each of the blocks BLOCK0 to BLOCKm. A certain block BLOCKi (i = 0 to m) includes a plurality of NAND strings NS provided corresponding to the bit lines BL of each column. The NAND string NS is formed of a plurality of memory cells MC connected in series and select gate transistors ST connected to both ends of these memory cells MC. One end of the NAND string NS is connected to the corresponding bit line BL, and the other end is connected to the common source line SL. For example, the NAND strings NSi (i = 0 to 5) are connected to the bit lines BLi (i = 0 to 5), respectively.

  The control gate of the memory cell MC is connected to the word line WL of the page to which the memory cell MC belongs. For example, the control gate of the memory cell MC belonging to the page i (i = 0 to 4) is connected to the word line WLi (i = 0 to 4). The gate of the selection transistor ST is connected to the selection gate line SGL1 or SGL2.

  The plurality of word lines WL extend in the row direction as the first direction, and the plurality of bit lines BL extend in the column direction as the second direction intersecting so as to be substantially orthogonal to the row direction. Yes. Since the row direction and the column direction are referred to for convenience, the first direction may be the column direction and the second direction may be the row direction.

  As shown in FIG. 3, the memory cell MC is provided corresponding to a lattice-shaped intersection formed by the word line WL and the bit line BL. For example, the lattice-shaped intersections constituted by the word lines WL0 to WL4 and the bit lines BL0 to BL5 are located in a 5 × 6 matrix. The memory cells MC are two-dimensionally arranged in a 5 × 6 matrix so as to correspond to these intersections. The block of the present embodiment is composed of 5 × 6 (30) memory cells MC, but the number of memory cells MC in one block is not limited to this. That is, the number of word lines and the number of bit lines are not limited to 5 and 6, respectively.

  The memory cell MC is composed of an n-type FEF (Field-Effect Transistor) having a floating gate and a control gate. A potential is applied to the control gate by the word line, and charges (electrons) are accumulated in the floating gate, or charges (electrons) are discharged from the floating gate. As a result, data is written to the memory cell MC or data in the memory cell MC is erased. Depending on the number of charges (electrons) accumulated in the floating gate, the memory cell MC can electrically store multi-value data.

    Further, the memory cell MC may be a charge storage type nonvolatile memory. Further, the memory cell MC may be a memory element of a type that uses resistance change as information.

  FIG. 4 is a graph showing the threshold voltage of the memory cell MC storing quaternary data as an example of this embodiment. The memory cell MC stores any one of quaternary data (11, 10, 01, 00). Of the quaternary data, the lower bit is stored in each memory cell MC as Lower Page data, and the upper bit is stored as Upper Page data. In FIG. 4, the lower page data is indicated by a circle, and the upper page data is indicated by a square. The vertical axis represents the number of memory cells MC. Therefore, the width W of the graph in each state shown in FIG. 4 indicates variations in threshold voltage. Therefore, it is preferable that the width W of the graph in each state is small.

  The E state (11) is an erase state (erased state) in which data “0” is not written as lower page data and upper page data. Prior to data writing, all memory cells MC are in the E state. In the E state, the threshold voltage of the memory cell MC is negative. The other A state to C state are threshold voltages in the write state of the memory cell MC, and are assigned to positive voltages between 0 and 5V.

  The writing of the quaternary data is executed by two operations of the lower page writing and the upper page writing. Lower Page writing determines Lower Page data. As a result, the data state of the memory cell MC is distributed to either the E state and the B state, or the A state and the C state. Upper Page writing determines Upper Page data. As a result, the data state of the memory cell MC is assigned to one of the E state, the B state, the A state, and the C state.

  In lower page writing, when the lower page data is kept at 1, the bit line is set to high level so that electrons are not accumulated in the floating gate of the memory cell MC connected to the selected word line. Thereby, the memory cell MC maintains the E state (erased state). On the other hand, when 0 is written in the lower page data, electrons are accumulated in the floating gate of the memory cell MC connected to the selected word line by setting the bit line to the low level. As a result, 0 is written in the lower page data, and the A state is entered.

  In upper page writing, when the upper page data remains at 1, the bit line is set to high level so that electrons are not accumulated in the floating gate of the memory cell MC connected to the selected word line. Thereby, the memory cell MC in the E state maintains the E state (erased state), and the memory cell MC in the A state maintains the A state. On the other hand, when 0 is written in the upper page data, electrons are stored in the floating gate of the memory cell MC connected to the selected word line by setting the bit line to the low level. When 0 is written to the Upper Page of the memory cell MC in the E state, the memory cell MC in the B state is obtained. When 0 is written to the upper page of the memory cell MC in the A state, the memory cell MC in the C state is obtained. At this time, the voltage of the selected word line is set higher than the voltage of the selected word line in lower page writing. Alternatively, the potential of the bit line is set lower than the voltage of the bit line in lower page writing. As a result, the amount of electrons accumulated in the floating gate in the upper page zero write becomes larger than that in the lower page zero write. Therefore, the threshold voltage of the memory cell MC in the B state is higher than the threshold voltage of the memory cell MC in the A state, and the A state (10) and the B state (01) can be distinguished. Thus, the memory cell MC can be in four states E, A, B, and C depending on the threshold voltage.

  Vcgr10 is a voltage applied to the control gate when distinguishing data (10) and (11) at the time of reading. Vcgr01 is a voltage applied to the control gate when distinguishing data (01) and (10) at the time of reading. Vcgr00 is a voltage applied to the control gate when distinguishing data (00) and (01) at the time of reading. For example, when the threshold voltage is smaller than Vcgr10 (0 V), the memory cell MC is in the E state (11). When the threshold voltage is lower than Vcgr01 (1V) among the cells excluding the cells determined to be in the E state, the memory cell MC is in the A state (10) and the threshold voltage is lower than Vcgr00 (2V). The memory cell MC is in the B state (10). Other cells are determined to be in the C state.

  Further, Vcgv10 shown in FIG. 4 is a voltage applied to the control gate at the time of verify reading of data (10), and is set in consideration of a constant margin (for example, 0.4 V) with respect to Vcgr. Vcgv10 is, for example, 0.4V. Vcgv01 is a read voltage used for verify read of data (01), and is 1.4 V, for example. Vcgv00 is a read voltage used for verify read of data (00), and is 2.4 V, for example. Vread is a voltage applied to the control gate of the non-selected memory cell when reading data.

  Reading of quaternary data can be realized by three reading steps. For example, Vcgr10 (0 V) is applied to the control gate in the first step. Thereby, the memory cell MC in the E state can be detected. In the second step, Vcgr00 (2V) is applied to the control gate. Thereby, the memory cell MC in the C state can be detected. Further, in the third step, Vcgr01 (1V) is applied to the control gate. Thereby, the memory cells MC in the A state and the B state can be detected.

  FIG. 5 is an explanatory diagram showing the write operation time. FIG. 5 shows QWR (Quick Pass Write) as an example. The horizontal axis is the threshold voltage as in FIG. The threshold voltage of the memory cell MC needs to be within the range of the target distribution Vtgt by writing data. The threshold voltage actually assigned (actually targeted) is in the range of the assigned width as shown by the broken line. However, in consideration of the noise component Vn including the proximity effect and noise at the time of reading, the target distribution spreads in a range indicated by Vtgt.

  Normally, the threshold voltage of all the memory cells MC cannot be shifted into the target distribution by one writing (one voltage application). With a single voltage application, the threshold voltage is distributed over a wide range, such as a one-time writing distribution D1. The width of the one-time distribution D1 is Vp1. Next, the writing step is repeated so that the threshold voltage does not exceed the allocated range. At this time, the potential of the selected word line is stepped up for each writing step. As a result, data is written into the memory cell MC so that the threshold voltage increases by the step voltage width ΔVPGM. The step voltage width ΔVPGM is twice the threshold voltage allocation width Wa. In each write step, weak write is executed so that the threshold voltage is shifted by (1/2) ΔVPGM to the memory cell MC having the threshold voltage from VL to the allocation range. Thereby, the threshold voltage from VL to the allocation range does not exceed the allocation range Wa. By repeating this writing step, the threshold voltage distributed in the one-time writing distribution width Vp1 is shifted into the range of the allocation width Wa. In consideration of the noise component Vn as described above, the threshold voltage of each memory cell MC actually falls within the range of the target distribution Vtgt.

  The number of write steps after one write is (Vp1−ΔVPGM) / ΔVPGM + 1. Therefore, in order to reduce the number of write steps, it is necessary to increase the step width ΔVPGM. Here, as can be seen from FIG. 5, if the allocation width Wa can be increased, the step width ΔVPGM can be increased.

  FIG. 6 is a conceptual diagram showing data levels of the flash memory according to the first embodiment. 4 shows the data level of 4-level data (2-bit data), but FIG. 6 shows the data level of 8-level data (3-bit data). The memory cell of the present embodiment may be a memory cell that stores arbitrary multi-value data of three or more values. The data level is a threshold voltage level that a memory cell can take when certain data is stored. In the conventional data level, Er indicates a level (erased state) in which the threshold voltage of the memory cell is the lowest. The threshold voltage of the memory cell increases in the order of A to G.

  The distribution indicated by the broken line in FIG. 6 indicates the initial threshold distribution written in the allocation range. The distribution indicated by the solid line is an actual writing distribution spread by the proximity effect. The horizontal axis in FIG. 6 indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of cells.

  In the present embodiment, the sense amplifier 40 writes a plurality of data levels of N-bit data to the memory cell as data of the first threshold voltage. For example, the sense amplifier 40 writes the data levels of Er and A to the memory cell as data of the threshold voltage Vt1. That is, the plurality of data levels Er and A are stored in the memory cell overlapping with substantially the same threshold voltage. As a result, one of the eight data levels can be omitted. That is, the memory cell of this embodiment can store 3-bit data at 7 levels. As a result, one or both of the gap (read margin) Mr between the data levels and the distribution width Vtgt of each data level can be widened. By increasing the read margin Mr, the reliability of read data can be increased. By increasing the distribution width Vtgt, the writing speed can be improved. By expanding both the read margin Mr and the distribution width Vtgt, the trade-off relationship between the reliability of read data and the write speed can be eliminated. Further, either the read margin Mr or the distribution width Vtgt may be widened depending on the situation. It is assumed that the difference between the maximum threshold voltage and the minimum threshold voltage of the memory cell storing data is constant.

To further generalize this embodiment, when N-bit data is stored in a memory cell, the data level is less than ^2N . Thereby, if the maximum threshold voltage and the minimum threshold voltage of the memory cell are fixed, both the read margin Mr and the distribution width Vtgt can be widened.

  Data of a certain memory cell tends to be greatly affected by the proximity effect when data having a high threshold voltage is written in a memory cell adjacent to the memory cell of interest. For example, the proximity effect to the target memory cell when the level G data is written in the adjacent memory cell is larger than that when the level A data is written in the adjacent memory cell. Therefore, it is preferable that data having a low threshold voltage is written in the adjacent memory cell. According to the present embodiment, the data of a plurality of levels to be overlapped with the same threshold voltage is the data level Er having the lowest threshold voltage of the memory cell and the data level A having the second lowest. Therefore, the levels B to F are moved to levels having a lower threshold voltage than the conventional level as shown in FIG. That is, each threshold voltage other than the level G having the highest threshold voltage is lowered. As a result, when data of a level other than the level G is written to the adjacent memory cell, the proximity effect on the memory cell of interest is reduced.

  FIG. 7A to FIG. 7C show a modification of the first embodiment. In FIG. 6, the data Er of the lowest level and the data A of the second lowest level are overlapped (combined). However, as shown in FIG. 7A, the highest level data G and the second level data F from the highest level may be overlapped. In this case, the reduction of the proximity effect may be inferior to the embodiment of FIG. 6, but both the read margin Mr and the distribution width Vtgt can be widened. Therefore, even in the modification of FIG. 7A, the effect of the present embodiment can be obtained. FIG. 7B shows a modification in which data levels B and C are overlapped. Even in the modification of FIG. 7B, the effect of the present embodiment can be obtained in the same manner as in FIG.

  FIG. 7C shows a modification in which four data levels are overlapped with two threshold voltages. More specifically, the data levels Er and A are overlapped and one threshold voltage is assigned, and further, the data levels B and C are overlapped and another threshold voltage is assigned. As a result, the memory cell of this modification can store 3-bit data in 6 levels. As a result, one or both of the read margin Mr and the distribution width Vtgt can be further expanded. The modification of FIG. 7C can also obtain the effect of this embodiment.

  Furthermore, the present invention is not limited to the examples of FIGS. 7A to 7C, and any two data levels of the data levels Er to G may be overlapped. Further, the number of pairs of data levels to be overlapped may be two or more as in the modified example of FIG.

  In the present embodiment, the two data levels are overlapped with substantially the same threshold voltage. However, the threshold voltages corresponding to the two data levels may be slightly shifted. That is, the threshold distributions of the two data levels do not need to completely overlap one peak, and may be a peak having two peaks. Even in such a case, the effect of this embodiment is not lost.

  Next, data decoding in data reading will be described. In the present embodiment, since the threshold distributions of the two data levels Er and A overlap, the distinction between the two data is lost. Therefore, in this embodiment, when reading data of a plurality of levels (also referred to as coalesced bits) written as a single threshold voltage, the data is restored and read using an error correction code.

  FIG. 8 is a conceptual diagram showing read data in the present embodiment. A memory access unit is a block. This block may be the same as the block of FIG. 2, or may be a data chunk having a size different from that of FIG. A block to be accessed includes a data area Data and an error correction code ECC. An error correction code ECC is assigned corresponding to the data area Data of each block. The error correction code ECC is stored in the data area 100 and is obtained from the data area 100 when data is read. The error correction code ECC includes information on the number k of combined bits of data. The information may be the number of bits of k itself, or may be a value different from the value of k: for example, encoded according to a predetermined method together with normal ECC information. Further, the combined bit number k may be held in a different area from the ECC area.

  In the present embodiment, the combined bit number k is the number of pairs of data levels that are written redundantly to one threshold voltage. For example, in the form shown in the lower part of FIG. 6 and the form shown in FIGS. 7A and 7B, the number k of combined bits is 1. In the form shown in FIG. 7C, the combined bit number k is two.

  FIG. 9 is a flowchart showing data decryption in the present embodiment. First, the merged bit number k included in the original data stored in the memory cell is detected (S10). When k is 0, the original data does not include a coalescing bit. Therefore, data may be decrypted as usual. The presence or absence of an error is detected (S20), and if the error does not exist in the original data, the original data may be read as restored data without any error correction. If the error is in the original data, the error in the original data is corrected using ECC (S30). For error correction at this time, a known error correction method may be used. If error correction is impossible due to many errors, the block is NG. This is a conventionally performed operation.

  As an example of the ECC, for example, there is a code having an inter-code distance of k + 1 or more. The number of merged bits k is known in advance for each block. Therefore, for example, the ECC inter-code distance is changed according to the number k of merged bits. As a result, error correction with a strength corresponding to the number k of combined bits can be applied to the original data. However, the error correction method is not particularly limited. Since there are many error correction methods, the ECC may be a code that conforms to the method.

  In general, many redundant bits are required for strong error correction. Therefore, strong error correction requires a large area to hold a large number of redundant bits. On the other hand, fewer redundant bits are sufficient for weak error correction. Therefore, an area for holding redundant bits is small for weak error correction. Therefore, by applying error correction with a strength corresponding to the number k of merged bits and the number of error bits, it is possible to achieve an error correction capability with a required strength while suppressing the number of redundant bits required for the entire chip. .

  In general, since strong error correction requires many circuits, the processing time for strong error correction tends to be long. On the other hand, the processing time for weak error correction is short. Therefore, the average error processing time can be reduced by applying only the error correction with the minimum necessary strength according to the degree of error occurrence. In the present embodiment, since the value of k represents the likelihood of an error, the degree of error strength to be applied can be determined with high accuracy in advance while observing the k value.

  According to the present embodiment, data is written into the memory cell so that the data of a plurality of levels are overlapped with substantially the same threshold voltage. Thereby, both the read margin Mr and the distribution width Vtgt can be widened, and as a result, the reliability and write speed of read data can be improved. In addition, when reading data of a plurality of levels (combined bits) written at substantially the same threshold voltage, the combined bits are regarded as an error, and the data is decoded using error correction. Therefore, even if data of a plurality of levels are overlapped with substantially the same threshold voltage, the reading operation is not affected.

  As shown in FIG. 10, the error detection step of step S20 of FIG. 9 may be included in step S30. In this case, steps S10 to S30 are executed regardless of the value of k. However, processing equivalent to that in FIG. 9 is possible. That is, in step S30, if k = 0, error correction processing may be executed as in the conventional case as error correction according to k. On the other hand, when k is 1 or more, the same processing as the error correction processing described when k is 1 or more in FIG.

(Second Embodiment)
FIG. 11 is a flowchart showing a read operation of the NAND flash memory according to the second embodiment of the present invention. In the second embodiment, arbitrary data is assigned to the merged bit, and error detection is executed. Data is decoded by repeating data allocation and error detection. The configuration of the flash memory according to the second embodiment may be the same as the configuration of the first embodiment. The conceptual diagram of the read data may be the same as that shown in FIG.

  First, the merged bit number k included in the original data stored in the memory cell is detected (S10). When k is 0, the original data does not include a coalescing bit. Therefore, data may be decrypted as usual. The presence or absence of an error is detected (S20), and if the error does not exist in the original data, the original data may be read as restored data without any error correction. If the error is in the original data, the error in the original data is corrected using ECC (S30). For error correction at this time, a known error correction method may be used. If error correction is impossible due to many errors, the block is NG.

  If the combined bit number k is 1 or more, the error of the original data is corrected using ECC (S31). If it is OK after correction, restored data is obtained.

  On the other hand, if the error correction is NG, predetermined data is assigned to the merged bits of the original data (S40). Data allocation is speculatively performed on the merged bits. For example, as shown in the lower part of FIG. 6, when the data levels Er and A are merged, first, the data of the data level A is allocated to all merged bits included in the block. Error correction is performed on the allocated data (S50). If the data after allocation is not necessary or can be corrected, restored data is obtained. If the allocated data cannot be corrected, another data is allocated to all the merged bits again in step S40. For example, only one bit out of all the combined bits included in the block is the data level Er, and the other bits are the data level A. Further, error correction is again performed on the allocated data (S50). By repeating steps S40 and S50, the data of the merged bit is restored. If error correction fails more than m times (S60), the block is determined to be NG.

  In addition, as shown in FIG. 12, you may include step S20 and S30 in step S31. In this case, steps S10 to S31 are executed regardless of the value of k. However, processing equivalent to that in FIG. 11 is possible. That is, in step S31, when k = 0, error correction processing may be executed as in the conventional case as error correction according to k. On the other hand, when k is 1 or more, the same processing as the error correction processing described when k is 1 or more in FIG.

  According to the second embodiment, since various data can be assigned to the merged bit, the success probability of error correction in step S50 can be increased. Furthermore, the second embodiment can improve the reliability and write speed of read data as in the first embodiment.

  In the second embodiment, when the number k of merged bits in the block is small, the number of repetitions of steps S40 and S50 is small, and the probability that restored data is obtained increases.

  In the second embodiment, when the number of repetitions of steps S40 and S50 is m or more, the block is determined as NG. However, the block may be decoded using other methods.

  In the foregoing, the method of applying the present technology mainly to the flash memory has been described. On the other hand, the present embodiment can also be applied to a resistance change type memory. For example, a resistance change type memory changes the state of a memory element with a change in temperature, and stores a difference in electrical resistance value depending on the state as information. When the state is changed, the memory cell itself is exposed to a high temperature. The heat has a considerable effect on nearby cells. This becomes more prominent as miniaturization progresses. That is, the resistance change type memory also has a problem of proximity effect between cells due to miniaturization. Further, when the memory element is miniaturized, a problem of data retention characteristics inevitably occurs.

  In general, in order to meet the demand for larger capacity, memory devices are miniaturized and the memory element intervals are reduced. As a result, an increase in proximity effect and deterioration of data retention characteristics inevitably become problems. In order to cope with such a problem, the present embodiment stores data of a plurality of levels in a memory cell as data of a single threshold voltage. The above-described effect is a system that can be effectively applied to all memory devices that store N-bit data (N ≧ 2) (multi-valued data), not limited to NAND flash memory or resistance change memory. Of course, the present invention can be applied not only to a nonvolatile memory but also to a volatile memory such as a DRAM.

  Further, when the proximity effect is large, a reading method for correcting the proximity effect may be used. For example, when data is read from the memory cell MC connected to the selected word line WLn, the data of the selected word line WLn is corrected in order to cancel the proximity effect based on the data of the adjacent word line WLn + 1 ( DLA (Direct Look Ahead) method). However, in the present embodiment, since the proximity effect is small, such correction of data becomes unnecessary. As a result, the data reading speed is also increased.

  In the above-described embodiment, the control circuit 90 or the NAND controller 220 that generates the ECC may be incorporated in the memory chip 10 or may be provided outside the memory chip 10. When writing the N-bit data to the memory chip 10 shown in FIG. 1, the control circuit 90 or the NAND controller 220 overlaps a plurality of levels of data with substantially the same threshold voltage as described in the above embodiment. Write to memory cell. At this time, as shown in FIG. 8, the control circuit 90 or the NAND controller 220 generates an ECC including information on the number of combined bits k for each block and stores it in the data area 100.

  Further, when reading data, the control circuit 90 or the NAND controller 220 obtains the ECC from the data area 100 and controls the memory chip 10 so as to decode the data including the merged bit by using this ECC.

1 is a block diagram showing an example of a configuration of a NAND flash memory 10 (hereinafter simply referred to as a memory 10) according to a first embodiment of the present invention. 2 is a diagram illustrating an example of a configuration of a memory cell array 100. FIG. The figure which shows an example of each structure of block BLOCK0-BLOCKm. The graph which shows the threshold voltage of the memory cell MC which stores quaternary data as an example of this embodiment. Explanatory drawing which shows write-in operation time. The conceptual diagram which shows the data level of the flash memory by 1st Embodiment. The figure which shows the modification of 1st Embodiment. The conceptual diagram which shows the read data in this embodiment. The flowchart which shows the decoding of the data in this embodiment. The flowchart which shows the decoding of the data in the modification of this embodiment. The flowchart which shows read-out operation | movement of the NAND type flash memory according to 2nd Embodiment based on this invention. The flowchart which shows read-out operation | movement of the NAND type flash memory according to the modification of 2nd Embodiment.

Explanation of symbols

100 ... Memory cell array 120 ... ROM
WL ... Word line BL ... Bit line MC ... Memory cells Er, A, B, C, D, E, F, G ... Data levels

Claims (5)

A plurality of word lines extending in a first direction;
A plurality of bit lines extending in a second direction intersecting the first direction;
A plurality of memory cells provided corresponding to intersections of a lattice shape constituted by the word lines and the bit lines, and storing N-bit data (N ≧ 2);
A sense amplifier that is provided corresponding to the plurality of bit lines, detects data stored in the memory cell, or writes data to the memory cell;
When data of a plurality of levels among the N-bit data is written to the memory cell as data of a first threshold voltage, and the data written as the first threshold voltage is read, the data is stored using an error correction code. A semiconductor memory device characterized by reading. A lattice-shaped intersection formed by a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and the word lines and the bit lines A plurality of memory cells provided corresponding to the vicinity and storing N-bit data (N ≧ 2) and a data provided corresponding to the plurality of bit lines and detecting data stored in the memory cells; or A write controller for writing data to a memory unit including a sense amplifier for writing data to the memory cell,
A write controller that controls the memory unit to write data of a plurality of levels among the N-bit data to the memory cell as data of a first threshold voltage. A lattice-shaped intersection formed by a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and the word lines and the bit lines A plurality of memory cells provided corresponding to the vicinity and storing N-bit data (N ≧ 2) and a data provided corresponding to the plurality of bit lines and detecting data stored in the memory cells; or A read controller for reading data from a memory unit including a sense amplifier for writing data to the memory cell,
Controlling the memory unit to read out the data using an error correction code when reading out the data from the memory cell storing a plurality of levels of data among the N-bit data as data of a first threshold voltage Read controller to do.   The data of the plurality of levels corresponding to the first threshold voltage is data having a lowest threshold voltage and a second lowest data of the memory cell among the N-bit data. The semiconductor memory device described. A lattice-shaped intersection formed by a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and the word lines and the bit lines A plurality of memory cells provided corresponding to the vicinity and storing N-bit data (N ≧ 2) and a data provided corresponding to the plurality of bit lines and detecting data stored in the memory cells; or A method of driving a semiconductor memory device comprising a sense amplifier for writing data to the memory cell,
A plurality of levels of data among the N-bit data are written to the memory cell as first threshold voltage data,
A method for driving a semiconductor memory device, comprising: when reading data written as the first threshold voltage, reading the data using an error correction code.

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