TWI750557B - 按行緩衝器單元記憶體分配之判定 - Google Patents
按行緩衝器單元記憶體分配之判定 Download PDFInfo
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- TWI750557B TWI750557B TW108147270A TW108147270A TWI750557B TW I750557 B TWI750557 B TW I750557B TW 108147270 A TW108147270 A TW 108147270A TW 108147270 A TW108147270 A TW 108147270A TW I750557 B TWI750557 B TW I750557B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
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- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/068—Hybrid storage device
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- G—PHYSICS
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- G06F30/32—Circuit design at the digital level
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- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
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- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2117/00—Details relating to the type or aim of the circuit design
- G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/455—Image or video data
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/601—Reconfiguration of cache memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Computer Graphics (AREA)
- Image Processing (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/594,512 | 2017-05-12 | ||
| US15/594,512 US10430919B2 (en) | 2017-05-12 | 2017-05-12 | Determination of per line buffer unit memory allocation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW202014888A TW202014888A (zh) | 2020-04-16 |
| TWI750557B true TWI750557B (zh) | 2021-12-21 |
Family
ID=61599563
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW108147270A TWI750557B (zh) | 2017-05-12 | 2018-02-01 | 按行緩衝器單元記憶體分配之判定 |
| TW107103560A TWI684132B (zh) | 2017-05-12 | 2018-02-01 | 按行緩衝器單元記憶體分配之判定 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107103560A TWI684132B (zh) | 2017-05-12 | 2018-02-01 | 按行緩衝器單元記憶體分配之判定 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US10430919B2 (enExample) |
| EP (1) | EP3622399B1 (enExample) |
| JP (1) | JP7208920B2 (enExample) |
| KR (1) | KR102279120B1 (enExample) |
| CN (1) | CN110574011B (enExample) |
| TW (2) | TWI750557B (enExample) |
| WO (1) | WO2018208334A1 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10387988B2 (en) * | 2016-02-26 | 2019-08-20 | Google Llc | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform |
| US10489878B2 (en) * | 2017-05-15 | 2019-11-26 | Google Llc | Configurable and programmable image processor unit |
| US10534639B2 (en) * | 2017-07-06 | 2020-01-14 | Bitfusion.io, Inc. | Virtualization of multiple coprocessors |
| CN110706147B (zh) * | 2019-09-29 | 2023-08-11 | 阿波罗智联(北京)科技有限公司 | 图像处理的环境确定方法、装置、电子设备和存储介质 |
| US11093400B2 (en) * | 2019-10-15 | 2021-08-17 | Sling Media Pvt. Ltd. | Lock-free sharing of live-recorded circular buffer resources |
| CN114661634A (zh) * | 2020-12-22 | 2022-06-24 | 中科寒武纪科技股份有限公司 | 数据缓存装置、方法、集成电路芯片、计算装置和板卡 |
| US12468581B2 (en) * | 2021-07-26 | 2025-11-11 | Xilinx, Inc. | Inter-kernel dataflow analysis and deadlock detection |
| CN114168524B (zh) * | 2021-12-07 | 2023-10-20 | 平头哥(上海)半导体技术有限公司 | 行缓存单元、加速单元、片上系统和行缓存配置方法 |
| CN114333930B (zh) * | 2021-12-23 | 2024-03-08 | 合肥兆芯电子有限公司 | 多通道存储器存储装置、控制电路单元及其数据读取方法 |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI297468B (en) * | 2004-05-14 | 2008-06-01 | Nvidia Corp | Graphics processor, graphics system, embedded processor, method of performing a graphics processing operation, method of operating a graphics pipeline, method of performing a register write, and method of monitoring a graphics processor |
| US20130194286A1 (en) * | 2012-01-27 | 2013-08-01 | Qualcomm Incorporated | Graphics processing unit buffer management |
| US20140040855A1 (en) * | 2011-07-28 | 2014-02-06 | National Instruments Corporation | Optimization of a Data Flow Program Based on Access Pattern Information |
| US20150055861A1 (en) * | 2013-08-23 | 2015-02-26 | Amlogic Co., Ltd | Methods and Systems for Image Demosaicing |
| WO2016171893A1 (en) * | 2015-04-23 | 2016-10-27 | Google Inc. | Virtual image processor instruction set architecture (isa) and memory model and exemplary target hardware having a two-dimensional shift array structure |
| WO2016171869A1 (en) * | 2015-04-23 | 2016-10-27 | Google Inc. | Line buffer unit for image processor |
| CN106104488A (zh) * | 2014-03-19 | 2016-11-09 | 高通股份有限公司 | 用于支持任务间通信的基于硬件的原子操作 |
| US20160378441A1 (en) * | 2015-06-24 | 2016-12-29 | Altera Corporation | Channel sizing for inter-kernel communication |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5398079A (en) * | 1993-01-27 | 1995-03-14 | General Instrument Corporation | Half-pixel interpolation for a motion compensated digital video system |
| US7499960B2 (en) | 2001-10-01 | 2009-03-03 | Oracle International Corporation | Adaptive memory allocation |
| US7331037B2 (en) | 2004-08-12 | 2008-02-12 | National Instruments Corporation | Static memory allocation in a graphical programming system |
| US8024549B2 (en) * | 2005-03-04 | 2011-09-20 | Mtekvision Co., Ltd. | Two-dimensional processor array of processing elements |
| US7818725B1 (en) | 2005-04-28 | 2010-10-19 | Massachusetts Institute Of Technology | Mapping communication in a parallel processing environment |
| JP4923602B2 (ja) | 2006-02-10 | 2012-04-25 | 富士ゼロックス株式会社 | 画像形成処理シミュレーション装置及び画像形成処理シミュレーション方法 |
| US7890314B2 (en) | 2007-12-05 | 2011-02-15 | Seagate Technology Llc | Method for modeling performance of embedded processors having combined cache and memory hierarchy |
| US20110191758A1 (en) | 2010-01-29 | 2011-08-04 | Michael Scharf | Optimized Memory Allocator By Analyzing Runtime Statistics |
-
2017
- 2017-05-12 US US15/594,512 patent/US10430919B2/en active Active
-
2018
- 2018-01-09 WO PCT/US2018/012875 patent/WO2018208334A1/en not_active Ceased
- 2018-01-09 CN CN201880028856.6A patent/CN110574011B/zh active Active
- 2018-01-09 EP EP18709813.2A patent/EP3622399B1/en active Active
- 2018-01-09 KR KR1020197032090A patent/KR102279120B1/ko active Active
- 2018-01-09 JP JP2019559299A patent/JP7208920B2/ja active Active
- 2018-02-01 TW TW108147270A patent/TWI750557B/zh active
- 2018-02-01 TW TW107103560A patent/TWI684132B/zh active
-
2019
- 2019-09-27 US US16/585,834 patent/US10685423B2/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI297468B (en) * | 2004-05-14 | 2008-06-01 | Nvidia Corp | Graphics processor, graphics system, embedded processor, method of performing a graphics processing operation, method of operating a graphics pipeline, method of performing a register write, and method of monitoring a graphics processor |
| US20140040855A1 (en) * | 2011-07-28 | 2014-02-06 | National Instruments Corporation | Optimization of a Data Flow Program Based on Access Pattern Information |
| US20130194286A1 (en) * | 2012-01-27 | 2013-08-01 | Qualcomm Incorporated | Graphics processing unit buffer management |
| US20150055861A1 (en) * | 2013-08-23 | 2015-02-26 | Amlogic Co., Ltd | Methods and Systems for Image Demosaicing |
| CN106104488A (zh) * | 2014-03-19 | 2016-11-09 | 高通股份有限公司 | 用于支持任务间通信的基于硬件的原子操作 |
| WO2016171893A1 (en) * | 2015-04-23 | 2016-10-27 | Google Inc. | Virtual image processor instruction set architecture (isa) and memory model and exemplary target hardware having a two-dimensional shift array structure |
| WO2016171869A1 (en) * | 2015-04-23 | 2016-10-27 | Google Inc. | Line buffer unit for image processor |
| US20160378441A1 (en) * | 2015-06-24 | 2016-12-29 | Altera Corporation | Channel sizing for inter-kernel communication |
Also Published As
| Publication number | Publication date |
|---|---|
| US10685423B2 (en) | 2020-06-16 |
| TWI684132B (zh) | 2020-02-01 |
| EP3622399B1 (en) | 2023-10-04 |
| TW201907298A (zh) | 2019-02-16 |
| US10430919B2 (en) | 2019-10-01 |
| CN110574011A (zh) | 2019-12-13 |
| US20180330467A1 (en) | 2018-11-15 |
| EP3622399A1 (en) | 2020-03-18 |
| WO2018208334A1 (en) | 2018-11-15 |
| KR102279120B1 (ko) | 2021-07-20 |
| CN110574011B (zh) | 2023-06-27 |
| JP7208920B2 (ja) | 2023-01-19 |
| TW202014888A (zh) | 2020-04-16 |
| JP2020519993A (ja) | 2020-07-02 |
| US20200098083A1 (en) | 2020-03-26 |
| KR20190135034A (ko) | 2019-12-05 |
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