CN110574011B - 每线缓冲器单元存储器分配的确定 - Google Patents

每线缓冲器单元存储器分配的确定 Download PDF

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CN110574011B
CN110574011B CN201880028856.6A CN201880028856A CN110574011B CN 110574011 B CN110574011 B CN 110574011B CN 201880028856 A CN201880028856 A CN 201880028856A CN 110574011 B CN110574011 B CN 110574011B
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line buffer
execution
image data
kernel
image
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CN110574011A (zh
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H.朴
A.梅克斯纳
Q.朱
W.R.马克
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/60Memory management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629Configuration or reconfiguration of storage systems
    • G06F3/0631Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662Virtualisation aspects
    • G06F3/0664Virtualisation aspects at device level, e.g. emulation of a storage device or system
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/068Hybrid storage device
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/33Design verification, e.g. functional simulation or model checking
    • G06F30/3308Design verification, e.g. functional simulation or model checking using simulation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363Graphics controllers
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00Details relating to the type or aim of the circuit design
    • G06F2117/08HW-SW co-design, e.g. HW-SW partitioning
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45Caching of specific data in cache memory
    • G06F2212/455Image or video data
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/601Reconfiguration of cache memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computer Graphics (AREA)
  • Image Processing (AREA)
  • Advance Control (AREA)
CN201880028856.6A 2017-05-12 2018-01-09 每线缓冲器单元存储器分配的确定 Active CN110574011B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/594,512 US10430919B2 (en) 2017-05-12 2017-05-12 Determination of per line buffer unit memory allocation
US15/594,512 2017-05-12
PCT/US2018/012875 WO2018208334A1 (en) 2017-05-12 2018-01-09 Determination of per line buffer unit memory allocation

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CN110574011A CN110574011A (zh) 2019-12-13
CN110574011B true CN110574011B (zh) 2023-06-27

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EP (1) EP3622399B1 (enExample)
JP (1) JP7208920B2 (enExample)
KR (1) KR102279120B1 (enExample)
CN (1) CN110574011B (enExample)
TW (2) TWI750557B (enExample)
WO (1) WO2018208334A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10387988B2 (en) * 2016-02-26 2019-08-20 Google Llc Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US10489878B2 (en) * 2017-05-15 2019-11-26 Google Llc Configurable and programmable image processor unit
US10534639B2 (en) * 2017-07-06 2020-01-14 Bitfusion.io, Inc. Virtualization of multiple coprocessors
CN110706147B (zh) * 2019-09-29 2023-08-11 阿波罗智联(北京)科技有限公司 图像处理的环境确定方法、装置、电子设备和存储介质
US11093400B2 (en) * 2019-10-15 2021-08-17 Sling Media Pvt. Ltd. Lock-free sharing of live-recorded circular buffer resources
CN114661634A (zh) * 2020-12-22 2022-06-24 中科寒武纪科技股份有限公司 数据缓存装置、方法、集成电路芯片、计算装置和板卡
US12468581B2 (en) * 2021-07-26 2025-11-11 Xilinx, Inc. Inter-kernel dataflow analysis and deadlock detection
CN114168524B (zh) * 2021-12-07 2023-10-20 平头哥(上海)半导体技术有限公司 行缓存单元、加速单元、片上系统和行缓存配置方法
CN114333930B (zh) * 2021-12-23 2024-03-08 合肥兆芯电子有限公司 多通道存储器存储装置、控制电路单元及其数据读取方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104081449A (zh) * 2012-01-27 2014-10-01 高通股份有限公司 用于图形并行处理单元的缓冲器管理
WO2016171869A1 (en) * 2015-04-23 2016-10-27 Google Inc. Line buffer unit for image processor
WO2016171893A1 (en) * 2015-04-23 2016-10-27 Google Inc. Virtual image processor instruction set architecture (isa) and memory model and exemplary target hardware having a two-dimensional shift array structure
CN106293958A (zh) * 2015-06-24 2017-01-04 阿尔特拉公司 用于内核间通信的信道大小调整

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398079A (en) * 1993-01-27 1995-03-14 General Instrument Corporation Half-pixel interpolation for a motion compensated digital video system
US7499960B2 (en) 2001-10-01 2009-03-03 Oracle International Corporation Adaptive memory allocation
JP4914829B2 (ja) 2004-05-14 2012-04-11 エヌヴィディア コーポレイション 低電力プログラマブルプロセッサ
US7331037B2 (en) 2004-08-12 2008-02-12 National Instruments Corporation Static memory allocation in a graphical programming system
US8024549B2 (en) * 2005-03-04 2011-09-20 Mtekvision Co., Ltd. Two-dimensional processor array of processing elements
US7818725B1 (en) 2005-04-28 2010-10-19 Massachusetts Institute Of Technology Mapping communication in a parallel processing environment
JP4923602B2 (ja) 2006-02-10 2012-04-25 富士ゼロックス株式会社 画像形成処理シミュレーション装置及び画像形成処理シミュレーション方法
US7890314B2 (en) 2007-12-05 2011-02-15 Seagate Technology Llc Method for modeling performance of embedded processors having combined cache and memory hierarchy
US20110191758A1 (en) 2010-01-29 2011-08-04 Michael Scharf Optimized Memory Allocator By Analyzing Runtime Statistics
US9335977B2 (en) 2011-07-28 2016-05-10 National Instruments Corporation Optimization of a data flow program based on access pattern information
US20150055861A1 (en) * 2013-08-23 2015-02-26 Amlogic Co., Ltd Methods and Systems for Image Demosaicing
US10055342B2 (en) 2014-03-19 2018-08-21 Qualcomm Incorporated Hardware-based atomic operations for supporting inter-task communication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104081449A (zh) * 2012-01-27 2014-10-01 高通股份有限公司 用于图形并行处理单元的缓冲器管理
WO2016171869A1 (en) * 2015-04-23 2016-10-27 Google Inc. Line buffer unit for image processor
WO2016171893A1 (en) * 2015-04-23 2016-10-27 Google Inc. Virtual image processor instruction set architecture (isa) and memory model and exemplary target hardware having a two-dimensional shift array structure
CN106293958A (zh) * 2015-06-24 2017-01-04 阿尔特拉公司 用于内核间通信的信道大小调整

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EP3622399A1 (en) 2020-03-18
WO2018208334A1 (en) 2018-11-15
EP3622399B1 (en) 2023-10-04
TW201907298A (zh) 2019-02-16
US10430919B2 (en) 2019-10-01
US20200098083A1 (en) 2020-03-26
CN110574011A (zh) 2019-12-13
TW202014888A (zh) 2020-04-16
TWI750557B (zh) 2021-12-21
JP2020519993A (ja) 2020-07-02
JP7208920B2 (ja) 2023-01-19
US10685423B2 (en) 2020-06-16
KR20190135034A (ko) 2019-12-05
US20180330467A1 (en) 2018-11-15
KR102279120B1 (ko) 2021-07-20
TWI684132B (zh) 2020-02-01

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