JP7208920B2 - ラインバッファユニット単位メモリ割り当ての決定 - Google Patents

ラインバッファユニット単位メモリ割り当ての決定 Download PDF

Info

Publication number
JP7208920B2
JP7208920B2 JP2019559299A JP2019559299A JP7208920B2 JP 7208920 B2 JP7208920 B2 JP 7208920B2 JP 2019559299 A JP2019559299 A JP 2019559299A JP 2019559299 A JP2019559299 A JP 2019559299A JP 7208920 B2 JP7208920 B2 JP 7208920B2
Authority
JP
Japan
Prior art keywords
data
line buffer
execution
simulated
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019559299A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020519993A5 (enExample
JP2020519993A (ja
Inventor
パク，ヒョンチョル
メイクスナー，アルバート
ヂュー，チウリン
マーク，ウィリアム・アール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google LLC
Original Assignee
Google LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Google LLC filed Critical Google LLC
Publication of JP2020519993A publication Critical patent/JP2020519993A/ja
Publication of JP2020519993A5 publication Critical patent/JP2020519993A5/ja
Application granted granted Critical
Publication of JP7208920B2 publication Critical patent/JP7208920B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/068—Hybrid storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/455—Image or video data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Computer Graphics (AREA)
  • Image Processing (AREA)
  • Advance Control (AREA)
JP2019559299A 2017-05-12 2018-01-09 ラインバッファユニット単位メモリ割り当ての決定 Active JP7208920B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/594,512 2017-05-12
US15/594,512 US10430919B2 (en) 2017-05-12 2017-05-12 Determination of per line buffer unit memory allocation
PCT/US2018/012875 WO2018208334A1 (en) 2017-05-12 2018-01-09 Determination of per line buffer unit memory allocation

Publications (3)

Publication Number Publication Date
JP2020519993A JP2020519993A (ja) 2020-07-02
JP2020519993A5 JP2020519993A5 (enExample) 2020-08-13
JP7208920B2 true JP7208920B2 (ja) 2023-01-19

Family

ID=61599563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019559299A Active JP7208920B2 (ja) 2017-05-12 2018-01-09 ラインバッファユニット単位メモリ割り当ての決定

Country Status (7)

Country Link
US (2) US10430919B2 (enExample)
EP (1) EP3622399B1 (enExample)
JP (1) JP7208920B2 (enExample)
KR (1) KR102279120B1 (enExample)
CN (1) CN110574011B (enExample)
TW (2) TWI750557B (enExample)
WO (1) WO2018208334A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10387988B2 (en) * 2016-02-26 2019-08-20 Google Llc Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US10489878B2 (en) * 2017-05-15 2019-11-26 Google Llc Configurable and programmable image processor unit
US10534639B2 (en) * 2017-07-06 2020-01-14 Bitfusion.io, Inc. Virtualization of multiple coprocessors
CN110706147B (zh) * 2019-09-29 2023-08-11 阿波罗智联(北京)科技有限公司 图像处理的环境确定方法、装置、电子设备和存储介质
US11093400B2 (en) * 2019-10-15 2021-08-17 Sling Media Pvt. Ltd. Lock-free sharing of live-recorded circular buffer resources
CN114661634A (zh) * 2020-12-22 2022-06-24 中科寒武纪科技股份有限公司 数据缓存装置、方法、集成电路芯片、计算装置和板卡
US12468581B2 (en) * 2021-07-26 2025-11-11 Xilinx, Inc. Inter-kernel dataflow analysis and deadlock detection
CN114168524B (zh) * 2021-12-07 2023-10-20 平头哥(上海)半导体技术有限公司 行缓存单元、加速单元、片上系统和行缓存配置方法
CN114333930B (zh) * 2021-12-23 2024-03-08 合肥兆芯电子有限公司 多通道存储器存储装置、控制电路单元及其数据读取方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140040855A1 (en) 2011-07-28 2014-02-06 National Instruments Corporation Optimization of a Data Flow Program Based on Access Pattern Information
US20160313980A1 (en) 2015-04-23 2016-10-27 Google Inc. Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398079A (en) * 1993-01-27 1995-03-14 General Instrument Corporation Half-pixel interpolation for a motion compensated digital video system
US7499960B2 (en) 2001-10-01 2009-03-03 Oracle International Corporation Adaptive memory allocation
WO2005114646A2 (en) 2004-05-14 2005-12-01 Nvidia Corporation Low power programmable processor
US7331037B2 (en) 2004-08-12 2008-02-12 National Instruments Corporation Static memory allocation in a graphical programming system
US8024549B2 (en) * 2005-03-04 2011-09-20 Mtekvision Co., Ltd. Two-dimensional processor array of processing elements
US7818725B1 (en) 2005-04-28 2010-10-19 Massachusetts Institute Of Technology Mapping communication in a parallel processing environment
JP4923602B2 (ja) 2006-02-10 2012-04-25 富士ゼロックス株式会社 画像形成処理シミュレーション装置及び画像形成処理シミュレーション方法
US7890314B2 (en) 2007-12-05 2011-02-15 Seagate Technology Llc Method for modeling performance of embedded processors having combined cache and memory hierarchy
US20110191758A1 (en) 2010-01-29 2011-08-04 Michael Scharf Optimized Memory Allocator By Analyzing Runtime Statistics
US9256915B2 (en) * 2012-01-27 2016-02-09 Qualcomm Incorporated Graphics processing unit buffer management
US20150055861A1 (en) * 2013-08-23 2015-02-26 Amlogic Co., Ltd Methods and Systems for Image Demosaicing
US10055342B2 (en) 2014-03-19 2018-08-21 Qualcomm Incorporated Hardware-based atomic operations for supporting inter-task communication
US9756268B2 (en) 2015-04-23 2017-09-05 Google Inc. Line buffer unit for image processor
US11016742B2 (en) 2015-06-24 2021-05-25 Altera Corporation Channel sizing for inter-kernel communication

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140040855A1 (en) 2011-07-28 2014-02-06 National Instruments Corporation Optimization of a Data Flow Program Based on Access Pattern Information
US20160313980A1 (en) 2015-04-23 2016-10-27 Google Inc. Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure

Also Published As

Publication number Publication date
US10685423B2 (en) 2020-06-16
TWI684132B (zh) 2020-02-01
EP3622399B1 (en) 2023-10-04
TWI750557B (zh) 2021-12-21
TW201907298A (zh) 2019-02-16
US10430919B2 (en) 2019-10-01
CN110574011A (zh) 2019-12-13
US20180330467A1 (en) 2018-11-15
EP3622399A1 (en) 2020-03-18
WO2018208334A1 (en) 2018-11-15
KR102279120B1 (ko) 2021-07-20
CN110574011B (zh) 2023-06-27
TW202014888A (zh) 2020-04-16
JP2020519993A (ja) 2020-07-02
US20200098083A1 (en) 2020-03-26
KR20190135034A (ko) 2019-12-05

Similar Documents

Publication Publication Date Title
JP7208920B2 (ja) ラインバッファユニット単位メモリ割り当ての決定
JP6858239B2 (ja) プログラムコードを、高性能で電力効率の良いプログラマブルな画像処理ハードウェアプラットフォームにマッピングするためのコンパイラ技法
JP7202987B2 (ja) 高性能で、電力効率の良い、プログラマブルな画像処理のためのアーキテクチャ
JP6967570B2 (ja) 画像プロセッサのためのエネルギ効率的なプロセッサコアアーキテクチャ
JP6793162B2 (ja) 画像プロセッサのためのラインバッファユニット
JP6793228B2 (ja) 画像プロセッサのためのシート生成部
CN107430760B (zh) 用于图像处理器的二维移位阵列
CN107533750B (zh) 虚拟图像处理器及在其上处理图像数据的方法和系统
TWI752343B (zh) 用於執行絕對差計算之加總的執行單元電路、影像處理器以及方法
JP6775088B2 (ja) 画像プロセッサランタイム効率を向上するためのプログラムコード変形
JP6967597B2 (ja) 設定可能な数のアクティブなコアを有する画像処理プロセッサおよびサポートする内部ネットワーク
JP6820428B2 (ja) マルチコア画像プロセッサ上のアプリケーションソフトウェアの構成

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200608

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200608

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20210719

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210803

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211104

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20211116

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220316

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20220316

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20220331

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20220405

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20220415

C211 Notice of termination of reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C211

Effective date: 20220420

C22 Notice of designation (change) of administrative judge

Free format text: JAPANESE INTERMEDIATE CODE: C22

Effective date: 20220726

C22 Notice of designation (change) of administrative judge

Free format text: JAPANESE INTERMEDIATE CODE: C22

Effective date: 20221025

C23 Notice of termination of proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C23

Effective date: 20221115

C03 Trial/appeal decision taken

Free format text: JAPANESE INTERMEDIATE CODE: C03

Effective date: 20221213

C30A Notification sent

Free format text: JAPANESE INTERMEDIATE CODE: C3012

Effective date: 20221213

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230106

R150 Certificate of patent or registration of utility model

Ref document number: 7208920

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150