JP2020519993A5 - - Google Patents
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- Publication number
- JP2020519993A5 JP2020519993A5 JP2019559299A JP2019559299A JP2020519993A5 JP 2020519993 A5 JP2020519993 A5 JP 2020519993A5 JP 2019559299 A JP2019559299 A JP 2019559299A JP 2019559299 A JP2019559299 A JP 2019559299A JP 2020519993 A5 JP2020519993 A5 JP 2020519993A5
- Authority
- JP
- Japan
- Prior art keywords
- line buffer
- image data
- buffer memory
- computing system
- simulated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 23
- 238000004364 calculation method Methods 0.000 claims 2
- 238000004088 simulation Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/594,512 | 2017-05-12 | ||
| US15/594,512 US10430919B2 (en) | 2017-05-12 | 2017-05-12 | Determination of per line buffer unit memory allocation |
| PCT/US2018/012875 WO2018208334A1 (en) | 2017-05-12 | 2018-01-09 | Determination of per line buffer unit memory allocation |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2020519993A JP2020519993A (ja) | 2020-07-02 |
| JP2020519993A5 true JP2020519993A5 (enExample) | 2020-08-13 |
| JP7208920B2 JP7208920B2 (ja) | 2023-01-19 |
Family
ID=61599563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019559299A Active JP7208920B2 (ja) | 2017-05-12 | 2018-01-09 | ラインバッファユニット単位メモリ割り当ての決定 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US10430919B2 (enExample) |
| EP (1) | EP3622399B1 (enExample) |
| JP (1) | JP7208920B2 (enExample) |
| KR (1) | KR102279120B1 (enExample) |
| CN (1) | CN110574011B (enExample) |
| TW (2) | TWI750557B (enExample) |
| WO (1) | WO2018208334A1 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10387988B2 (en) * | 2016-02-26 | 2019-08-20 | Google Llc | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform |
| US10489878B2 (en) * | 2017-05-15 | 2019-11-26 | Google Llc | Configurable and programmable image processor unit |
| US10534639B2 (en) * | 2017-07-06 | 2020-01-14 | Bitfusion.io, Inc. | Virtualization of multiple coprocessors |
| CN110706147B (zh) * | 2019-09-29 | 2023-08-11 | 阿波罗智联(北京)科技有限公司 | 图像处理的环境确定方法、装置、电子设备和存储介质 |
| US11093400B2 (en) * | 2019-10-15 | 2021-08-17 | Sling Media Pvt. Ltd. | Lock-free sharing of live-recorded circular buffer resources |
| CN114661634A (zh) * | 2020-12-22 | 2022-06-24 | 中科寒武纪科技股份有限公司 | 数据缓存装置、方法、集成电路芯片、计算装置和板卡 |
| US12468581B2 (en) * | 2021-07-26 | 2025-11-11 | Xilinx, Inc. | Inter-kernel dataflow analysis and deadlock detection |
| CN114168524B (zh) * | 2021-12-07 | 2023-10-20 | 平头哥(上海)半导体技术有限公司 | 行缓存单元、加速单元、片上系统和行缓存配置方法 |
| CN114333930B (zh) * | 2021-12-23 | 2024-03-08 | 合肥兆芯电子有限公司 | 多通道存储器存储装置、控制电路单元及其数据读取方法 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5398079A (en) * | 1993-01-27 | 1995-03-14 | General Instrument Corporation | Half-pixel interpolation for a motion compensated digital video system |
| US7499960B2 (en) | 2001-10-01 | 2009-03-03 | Oracle International Corporation | Adaptive memory allocation |
| WO2005114646A2 (en) | 2004-05-14 | 2005-12-01 | Nvidia Corporation | Low power programmable processor |
| US7331037B2 (en) | 2004-08-12 | 2008-02-12 | National Instruments Corporation | Static memory allocation in a graphical programming system |
| US8024549B2 (en) * | 2005-03-04 | 2011-09-20 | Mtekvision Co., Ltd. | Two-dimensional processor array of processing elements |
| US7818725B1 (en) | 2005-04-28 | 2010-10-19 | Massachusetts Institute Of Technology | Mapping communication in a parallel processing environment |
| JP4923602B2 (ja) | 2006-02-10 | 2012-04-25 | 富士ゼロックス株式会社 | 画像形成処理シミュレーション装置及び画像形成処理シミュレーション方法 |
| US7890314B2 (en) | 2007-12-05 | 2011-02-15 | Seagate Technology Llc | Method for modeling performance of embedded processors having combined cache and memory hierarchy |
| US20110191758A1 (en) | 2010-01-29 | 2011-08-04 | Michael Scharf | Optimized Memory Allocator By Analyzing Runtime Statistics |
| US9335977B2 (en) | 2011-07-28 | 2016-05-10 | National Instruments Corporation | Optimization of a data flow program based on access pattern information |
| US9256915B2 (en) * | 2012-01-27 | 2016-02-09 | Qualcomm Incorporated | Graphics processing unit buffer management |
| US20150055861A1 (en) * | 2013-08-23 | 2015-02-26 | Amlogic Co., Ltd | Methods and Systems for Image Demosaicing |
| US10055342B2 (en) | 2014-03-19 | 2018-08-21 | Qualcomm Incorporated | Hardware-based atomic operations for supporting inter-task communication |
| US10095479B2 (en) * | 2015-04-23 | 2018-10-09 | Google Llc | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure |
| US9756268B2 (en) | 2015-04-23 | 2017-09-05 | Google Inc. | Line buffer unit for image processor |
| US11016742B2 (en) | 2015-06-24 | 2021-05-25 | Altera Corporation | Channel sizing for inter-kernel communication |
-
2017
- 2017-05-12 US US15/594,512 patent/US10430919B2/en active Active
-
2018
- 2018-01-09 WO PCT/US2018/012875 patent/WO2018208334A1/en not_active Ceased
- 2018-01-09 CN CN201880028856.6A patent/CN110574011B/zh active Active
- 2018-01-09 EP EP18709813.2A patent/EP3622399B1/en active Active
- 2018-01-09 KR KR1020197032090A patent/KR102279120B1/ko active Active
- 2018-01-09 JP JP2019559299A patent/JP7208920B2/ja active Active
- 2018-02-01 TW TW108147270A patent/TWI750557B/zh active
- 2018-02-01 TW TW107103560A patent/TWI684132B/zh active
-
2019
- 2019-09-27 US US16/585,834 patent/US10685423B2/en active Active
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