TWI297468B - Graphics processor, graphics system, embedded processor, method of performing a graphics processing operation, method of operating a graphics pipeline, method of performing a register write, and method of monitoring a graphics processor - Google Patents

Abstract

A graphics piocessor has a programmable Arithmetic Logic Unit (.ALL ) capable of scalar arithmetic operations for processing pixel packets and pixel packets formatted in a S l 8 format to improve dynamic range or in a different data format (see figure 3) The graphic processor may be implemented as a configurable graphics pipeline, as distributors couple elements of a graphics pipeline to permit the process flow of pixel packets through to be reconfigured in response to a command from a host and a data packet triggers an element of the graphics pipeline to discover an identifier A configurable test point selector may be used to monitor a selected subset of tap points of the graphics pipeline and count statistics for at least one condition associated with each tap point ot the subset of tap points Pixels may be assigned even pixels or odd pixels and the pixel packets of odd and even pixels then interleaved to account for ALU latency.

Description

1297468 IX. Description of the invention: [Technical field to which the invention pertains] The large system of the present invention is about the imaginary cry of the program. ^ 八 < 慝理窃. More specifically, the present invention is directed to a low power programmable processor for graphics applications. [Prior Art] w Producing 2D graphics images is turned off/main in various video games and other applications. Some of the steps used to generate a two-dimensional image of a scene include generating a two-dimensional model of the object to be displayed. A geometric primitive (ge〇metHcal • primitive) (eg, a triangle) is formed, which is mapped to the two-dimensional projection along with the depth information. Reproducing (drawing) the map originally includes interpolating parameters such as depth and color on each of the two-dimensional projections of the original image. A graphics processing unit (GPU) is typically used in graphics systems to generate three-dimensional images' in response to instructions from the central processing unit (instructi). Modern Gpus typically use graphics pipelines to process data. Figure 1 is a prior art diagram of a conventional pipeline architecture, which is a deep pipeline with stages dedicated to performing specific functions. The conversion phase 1 〇 5 performs the original geometry calculation and can also perform the φ dipping operation. The set/raster stage 110 rasterizes the picture. The texture address stage 115 and the texture extraction stage 12 are used for texture mapping. The materialization stage 130 implements a fog algorithm (f〇g algorithm). Transparency Test phase 135 performs an alpha test. The depth test phase 140 performs a depth test for picking occluded pixels. The transparency blending stage 145 performs a transparency blending color combination algorithm. The memory write phase 1 50 writes to the output of the pipeline. The OpenGL® graphics language is generally used to optimize the 101822.doc 1297468 system pipeline architecture illustrated in Figure 1 for fast texturing. The benefits of a deep pipeline architecture allow for the reproducibility of even the most complex scenarios. The use of three-dimensional graphics has increased in wireless telephones, personal digital assistants (PDAs), and other devices where cost and power consumption are important design requirements. Traditional deep pipeline architectures require significant wafer areas that lead to death: At the cost. In addition, even if the phase is performing quite a bit: the process = pipeline consumes significant power. This is because many phases consume approximately the same i power regardless of whether they are processing pixels. For the sake of cost and power considerations, the conventional deep pipeline architecture illustrated in Figure 1 is not suitable for many graphics applications, such as implementing 3D gaming on wireless phones and pDA. So what we want is a processor architecture that is suitable for graphics processing applications but with reduced power and size requirements. SUMMARY OF THE INVENTION A graphics processor includes a programmable arithmetic logic unit (ALU) for processing pixel packets. Phase 4 ALU stages perform scalar arithmetic operations on pixel packets to implement graphics functions. An embodiment of the method for performing a graphics processing operation on a pixel includes: identifying a function to be performed on a pixel packet - a scalar computing sequence reading line graphic function; generating a plurality of pixel packets for the pixel, each pixel packet being included a sub-group pixel attribute to be processed as an operation element in the scalar arithmetic operation sequence; reading an operation element from at least one of the pixel packets; and performing a scalar arithmetic operation according to the instruction sequence to execute the scalar arithmetic operation sequence . The embodiment of the graphics processor includes: _ having a programmable ALU stage for processing the pixel packet 101822.doc I297468 = tALU, each - programmed to perform a scalar arithmetic operation on a scalar quantity 'the scalar arithmetic The operation is silly /. The incoming instruction is executed on the incoming pixel packet, wherein the sequence of arithmetic operations is performed on the prime packet to perform graphics processing functions. Figure: The device includes a poetic logic unit (alu) that performs scalar arithmetic operations on the pixel packet. For the selected scalar arithmetic operation, the operands in the pixel packet can be formatted to improve the dynamic state. For at least one other έ 晋 曾 ;;; In other data formats, in one method embodiment, a scalar arithmetic operation is identified that can be executed on a pixel packet to implement a graphics function. For each pixel to be processed, at least - like (four) packets are generated, each pixel packet includes at least - a block of the sub-group pixel attributes to be processed as a 7L process, the at least - column having - an associated instruction sequence. The assigned operands are read in a plurality of integers: at least one of the operands corresponds to an operand read by a pixel packet in a self-pixel packet column. In each alu, a scalar arithmetic calculation is performed on the assigned operands according to the sequence of instructions. For the selected scalar arithmetic operation requiring [0, the result of the surrounding, the corresponding operand of the pixel packet is formatted in S18 format, which corresponds to the range of [_2, +2] having the 8-bit fractional component The base 2 of the operand represents 'and clamps the result of the selected scalar arithmetic function to the range of [(), 丨]. For at least one other scalar arithmetic operation, the pixel packet is formatted in a different data format. The graphics processor has elements of a graphics pipeline coupled by a distributor. The allocator such as 101822.doc -8· 1297468 allows the re-domain pixel packet to respond to commands from the host via process f of f-line. In one embodiment of an apparatus, a graphics port S line includes a plurality of stages. The first-distributor faces the individual inputs of the plurality of stages. A second allocation write is coupled to the individual outputs of the plurality of stages. The first splitter and the second splitter are adapted to reconfigure the pixel packets ^, ^, and 2 by a plurality of stages of processing in response to commands from the host. In a method-embodiment, a command from a software host is received to reconfigure the processing flow of the component of the pixel packet via the (4) (four) line. In response, at least one of the dispensers is adjusted to re-establish the process from the s-process to the second process. The graphics processor includes - an arithmetic logic unit for processing pixel packets. The pixels may need to process more than one pixel packet column. Parental errors such as odd and even pixels are similar to pixel buffers to resolve ALU latency. Made into

In a method-embodiment, a sequence of sess-quantity arithmetic operations is identified that can be performed on a pixel packet to perform a graphics function on a plurality of pixels to assign pixels as even or odd pixels. For each master ua, the Beijing generates at least two pixel-packed columns 'per-pixel packet (four) at least two columns of the sub-group pixel attributes to be processed as operands in the scalar arithmetic operation. There is an associated instruction, a flag to indicate whether the image packet is for an odd pixel or an even pixel. In a group of pixels, a column of pixel packets for even and odd pixels is interleaved, wherein each of the columns is assigned for continuous clock cycle 〇Λ ~w τ 蜒. At the ALU stage 101822.doc 1297468, the current clock cycle is received. At least one of the data = column read by the pixel packet column. According to the instruction sequence, the scalar arithmetic calculation is performed on the 像 运 运 , , , , , , , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The one::: graphics pipeline has a process for the pixel packet to be sent through the component of the graphics pipeline. The data packet triggers the element of the graphics pipeline to find the identifier. Only the red case of the line, the received data packet triggers the graphic tube

Position:, 'to find an identifier for the component within the processing flow for each component. Each component writes an identifier in its relative bit register indicating its processing flow. In the embodiment, the component obtains the current value of (4) in the L35, writes the pre-t value to the configuration temporary stolen 'increment the identifier' and forwards the data packet with the incremental identifier to the processing flow. Next component. The graphics processor includes a graphics pipeline. The tap point is associated with the component of the graphics pipeline. A configurable test point selector monitors a selected sub-component joint point and counts at least one conditional count statistic associated with each tap point of the sub-component joint point. In an embodiment, the configurable test point selector functions in response to commands from the software host and collects statistics for the software host. Embodiments Fig. 2 is a block diagram showing an embodiment of the present invention. The programmable graphics processor 205 is coupled to a scratchpad interface 21, a host interface 22, and a memory interface, such as a direct memory access (DMA) engine 230, for use with, for example, a frame. The buffer's graphics memory (not shown) performs the memory read 101822.doc -10- 1297468 fetch/write operation. The host interface 22 allows the programmable graphics processor 205 to receive commands from the host for generating graphics images. For example, the host can send vertex data, commands, and program instructions to the programmable graphics processing state 205. A memory interface such as the DMA engine 23 allows the use of graphics memory (not shown) to perform read/write operations. The scratchpad interface 210 provides an interface for interfacing with the scratchpad interface of the programmable graphics processor 2〇5. The programmable graphics processor 205 can be implemented as part of a system 290 that includes at least one other central processing unit 260 executing a software application program 27 that functions as a programmable graphics processor. 5 hosts. The illustrative system 290 can, for example, include a palm-sized unit such as a mobile phone or a personal digital assistant (PDA). For example, the software application 27A can include a graphics application 275 for generating graphics images on the display 295. Additionally, as described in greater detail below, in some embodiments, the software application 270 can include a graphics processor management software application 28 for executing management functions associated with the programmable graphics processor 2.5A. These management functions such as, for example, pipeline reconfiguration, scratchpad configuration, and testing. In one embodiment, the programmable graphics processor 205, the scratchpad interface 210, the host interface 220, and the DMA engine 230 are components of an embedded graphics processing core 25 formed on a single integrated circuit 200. The single integrated circuit includes a host, such as an integrated circuit 200 formed on the wafer including a central processing unit 26, the central processing unit having a software 270 resident on the memory. Alternatively, the graphics processing core 250 may be disposed on the first integrated circuit, and the CPU 260 is disposed on the second integrated circuit. 3 is a stage 310 stylized instruction detailing a programmable graphic 101822.doc 1297468 in accordance with an embodiment of the present invention. The raster stage 31 processes each pixel of a given triangle and determines the parameters that need to be calculated for the pixel as part of the reproduction, such as computational color, texture, transparency test, transparency blending, z-depth testing, and fogging parameters. In one embodiment, the raster stage 31 计算 calculates the center of gravity coefficients for the pixel packets. In the center of gravity, coordinate system, and system, measure the distance from the vertices in the triangle. Using the center of gravity factor reduces the dynamic range required, which allows the use of fixed points that require less power than floating point calculations. The raster stage 31 produces at least one pixel packet for each pixel of the triangle to be processed. The mother-pixel packet includes an intercept for the payload of the desired pixel attributes (e.g., 'color, texture, depth, fog, (X, y) position). Additionally, each-pixel packet has associated sideband information that includes instructions (4) to be performed on the pixel packet. The instruction area (not shown) in the raster stage 31 指派 assigns instructions to the pixel packet. FIG. 4 illustrates an exemplary pixel package 43 of a pixel. And paste. In the embodiment - the grating stage (4), the pixel attribute is divided into two or more different classes: a pixel packet one, wherein each type of image = is used for the instruction of the special type, and only the data is Dividing into smaller jobs will reduce the bandwidth requirement by + ^ for a particular processing operation and if (for example) 目, 丨〇, only a subset of the pixel attributes will be processed, it will also reduce processing. demand. Ding Yun, the news 49if. The prime packet has an associated sideband information 410 and a payload. The inactive sideband information includes a valid field 412, a kill fleid 4l4, a cancel a % A field, and an instruction field including the current instruction 101822.doc * 13 - 1297468 416. The exemplary pixel packet 43G includes a block and fogging field 426 of the -th set (S, t) texture coordinates 422 and 424. The exemplary pixel packet 46 includes a color block 462 and a second set of texture coordinates (s, t) 464 and a pick. In an embodiment, each pixel packet is represented by a fixed point representation of payload information 42. Examples of pixel attributes that may be included in a pixel packet (where the pixel attribute size of the pixel attribute is Langer) include: - Z l6 hexadecimal warfare value; a 16-bit S/T texture coordinate and 4 bit Fineness; a pair of color values, each with an accuracy of 8 bits; or a 25555 argb color, where each of the five bits is in each ARGB variable. The sideband information of the pixel packet may include the (x, y) position of the pixel. However, in an embodiment, the start span command is generated by the raster stage 310, y) origin, where it begins to pass through the triangle along the scan line. Using the Start Span command will allow the self (image) package to omit the (x,y) position. The start span command informs other entities (e.g., data writer stage state and data extraction phase 330) at the initial (x, y) position at the beginning of the scan line. Along the scan line: the (x'y) position of his pixel can be inferred from the number of pixels from which a given pixel is derived. In one embodiment, the 'data writing phase and data extraction phase 330 includes native cache memory, and the native cache memory is adapted to increment the local count H, based on its cross-four command. The number of pixels encountered is calculated to update the (x, y) position. > Looking at Figure 5, in the embodiment, the raster stage 3 bay is to be processed - at least - pixel packet column 51 (). In some embodiments, each column = has a common sideband information defining a sequence of instructions for the column 510. The right pixel requires more than - column 510, and the columns 510 are organized as _101822.doc -14 - 1297468 and queues 'which are processed continuously with each new clock cycle. In:, the sub-pixel data is divided into four riding element pixel attributes ^ profit value 'where the four pixel register values define the pixels of the pixel (R0, Rl, R2 and R3) of the column, 51迭代. The iterative register (4) of the raster stage 3丨0 (not shown) has a corresponding register to support the pixel packet column 510β. In the embodiment, the raster stage includes - supporting the four-pixel packet column of the Shangda Scratchpad pools. Some types of pixel-packet attributes (such as textures) may require high precision. Conversely, some types of pixel-packet attributes may require lower precision, such as color. Configurable scratchpad pools To support the high accuracy and low accuracy of each pixel packet in column 51G. In the implementation, the scratchpad pool includes 4 high precision and 4 low precision perspective correction iteration values per column plus z depth value. For example, in this way the software assigns the iterator's precision for processing specific pixel packet attributes. In one embodiment, the raster stage 3 ι includes a register set that is adapted to track the integer portion of the texture. Zone, thus allowing The decimal bit is transmitted as a data packet. The raster stage 310 can, for example, receive an instruction from the host that needs to perform an operation on the pixel. In response to the 'raster stage 31', a multi-pixel packet with an associated instruction sequence is generated. The columns, wherein the pixel packet columns and instructions are configured to perform the desired processing operations. As described in more detail below, in the embodiment, the ALU stage 34 is capable of performing scalar arithmetic operations: where the operands comprise pixel packets A pre-selected subset of pixel attributes, constant values, and previously calculated temporary storage results on the pixel packet in column 51. Various graphical algorithms can be expressed as one or more scalar arithmetic operations. 101822.doc 15- 1297468 Additionally, Various vector graphics operations can be expressed as a plurality of scalar arithmetic operations. Thus, it should be appreciated that the programmable graphics processor 205 of the present invention can be programmed to perform any graphics operation on a pixel, which can be represented as a pure Sequence of arithmetic operations, such as atomization operations, color (transparency) color mixing, texture combining, transparency testing, or deep Degree test, such as in 〇pen Gjl®

The operations described in Graphics System: A Specification (Version ι. 2) are incorporated herein by reference. For example, in response to raster segment 3 10 pre-determining the desired graphics processing function (eg, atomization operation) to be performed on the pixel, raster stage 3 10 may determine the pixel using a programmable mapping table or mapping algorithm. Encapsulation and assignment of associated instructions for performing scalar arithmetic operations required to implement graphics functions on pixels. The mapping can be stylized, for example, by the graphics processor management software application 28. Referring again to Figure 3, as each pixel of the triangle is navigated by the raster stage 310, the raster stage 3 1 〇 produces pixel packets for further processing, which are received by the gateway manager stage 32 。. The gateway manager stage 320 performs data flow control functions. In one embodiment, the gateway manager stage _ 320 has an associated scoreboard 325 for scheduling, load balancing, resource allocation, and avoidance of pixel packets. Scoreboard 325 tracks the entry and exit of pixels. The score packet entering the gateway manager stage 320 sets the scoreboard, and the scoreboard is reset to the pixel packets ejected from the programmable processor 2〇5 after processing is completed. As an illustrative example, if the compact display 295 has an area of 128 x 32 pixels, the scoreboard 325 can maintain a table for each pixel of the display to monitor pixels. The scoreboard 325 provides several benefits. For example, when one of the triangles is like 101822.doc. 1297468 is located on top of another pixel being processed and in flight, the scoreboard 325 prevents danger. In one embodiment, the scoreboard milk monitors the idle conditions and causes the scoreboard technique (s(10)eb_ding) to record the idle unit time. For example, if there are no valid pixels, the scoreboard 325 can turn off the ALU to save power. As described in more detail below, the scoreboard milk tracks the pixel packets, which can be processed by the ALU 350 along with the pixel packets with the canceled bytes, such that the pixel packets flow through the ALU 35 without being actively activated. In one embodiment, the scoreboard 325 tracks the recirculating pixel seals, which are (X, 3 〇 position. If the pixel packets are recycled, the scoreboard 325 increments the sequence of instructions in the pixel packets to pixels in subsequent passes. The next instruction, for example, if the instruction is used for atomization operations on the number i, then the instruction is iterated over the number 2 to a translucent color mixing operation. The nurturing extraction stage 330 is extracted by the gateway manager 32 〇 The data of the pixel packets may include, for example, performing color, depth, or texture data reading by performing a color, depth, or texture data read by a pixel packet column. The data extraction phase 33 may, for example, By self-memory: please call for reading (for example, use the DMA engine 23〇 to read the frame buffer (not shown)) to extract pixel or quality data. In the embodiment The fetch stage 330 can also manage native cache memory, such as texture/atomized cache memory 332, color/depth cache memory 334, and z cache memory for depth data (not shown). Before the pixel packet is sent to the next stage, the extracted data is placed on the corresponding pixel packet field. In the embodiment, the data extraction stage 330 includes a shelf for accessing the pixel packet attribute. The required data-instruction command random access memory (ram). In some 101822.doc -17 - 1297468 embodiments, the data extraction phase 330 also performs a Z-depth test. In this embodiment, the data extraction phase 330 uses one or more depth comparison tests to compare the Z-depth value of the pixel packet with the stored Z-value. If the Z-depth value of the pixel indicates that the pixel is occluded, then the cancellation bit is set. The pixel packet column enters the arithmetic logic unit ( ALU) stage 340 for processing. ALU stage 340 has a set of ALUs 350 including at least one ALU 350, such as ALU 3 5 0-0, 3 50-1, 35 0-2, and 3 50-3. ALU 350' but depending on the application, available at More or less ALUs 350 are used in the alu stage 340. The individual ALUs 350 read the current instructions for at least one pixel packet column 5 1 , and implement any instructions to perform the alu stylization to support the scalar amount Arithmetic operations are included in each ALU 3 5 and can be stored, for example, in a native instruction RAM (not shown in Figure 3). Each ALU 350 includes a product for the first operand (a *b) and an instruction to perform at least one arithmetic operation on the second operand product (b*c), where &, b, 〇, and d are operands and * is multiplication. Some or all of the operands may correspond to (10) as in the scratchpad value column 510 within the scratchpad value attribute. ALU35〇 can also have one or more telegrams for normal or software loading; γ to » ^ , ' 乂 彳 彳 彳 异 。 。 。 。 。. In some embodiments, the ALU may support the use of a temporary storage result from a singular sentence of πI on the bar. In an embodiment, each ALU 350 is programmable. A switch (cr〇ssbar) (not shown) or other programmable selector may be included in the "noon" option and the result of the response in response to the software (eg 'software application 270') Instructions. For example, in the middle, the operation command code can be used to encapsulate the column 51 from the pixel. The source, temporary value, and constant value of any temporary 101822.doc •18 * 1297468 are selected as the source of each operand (a, b, c, d). = This is the case, the # command also indicates where the ALU 35q sends the arithmetic. For example, using the result to update the pixel packet, storing the result; , , , α temple value or both using the result to update the pixel packet and storing the result as a temporary value. For example, &, programmatic alu can be used to read a specific attribute in a pixel packet as an operand, and apply the purely different operation specified by the #pre-instruction. The operation command code may also include a complementary operation element (for example, calculating l_x, where the parent is a read value), a negation operation element (for example, π-Χ, where X is a read value), or a clamp operation element or The result of the order. Other examples of operations may include, for example, commands to select data patterns. An example of an arithmetic operation performed by ALU 350 is a scalar arithmetic operation of at least one variable form (a*b)+(c*d) within a pixel packet, where a, b, e

And d is an operand and * is computed as a multiplication. Preferably, each alu 350 can also be programmed to perform other mathematical operations, such as complementary operands and negation elements. Additionally, in some embodiments, each ALU 35 can calculate a minimum and a maximum from (a*b, c*d) and perform a logical comparison (eg, if a*b is equal, not equal, less than, or Less than or equal to the logical result of c*d). In some embodiments, each ALU 35 can also include instructions for determining whether to generate a cancellation bit in the cancellation field 414 based on a test, such as a*b and c*d. Comparison (for example, if a*b is not equal to c*d, cancel, if a*b is equal to c*d, cancel, if a*b is less than c*d, cancel, or if a*b is greater than or equal to c*d cancel). An example of an alu operation that can generate a cancel bit includes a transparency test in which a color value is compared to a test color value, such as the expression IF (Transparency > Transparency Reference), then the pixel is cancelled, 101822.doc -19- 1297468 where transparency is The color value, and the transparency reference is the reference color value. Another example of an ALU operation that can produce a 4-bit το is a 2-depth test in which the Z-value of a pixel is compared to at least one Z-value of a previous pixel having the same position and the depth test indicates that the pixel is occluded. , then cancel the pixel. In the embodiment, if the cancellation bit is set in the pixel packet, then the individual ALU 35G is deactivated. In the embodiment, when a cancel bit is detected in the square band body, a clock gating mechanism is used to disable the ALU 35G. As a result, after the cancellation bit is generated for the pixel packet, the ALU 350 does not waste power on the pixel packet because it propagates via phase =0. However, it should be noted that the pixel packet with the canceled byte is still propagated forward, allowing it to be resolved by the data write phase 355 and the scoreboard 325. This way all pixel packets are allowed to be resolved by the scoreboard 325, even The pixels marked by the cancellation bit as not requiring further alu processing are encapsulated in the embodiment. If any column 5 10 of the pixel is marked by the cancel bit: the other columns 51 of the same pixel are also cancelled. This can be done, for example, by forwarding the cancellation information between & or by tracking the "or multiple phases" of the pixels (where column 5 10 is marked by the cancellation bit). In some embodiments, a 'corner 7L is set, and only the sideband information of the pixel packet column 〇1 (which includes the cancellation bit) is propagated to the next stage. & ALUP "The output of the other 34" goes to the data writing stage 355. The data writing stage 355 converts the processed pixel packet into pixel data and writes the result to the memory interface (eg 'via DMA engine 23〇) In one embodiment, the write value of the pixel is accumulated in the write buffer 352, and the accumulated write of the pixel is written to the memory by the cutter. The function of the data writer stage 355 is 101822.doc 1297468 Examples include color and depth write back and format conversion. In some embodiments, data writing stage 355 can also identify pixels to be cancelled and set up silk distracting elements. Loop back to the gateway manager 320. The re-routing path 36 allows, for example, the need to use the process of performing an arithmetic operation sequence through the stage "o more than once. Data Write Phase Indicates that the retirement is written to the Gateway Manager Phase 32 for use in the scoreboard technology. Figure 6 is a block diagram of an exemplary individual ALU 35〇. The ALu 35A has an input bus 605 having a data bus for receiving pixel packet columns 51 of the corresponding registers r, R1, R2, and R3. Includes instruction RAM6H) for ALU instructions. An exemplary set of instructions is in block 62: to illustrate. In one embodiment, the programmable ALU 35 reads any of the four 20-bit scratchpad values from column 51 and selects a set of operations from column 51. In addition, the programmable ALU 350 selects the temporary value as an operand from the scratchpad (T) 63, such as two 20-bit temporary values per ALU 350, which can be temporarily stored as a result, such as path 64. Instructed. The ALU 35〇 can also select a constant value (not shown) as an operand, which can also be programmed by software. In one embodiment, the first multiplexer (MUX) stage 645 selects operands, any temporary values 630, and any constant values (not shown) from the pixel packet column. A format conversion module 650 can be included to convert the operands into a desired data format suitable for the computational accuracy of eight 1^11 3 50 in the arithmetic calculation unit 67.八乙1; 35〇 includes elements to allow selection of each operand or its complement in the second MUX stage 660. The resulting four operands are input to a scalar arithmetic calculation unit 67, which performs two multiplications and one addition. The resulting value can be clamped to the desired range (e.g., 〇 to 1 〇) using a clamp 680, as appropriate. Pixel 1018|2, d〇c - 21 - 1297468 Packet column 510 exits on bus bar 690. In an embodiment, the selected pixel packet attribute may be in the -symbol i8 (si8) format. The S1.8 format is - the number of base 2 with an 8-bit fraction, which ranges from [-2 to +2]. The S1.8 format allows for a higher dynamic range of calculations. For example, in the calculation of processing illumination, the S1.8 format allows for an increased dynamic range, resulting in improved authenticity. If the result of the scalar arithmetic transfer performed by (1) must be in the range of [G, l], the result can be clamped to force the result to be in [〇, im, as an illustrative example, in S8 format^ The network of color data (4) is calculated and then _ results. In the embodiment of the invention, the different types of pixel packets may have data attributes in different formats. For example, t, the color data may be represented by a first type of pixel packet of the S18 format, and (s, the texture material may be represented by a second type of pixel packet of a high precision ^bit format. In some embodiments The pixel packet bit size is set by the bit size requirement of the highest precision pixel attribute. For example, since the texture attribute—heart color requires greater precision, the pixel packet size can be expressed with high precision. Texture data such as 16-bit texture data. The improved dynamic range of the S8 format allows, for example, efficient encapsulation of data for more than one color component into a 2G bit pixel packet size, which is required (for example) 16-bit texture data and 4-bit fineness (L0D) for higher-precision data texture data. For example, ^, I., because the mother-S1.8 color component requires 10 bits 70' The two color components can be packaged into 2G bit pixel packages. Figure 7 illustrates an exemplary ALU stage 34, which includes more than one ALU 3 50 configured as a pipeline, J: φ two plus buckets, work plus, Two or more ALUs 35〇 are chained together at 101822.doc * 22 1297468. As previously explained, individual ALU35 (m self-pixel packet reads - or multiple operands can be programmed to generate The result of the arithmetic operation, and use the result to update the pixel packet or temporary register. Each (10) can be assigned to read the operand, produce an arithmetic result, and update the pixel packet column to the next alu. Or multiple pixel packets or temporary values. Depending on the processing operations to be performed, ALU latency, and efficiency considerations, the data flow between alu 35〇 in the ALU phase 34〇 can be configured in various ways. The present invention allows each lu to be programmed to read selected operands within the column of the prime packet and use the result to update the selected pixel packet register. In an embodiment, then stage 34A is included for each At least one ALU 350 of a color channel (eg, red, green, blue, and transparency). In this manner, for example, load balancing is allowed, wherein the ALs are configured to operate in parallel on the pixel packet column 5 10 (although due to tube Techniques at different points in time to perform similar or different processing tasks. As an example of how the ALU 350 can be programmed, the first ALU 35〇-〇 can be programmed to perform the calculation of the first color component, which can be programmed :ALU35〇_1 to perform the second color into a punch operation, the third ALU35〇-2 can be programmed to perform the third color component, and the fourth ALU 3 50-3 can be programmed to perform the atomization. Thus, in some embodiments, for a pixel packet column 5, each ALU 35 can be assigned a different processing task. Additionally, as described in more detail below, in some κ embodiments The software configurable ALU 350 selects the data stream of the ALU 350 within the ALU stage 340, including the execution order of the ALU 3 5〇. However, since the data stream can be configured, it will be appreciated that in some embodiments, the data stream along an ALU chain can be configured such that the result of an ALU 35 is updated by one or 101822.doc 1297468

To read. It is used as an arithmetic unit by the subsequent ALU 350-1. FIG. 8 is a graphics processor 205.

Reconfigure the pixel packet through the processing flow of the stage. It is therefore preferred to utilize synchronization techniques to coordinate the flow of pixels in flight during a change from one configuration to another, meaning that synchronization is performed such that it is in flight intended to be in the first configuration. The processed pixel packet is changed in the configuration to Figure 8 is a block diagram of an embodiment of a programmable portion having a reconfigurable pipeline, wherein the pixel conjunction process is configurable in response to a software command, such as a second group Complete its processing before the state. In one embodiment, the data extraction phase 830, the data writing phase 855, and the individual ALUs 850 have individual inputs that are each coupled to the first distributor 89A and respective outputs that are coupled to the first distributor 895. Each of the splitters 890 and 895 can, for example, include a switch, crossbar switch, router or MUX circuit to select the incoming stream of incoming packets to the data extraction stage 830, the ALU 8 50, and the data write stage 855. Distributors 890 and 895 determine the incoming pixel packet 810 via the data extraction phase 830, the data write phase 855, and the individual ALU 850 data paths. Signal inputs 892 and 894 allow allocators 890 and 895 to receive software commands (e.g., from a software application executing on the CPU) to extract phase 830, data write phase 855, and ALU 850 in data 101822.doc -24· 1297468 Re-distribution and allocation of pixel packets. One instance of reconfiguration is to assign the execution order of the ALU 850. Another example of reconfiguration is if the data extraction phase is not required for a particular time processing task, then the data extraction phase 83 is bypassed. As yet another example of reconfiguration, it may be necessary to change the order in which the data extraction phase 83 is coupled to the ALU. As another example, it may be necessary to reorder the data write phase 855. As an illustrative example, there may be the following cases: where it is more efficient to operate on the texture coordinates prior to data extraction, in which case the data stream is configured to cause the data extraction phase 83 to receive after the aloe 85 texture processing operation Pixel packet. Therefore, one benefit of the reconfigurable pipeline is that the software application can reconfigure the programmable graphics processor 205 to increase efficiency. Referring again to Figure 5, as previously discussed, the grating phase 31 is generated for use at

The pixel block column 510. The columns 51A can be further configured as a group of MO columns, such as a four column 5 丨〇 sequence, which are passed for processing in a continuous clock cycle. However, some of the operations that can be performed on the pixel packet column 51 can require the result of an arithmetic operation of another pixel packet column. Thus, in one embodiment the 'raster stage 310 configures pixel packets in the _group 52() column to account for data. As an illustrative example, if the texture operation on the pixel packet is the result of another pixel packet, then the group 52 is configured such that there is a dependency on the texture (4). Referring to Figure 9, JZ _ , in her case alone, the pixels are alternately assigned odd or even by the raster stage 310. The respective registers (R0, R1, R2, and R3) of each 4-pixel column are assigned as even or odd. Then use one or more rules to interleave the even pixel packets (4) 5 of the 10822.doc -25 - 1297468 pixels and the (4) 9ig clear data of the odd pixels. Interleaving every other column will provide an additional clock cycle to solve the ALU latency. . 51 If the even pixel column G requires two clock cycles to achieve the desired result, then the odd-numbered pixel column 0 is interleaved by the ALU waiting time for the additional clock cycle. As a two-intelligence example, a multi-texture operation is considered in which the column of even pixels is mixed color and the column 1 of the same pixel corresponds to the result of the need for the first-color mixing operation: the /ttl color of the texture. If the ALU latency of the first operation is two, 2 cycles' then the interleaving will allow the result of the color mixing operation to be used for the texture of the nose. In an interleaved embodiment, sideband information is preferably included to coordinate interleaving. For example, in one embodiment, the sideband information in each pixel packet includes an - even/odd block to distinguish between even and odd columns. Each of the surveys (10) = includes two sets of temporary temporary registers corresponding to even and odd pixels, providing a suitable temporary value for the dual/odd pixel packets. The even/odd block is used to select the appropriate temporary register set, e.g., for the odd pixel even temporary register' and the odd pixel selects an odd temporary register set. In one embodiment, both the even and odd pixels share a constant register to reduce the amount of storage required for constant values of even and odd pixels. In the embodiment, the software host can use the constant value to set the temporary temporary register up-extension period to verify the constant register. Although interleaving two pixels is an embodiment, it should be understood that if, for example, the ALU latency corresponds to more than two clock periods, then the interlace can be further extended to interlace two or more image raster stages 3 10 interlaced pixel packets

One is that the hardware considers the ALU 101822.doc -26- 1297468 latency, which reduces the burden on the software to solve the ALU latency. If the raster phase 3 10 is not interlaced, for example, the ALU will occur separately. waiting time. As discussed previously, in a configurable pipeline, the data flow within the ALU 350 can be configured. For example, in hardware, each ALU 3 50 can be substantially the same. However, a particular ALU can be configured to have more than one location in the data stream, e.g., a different order of execution. Therefore, an identifier needs to be provided in each ALU 350 to indicate its location within the data stream. Each ALU 350 can be provided with an identifier, for example, by |direct register write technology for each ALU 350. However, this approach has the disadvantage of requiring significant software consumption. Thus, in one embodiment, a packet technique is used to trigger an element that needs to configure information to find its relative position within the process flow and to write a corresponding identifier in the local register. Referring to Fig. 10, in one embodiment, the scratchpad address space of the ALU 350 uses a software configurable type of packet initialization techniques to communicate an identification (10) to each october 11 350 using a data packet. Each of the eight 1^11 350 can, for example, include a conventional network module for receiving and forwarding data packets. In one embodiment, the '10 packet 1' is initiated by the software application. 1 £) Packet 1〇1〇 Contains the initial ID code, such as a number. The ID packet 1010 is injected into the graphics pipeline at a point before the component requiring 1]3 code and then passed to subsequent components of the processing flow defined by the current pipeline configuration. In an embodiment, the configuration register 1020 in the first ALU 350 receives the ID packet, writes the current value of the ID code into the configuration register, and then passes the 1〇 packet to the next The 10 code of the ID packet is incremented before an ALU. Continuing with this process, 101822.doc -27- 1297468 each subsequent ALU 350 writes the current value of the ID code into its configuration register, and then passes the ID packet with the incremental ID code to the next alu . It should be understood that the configuration registers can be configured in a similar manner along other stages of the data flow path. For example, the components in the configuration stream may also include a data extraction phase or a data write phase, which also has a configuration register set by reading still packets, and which will have 1 packet with increments (1). The code is incremented by 10 yards before being passed to the next component in the configuration stream. One benefit of this form of register configuration is that it does not require hardware differences between ALU 350 units, so Φ allows data flow to be reconfigured via pipeline software. Thus, for example, in one embodiment, the graphics processor management application 28 only needs to generate an initial packet 1010, such as by issuing a command to generate an ID packet 1010 via the host interface 220, the command being packetized by the ID. The generator 1030 receives it. In an alternate embodiment, a broadcast packet technique is used to write a 1 £&gt; code into the configuration register to trigger an element that needs to be written to the configuration register to find its ID. In this embodiment, the elements (e.g., ALU 35A) can use a network protocol to discover their ID. Broadcast packet techniques can be used, for example, in embodiments where the pipeline is branched ® to allow the branches of the pipeline to process pixels in parallel. The figure illustrates an embodiment including diagnostic monitoring capabilities. In one embodiment, there is a series of taps along the components of graphics processor 2〇5, such as taps associated with each ALU 35〇 and data extraction phase 33〇. Taps can also be included at other stages. The configurable test point selector 丨丨〇5 is adapted to allow monitoring of selected taps such as two taps 112〇 and 113〇 in response to software commands such as those from the graphics processor management application 28 Software command. A configurable test point can be implemented, for example, using a multiplexer 101822.doc -28- I297468 L selector 1105. In an embodiment, at least - a counter (1) is included for statistical collection for each selected test point. In one embodiment, the instrumentation packet generated by the software provides information about the taps to be monitored and enables counting for the selected test points. In addition, the recordable temporary storage Hsaki is based on the tubular operation mode (4) metering collection (for example, a tracking record register can be provided to allow the software to be a specific type of graphics operation number, such as enabling statistical counting when a transparency color mixing operation occurs. One of the benefits of the configured test point selector 11〇5 is that it allows software such as the graphics processing H management application to have statistics collected only for the test points of interest, thereby reducing hardware complexity and cost. 'A P-knife that still allows the software to analyze the behavior of the programmable processor 2〇5 can, for example, select a test point of interest to collect statistics associated with the ALU 350 that processes a particular type of poor material, which ALU 35 such as ALU 350 for processing textured beakers. Additionally, statistic collection can be enabled for specific graphics operations, such as transparency blending. In one embodiment, the 'configurable' test point selector 11〇5 utilizes a three-wire protocol Each component, such as ALU 350-0, having payload data produces a valid signal that can, for example, flow down to the next component (eg For example, ALU 350-1). A component ready to receive a payload generates a ready signal that can, for example, flow up to the previous component. However, if the component is not ready to receive a payload, the component generates a not ready signal. The not ready signal may, for example, correspond to an undetermined ready signal. The enable signal corresponds to an element enabled for monitoring 'this monitoring is enabled by means of software control via a monitoring enable control bit stored adjacent to the monitored point Pipelined register 101822.doc -29- 1297468 Write the nickname to directly tap the component that generated the S signal or the component that receives the signal. The valid, ready, and not available at the selected tap point can be used. The ready signal determines the different state of the transfer. A transfer state corresponds to a clock mark having a valid payload (ie, a valid byte) for downstream data and a downstream block The ready signal to receive data in the downstream block (eg, at tap point 1120, - a valid signal from ALU_0, and at tap point 113〇, - The ready signal from ALMM. - The wait state corresponds to a clock token with a valid payload, the valid payload being blocked because the following block is not ready to receive data (eg, at tap point 1120, A valid signal from IVAL_0, and a 'not ready signal from ALU-i' at tap point 1130. In this embodiment, statistics on selected tap points can be collected, such as counting shifts. The number of clock cycles in which the wait state is detected. Embodiments of the present invention provide various benefits that can be used in the embedded graphics processor core 250. In a compact system, low power palm-sized systems 29, power, space, and CPU power can be fairly limited. In one embodiment, the ALU 350 is clocked (e.g., by detecting cancellation bits) when processing is not required, thereby reducing processing power requirements. In addition, the raster stage 31〇 only needs to generate pixel packets for the processed subset of pixel data, thereby also reducing power requirements. The programmable ALU stage 34(R) requires a smaller wafer area than a conventional pipeline having a dedicated stage for performing dedicated graphics functions, thereby reducing cost. The programmable processor 2〇5 can be implemented as a software configurable block&apos; to provide improved efficiency. Test Monitoring 101822.doc -30- 1297468 is configured to test a subset of test points, thereby reducing the bandwidth and analysis requirements of the software. These and other previously described features enable the tangible graphics processor 205 of interest to be used in the embedded graphics processor core. The above description for the purpose of explanation is used to provide a complete understanding of the invention. However, it will be apparent to those skilled in the art that <RTIgt; Accordingly, the above description of the specific embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. It is obvious that many modifications and variations are possible in light of the teachings of the above. The embodiments were chosen and described in order to best explain the embodiments of the invention, For the specific use covered. The scope of the claims below and the equivalents thereof are intended to define the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of a prior art pipeline of a three-dimensional graph; "2 is a block diagram of an integrated circuit including a programmable graphics processing Φ device according to an embodiment of the present invention; FIG. 3 is based on A block diagram of a programmable graphics processor in accordance with an embodiment of the present invention; FIG. 4 illustrates an exemplary pixel packet in accordance with an embodiment of the present invention; FIG. 5 illustrates a pixel packet configured as a group of pixels in accordance with an embodiment of the present invention. Illustrative configuration of a packet column; Figure 6 is a block diagram of a single-arithmetic logic unit in accordance with an embodiment of the present invention; 101822.doc - 31 · 1297468 Figure 7 is an embodiment of the present invention - containing two arithmetic a block diagram of the sequence of logical units;

8 is a block diagram of a configurable programmable processor of FIG. 3 in accordance with an embodiment of the present invention; FIG. 9 illustrates a staggered row of pixel packs in accordance with an embodiment of the present invention; FIG. A block diagram of an arithmetic logic unit having a configuration register in one embodiment; and FIG. 11 is a block diagram illustrating a configurable test point selector in accordance with an embodiment of the present invention. The same reference numbers are used in the corresponding drawings throughout the drawings. [Major component symbol description] 105 Conversion phase 110 Setting/raster phase 115 Texture address phase 120 Texture extraction phase 130 Atomization phase 135 Transparency test phase 140 Depth test phase 145 Transparency color mixing phase 150 Memory writing phase 200 Integrated circuit 205 Graphics Processor 210 Scratchpad Interface 丨.doc -32- 1297468

220 Host Interface 230 Direct Memory Access (DMA) Engine 250 Graphics Processing Core 260 Central Processing Unit 270 Software Application 275 Graphics Application 280 Graphics Processor Management Software Application 290 System 295 Display 305 Setup Phase 308 Vertex Buffer to 310 Raster Stage 320 Gateway Manager Stage 325 Scoreboard 330 Data Extraction Phase 331 Texture/Atomization Cache Memory 334 Color/Deep Cache Memory 340 Arithmetic Logic Unit (ALU) Stage 350 Arithmetic Logic Unit (ALU) 350-0 350-1 , ALU 350-2 &gt; 350-3 355 Data Write Phase 360 Recycling Path 410 Side Band Information 101822.doc -33- 1297468

412 Effective Shelf 414 Cancel Field 416 Command Field 420 Payload Information 422~ 424 First Set (s, t) Texture Coordinates 426 Air Flow Field 430, 460 Pixel Packet 462 Color Field 464 - 466 Second Set of Textures Coordinate (s, t) 510 pixel packet column 520 group 605 input bus 610 instruction RAM 620 block 630 register (T) 640 path 645 first multiplexer (MUX) stage 650 format conversion module 660 second MUX stage 670 Arithmetic Calculation Unit 680 Clamp 690 Bus 810 Pixel Packet 830 Data Extraction Stage 101822.doc -34- 1297468 850 ALU 855 Data Write Stage 890, 895 Distributor 892 Signal Input 905 Even Pixel Packet Column 910 Chile 1010 ID Packet 1020 Configuration Register 1030 ID Packet Generator 1105 Configurable Test Point Selector 1110 Counter 1120, 1130 Tap/Tap Point R0, R1, R2, R3 Pixel Packet

101822.doc 35-

Claims (1)

\6S Patent Application Range: 1. A graphics processor comprising: a raster stage that receives data about a picture to be rasterized, the t phase of the t generating a plurality of pixels for each pixel to be processed The second parent-pixel packet includes payload information identifying at least the pixel attribute to be processed and having the sideband information associated with the sequence containing at least the instruction to be executed on the image (four) packet; A programmable arithmetic logic unit (ALU) stage for processing the pixel packets, the ALW segment comprising at least one ALU, each alu being programmed to: have-group at least one possible scalar arithmetic operation, the group The scalar arithmetic operation is performed on an incoming pixel packet having a corresponding current instruction; wherein an arithmetic operation sequence is performed on the plurality of pixel packets to perform a graphics processing function. The graphics processor of claim 1, wherein the sideband information includes a cancel field, and each ALU is gated to respond to detecting a cancel bit in the cancel block to reduce the plurality of bits. ALu's power consumption. The graphics processor of claim 2, wherein the at least one ALU responds to the detection of a true value of one of the logical comparisons of the 异, and sets the cancellation bit 0 such as the graphics processor of the request item 1, The form of the arithmetic operation is a*b + c*d, where a, b, e, and d are operands and * is a multiplication operation. The graphics processor of claim 1, wherein the ALU stage is adapted to perform a network function. The image processor of claim 1, wherein the ALU stage performs at least one of an atomization, texture mapping, transparency blending, z-test, or a transparency test. A graphics processor as claimed in claim 1, wherein the raster stage produces at least one pixel packet column for each of the pixels, each column having a plurality of pixel packets transmitted to the ALU phase in a particular clock cycle. The graphics processor of claim 1, further comprising a gateway manager stage having a scoreboard for tracking pixel packets received from the raster phase. 9. The graphics processor of claim 8, further comprising: a data extraction phase for extracting data of the pixel packets; and a data writing phase for performing the process received from the ALU phase One of the pixel data of the processed pixel packet is written to the memory. 10. The graphics processor of claim 9, further comprising: a recirculation path from the data write phase to the gateway manager phase for recycling pixel packets for additional pass through the ALU phase. 11. A graphics processor as claimed in claim 1, wherein information about the pixel packets marked as cancelled in the alu phase is provided to the scoreboard to resolve the cancelled packet pixels. 12. A graphics processor, comprising: at least a stage for converting and setting a top black share of a picture to be rasterized, and a field segment 'receiving information about a picture to be rasterized, the 101822. Doc 1297468 The first gate k# is generated for each pixel of the pattern to be used by a pattern /1, a #m^π, and to the pixel packet column, and the graph operation sequence π j is expressed as a scalar arithmetic one. a gateway manager, comprising: a scoreboard for tracking the processing of the pixel packet; - a data extraction phase 'to extract data for each pixel packet column; a second phase' comprising a plurality of programmable An Arithmetic Logic Unit (ALU) is used to process each ^ ^ ^ ^ ^ ^ ^ ^ ^ , , , , , , 每一 每一 每一 每一 每一 每一 每一 每一 a a a a a a a a a a a a a a a a a a a a a a a a An operand, 至少 至少 至少 来 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行 执行In the attribute register One of the lesser; and the negative material is written to the white white and the memory is used to perform one of the pixel data of the processed pixel packet received from the plurality of copies; wherein the plurality of pixel packets are on the plurality of pixel packets Execution—A sequence of arithmetic operations to perform the graphics processing function. 13. The graphics processor of claim 12, wherein the plurality of ALUs are configured with a - pipe. 14. The graphics processor of claim 12, wherein each of the pixel packets includes payload information identifying at least one pixel attribute to be processed, and each column has at least one of identifying to be performed on each of the pixel packets of the column The associated sideband information of an instruction. 15. The graphics processor of claim 12, further comprising a recirculation path 101822.doc 1297468, the money path for retrieving the pixel packet from the data writer phase to the gateway management, whereby the Then one or two people or more are used to process the pixel packet. 16. The graphics processor of item 12, wherein each is adapted to allow the human body host to select an operation element to be selected from the column and - a constant value and a temporary value At least one, . , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The arithmetic processing in the middle, , and 被 is deactivated in response to (4) to - the pixel packet is marked as cancelled. 18. The graphics processor of claim 12, wherein the scalar arithmetic operation has the form ^ c d, wherein a, b, c &amp; d are operands and * is a multiplication operation. 19. The graphics processor of claim 12, wherein the alu phase is adapted to perform a network function. 20. The graphics processor of claim 12, wherein the ALU stage performs at least one of atomization, texture mapping, transparency blending, :z testing, or a transparency test. 21. The graphics processor of claim 12, wherein the raster stage and the plurality of ALUs are adapted to convert a vector arithmetic operation into a scalar arithmetic operation sequence. 22. A graphics system, comprising: a central processing unit having a graphics software module; a programmable graphics processor receiving vertex information from the graphics software module and for programming the programmable The process of the stage of the graphics processor 101822.doc 1297468 The instructional program 'The programmable graphics processor comprises: 尤树丨自丨, which generates a plurality of pixel seals for each 待I to be processed in response to the An instruction of the graphics software module, each image packet includes identifying at least a "pixel attribute" to be processed: a message: and having an associated sideband identifying at least: an instruction to be executed on each of the pixel packets Information; and a programmable logic unit (ALU) stage comprising a plurality of ALUs configured to process the pixel packets, each alu being assigned by the graphics software module to receive The pixel packet reads the selected operand, performs a scalar arithmetic operation in response to the current instruction to generate a result, and executes the result to update a pixel attribute register and store the result And storing at least one of the temporary values, wherein a scalar arithmetic operation sequence is performed on the plurality of pixel packets to perform a graphics processing function on each of the pixels. 23. The graphics system of claim 22, wherein the sideband information comprises a cancellation field, and each ALU is gated in response to detecting a cancellation bit in the cancellation field to reduce the plural The power consumption of the ALU. 24. The graphics system of claim 22, wherein the arithmetic operation is of the form a*b + c*d, wherein a, b, c, and d are operands and * is a multiplication operation. 25. The graphics system of claim 22, wherein the ALU phase is adapted to perform a network function. 26. The graphics system of claim 22, wherein the ALU stage performs at least one of a fogging operation, a texture mapping, a transparency blending, a z-test, or a transparency test. The graphics system of claim 22, wherein the raster stage generates at least one pixel packet column for each of the pixels, each column having a plurality of pixels transmitted to the ALU phase in a particular clock cycle Packet. 28. The graphics system of claim 22, further comprising a gateway manager stage slave circuit having a scoreboard for tracking pixel packets received from the raster stage. The graphics system of claim 22, further comprising: a data extraction phase for extracting data of the pixel packets; a write phase for performing the process received from the ALU phase A memory write of one of the pixel data of the processed pixel packet; and a recirculation path from the data write phase to the gateway manager phase for recycling pixel packets for additional pass through the ALU phase. 30. The graphics system of claim 29, wherein information regarding pixel packets marked as cancelled in the ALU phase is provided to the scoreboard to resolve the cancelled packet pixels. An embedded processor, comprising: a scratchpad interface for a host to program a scratchpad of a graphics core; a host interface for a host to perform with the graphics core a δ mnemonic interface for the graphics core to read and write data; a programmable graphics processor disposed in the graphics core, the programmable graphics processor comprising: at least one stage , which is used to set and convert the 101822.doc 1297468 vertex of the primitive to be rasterized; a raster phase that receives information about the original image to be rasterized. The raster unit is each pixel to be processed using a graphics operation Generating at least one pixel packet sequence, the graphics operation can be expressed as a purely denier arithmetic operation sequence, each pixel packet includes payload information identifying at least - pixel attributes to be processed, and each column has a signature identifying each of the columns - associated information of at least one instruction executed on the pixel packet; ❿ - a closed channel manager comprising - a scoreboard for tracking the processing of the pixel packet - a data extraction phase for extracting data for each pixel packet column; '- ALU phase, which includes a plurality of programmable arithmetic logic units (then) for processing each of the pixel packet columns, each receiving An input pixel packet column and output an output pixel packet column, each ALU I: = = prime packet column reads at least - an operation element, using the to perform - scalar arithmetic and execution of the result is written to a 守 守 守 守 及 及 及 及 及 及 及 及 及 及 及 及 及 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守Sealing in the plurality of pixel seals: one memory write; performing the graphics processing function:, executing an arithmetic operation sequence on the block 32. The embedded process w of claim 31, wherein the plurality of ALU systems Configured in a 101822.doc 1297468 pipeline. 33. = embedded processor of claim 31, with an ingress-recirculation path. The % path is used for the data write phase to the gateway management. = stage recycling pixel packet The pixel packet can be processed by using the stage-times or more. 34. The embedded processor of claim 31, wherein each - is configurable to allow the selected from the column + β i and - often At least one of a value and a temporary value. 35. The embedded process 11 of item 31, wherein at least the stage is configured to cancel the condition and mark the pixel packet as cancelled (one is cancelled). In response to detecting that a pixel packet is marked as A, as in the case of request item 31, it enters the processor, and then executes the -3 centrally-sized application to operate the graphics core. /, the middle 4 graphics core and the central 37 - a type of graphics processing on a pixel:: two - on the wafer. For at least one of the pixels to be executed on a pixel: ^' contains: a 'scaling arithmetic operation performed on the pixel packet 2 = actual knowledge = in a graphics function; ^ only knowing that at least a plurality of pixel packets are generated for the pixel, Each image: one of the scalar arithmetic operation sequences to be treated as an operand:: genus =, the plurality of pixel packets have - the phase of the sinusin at least - the arithmetic logic single 7 sequence, the operand; W from 4 money The prime packet reads 10l822.doc 1297468. In the δ hai at least _ A Τ τ γ » 瞀, ALU, the scalar arithmetic operation sequence is executed according to the instruction sequence, and the scalar arithmetic operation sequence is used to implement the at least one graphics function. %, the method of item 37, further comprising: determining that a pixel does not require further processing; assigning a cancel state to at least one pixel packet; and using each subsequent one encountered by the at least one pixel packet Arithmetic calculations in the ALU to save power. ^A method of clause 37, wherein the graphics function includes a texture combination, ^ &amp;'then&quot;, a transparency blend, a transparency test, or an atomization At least one of the following. 40. If the request item 37*, the method 'where the scalar arithmetic operation is of the form a*b + c , where a, b, c, and d are operands and * is a multiplication operation. A method for performing a graphics processing operation on a pixel, comprising: a graphics, a power consumption, and a scalar arithmetic operation sequence performed on a pixel and a cymbal to perform on the pixel a graphics function; generating at least one pixel of the pixel to be processed in the continuous clock cycle 'per-pixel packet (four) at least one of the subset of pixel attributes to be processed as an operand in the scalar arithmetic operation sequence a shelf, the at least one column having an associated sequence of instructions; in each of the plurality of arithmetic logic units (ALUs), the read operand 'at least one of the operands corresponds to a self-styled packet The operand read by one of the pixel packets; ', in each ALU, according to the sequence of instructions assigned to the ship 101822.doc 1297468 42. 43. 44. 45. 46. 47. 48. 49. A scalar arithmetic calculation is performed on το to perform the scalar arithmetic operation sequence for performing the graphics function. The method of claim 41, wherein each of the ALUs performs at least one of: updating a pixel packet using a result of the scalar arithmetic operation; and storing a result of the scalar arithmetic operation to It is used as an operand in one of the arithmetic operations performed in the later clock cycle. The method of claim 41, further comprising: identifying a pixel that does not require further processing, and in response, marking at least one pixel packet of the pixel as canceled; and j in each ALU, deactivating has been marked as being Cancel the arithmetic of the pixel packet of the pixel s. The method of claim 43 wherein the identification is performed in the data extraction phase. The method of item 43, wherein the identification is in a data writing stage =: 41, which further comprises: assigning the one to be read, 5, #彳#彳彳之-corresponding scalar This is the same as the current instruction. As a result of the method of item 41, the pot pushes a cow. ‘, ^匕3: Extracting the Pixel Packets As in the method of claim 41, the improvement includes: pixel data that is processed by the graphics table t. (4) The power month b is written as in the method of claim 41, and the increment is referred to as a flute-old 匕3. In the 4ALU, 7 is used for the first process and the dan is followed by the %-processed pixel 101822.doc 1297468 Packet. The method of [00], wherein the method further comprises the step of performing the first graphics function on the 2-pixel packet column and the second graphics 1 wherein the one-group ALU is on the --group pixel packet The first type of graphics function is performed, and the second group of ALUs are executed on the second packet - the second type of the TM function. , 51. A method of performing a graphics processing operation, comprising: formulating a plurality of arithmetic logic units (then), taking a selected operation 自 from a pixel-packet column, and performing a selected scalar arithmetic operation in response to - a selected current instruction associated with the pixel packet column; for at least a graphics operation to be performed on the pixel, identifying at least one corresponding scalar arithmetic operation/pair to be performed on the sub-group of the pixel The pixel generates a column of pixel packets, the per-pixel packet including at least one attribute associated with the pixel to be processed as at least one operand = the block 'the pixel packet has — indicating the sufficiency arithmetic to be executed The associated instruction of the different sequence; in the ALU, the selected operations are read in the pixel packet column and the selected scalar arithmetic operation corresponding to the associated current instruction is executed. 52. The method of claim 51, further comprising: stylizing a data extraction phase to extract data from the pixel packet. 101822.doc -11 - 1297468 3 The method of claim 51, which further comprises: stylizing the raster phase = mapping the graphics operation to - pixel packet assignment and - associated instructions. 54. The method of item 51, wherein the method further comprises: stylizing at least one, 屯 比 乂 乂 test and if the pixel packet compares the scalar quantity: if the test fails, marking the pixel packet as got canceled. A method for performing a graphics processing operation on a pixel, A comprising: • performing at least one graphics function to be performed on a pixel, and identifying a scalar arithmetic operation 1 executable on a 1-bit packet to implement the at least one graphics The pixel of the second processing generates at least a pixel packet column, and each pixel packet includes a per-blocker for the sub-transportant attribute to be processed as an operand 'the at least-column has an associated instruction Sequence; in each of = a number of arithmetic logic units (ALUs), reading the assigned 2' of at least one of the operands corresponding to - reading from one of the pixel packets in a column of pixel packets Arithmetic: - In the ALU, a scalar arithmetic calculation is performed on the assigned operations 7C according to the sequence of instructions; the selected pure for the result of a need-in the range [[,1] Measure: s two irS1.8 format to format the corresponding operand of the pixel packet, : the formula corresponds to the base-base 2 representation of the [-2, +2] range of operators with -8-bit fractional components, and The selected scalar arithmetic operation is clamped to the [0, 1] range; At least - Other scalar arithmetic operation to - different data formats 101822.doc -12- 1297468 corresponds to the pixel format of the packet. 56. The method of claim 55, wherein the result of the at least one-ton 曰~ is less than one μ in the range of [0, 1], and the nasal operation is in the (4) S1.8 format. a calculation. 57. The method of claim 56, and in the middle of the eighth, the other scalar arithmetic operation is an operation on the texture represented by a format different from S1.8. 58. For example, the method of claim 57, the rainy solid of the Gansian* 〃 mother-in-one pixel packet has a fixed bit size for the pixel packet _ u ^ pixel packet including high precision (s, t ),, Wen Li Bei Yu, and the color of the material. The cut pixel packet includes at least two color components 59. - a method of performing a graphics processing operation on the pixel, . = one of the color components of a pixel is performed: the second power - the identification of a younger - scalar The sequence of arithmetic operations is implemented to perform the first-graph function, which requires a scalar arithmetic operation to result in the range of [〇, 1]; ^ for the texture to be associated with a pixel, (1) another second graphic function 'recognition-second scalar arithmetic operation sequence to implement the first function; / or pixel to generate at least one pixel packet column, each pixel block having a fixed length of at least one of the service elements The meta size 'and includes = at least _ rotten bits of one of the sub-pixel attributes of the operand, the at least one column having an associated sequence of instructions; for each child associated with the first graphical function 11 S1.8 The format is to encapsulate at least two color components, and the S1.8 type is slanted in a 1 豕 Beijing packet, and is operated in a range of [-2, +2] of 101822.doc -13 - 1297468 - 8 bit fractional components. One base of the yuan 2 is not; Each pixel packet associated with the second graphics function encapsulates a single high-precision texture requiring more than 8 bits; in each of a plurality of arithmetic logic units (ALUs), the assigned operand is read, and Performing a scalar arithmetic calculation on the assigned operands according to the sequence of instructions; wherein for the first graphics function, the color component is selected in the 818 format as an operand, and a result is processed to the [ 0, 丨] range, and for the second graphics function, the texture is selected as an operand in a format having an accuracy greater than 8 bits. 60. A graphics processor, comprising: at least a stage, which is used to set and convert a pedestal of the image to be rasterized to receive information about the original image of the image to be rasterized. Each pixel of the processing generates at least one image (four) packet sequence, and the material-object material counts the recordable operation sequence; a gateway manager, 1_, includes a scoreboard for tracking the processing of the pixel packet, _ batting extraction stage, which is used to extract the data of each pixel packet column; (ALU^^ into the pixel sealing spoon, processing the parent one of the pixel packet column, each ALU receives an input... 匕列亚轮出-output pixel The packet column, each ALU receives the image 44 44 u + from the - 101822.doc -14 - 1297468, reads the at least one operand, and uses the at least one operand to execute the thousand _ # e - Purely setting the nose operation, generating a result, and executing the write to a temporary value or using the result to update at least one of the output column - the pixel packet; and the bedding write phase, Used to perform the reception from the plurality of ALUs, The pixel data of the processed pixel packet is a memory write; wherein an arithmetic operation sequence is performed on the plurality of pixel packets to perform the graphic processing function; and the second black raster ρ white segment is in a S8 format a type of scalar arithmetic operation pixel packet, the S 8 format corresponding to a base 2 of the operand having one of the bins, and a parent-ALU Processing the first type of scalar operation, which clamps a result within the range of [〇, 1]; the second pair of scalar arithmetic operations requiring a precision greater than 8 bits for the raster stage Formatting the pixel packet. 6^• The graphics processor of claim 60, wherein the singular type of the _ type has corresponded to the - operation on the -color component, and at least two color components are included: In the pixel sealing spoon generated by the scalar operation, and the scalar operation of the second type corresponds to the operation, the operation has: a size larger than one half of the size of the pixel packet; 62. The graphics processor of claim 60 corresponds to a pattern One of the operations 63. The graphics processor of claim 62, wherein the second type of scalar operation wherein each-pixel packet has - 101822.doc -15 - I297468 at least 20 bits in size, one, ,, The attribute is at least 16 bits and has an associated 4-bit fineness, and each _si wipes the element, so that each of the images can contain two Sh8 operands in the packet. = type operation 'and may include a set of texture attributes for the operation of the pixel in each pixel packet for use in the second type of graphics processor, which includes ··, -raster Stage 'which receives data about the original to be rasterized, the =gate phase generates a plurality of pixel packets for each pixel to be processed, and each prime packet includes a payload identifying at least the pixel attribute to be processed ^ ' Sensing associated sideband information for at least one instruction executed on each of the pixel packets; a programmable arithmetic logic unit (ALU) stage for processing the pixel packets, the ALU stage including a plurality of ALUs , each A Lu has one, and at least, a possible arithmetic operation, and the unique arithmetic operation system _ has an incoming pixel packet corresponding to the current imperative command to execute; a data extraction phase for extracting data of the pixel packet a stuffing stage for performing memory writing of one of pixel data of the processed pixel packets received from the ALU stage; the first tooling's face to the ALU stage, the data extraction stage and The data is written into the individual inputs of the phase; and the distributor is integrated into the ALU phase, the data extraction phase and the individual output of the data writing phase; the first dispenser and the second dispenser are adapted Reconfigure the pixel 101822.doc. -16 - 1297468 The process of processing the data extraction phase, the ALU phase, and the ALU write phase in response to a command from a host. 65. The graphics processor of claim 64, wherein the first allocator and the second allocator are adapted to allow at least a portion of the graphics processor to be bypassed in response to a software command. 66. The graphics processor of claim 65, wherein the first allocator and the second allocator are adapted to allow the data extraction phase to be bypassed in response to a software command. 67. The graphics processor of claim 64, wherein the first allocator and the second allocator are spliced to each of the ALU stages - to allow an ALU execution order to be assigned in response to a software command. 68. The graphics processor of claim 64, wherein the graphics processor is adapted to allow reconfiguration of the processing flow to have a data extraction after a scalar arithmetic operation. 69. The graphics processor of claim 64, wherein the graphics processor is adapted to allow the host to reconfigure the processing flow to have a data fetch prior to a scalar arithmetic operation. 70. A method for operating a graphics pipeline, the graphics pipeline having a rasterizer eight for generating a pixel packet; a data extraction phase for extracting data of the pixel packet; and an ALU phase having at least one alu For performing a scalar arithmetic operation on a pixel packet; a data writing phase for writing pixel data; and a distributor coupled to the data extraction phase, the data writing phase, and the ALU phase; The method includes: responding to the first command, stylizing the allocators to define a pixel packet via 101822.doc -17- 1297468, the first processing flow by the data extraction phase, the ALU phase, and the data writing phase; and the response a second command 'programming the allocators to define a pixel packet via the data extraction phase, the ALU phase, and the second phase of the data writing phase; wherein the software host can have any of a plurality of processing flows To configure the pipeline. The method of claim 70, wherein the first processing flow includes the data extraction, the ALU phase, and the data writing phase, and the second processing flow bypasses the data extraction phase. The method of claim 7, wherein the first processing flow includes a first execution order of the one of the alus, and the second processing flow includes a second execution order of the ALUs. 73. The method of claim 7, wherein the first processing flow comprises data extraction prior to a scalar arithmetic operation, and the second processing flow includes a data extraction subsequent to a scalar arithmetic operation. 74. A method of operating a graphics pipeline, the graphics pipeline having: a rasterizer for generating a pixel packet; a data extraction phase for extracting data of the pixel packet; and an ALU phase having at least one ALU For performing a quantization arithmetic operation on a pixel packet; a data writing phase for writing pixel data; and a distributor coupled to the data extraction phase, the data writing phase, and the ALU phase; The method includes: receiving a command from a software host to reconfigure the pipeline from the pixel packet via the data extraction phase, the ALU phase, and the data writing phase 101822.doc -18- 1297468 Up to the second processing flow of the pixel packet via the data extraction phase, the ALU phase, and the data writing phase; and adjusting the distributors to reconfigure the pipeline from the first processing flow to the second processing Process. 75. The method of claim 74, wherein the first processing flow includes the data extraction phase, the ALU phase, and the data writing phase, and the second processing flow bypasses the data extraction phase. The method of claim 74, wherein the first processing flow includes a first execution order of the ones of the mus, and the second processing flow includes a second execution order of the ALUs. 77.:: method of claim 74 wherein the first processing flow includes data extraction prior to a scalar = operation, and the processing flow includes a data extraction after a purely different operation. 78. A graphics processor, comprising: a plurality of components for processing a pixel packet; a sub-distributor that engages to an individual input of the plurality of components, and a second distributor that is coupled to the plurality of components Individual outputs of the components; the first distributor and the adapter are adapted to reconfigure the pixel packets via the plurality of components - in response to the process - from;; host commands. 79: request item 78 a graphics processor, wherein the components are in stages. 80. - Operation - a method of graphics pipelines. The graphics pipeline has a graphics pipeline having a plurality of components for processing pixel packets, the method comprising 101822.doc • 19 - 1297468 The mouth should be command-command, stylized into one of the plurality of components, ♦. 疋 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素= allocator to define a pixel packet, one of the software hosts can borrow the I state of the pipeline. The method of grouping any of several processing flows 'these components are staged. A method of performing a graphics processing operation, comprising: sounding a scalar arithmetic operation to be performed on a plurality of pixel 封3 prime packets == this function, identifying an image function; π sequence, to implement the graphics to pixel Assigned as an even pixel or an odd pixel; generating at least two pixels for the pixel, including for processing in the scalar arithmetic operation bank w J 'mother one pixel packet-early feng s column to be processed as an arithmetic element At least-blocking of pixel attributes, such at least two columns having an associated sequence of instructions and _ using 4 /, • ... for the pixel packet is used for - odd pixels and for identification of an even pixel a packet sequence that is interleaved in a group of pixel packets, where each column of the group is processed in the pixel period of the prime and odd pixels; the bottom is used for a plurality of arithmetic logic units in the continuous clock PALU phase (in the case of each), for a current clock cycle to receive a pixel packet column 'and the instruction sequence is from the pixel packet column 乂 Kangkouhai line a scalar arithmetic calculation; M (10) at least one operation element on the 101822 .doc -20- 1297468 wherein the processing of pixel packets is interleaved in the ALUs. 83. As before request item 82, the pixel is packed between columns. The method, wherein a pixel packet column requires a result from the first, and the interlace is selected to resolve the ALU wait time 84. The method of claim 82, further comprising: storing both the even pixel and the odd pixel in each of the methods A shared group constant value. 85. The method of claim 82, further comprising: storing in each (10). One of the first set of temporary values and one of the even pixels of the second set of temporary values. 6. The method of claim 85, further comprising: using the identifier to select a (four)-set temporary value for the pixel block of the pixel and select the second set of temporary values for the image of the odd pixel. 87. As in the method of claim 85, j: push half a spoonful of people • suppress _, enter 乂匕έ • store the temporary values for a sufficient period of time to simulate a constant register. 88. One of the identifiers executed in the component of the configurable graphics pipeline: the method of writing the device 'The configurable graphics pipeline has pixel packets = components of the graphics pipeline - more than one possible processing flow, The method comprises: receiving, by a location, a data packet of the component that triggers the graphics pipeline is used for an identifier of the component in the processing flow; and entering a software indicating the processing flow A command is generated to generate an identifier that triggers the relative position of each of the components to be written in a configuration register. The method of claim 88, wherein the data packet of the first component is responded to. 101822.doc -21- I297468 9〇.: The method of claim 88, wherein the data packet is injected into the pipeline at a position of one of the components requiring configuration information, (1) consulting 4 A 八甲转组State:: The mother-continuous component reads an identifier in the data packet—the current value, writes the current value to its configured temporary storage effect, and 1 increments the identification payment. The next element of the data flow that increments the identifier. L. The method of claim 88, wherein the elements comprise a different logic unit for processing the packet. And a graphics processor comprising a raster stage that receives data about a picture to be rasterized, the raster stage generating a plurality of pixel packets for each pixel to be processed, each pixel packet including identification At least - payload information of the pixel attribute to be processed, and having associated sideband information identifying at least one instruction to be executed on each of the pixel packets; a programmable arithmetic logic unit (ALU) stage, In processing the pixel packets, the ALU stage includes a plurality of ALUs, each ALU having a set of at least one possible arithmetic operation performed on an incoming pixel packet having a corresponding current imperative command a data extraction phase for extracting data of the pixel packets; a data writing phase for performing memory writing of one of pixel data of the processed pixel packets received from the ALU phase; a first distributor coupled to the segment, the data extraction phase and the individual input of the data writing phase; and a second dispenser, Coupling to the ALU stage 'the data extraction stage I0l822.doc -22- 1297468 and the individual output of the data writing stage; 5 Hai's knife and the brother * a distribution benefit is adapted into a re-grouping pixel packet via the Processing flow from the data extraction phase, the ALU phase, and the ALU write phase in response to a command from a host; wherein each ALU of the ALU phase is adapted to receive an identification initiated by a software identification code The packet, each ALU writes the current value of one of the identifiers of one of the identification packets into a configuration register, increments the identifier, and forwards the identification packet to the next ALU. _93. A graphics processor comprising: a graphics pipeline having a set of tap points associated with elements of the graphics pipeline; a configurable test point selector receiving the same from a software host The testable point selector is adapted to monitor a sub-assembly joint point selected by a software command and to associate at least each of the sub-joint points associated with the sub-assembly joint point A condition to count the statistic·, φ where the statistics of a sub-component joint point are collected for the software host. 94. The graphics processor of claim 93, wherein the graphics pipeline includes an arithmetic logic unit (ALU) chain for processing pixel packets. 95. The graphics processor of claim 94, wherein the subcomponent joint points are comprised of two tap points associated with successive elements in the graphics pipeline. 96. The graphics processor of claim 95, wherein an indication of the payload data, a valid signal flowing from a first component to a second component, and a determination of whether the second component is capable of receiving the payload data The ready signal 10l822.doc -23 - 1297468 and l regard these two tap points. For example, the graphics processor of % seeking 96, wherein a transition state is counted for each clock cycle when a valid condition and a precondition are detected, and each of the detection, 丨, and a ready condition is used. One clock cycle counts a wait state. ▲: The graphics processor of claim 94, wherein the transition state and a wait state are monitored at each of two selected tap points associated with the alu. The graphics processor of claim 98, wherein the transition state corresponds to a downstream ALU in a-ready state and an upstream ALU in an active state. Dan further includes 1〇〇. The graphics processor host of claim 93 to enable the statistics collection of the trace record register ν 101 · If the request item 93 is a graphic imaginary crying sorrow ^ the heart is processed, wherein the group can be The test point selector includes at least one counter. 102. A method of monitoring a graphics processor, comprising: 2: receiving a command with two test points capable of transmitting a payload to a second component of the second component; a test point; and a statistic for collecting at least two conditions associated with the first element and the parent. The first condition is - for the first element, the component two: the loaded valid signal 'and the second condition is - for the heart of the piece to indicate that the second element is ready to receive a payload 101822. Doc -24- 1297468 The signal number. 104. The method of claim 103, wherein a clock state is counted for each clock cycle in which a valid signal and a ready signal are present, and a clock cycle is counted for each valid signal but no ready signal is present. Bear. 105. The method of claim 102, wherein the collection of statistics is performed by preselecting an operational mode for one of the graphics processors. As in the method of claim 1 () 2, the further step includes: receiving - a command to enable statistics collection for the two test points. The method in which one of the graphics processors is selected to collect the statistic associated with the graphics operation, and the statistic collection statistic is enabled. 108. If the party to claim 1〇2 is the software host that enables the collection of statistics in response to a value of one of the trace record registers. 101822.doc -25-