TWI747405B - Pixel circuit and driving method thereof - Google Patents
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
Description
本發明是有關於一種顯示裝置,且特別是有關於一種畫素電路及其驅動方法。The present invention relates to a display device, and particularly relates to a pixel circuit and a driving method thereof.
在顯示裝置中,當製程發生變異時,畫素電路中的驅動電晶體的臨界電壓(Threshold Voltage)往往容易發生漂移的現象,使得流經發光元件的電流產生非預期的變化,進而造成顯示面板的發光亮度不穩定,以影響顯示畫面的品質。In a display device, when the manufacturing process changes, the threshold voltage of the driving transistor in the pixel circuit is often prone to drift, causing unexpected changes in the current flowing through the light-emitting element, which in turn causes the display panel The brightness of the light is unstable to affect the quality of the display picture.
針對驅動電晶體的臨界電壓的補償技術,習知的畫素電路通常會是在閘極驅動信號為致能狀態的期間,開始對驅動電晶體的臨界電壓進行補償動作。然而,由於在顯示裝置操作於高解析度(或高頻率)時,閘極驅動信號的致能時間相當有限,導致補償畫素電路的臨界電壓的補償時間過短,進而使得畫素電路的補償效果無法達到最佳化。因此,如何改善臨界電壓對於顯示畫面的品質影響,將是本領域相關技術人員重要的課題。Regarding the compensation technology of the threshold voltage of the driving transistor, the conventional pixel circuit usually starts to compensate the threshold voltage of the driving transistor during the period when the gate driving signal is in the enabled state. However, when the display device is operating at a high resolution (or high frequency), the enable time of the gate drive signal is quite limited, resulting in the compensation time of the threshold voltage of the pixel circuit being too short, which in turn makes the pixel circuit compensation The effect cannot be optimized. Therefore, how to improve the impact of the threshold voltage on the quality of the display image will be an important issue for those skilled in the art.
本發明提供一種畫素電路及其驅動方法,能夠透過調整補償控制信號的致能時間,以增加對於驅動電晶體的臨界電壓的補償時間,藉以有效地提升顯示畫面的品質。The present invention provides a pixel circuit and a driving method thereof, which can increase the compensation time for the threshold voltage of the driving transistor by adjusting the enable time of the compensation control signal, thereby effectively improving the quality of the display picture.
本發明的畫素電路包括驅動電晶體、初始化電路、資料寫入電路、電壓補償電路、發光元件以及第一發光控制電路。驅動電晶體具有驅動端以及耦接至第一系統電壓的第一端。初始化電路耦接至輸入端以及驅動端,依據前級閘極驅動信號以調整輸入端以及驅動端的電壓準位。資料寫入電路耦接至輸入端,依據閘極驅動信號以提供資料電壓至輸入端。電壓補償電路耦接至輸入端以及驅動端,依據補償控制信號以調整驅動端的電壓準位。發光元件具有陰極端以及耦接至第二系統電壓的陽極端。第一發光控制電路耦接至發光元件的陰極端、電壓補償電路以及驅動電晶體的第二端,依據發光控制信號以控制發光元件的發光狀態,其中補償控制信號的致能時間介於前級閘極驅動信號的下降沿以及閘極驅動信號的上升沿之間。The pixel circuit of the present invention includes a driving transistor, an initialization circuit, a data writing circuit, a voltage compensation circuit, a light-emitting element, and a first light-emitting control circuit. The driving transistor has a driving terminal and a first terminal coupled to the first system voltage. The initialization circuit is coupled to the input terminal and the drive terminal, and adjusts the voltage levels of the input terminal and the drive terminal according to the previous gate drive signal. The data writing circuit is coupled to the input terminal, and provides a data voltage to the input terminal according to the gate drive signal. The voltage compensation circuit is coupled to the input terminal and the driving terminal, and adjusts the voltage level of the driving terminal according to the compensation control signal. The light-emitting element has a cathode terminal and an anode terminal coupled to the second system voltage. The first light-emitting control circuit is coupled to the cathode end of the light-emitting element, the voltage compensation circuit, and the second end of the driving transistor, and controls the light-emitting state of the light-emitting element according to the light-emitting control signal, wherein the activation time of the compensation control signal is in the previous stage Between the falling edge of the gate drive signal and the rising edge of the gate drive signal.
本發明的畫素電路的驅動方法,包括:提供具有驅動端、第一端以及第二端的驅動電晶體;提供初始化電路以依據前級閘極驅動信號來調整輸入端以及驅動端的電壓準位;提供資料寫入電路以依據閘極驅動信號來提供資料電壓至輸入端;提供電壓補償電路以依據補償控制信號來調整驅動端的電壓準位;提供具有陰極端以及陽極端的發光元件;以及提供第一發光控制電路以依據發光控制信號來控制發光元件的發光狀態,其中補償控制信號的致能時間介於前級閘極驅動信號的下降沿以及閘極驅動信號的上升沿之間。The driving method of the pixel circuit of the present invention includes: providing a driving transistor having a driving end, a first end, and a second end; providing an initialization circuit to adjust the voltage levels of the input end and the driving end according to the previous gate driving signal; Provide a data writing circuit to provide a data voltage to the input terminal according to the gate drive signal; provide a voltage compensation circuit to adjust the voltage level of the drive terminal according to the compensation control signal; provide a light-emitting element with a cathode terminal and an anode terminal; and provide a A light emitting control circuit controls the light emitting state of the light emitting element according to the light emitting control signal, wherein the enable time of the compensation control signal is between the falling edge of the previous gate drive signal and the rising edge of the gate drive signal.
本發明的畫素電路包括驅動電晶體、初始化電路、資料寫入電路、電壓補償電路、發光元件以及發光控制電路。驅動電晶體具有驅動端以及耦接至第一系統電壓的第一端。初始化電路耦接至輸入端以及驅動端,用以基於參考電壓,並依據閘極驅動信號以及前級閘極驅動信號以調整輸入端以及驅動端的電壓準位。資料寫入電路耦接至輸入端,依據閘極驅動信號以提供資料電壓至輸入端。電壓補償電路耦接至初始化電路,電壓補償電路用以於補償階段依據閘極驅動信號以及前級閘極驅動信號以調整驅動端的電壓準位。發光元件具有陰極端以及耦接至第二系統電壓的陽極端。發光控制電路耦接至發光元件的陰極端、電壓補償電路以及驅動電晶體的第二端,依據控制信號以控制發光元件的發光狀態,其中補償階段介於前級閘極驅動信號的下降沿以及閘極驅動信號的上升沿之間。The pixel circuit of the present invention includes a driving transistor, an initialization circuit, a data writing circuit, a voltage compensation circuit, a light-emitting element, and a light-emitting control circuit. The driving transistor has a driving terminal and a first terminal coupled to the first system voltage. The initialization circuit is coupled to the input terminal and the driving terminal for adjusting the voltage levels of the input terminal and the driving terminal based on the reference voltage and the gate driving signal and the previous gate driving signal. The data writing circuit is coupled to the input terminal, and provides a data voltage to the input terminal according to the gate drive signal. The voltage compensation circuit is coupled to the initialization circuit, and the voltage compensation circuit is used for adjusting the voltage level of the driving terminal according to the gate driving signal and the previous gate driving signal in the compensation stage. The light-emitting element has a cathode terminal and an anode terminal coupled to the second system voltage. The light-emitting control circuit is coupled to the cathode terminal of the light-emitting element, the voltage compensation circuit, and the second terminal of the driving transistor, and controls the light-emitting state of the light-emitting element according to the control signal. The compensation phase is between the falling edge of the previous gate drive signal and Between the rising edges of the gate drive signal.
本發明的畫素電路的驅動方法,包括:提供具有驅動端、第一端以及第二端的驅動電晶體;提供初始化電路以基於參考電壓,並依據閘極驅動信號以及前級閘極驅動信號以調整輸入端以及驅動端的電壓準位;提供資料寫入電路以依據閘極驅動信號來提供資料電壓至輸入端;提供電壓補償電路以於補償階段依據閘極驅動信號以及前級閘極驅動信號來調整驅動端的電壓準位;提供具有陰極端以及陽極端的發光元件;以及提供發光控制電路以依據控制信號來控制發光元件的發光狀態,其中補償階段介於前級閘極驅動信號的下降沿以及閘極驅動信號的上升沿之間。The driving method of the pixel circuit of the present invention includes: providing a driving transistor having a driving terminal, a first terminal, and a second terminal; Adjust the voltage levels of the input terminal and the drive terminal; provide a data writing circuit to provide the data voltage to the input terminal according to the gate drive signal; provide a voltage compensation circuit to according to the gate drive signal and the previous gate drive signal in the compensation stage Adjust the voltage level of the driving terminal; provide a light-emitting element with a cathode terminal and an anode terminal; and provide a light-emitting control circuit to control the light-emitting state of the light-emitting element according to the control signal, wherein the compensation phase is between the falling edge of the previous gate drive signal and Between the rising edges of the gate drive signal.
基於上述,本發明諸實施例所述畫素電路可透過將補償控制信號的致能時間設定為介於前級閘極驅動信號的下降沿至閘極驅動信號的上升沿之間,以作為對於補償驅動電晶體的臨界電壓的補償時間。如此一來,相較於習知的畫素電路僅能夠在有限的閘極驅動信號的致能期間中對驅動電晶體的臨界電壓進行補償動作,本發明的畫素電路則可透過拉長補償控制信號的致能時間,以增加對於驅動電晶體的臨界電壓的補償時間,並藉以有效地提升顯示畫面的品質。Based on the above, the pixel circuits of the embodiments of the present invention can set the enable time of the compensation control signal to be between the falling edge of the previous-stage gate drive signal and the rising edge of the gate drive signal as a countermeasure. Compensation time for compensating the critical voltage of driving transistor. In this way, compared to the conventional pixel circuit which can only compensate for the threshold voltage of the driving transistor during the limited enable period of the gate drive signal, the pixel circuit of the present invention can compensate by lengthening The enabling time of the control signal is used to increase the compensation time for the threshold voltage of the driving transistor, thereby effectively improving the quality of the display image.
在本案說明書全文(包括申請專利範圍)中所使用的「耦接(或連接)」一詞可指任何直接或間接的連接手段。舉例而言,若文中描述第一裝置耦接(或連接)於第二裝置,則應該被解釋成該第一裝置可以直接連接於該第二裝置,或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。另外,凡可能之處,在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。The term "coupling (or connection)" used in the full text of the specification of this case (including the scope of the patent application) can refer to any direct or indirect connection means. For example, if the text describes that the first device is coupled (or connected) to the second device, it should be interpreted as that the first device can be directly connected to the second device, or the first device can be connected through other devices or some This kind of connection means is indirectly connected to the second device. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terms in different embodiments may refer to related descriptions.
圖1是依照本發明一實施例的畫素電路100的示意圖。請參照圖1,畫素電路100包括驅動電晶體TD、初始化電路110、電壓補償電路120、資料寫入電路130、發光控制電路140以及發光元件EL。發光元件EL的陽極端耦接至系統電壓VDD,發光元件EL的陰極端耦接至發光控制電路140。發光元件EL可以依據導通電流ID來對應的被點亮。其中,本實施例的發光元件EL可以例如是有機發光二極體(Organic Light Emitting Diode,OLED)、發光二極體(LED)或其他發光元件,本發明並未特別限制。FIG. 1 is a schematic diagram of a
驅動電晶體TD的第一端(亦即,源極端)耦接至系統電壓VSS,驅動電晶體TD的第二端(亦即,汲極端)耦接至發光控制電路140,驅動電晶體TD的驅動端PD(亦即,閘極端)耦接至電壓補償電路120。其中,本實施例的系統電壓VDD可以為系統高電壓,而系統電壓VSS可以為系統低電壓,並且系統電壓VDD的電壓值可以大於系統電壓VSS的電壓值。The first terminal (that is, the source terminal) of the driving transistor TD is coupled to the system voltage VSS, and the second terminal (that is, the drain terminal) of the driving transistor TD is coupled to the light-
初始化電路110耦接至輸入端PIN以及驅動端PD。初始化電路110可用以依據前級閘極驅動信號SN-m以調整輸入端PN以及驅動端PD的電壓準位。電壓補償電路120耦接至輸入端PIN以及驅動端PD。電壓補償電路120可依據輸入端PIN上的電壓以及/或補償控制信號RN以調整驅動端PD的電壓準位。The
另一方面,資料寫入電路130耦接至輸入端PIN。資料寫入電路130可用以依據閘極驅動信號SN以提供資料電壓VDATA至輸入端PIN。發光控制電路140耦接至發光元件EL的陰極端、電壓補償電路120以及驅動電晶體TD的第二端。發光控制電路140可依據發光控制信號EM以控制發光元件EL的發光狀態。On the other hand, the
特別一提的是,在本實施例中,閘極驅動信號SN、前級閘極驅動信號SN-m、補償控制信號RN以及發光控制信號EM可以是由控制信號產生器(未繪示)所產生。其中,所述控制信號產生器(未繪示)可以是由三組陣列上閘極驅動(Gate-Driver-on-Array, GOA)電路來進行建構。換言之,由於本實施例可以僅透過三組GOA電路來控制畫素電路100,因此能夠有效地節省整體的面積。In particular, in this embodiment, the gate drive signal SN, the previous gate drive signal SN-m, the compensation control signal RN, and the light emission control signal EM can be generated by a control signal generator (not shown). produce. Wherein, the control signal generator (not shown) can be constructed by three groups of gate-driver-on-array (Gate-Driver-on-Array, GOA) circuits. In other words, since this embodiment can control the
除此之外,在本實施例中,閘極驅動信號SN可以為GOA電路(未繪示)所產生的第N級閘極驅動信號,而前級閘極驅動信號SN-m可以為GOA電路(未繪示)所產生的第N-m級閘極驅動信號。其中,上述的N以及m可為大於1的正整數,並且可依照畫素電路100的設計需求來決定,本發明並未特別限制。In addition, in this embodiment, the gate drive signal SN may be an Nth stage gate drive signal generated by a GOA circuit (not shown), and the previous stage gate drive signal SN-m may be a GOA circuit (Not shown) The generated Nm-th gate drive signal. Wherein, the aforementioned N and m can be positive integers greater than 1, and can be determined according to the design requirements of the
針對畫素電路100的操作動作,具體來說,當畫素電路100操作於一畫素期間的補償階段時,電壓補償電路120可以依據輸入端PIN上的電壓以及/或被拉高的補償控制信號RN來調整驅動電晶體TD的驅動端PD的電壓準位,藉以對驅動電晶體TD的臨界電壓進行補償動作。Regarding the operation of the
值得一提的是,畫素電路100可以透過調整前級閘極驅動信號SN-m以及補償控制信號RN來提升驅動電晶體TD的臨界電壓的補償效果。舉例來說,在本實施例中,電壓補償電路120所接收的補償控制信號RN的致能時間可以被設定為介於前級閘極驅動信號SN-m的下降沿以及閘極驅動信號SN的上升沿之間。It is worth mentioning that the
進一步來說,畫素電路100可以在前級閘極驅動信號SN-m(亦即,第N-m級閘極驅動信號)從致能狀態轉換為禁能狀態(例如是從高電壓準位轉換為低電壓準位)之後,接續將補償控制信號RN設定為致能狀態(例如是高電壓準位),直到閘極驅動信號SN(亦即,第N級閘極驅動信號)欲從禁能狀態轉換為致能狀態(例如是從低電壓準位轉換為高電壓準位)為止。Furthermore, the
也就是說,本實施例可以將前級閘極驅動信號SN-m的下降沿至閘極驅動信號SN的上升沿之間的時間區間,作為對於補償驅動電晶體TD的臨界電壓的補償時間。因此,相較於習知的畫素電路僅能夠在有限的閘極驅動信號的致能期間中對驅動電晶體的臨界電壓進行補償動作,本實施例的畫素電路100則可透過拉長補償控制信號RN的致能時間,以增加對於驅動電晶體TD的臨界電壓的補償時間,並藉以有效地提升顯示畫面的品質。That is, in this embodiment, the time interval between the falling edge of the previous gate drive signal SN-m and the rising edge of the gate drive signal SN can be used as the compensation time for compensating the threshold voltage of the drive transistor TD. Therefore, compared to the conventional pixel circuit which can only compensate for the threshold voltage of the driving transistor during the limited enable period of the gate driving signal, the
圖2A至圖2G是依照圖1實施例的畫素電路100繪示本發明不同實施例的畫素電路200~800的電路圖。請參照圖2A,畫素電路200包括驅動電晶體TD、初始化電路210、電壓補償電路220、資料寫入電路230、發光控制電路240以及發光元件EL。2A to 2G are circuit diagrams of pixel circuits 200-800 according to different embodiments of the present invention according to the
初始化電路210包括電晶體T1~T2。電晶體T1的第一端(亦即,源極端)耦接至輸入端PIN,電晶體T1的第二端(亦即,汲極端)以及控制端(亦即,閘極端)可以共同接收前級閘極驅動信號SN-m。其中,電晶體T1可以為二極體組態(Diode Connection)的連接方式來形成一個二極體。電晶體T2的第一端(亦即,源極端)耦接至驅動端PD,電晶體T2的第二端(亦即,汲極端)耦接至系統電壓VDD以及發光元件EL的陽極端,電晶體T2的控制端(亦即,閘極端)可以接收前級閘極驅動信號SN-m。The
電壓補償電路220包括電晶體T3~T4以及電容器C1。電晶體T3的第一端(亦即,源極端)耦接至驅動端PD,電晶體T3的第二端(亦即,汲極端)耦接至驅動電晶體TD的第二端,電晶體T3的控制端(亦即,閘極端)接收補償控制信號RN。電晶體T4的第一端(亦即,源極端)耦接至參考電壓VREF,電晶體T4的第二端(亦即,汲極端)耦接至輸入端PIN,電晶體T4的控制端(亦即,閘極端)接收補償控制信號RN。電容器C1的第一端耦接至輸入端PIN,電容器C1的第二端耦接至驅動端PD。The
資料寫入電路230包括電晶體T5。電晶體T5的第一端(亦即,源極端)耦接至輸入端PIN,電晶體T5的第二端(亦即,汲極端)接收資料電壓VDATA,電晶體T5的控制端(亦即,閘極端)接收閘極驅動信號SN。The
發光控制電路240包括電晶體T6。電晶體T6的第一端(亦即,源極端)耦接至驅動電晶體TD的第二端,電晶體T6的第二端(亦即,汲極端)耦接至發光元件EL的陰極端,電晶體T6的控制端(亦即,閘極端)接收發光控制信號EM。The light
驅動電晶體TD的第一端耦接至系統電壓VSS,驅動電晶體TD的第二端耦接至電晶體T6的第一端,驅動電晶體TD的驅動端PD耦接至電容器C1的第二端。The first terminal of the driving transistor TD is coupled to the system voltage VSS, the second terminal of the driving transistor TD is coupled to the first terminal of the transistor T6, and the driving terminal PD of the driving transistor TD is coupled to the second terminal of the capacitor C1. end.
圖3是依照本發明圖2A至圖2G的畫素電路200~800的一實施例的波形示意圖。關於畫素電路200的操作細節,請同時參照圖2A以及圖3。詳細來說,當畫素電路200操作於重置階段TR時,前級閘極驅動信號SN-m可以被設定為致能狀態(例如為高電壓準位),而發光控制信號EM、閘極驅動信號SN以及補償控制信號RN皆可被設定為禁能狀態(例如為低電壓準位)。3 is a schematic diagram of waveforms of an embodiment of the pixel circuits 200-800 of FIGS. 2A to 2G according to the present invention. For details of the operation of the
在此情況下,初始化電路210的電晶體T1可依據被拉高的前級閘極驅動信號SN-m以提供閘極高電壓VGH至輸入端PIN,而初始化電路210的電晶體T2可依據被拉高的前級閘極驅動信號SN-m以提供系統電壓VDD(亦即系統高電壓)至驅動端PD。藉此,初始化電路210可拉高輸入端PIN以及驅動端PD的電壓準位,以對輸入端PIN以及驅動端PD進行重置動作,並使驅動電晶體TD可以被導通,藉以確保後續的補償操作能夠順利的進行。In this case, the transistor T1 of the
另一方面,當畫素電路200操作於補償階段TC時,補償控制信號RN可以被設定為致能狀態(例如為高電壓準位),而發光控制信號EM、前級閘極驅動信號SN-m以及閘極驅動信號SN皆可被設定為禁能狀態(例如為低電壓準位)。On the other hand, when the
在此情況下,電壓補償電路220可依據被拉高的補償控制信號RN而提供參考電壓VREF至輸入端PIN,並使驅動端PD的電壓準位調整為系統電壓VSS的電壓值以及驅動電晶體TD的臨界電壓VTH的電壓值的總和(亦即,VSS+VTH(其中,VSS為系統電壓VSS的電壓值;VTH為驅動電晶體TD的臨界電壓的電壓值))。In this case, the
接著,當畫素電路200操作於資料寫入階段TDA時,閘極驅動信號SN可以被設定為致能狀態(例如為高電壓準位),而發光控制信號EM、前級閘極驅動信號SN-m以及補償控制信號RN皆可被設定為禁能狀態(例如為低電壓準位)。Then, when the
在此情況下,資料寫入電路230可以依據被拉高的閘極驅動信號SN而將資料電壓VDATA提供至輸入端PIN。在此同時,透過電容器C1的耦合效應,電壓補償電路220可以將驅動端PD的電壓準位進一步的拉升至VSS+VTH+
V的電壓值,其中,
V為輸入端PIN操作在重置階段TR以及補償階段TC之間時的電壓值的變化量(亦即,VDATA-VREF(其中,VDATA為資料電壓VDATA的電壓值;VREF為參考電壓VREF的電壓值))。
In this case, the
另一方面,當畫素電路200操作於發光階段TE時,發光控制信號EM可以被設定為致能狀態(例如為高電壓準位),而前級閘極驅動信號SN-m、閘極驅動信號SN以及補償控制信號RN皆可被設定為禁能狀態(例如為低電壓準位)。On the other hand, when the
在此操作下,驅動電晶體TD的驅動端PD的電壓準位可以維持在資料寫入階段TDA時的電壓準位(亦即,VSS+VTH+(VDATA-VREF))。因此,當畫素電路200操作於發光階段TE,並且驅動電晶體TD操作於飽和區時,驅動電晶體TD可以產生導通電流ID,藉以驅動發光元件EL。此時,流經發光元件EL上的導通電流ID可以如下列式子所示:
ID=K
Under this operation, the voltage level of the driving terminal PD of the driving transistor TD can be maintained at the voltage level during the data writing phase TDA (ie, VSS+VTH+(VDATA-VREF)). Therefore, when the
其中,上述的ID為導通電流ID的電流值;K為驅動電晶體TD的製程參數;VSS為系統電壓VSS的電壓值;VTH為驅動電晶體TD的臨界電壓VTH的電壓值;VDATA為資料電壓VDATA的電壓值;VREF為參考電壓VREF的電壓值。Among them, the above ID is the current value of the conduction current ID; K is the process parameter of the driving transistor TD; VSS is the voltage value of the system voltage VSS; VTH is the voltage value of the threshold voltage VTH of the driving transistor TD; VDATA is the data voltage The voltage value of VDATA; VREF is the voltage value of the reference voltage VREF.
換言之,於發光階段TE中,畫素電路200可以有效地消除驅動電晶體TD因製程變異所造成的臨界電壓的偏移量。除此之外,在本實施例中,由於補償控制信號RN的致能時間是介於前級閘極驅動信號SN-m的下降沿至閘極驅動信號SN的上升沿之間,因此畫素電路200可以在足夠長的補償階段TC(或補償時間)中對驅動電晶體TD的臨界電壓VTH進行補償動作,藉以提升畫素電路200的補償效果。In other words, in the light-emitting phase TE, the
在此請參照圖2B,畫素電路300包括驅動電晶體TD、初始化電路310、電壓補償電路320、資料寫入電路330、發光控制電路340以及發光元件EL。畫素電路300大致相同或相似於畫素電路200,其中相同或相似元件使用相同或相似標號。不同於圖2A實施例的是,在初始化電路310中,電晶體T2的第一端耦接至驅動端PD,而電晶體T2的第二端以及控制端可以共同接收前級閘極驅動信號SN-m。2B, the
換言之,在圖2B所示的實施例中,當畫素電路300操作於重置階段TR時(如圖3所示),初始化電路310的電晶體T2則是依據被拉高的前級閘極驅動信號SN-m以提供閘極高電壓VGH至驅動端PD,以對驅動端PD進行重置動作。In other words, in the embodiment shown in FIG. 2B, when the
其中,圖2B所示的驅動電晶體TD、初始化電路310、電壓補償電路320、資料寫入電路330、發光控制電路340以及發光元件EL操作在重置階段TR、補償階段TC、資料寫入階段TDA以及發光階段TE時的實施細節可以參照圖2A的相關說明來類推,故不再贅述。Among them, the driving transistor TD, the
值得一提的是,在圖2A以及圖2B的實施例中,畫素200以及300僅需要7個電晶體即可構成,因此畫素200以及300可具有省面積以及省成本之優勢。It is worth mentioning that, in the embodiment of FIG. 2A and FIG. 2B, the
在此請參照圖2C,畫素電路400包括驅動電晶體TD、初始化電路410、電壓補償電路420、資料寫入電路430、發光控制電路440以及發光元件EL。畫素電路400大致相同或相似於畫素電路200、300,其中相同或相似元件使用相同或相似標號。不同於圖2A以及圖2B實施例的是,畫素電路400更包括漏電流補償電路450以及發光控制電路460。2C, the
發光控制電路460包括電晶體T8。電晶體T8的第一端(亦即,源極端)耦接至系統電壓VSS,電晶體T8的第二端(亦即,汲極端)耦接至驅動電晶體TD的第一端,電晶體T8的控制端(亦即,閘極端)接收發光控制信號EM。The light
漏電流補償電路450包括電晶體T7。電晶體T7的第一端(亦即,源極端)耦接至電晶體T8的第一端,電晶體T7的第二端(亦即,汲極端)耦接至電晶體T8的第二端,電晶體T7的控制端(亦即,閘極端)接收補償控制信號RN。The leakage
關於畫素電路400的操作細節,請同時參照圖2C以及圖3。詳細來說,當畫素電路400操作於重置階段TR時,初始化電路410的電晶體T1可依據被拉高的前級閘極驅動信號SN-m以提供閘極高電壓VGH至輸入端PIN,而初始化電路410的電晶體T2可依據被拉高的前級閘極驅動信號SN-m以提供閘極高電壓VGH至驅動端PD。藉此,初始化電路410可拉高輸入端PIN以及驅動端PD的電壓準位,以對輸入端PIN以及驅動端PD進行重置動作,並使驅動電晶體TD可以被導通,以確保後續的補償操作能夠順利的進行。For details of the operation of the
另一方面,當畫素電路400操作於補償階段TC時,電壓補償電路420可依據被拉高的補償控制信號RN而提供參考電壓VREF至輸入端PIN,並使驅動端PD的電壓準位調整為系統電壓VSS的電壓值以及驅動電晶體TD的臨界電壓VTH的電壓值的總和(亦即,VSS+VTH)。On the other hand, when the
需注意到的是,為了避免畫素電路400在長時間的補償時間下,導致驅動電晶體TD產生過大的漏電流,因此,當畫素電路400操作於補償階段TC時,漏電流補償電路450的電晶體T7可依據被拉高的補償控制信號RN而被導通,並藉以形成一漏電流宣洩路徑。藉此,漏電流補償電路450可在補償階段TC時透過所述漏電流宣洩路徑而將驅動電晶體TD所產生的漏電流宣洩至系統電壓VSS(亦即系統低電壓)。如此一來,本實施例的畫素電路400可以有效地抑制驅動電晶體TD所產生的瞬間漏電流。It should be noted that, in order to prevent the
特別一提的是,為了避免漏電流過大,在漏電流補償電路450的設計上,電晶體T7的長寬比可以被設計為小於電晶體T8的長寬比,但本發明並不限於此。In particular, in order to avoid excessive leakage current, in the design of the leakage
接著,當畫素電路400操作於資料寫入階段TDA時,資料寫入電路430可以依據被拉高的閘極驅動信號SN而將資料電壓VDATA提供至輸入端PIN。在此同時,透過電容器C1的耦合效應,電壓補償電路420可以將驅動端PD的電壓準位進一步的拉升至VSS+VTH+
V的電壓值,其中,
V為輸入端PIN操作在重置階段TR以及補償階段TC之間時的電壓值的變化量(亦即,VDATA-VREF)。
Then, when the
另一方面,當畫素電路400操作於發光階段TE時,驅動電晶體TD的驅動端PD的電壓準位可以維持在資料寫入階段TDA時的電壓準位(亦即,VSS+VTH+(VDATA-VREF))。因此,當畫素電路400操作於發光階段TE,並且驅動電晶體TD操作於飽和區時,驅動電晶體TD可以產生導通電流ID,藉以驅動發光元件EL。此時,流經發光元件EL上的導通電流ID可以如下列式子所示:
ID=K
On the other hand, when the
換言之,於發光階段TE中,畫素電路400同樣可以有效地消除驅動電晶體TD因製程變異所造成的臨界電壓的偏移量。並且,畫素電路400同樣可以在足夠長的補償階段TC(或補償時間)中對驅動電晶體TD的臨界電壓VTH進行補償動作,藉以改善畫素電路400的補償效果。In other words, in the light-emitting phase TE, the
在此請參照圖2D,畫素電路500包括驅動電晶體TD、初始化電路510、電壓補償電路520、資料寫入電路530、發光控制電路540、560、漏電流補償電路550以及發光元件EL。畫素電路500大致相同或相似於畫素電路400,其中相同或相似元件使用相同或相似標號。不同於圖2C實施例的是,在電壓補償電路520中,電晶體T4的第一端耦接至電晶體T7的第二端。2D, the
在此請同時參照圖2D以及圖3,關於畫素電路500操作重置階段TR時的實施細節可以參照圖2C的相關說明來類推,故不再贅述。Please refer to FIG. 2D and FIG. 3 at the same time. The implementation details of the
另一方面,當畫素電路500操作於補償階段TC時,電晶體T3、T4、T7可依據被拉高的補償控制信號RN而被導通。在此情況下,電晶體T4、T7可以透過導通路徑而提供系統電壓VSS至輸入端PIN。並且,電壓補償電路520以及漏電流補償電路550可依據被拉高的補償控制信號RN而使驅動端PD的電壓準位調整為系統電壓VSS的電壓值以及驅動電晶體TD的臨界電壓VTH的電壓值的總和(亦即,VSS+VTH)。On the other hand, when the
類似於圖2C實施例的是,在本實施例中,畫素電路500同樣可以於補償階段TC時透過漏電流補償電路550所形成的漏電流宣洩路徑,以將驅動電晶體TD所產生的瞬間漏電流宣洩至系統電壓VSS(亦即系統低電壓)。Similar to the embodiment in FIG. 2C, in this embodiment, the
接著,當畫素電路500操作於資料寫入階段TDA時,電晶體T5可依據被拉高的閘極驅動信號SN而被導通。在此情況下,資料寫入電路530可以依據被拉高的閘極驅動信號SN而將資料電壓VDATA提供至輸入端PIN。在此同時,透過電容器C1的耦合效應,電壓補償電路520可以將驅動端PD的電壓準位進一步的拉升至VDATA+VTH的電壓值。Then, when the
另一方面,當畫素電路500操作於發光階段TE時,電晶體T6、T8可依據被拉高的發光控制信號EM而被導通。在此操作下,驅動電晶體TD的驅動端PD的電壓準位可以維持在資料寫入階段TDA時的電壓準位(亦即,VDATA+VTH)。因此,當畫素電路500操作於發光階段TE,並且驅動電晶體TD操作於飽和區時,驅動電晶體TD可以產生導通電流ID,藉以驅動發光元件EL。此時,流經發光元件EL上的導通電流ID可以如下列式子所示:
ID=K
On the other hand, when the
換言之,於發光階段TE中,畫素電路500同樣可以有效地消除驅動電晶體TD因製程變異所造成的臨界電壓的偏移量。並且,畫素電路500同樣可以在足夠長的補償階段TC(或補償時間)中對驅動電晶體TD的臨界電壓VTH進行補償動作,藉以改善畫素電路500的補償效果。In other words, in the light-emitting phase TE, the
在此請參照圖2E,畫素電路600包括驅動電晶體TD、初始化電路610、電壓補償電路620、資料寫入電路630、發光控制電路640、660、漏電流補償電路650以及發光元件EL。畫素電路600大致相同或相似於畫素電路500,其中相同或相似元件使用相同或相似標號。不同於圖2D實施例的是,在初始化電路610中,電晶體T2的第一端耦接至驅動端PD,電晶體T2的第二端可耦接至系統電壓VDD,電晶體T2的控制端接收前級閘極驅動信號SN-m。2E, the
換言之,在圖2E所示的實施例中,當畫素電路600操作於重置階段TR時(如圖3所示),初始化電路610的電晶體T2則是依據被拉高的前級閘極驅動信號SN-m以提供系統電壓VDD(亦即系統高電壓)至驅動端PD,以對驅動端PD進行重置動作。In other words, in the embodiment shown in FIG. 2E, when the
其中,圖2E所示的驅動電晶體TD、初始化電路610、電壓補償電路620、資料寫入電路630、發光控制電路640、660、漏電流補償電路650以及發光元件EL操作在重置階段TR、補償階段TC、資料寫入階段TDA以及發光階段TE時的實施細節可以參照圖2D的相關說明來類推,故不再贅述。Among them, the driving transistor TD, the
在此請參照圖2F,畫素電路700包括驅動電晶體TD、初始化電路710、電壓補償電路720、資料寫入電路730、發光控制電路740、760、漏電流補償電路750以及發光元件EL。其中相同或相似元件使用相同或相似標號。不同於圖2D實施例的是,在漏電流補償電路750中,電晶體T7的第一端耦接至輸入端PIN,電晶體T7的第二端耦接至參考電壓VREF,電晶體T7的控制端接收補償控制信號RN。2F, the
進一步來說,在圖2F所示的實施例中,當畫素電路700操作於補償階段TC時(如圖3所示),電晶體T3、T4、T7可依據被拉高的補償控制信號RN而被導通。在此情況下,漏電流補償電路750可依據被拉高的補償控制信號RN而提供參考電壓VREF至輸入端PIN,並且電壓補償電路720可依據被拉高的補償控制信號RN而使驅動端PD的電壓準位調整為參考電壓VREF的電壓值以及驅動電晶體TD的臨界電壓VTH的電壓值的總和(亦即,VREF+VTH)。Furthermore, in the embodiment shown in FIG. 2F, when the
類似於圖2D實施例的是,畫素電路700可以於補償階段TC時透過漏電流補償電路750的電晶體T7以及電壓補償電路720的電晶體T4所形成的漏電流宣洩路徑,以將驅動電晶體TD所產生的瞬間漏電流宣洩至參考電壓VREF。Similar to the embodiment in FIG. 2D, the
其中,圖2F所示的驅動電晶體TD、初始化電路710、電壓補償電路720、資料寫入電路730、發光控制電路740、760、漏電流補償電路750以及發光元件EL操作在重置階段TR、補償階段TC、資料寫入階段TDA以及發光階段TE時的實施細節可以參照圖2D的相關說明來類推,故不再贅述。Among them, the driving transistor TD, the
在此請參照圖2G,畫素電路800包括驅動電晶體TD、初始化電路810、電壓補償電路820、資料寫入電路830、發光控制電路840、860、漏電流補償電路850以及發光元件EL。其中相同或相似元件使用相同或相似標號。不同於圖2C實施例的是,在初始化電路810中,電晶體T2的第一端耦接至驅動端PD,電晶體T2的第二端耦接至系統電壓VDD,電晶體T2的控制端接收前級閘極驅動信號SN-m。2G, the
換言之,在圖2G所示的實施例中,當畫素電路800操作於重置階段TR時(如圖3所示),初始化電路810的電晶體T2則是依據被拉高的前級閘極驅動信號SN-m以提供系統電壓VDD(亦即系統高電壓)至驅動端PD,以對驅動端PD進行重置動作。In other words, in the embodiment shown in FIG. 2G, when the
其中,圖2G所示的驅動電晶體TD、初始化電路810、電壓補償電路820、資料寫入電路830、發光控制電路840、860、漏電流補償電路850以及發光元件EL操作在重置階段TR、補償階段TC、資料寫入階段TDA以及發光階段TE時的實施細節可以參照圖2C的相關說明來類推,故不再贅述。Among them, the driving transistor TD, the
需注意到的是,針對上述的圖1、圖2A至圖2G以及圖3的諸多實施例,在一些設計需求下,各個畫素電路(如,畫素電路100~800)所接收的補償控制信號RN可以在當前的圖框(Frame)中被設定為致能狀態(例如是高電壓準位)。亦即,各個畫素電路可以在當前的圖框中對驅動電晶體TD的臨界電壓VTH進行補償操作。It should be noted that for many of the above-mentioned embodiments in FIG. 1, FIG. 2A to FIG. 2G, and FIG. The signal RN can be set to an enabled state (for example, a high voltage level) in the current frame (Frame). That is, each pixel circuit can compensate the threshold voltage VTH of the driving transistor TD in the current frame.
另一方面,請參照圖4,圖4是依照本發明圖2A至圖2G的畫素電路的另一實施例波形示意圖。在另一些設計需求下,各個畫素電路亦可在前一個圖框中預先致能補償控制信號RN,以使畫素電路可以在前一個圖框中預先開始對驅動電晶體TD的臨界電壓VTH進行補償操作。藉此,本實施例的畫素電路可以更加拉長補償階段TC的時間區間,以改善臨界電壓對於顯示畫面的品質影響。On the other hand, please refer to FIG. 4, which is a waveform diagram of another embodiment of the pixel circuit of FIGS. 2A to 2G according to the present invention. Under some other design requirements, each pixel circuit can also pre-enable the compensation control signal RN in the previous frame, so that the pixel circuit can start the threshold voltage VTH of the driving transistor TD in the previous frame in advance. Perform compensation operations. In this way, the pixel circuit of this embodiment can further extend the time interval of the compensation stage TC, so as to improve the influence of the threshold voltage on the quality of the display image.
圖5是依照本發明另一實施例的畫素電路900的示意圖。請參照圖5,畫素電路900包括驅動電晶體TD、初始化電路910、電壓補償電路920、資料寫入電路930、發光控制電路940以及發光元件EL。發光元件EL的陽極端耦接至系統電壓VDD,發光元件EL的陰極端耦接至發光控制電路940。發光元件EL可以依據導通電流ID來對應的被點亮。FIG. 5 is a schematic diagram of a
驅動電晶體TD的第一端(亦即,源極端)耦接至系統電壓VSS,驅動電晶體TD的第二端(亦即,汲極端)耦接至發光控制電路940,驅動電晶體TD的驅動端PD(亦即,閘極端)耦接至初始化電路910。The first terminal (that is, the source terminal) of the driving transistor TD is coupled to the system voltage VSS, and the second terminal (that is, the drain terminal) of the driving transistor TD is coupled to the light-emitting
初始化電路910耦接至輸入端PIN以及驅動端PD。初始化電路910可用以基於參考電壓VREF(或系統電壓VDD),並依據閘極驅動信號SN以及前級閘極驅動信號SN-m以調整輸入端PN以及驅動端PD的電壓準位。電壓補償電路920耦接至初始化電路920。電壓補償電路920可用以於補償階段依據閘極驅動信號SN以及前級閘極驅動信號SN-m以調整驅動端PD的電壓準位。The
另一方面,資料寫入電路930耦接至輸入端PIN。資料寫入電路930可用以依據閘極驅動信號SN以提供資料電壓VDATA至輸入端PIN。發光控制電路940耦接至發光元件EL的陰極端、電壓補償電路920以及驅動電晶體TD的第二端。發光控制電路940可依據控制信號CS以控制發光元件EL的發光狀態。On the other hand, the
值得一提的是,本實施例的控制信號CS可以例如是閘極驅動信號SN、發光控制信號EM或是後級閘極驅動信號SN+i。舉例來說,所述控制信號CS可以是由控制信號產生器(未繪示)所產生。其中,所述控制信號產生器(未繪示)可以是由一或多組GOA電路來進行建構。It is worth mentioning that the control signal CS in this embodiment can be, for example, a gate drive signal SN, a light emission control signal EM, or a subsequent gate drive signal SN+i. For example, the control signal CS may be generated by a control signal generator (not shown). Wherein, the control signal generator (not shown) may be constructed by one or more sets of GOA circuits.
針對畫素電路900的操作動作,具體來說,當畫素電路900操作於一畫素期間的補償階段時,電壓補償電路920可以依據被拉低的閘極驅動信號SN與前級閘極驅動信號SN-m來調整驅動電晶體TD的驅動端PD的電壓準位,藉以對驅動電晶體TD的臨界電壓進行補償動作。Regarding the operation of the
進一步來說,在本實施例中,所述補償階段可以被設定為介於前級閘極驅動信號SN-m的下降沿以及閘極驅動信號SN的上升沿之間。舉例來說,畫素電路900可以在前級閘極驅動信號SN-m從致能狀態轉換為禁能狀態(例如是從高電壓準位轉換為低電壓準位)之後,接續執行補償驅動電晶體TD的臨界電壓的補償動作,直到閘極驅動信號SN欲從禁能狀態轉換為致能狀態(例如是從低電壓準位轉換為高電壓準位)為止。Furthermore, in this embodiment, the compensation stage can be set to be between the falling edge of the previous gate drive signal SN-m and the rising edge of the gate drive signal SN. For example, the
也就是說,本實施例可以將前級閘極驅動信號SN-m的下降沿至閘極驅動信號SN的上升沿之間的時間區間,作為對於補償驅動電晶體TD的臨界電壓的補償時間。因此,相較於習知的畫素電路僅能夠在有限的閘極驅動信號的致能期間中對驅動電晶體的臨界電壓進行補償動作,本實施例的畫素電路900則可透過拉長補償階段的工作時間,以增加對於驅動電晶體TD的臨界電壓的補償時間,並藉以有效地提升顯示畫面的品質。That is, in this embodiment, the time interval between the falling edge of the previous gate drive signal SN-m and the rising edge of the gate drive signal SN can be used as the compensation time for compensating the threshold voltage of the drive transistor TD. Therefore, compared to the conventional pixel circuit which can only compensate for the threshold voltage of the driving transistor during the limited enable period of the gate drive signal, the
圖6A至圖6B是依照圖5實施例的畫素電路繪示本發明不同實施例的畫素電路1000、1100的電路圖。請參照圖6A,畫素電路1000包括驅動電晶體TD、初始化電路1010、電壓補償電路1020、資料寫入電路1030、發光控制電路1040以及發光元件EL。6A to 6B are circuit diagrams showing
初始化電路1010包括電晶體T1~T4以及電容器C1。電晶體T1的第二端(亦即,汲極端)以及控制端(亦即,閘極端)可以共同接收前級閘極驅動信號SN-m。其中,電晶體T1可以為二極體組態的連接方式來形成一個二極體。電晶體T2的第一端(亦即,源極端)耦接至電晶體T1的第一端(亦即,源極端),電晶體T2的第二端(亦即,汲極端)接收前級閘極驅動信號SN-m,電晶體T2的控制端(亦即,閘極端)接收閘極驅動信號SN。The
電晶體T3的第一端(亦即,源極端)耦接至輸入端PIN,電晶體T3的第二端(亦即,汲極端)耦接至參考電壓VREF,電晶體T3的控制端(亦即,閘極端)耦接至電晶體T2的第一端。電晶體T4的第一端(亦即,源極端)耦接至驅動端PD,電晶體T4的第二端(亦即,汲極端)以及控制端(亦即,閘極端)共同接收前級閘極驅動信號SN-m。其中,電晶體T4可以為二極體組態的連接方式來形成一個二極體。電容器C1的第一端耦接至輸入端PIN,電容器C1的第二端耦接至驅動端PD。The first terminal (that is, the source terminal) of the transistor T3 is coupled to the input terminal PIN, the second terminal (that is, the drain terminal) of the transistor T3 is coupled to the reference voltage VREF, and the control terminal (also That is, the gate terminal) is coupled to the first terminal of the transistor T2. The first terminal (that is, the source terminal) of the transistor T4 is coupled to the driving terminal PD, and the second terminal (that is, the drain terminal) and the control terminal (that is, the gate terminal) of the transistor T4 jointly receive the front gate Polar drive signal SN-m. Among them, the transistor T4 can be a diode configuration to form a diode. The first terminal of the capacitor C1 is coupled to the input terminal PIN, and the second terminal of the capacitor C1 is coupled to the driving terminal PD.
電壓補償電路1020包括電晶體T5。電晶體T5的第一端(亦即,源極端)耦接至驅動端PD,電晶體T5的第二端(亦即,汲極端)耦接至發光控制電路1040,電晶體T5的控制端(亦即,閘極端)耦接至電晶體T2的第一端。The
資料寫入電路1030包括電晶體T6。電晶體T6的第一端(亦即,源極端)耦接至輸入端PIN,電晶體T6的第二端(亦即,汲極端)接收資料電壓VDATA,電晶體T6的控制端(亦即,閘極端)接收閘極驅動信號SN。The
發光控制電路1040包括電晶體T7。電晶體T7的第一端(亦即,源極端)耦接至電晶體T5的第二端,電晶體T7的第二端(亦即,汲極端)耦接至發光元件EL的陰極端,電晶體T7的控制端(亦即,閘極端)接收閘極驅動信號SN。The light
驅動電晶體TD的第一端耦接至系統電壓VSS,驅動電晶體TD的第二端耦接至電晶體T7的第一端,驅動電晶體TD的驅動端PD耦接至電容器C1的第二端。The first terminal of the driving transistor TD is coupled to the system voltage VSS, the second terminal of the driving transistor TD is coupled to the first terminal of the transistor T7, and the driving terminal PD of the driving transistor TD is coupled to the second terminal of the capacitor C1. end.
圖7是依照本發明圖6A至圖6B的畫素電路1000、1100的波形示意圖。關於畫素電路1000的操作細節,請同時參照圖6A以及圖7。詳細來說,當畫素電路1000操作於重置階段TR時,前級閘極驅動信號SN-m可以被設定為致能狀態(例如為高電壓準位),而閘極驅動信號SN可被設定為禁能狀態(例如為低電壓準位)。FIG. 7 is a schematic diagram of waveforms of the
在此情況下,初始化電路1010的電晶體T1可依據被拉高的前級閘極驅動信號SN-m以提供閘極高電壓VGH至電晶體T3、T5的控制端,使電晶體T3、T5為導通狀態。接著,電晶體T5可透過導通路徑以提供閘極高電壓VGH至驅動端PD。此外,電晶體T3亦可透過導通路徑以提供參考電壓VREF至輸入端PIN。藉此,初始化電路1010可拉高輸入端PIN以及驅動端PD的電壓準位,以對輸入端PIN以及驅動端PD進行重置動作,並使驅動電晶體TD可以被導通,藉以確保後續的補償操作能夠順利的進行。In this case, the transistor T1 of the
另一方面,當畫素電路1000操作於補償階段TC時,前級閘極驅動信號SN-m以及閘極驅動信號SN可皆被設定為禁能狀態(例如為低電壓準位)。在此情況下,電壓補償電路1020的電晶體T5依據被拉低的前級閘極驅動信號SN-m以及閘極驅動信號SN,使其控制端的電壓準位維持於閘極高電壓VGH的電壓值。並且,電晶體T5會透過導通路徑使驅動端PD的電壓準位調整為系統電壓VSS的電壓值以及驅動電晶體TD的臨界電壓VTH的電壓值的總和(亦即,VSS+VTH)。On the other hand, when the
此外,電晶體T3仍可透過導通路徑使輸入端PIN的電壓準位維持於參考電壓VREF的電壓值。In addition, the transistor T3 can still maintain the voltage level of the input terminal PIN at the voltage value of the reference voltage VREF through the conduction path.
接著,當畫素電路1000操作於發光階段TE時,閘極驅動信號SN可以被設定為致能狀態(例如為高電壓準位),而前級閘極驅動信號SN-m可被設定為禁能狀態(例如為低電壓準位)。在此情況下,資料寫入電路1030可依據被拉高的閘極驅動信號SN而將資料電壓VDATA提供至輸入端PIN。在此同時,透過電容器C1的耦合效應,初始化電路1010可以將驅動端PD的電壓準位進一步的拉升至VSS+VTH+
V的電壓值,其中,
V為輸入端PIN操作在重置階段TR以及補償階段TC之間時的電壓值的變化量(亦即,VDATA-VREF(其中,VDATA為資料電壓VDATA的電壓值;VREF為參考電壓VREF的電壓值))。
Then, when the
除此之外,在發光階段TE中,發光控制電路1040的電晶體T7可依據被拉高的閘極驅動信號SN而被導通,並且驅動電晶體TD可依據驅動端PD上的電壓以產生導通電流ID,藉以驅動發光元件EL。此時,流經發光元件EL上的導通電流ID可以如下列式子所示:
ID=K
In addition, in the light-emitting phase TE, the transistor T7 of the light-emitting
換言之,於發光階段TE中,畫素電路1000可以同時將資料電壓VDATA提供至輸入端PIN,並且點亮發光元件EL。此外,畫素電路1000同樣可以有效地消除驅動電晶體TD因製程變異所造成的臨界電壓的偏移量。並且,畫素電路1000同樣可以在足夠長的補償階段TC(或補償時間)中對驅動電晶體TD的臨界電壓VTH進行補償動作,藉以改善畫素電路1000的補償效果。In other words, in the light-emitting phase TE, the
在此請參照圖6B,畫素電路1100包括驅動電晶體TD、初始化電路1110、電壓補償電路1120、資料寫入電路1130、發光控制電路1140以及發光元件EL。畫素電路1100大致相同或相似於畫素電路1000,其中相同或相似元件使用相同或相似標號。不同於圖6A實施例的是,在初始化電路1110中,電晶體T3的第二端可以耦接至系統電壓VDD。6B, the
換言之,在圖6B所示的實施例中,當畫素電路1100操作於重置階段TR時,電晶體T3可以依據其控制端的電壓以提供系統電壓VDD至輸入端PIN,以對輸入端PIN進行重置動作。In other words, in the embodiment shown in FIG. 6B, when the
其中,圖6B所示的驅動電晶體TD、初始化電路1110、電壓補償電路1120、資料寫入電路1130、發光控制電路1140以及發光元件EL操作在重置階段TR、補償階段TC以及發光階段TE時的實施細節可以參照圖6A的相關說明來類推,故不再贅述。Among them, the driving transistor TD, the
值得一提的是,在圖6A以及圖6B的實施例中,畫素電路1000、1100僅受控於前級閘極驅動信號SN-m以及閘極驅動信號SN。換言之,本實施例可以僅透過一組GOA電路來控制畫素電路1000、1100,因此能夠有效地節省整體的面積。It is worth mentioning that in the embodiments of FIGS. 6A and 6B, the
圖8是依照圖5實施例的畫素電路繪示本發明不同實施例的畫素電路1200的電路圖。請參照圖8,畫素電路1200包括驅動電晶體TD、初始化電路1210、電壓補償電路1220、資料寫入電路1230、發光控制電路1240以及發光元件EL。畫素電路1200大致相同或相似於畫素電路1000,其中相同或相似元件使用相同或相似標號。FIG. 8 is a circuit diagram of a
不同於圖6A實施例的是,在發光控制電路1240中,電晶體T7可以受控於發光控制信號EM。圖9是依照本發明圖8的畫素電路1200的波形示意圖。請同時參照圖8以及圖9,當畫素電路1200操作於發光階段TE時,發光控制電路1240可依據被拉高的發光控制信號EM以產生驅動電流ID,並透過驅動電流ID以點亮發光元件EL。Different from the embodiment of FIG. 6A, in the light
其中,圖8所示的驅動電晶體TD、初始化電路1210、電壓補償電路1220、資料寫入電路1230、發光控制電路1240以及發光元件EL操作在重置階段TR、補償階段TC、資料寫入階段TDA以及發光階段TE時的實施細節可以參照圖6A的相關說明來類推,故不再贅述。Among them, the driving transistor TD, the
圖10是依照圖5實施例的畫素電路繪示本發明不同實施
例的畫素電路1300的電路圖。請參照圖10,畫素電路1300包括驅動電晶體TD、初始化電路1310、電壓補償電路1320、資料寫入電路1330、發光控制電路1340以及發光元件EL。畫素電路1300大致相同或相似於畫素電路1100,其中相同或相似元件使用相同或相似標號。
FIG. 10 is a pixel circuit according to the embodiment of FIG. 5 showing different implementations of the present invention
The circuit diagram of the
不同於圖6B實施例的是,在發光控制電路1340中,電晶體T7可以受控於後級閘極驅動信號SN+i。圖11是依照本發明圖10的畫素電路1300的波形示意圖。請同時參照圖10以及圖11,當畫素電路1300操作於發光階段TE時,發光控制電路1340可依據被拉高的後級閘極驅動信號SN+i以產生驅動電流ID,並透過驅動電流ID以點亮發光元件EL。其中,上述的i為大於1的正整數。Different from the embodiment in FIG. 6B, in the light
其中,圖10所示的驅動電晶體TD、初始化電路1310、電壓補償電路1320、資料寫入電路1330、發光控制電路1340以及發光元件EL操作在重置階段TR、補償階段TC、資料寫入階段TDA以及發光階段TE時的實施細節可以參照圖6A以及圖6B的相關說明來類推,故不再贅述。Among them, the driving transistor TD, the
圖12是依照本發明圖1實施例的畫素電路100的驅動方法的流程圖。請同時參照圖1以及圖12,在步驟S1210中,畫素電路100可以提供具有驅動端、第一端以及第二端的驅動電晶體。在步驟S1220中,畫素電路100可以提供初始化電路以依據前級閘極驅動信號來調整輸入端以及驅動端的電壓準位。在步驟S1230中,畫素電路100可以提供資料寫入電路以依據閘極驅動信號來提供資料電壓至輸入端。在步驟S1240中,畫素電路100可以提供電壓補償電路以依據補償控制信號來調整驅動端的電壓準位。在步驟S1250中,畫素電路100可以提供具有陰極端以及陽極端的發光元件。在步驟S1260中,畫素電路100可以提供第一發光控制電路以依據發光控制信號來控制發光元件的發光狀態,其中補償控制信號的致能時間介於前級閘極驅動信號的下降沿以及閘極驅動信號的上升沿之間。FIG. 12 is a flowchart of a driving method of the
圖13是依照本發明圖5實施例的畫素電路900的驅動方法的流程圖。請同時參照圖5以及圖13,在步驟S1310中,畫素電路900可以提供具有驅動端、第一端以及第二端的驅動電晶體。在步驟S1320中,畫素電路900可以提供初始化電路以基於參考電壓,並依據閘極驅動信號以及前級閘極驅動信號以調整輸入端以及驅動端的電壓準位。在步驟S1330中,畫素電路900可以提供資料寫入電路以依據閘極驅動信號來提供資料電壓至輸入端。在步驟S1340中,畫素電路900可以提供電壓補償電路以於補償階段依據閘極驅動信號以及前級閘極驅動信號來調整驅動端的電壓準位。在步驟S1350中,畫素電路900可以提供具有陰極端以及陽極端的發光元件。在步驟S1360中,畫素電路900可以提供發光控制電路以依據控制信號來控制發光元件的發光狀態,其中補償階段介於前級閘極驅動信號的下降沿以及閘極驅動信號的上升沿之間。FIG. 13 is a flowchart of a driving method of the
關於圖12以及圖13各步驟的實施細節在前述的實施例及實施方式都有詳盡的說明,在此則不再贅述。The implementation details of the steps in FIG. 12 and FIG. 13 are described in detail in the foregoing embodiments and implementations, and will not be repeated here.
綜上所述,本發明諸實施例所述畫素電路可透過將補償控制信號的致能時間設定為介於前級閘極驅動信號的下降沿至閘極驅動信號的上升沿之間,以作為對於補償驅動電晶體的臨界電壓的補償時間。如此一來,相較於習知的畫素電路僅能夠在有限的閘極驅動信號的致能期間中對驅動電晶體的臨界電壓進行補償動作,本發明的畫素電路則可透過拉長補償控制信號的致能時間,以增加對於驅動電晶體的臨界電壓的補償時間,並藉以有效地提升顯示畫面的品質。In summary, the pixel circuits of the embodiments of the present invention can set the enable time of the compensation control signal to be between the falling edge of the previous gate drive signal and the rising edge of the gate drive signal. As a compensation time for compensating the critical voltage of the driving transistor. In this way, compared to the conventional pixel circuit which can only compensate for the threshold voltage of the driving transistor during the limited enable period of the gate drive signal, the pixel circuit of the present invention can compensate by lengthening The enabling time of the control signal is used to increase the compensation time for the threshold voltage of the driving transistor, thereby effectively improving the quality of the display image.
100~1300:畫素電路
110~1310:初始化電路
120~1320:電壓補償電路
130~1330:資料寫入電路
140~1340:發光控制電路
450~850:漏電流補償電路
460~860:發光控制電路
C1:電容器
CS:控制信號
EM:發光控制信號
EL:發光元件
ID:導通電流
PIN:輸入端
PD:驅動端
RN:補償控制信號
SN:閘極驅動信號
SN-m:前級閘極驅動信號
SN+i:後級閘極驅動信號
S1210~S1260、S1310~S1360:步驟
T1~T8:電晶體
TD:驅動電晶體
TDA:資料寫入階段
TE:發光階段
TR:重置階段
TC:補償階段
VGH:閘極高電壓
VDATA:資料電壓
VREF:參考電壓
VDD、VSS:系統電壓
VREF:參考電壓
100~1300:
圖1是依照本發明一實施例的畫素電路的示意圖。 圖2A至圖2G是依照圖1實施例的畫素電路繪示本發明不同實施例的畫素電路的電路圖。 圖3是依照本發明圖2A至圖2G的畫素電路的一實施例的波形示意圖。 圖4是依照本發明圖2A至圖2G的畫素電路的另一實施例波形示意圖。 圖5是依照本發明另一實施例的畫素電路的示意圖。 圖6A至圖6B是依照圖5實施例的畫素電路繪示本發明不同實施例的畫素電路的電路圖。 圖7是依照本發明圖6A至圖6B的畫素電路的波形示意圖。 圖8是依照圖5實施例的畫素電路繪示本發明不同實施例的畫素電路的電路圖。 圖9是依照本發明圖8的畫素電路的波形示意圖。 圖10是依照圖5實施例的畫素電路繪示本發明不同實施例的畫素電路的電路圖。 圖11是依照本發明圖10的畫素電路的波形示意圖。 圖12是依照本發明圖1實施例的畫素電路的驅動方法的流程圖。 圖13是依照本發明圖5實施例的畫素電路的驅動方法的流程圖。 FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the invention. 2A to 2G are circuit diagrams showing pixel circuits of different embodiments of the present invention according to the pixel circuit of the embodiment of FIG. 1. 3 is a schematic diagram of waveforms of an embodiment of the pixel circuit of FIGS. 2A to 2G according to the present invention. 4 is a schematic diagram of waveforms of another embodiment of the pixel circuit of FIGS. 2A to 2G according to the present invention. FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the invention. 6A to 6B are circuit diagrams showing pixel circuits of different embodiments of the present invention according to the pixel circuit of the embodiment of FIG. 5. FIG. 7 is a schematic diagram of waveforms of the pixel circuits of FIGS. 6A to 6B according to the present invention. FIG. 8 is a circuit diagram of a pixel circuit of a different embodiment of the present invention according to the pixel circuit of the embodiment of FIG. 5. FIG. 9 is a schematic diagram of waveforms of the pixel circuit of FIG. 8 according to the present invention. FIG. 10 is a circuit diagram of a pixel circuit of a different embodiment of the present invention according to the pixel circuit of the embodiment of FIG. 5. FIG. 11 is a schematic diagram of waveforms of the pixel circuit of FIG. 10 according to the present invention. FIG. 12 is a flowchart of the driving method of the pixel circuit according to the embodiment of FIG. 1 of the present invention. FIG. 13 is a flowchart of the driving method of the pixel circuit according to the embodiment of FIG. 5 of the present invention.
100:畫素電路 100: pixel circuit
110:初始化電路 110: Initialization circuit
120:電壓補償電路 120: Voltage compensation circuit
130:資料寫入電路 130: Data writing circuit
140:發光控制電路 140: Light-emitting control circuit
EM:發光控制信號 EM: Luminous control signal
EL:發光元件 EL: Light-emitting element
ID:導通電流 ID: On-current
VDD、VSS:系統電壓 VDD, VSS: system voltage
PIN:輸入端 PIN: input
PD:驅動端 PD: drive end
RN:補償控制信號 RN: Compensation control signal
SN:閘極驅動信號 SN: Gate drive signal
SN-m:前級閘極驅動信號 SN-m: Front-stage gate drive signal
TD:驅動電晶體 TD: drive transistor
VDATA:資料電壓 VDATA: data voltage
VREF:參考電壓 VREF: Reference voltage
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TW201434025A (en) * | 2013-02-25 | 2014-09-01 | Samsung Display Co Ltd | Pixel, display device including the same, and method thereof |
US20160071458A1 (en) * | 2013-07-08 | 2016-03-10 | Boe Technology Croup Co., Ltd. | Led pixel unit circuit, driving method thereof, and display panel |
TW201721619A (en) * | 2015-12-07 | 2017-06-16 | 友達光電股份有限公司 | Plxel circuit and driving method thereof |
TWM573055U (en) * | 2017-10-31 | 2019-01-11 | 大陸商昆山國顯光電有限公司 | Pixel circuit and display device |
CN207558368U (en) * | 2017-12-01 | 2018-06-29 | 京东方科技集团股份有限公司 | A kind of pixel compensation circuit, display panel and display device |
CN111445853A (en) * | 2020-05-08 | 2020-07-24 | 京东方科技集团股份有限公司 | Pixel driving circuit, display panel, driving method and display device |
Also Published As
Publication number | Publication date |
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CN113096584A (en) | 2021-07-09 |
TW202205239A (en) | 2022-02-01 |
CN113096584B (en) | 2023-07-14 |
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