TWI744113B - Interface device and interface method for 3d semiconductor device - Google Patents

Abstract

An interface device and an interface method for interfacing between a master device and a slave device is provided. The master device generates command and the slave device generates data according to the command. The interface device includes a master interface and a slave interface. The master interface is coupled to the master device and configured to send the command to the slave device and/or receive the data from the slave device. The slave interface is coupled to the slave device and configured to receive the command from the master device and/or send the data to the master device. The master interface and the slave interface are driven by a clock generated by a clock generator. The master interface and the slave interface are electrically connected by one or plurality of bonds and/or TSVs.

Description

Interface device and interface method for three-dimensional semiconductor device

The present disclosure relates to a technology for a three dimensional (3D) semiconductor device, and more specifically, to an interface device and an interface method for a 3D semiconductor device.

In recent years, electronic devices such as personal computers (PCs) or smart phones have been developed in terms of packaging. As a result, the size of the electronic devices has become compact and the production cost can be reduced accordingly. One of the key factors in the development of electronic devices is 3D semiconductor technology. Various semiconductor devices including the CPU and the memory can be integrated into a single chip by vertically interconnecting the central processing unit (CPU) and the memory. This structure is generally called a 3D integrated circuit (3D integrated circuit, 3D IC). On the other hand, in order to maintain reliable data transmission/communication, an interface device is required to adjust the internal connection between one CPU/memory and other CPU/memory. However, interface devices for 3D integrated circuits are still under development.

The invention provides an interface device and an interface method for a 3D semiconductor device. The interface device and the interface method provide reliable data communication between the master device and the slave device.

In an embodiment, the present invention provides an interface device for interfacing between a master device and a slave device. The master device generates a command and the slave device generates data according to the command. The interface device includes a master interface and a slave interface. The main interface is coupled to the main device. The master interface is configured to send the command to the slave device and/or receive the data from the slave device. The slave interface is coupled to the slave device. The slave interface is configured to receive the command from the master device and/or send the data to the master device. The master interface and the slave interface are driven by clocks generated by a clock generator. The master interface and the slave interface are electrically connected by one or more coupling elements. The clock used to drive the slave interface is trained by changing the clock phase of the clock to be aligned with the command data cluster and/or the data cluster of the data.

In an embodiment, the present invention provides an interface method for interfacing between a master device and a slave device. The master device generates a command and the slave device generates data according to the command, and the interface method includes: the master interface sends the command to the slave device and/or receives the data from the slave device; And the slave interface receives the command from the master device and/or sends the data to the master device. The master interface and the slave interface are driven by clocks generated by a clock generator. The master interface and the slave interface are electrically connected by one or more coupling elements. The clock used to drive the slave interface is trained by changing the clock phase of the clock to be aligned with the command data cluster and/or the data cluster of the data.

In order to make the above content easier to understand, several embodiments with drawings will be described in detail below.

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the formation of the first feature on the second feature or the second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include the first feature An embodiment in which an additional feature may be formed between the second feature so that the first feature and the second feature may not directly contact. In addition, the present disclosure may reuse reference numbers and/or letters in various examples. This repeated use is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and/or configurations discussed by itself.

In addition, for ease of description, this article may use, for example, "beneath", "below", "lower", "above )", "upper" and other spatially relative terms are used to describe the relationship between one element or feature shown in the figure and another (other) element or feature. The terms of spatial relativity are intended to cover different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can have other orientations (rotated by 90 degrees or in other orientations), and the spatial relativity descriptors used herein can also be interpreted accordingly.

The present disclosure discloses an interface device and an interface method for a 3D semiconductor device. The interface device provides reliable data communication between the master device and the slave device. The reliable data communication is generated by allocating the data waiting time provided by the master device to each slave device according to the clock generated by the clock generator. Each slave device has a local clock generated from the clock of the clock generator. Each slave device can adjust the local clock, in this way, data competition between slave devices can be avoided. In addition, by avoiding data competition between each slave device, bit errors can be minimized or avoided. In this way, there is no need to use error correction modules and methods. Therefore, the data communication speed can be increased.

In addition, when starting the electronic device, each slave device can train the local clock of each slave device by sending built-in-self-test (BIST) data to the master device. By accurately generating the local clock, each slave device can provide accurate data with low error rate or zero error rate. By doing so, there is no need for error correction and the data communication speed can be increased accordingly. In order to avoid data competition between each slave device and train the local clock of each slave device, the implementation of the interface device and interface method will be described in detail according to the embodiments provided below (especially considering the implementation of the slave to the master interface ).

FIG. 1 shows a schematic block diagram of a semiconductor device including a master device and a slave device according to an embodiment of the present disclosure. The semiconductor device 100 is implemented in, for example, the following 3D packages: chip-on-wafer-on-substrate (CoWoS), system-on-integrated-chip (SoIC), wafer-to-wafer ( wafer-on-wafer, WoW) and other 3D package integration.

1, the semiconductor device 100 includes a master wafer 120, a slave wafer 130, and a clock generator 115. The master wafer 120 is coupled to the slave wafer 130 through a through-silicon-via (TSV) 104. The main chip 120 includes a main device 105 and a main interface 102 coupled to the main device 105. On the other hand, the slave wafer 130 includes a slave device 110 and a slave interface 103 coupled to the slave device 110. The master device 105 is coupled to the slave device 110 via the master interface 102 and the slave interface 103. The master interface 102 and the slave interface 103 are coupled via the TSV 104 and integrated together as the interface device 101. The interface device 101 is suitable for vertically connecting the master device 105 and the slave device 110, which forms a 3D semiconductor device. The structure of the interface device 101 is called Glink-3D. In addition, the clock generator 115 generates clocks for driving the master device 105, the master interface 102, the slave interface 103, and the slave device 110. The clock generated by the clock generator 115 is used for the master interface 102 and the slave interface 103 in forward and reverse directions.

In the embodiment, the master device 105 and the slave device 110 are respectively implemented as, for example, a processor and a memory (ie, static random access memory (SRAM)). The clock generator 115 is implemented by, for example, an oscillator. The connection between the master interface 102 and the slave interface 103 is implemented by a TSV with a parallel bus for transmission at a sampling rate of up to 5.0 Gbps or a double data rate (DDR) of 2.5 GHz material. The parallel bus is also used for coupling between the slave device 110 and the slave interface 103 and also between the master device 105 and the master interface 102. In the embodiment, the waiting time between the master device 105 and the slave device 110 is set to 1 ns to 2 ns. The data transmission between the master device 105 and the slave device 110 has a low-bit error or no bit error (no bit error, no BER).

FIG. 2 shows a schematic block diagram of a semiconductor device including a master device and a slave device according to an embodiment of the present disclosure. The semiconductor device 200 shown in FIG. 2 is similar to the semiconductor device 100 shown in FIG. 1. The difference is that the clock generator 107 is implemented inside the main device 106 instead of being implemented as an external clock generator as shown in FIG. 1.

FIG. 3 shows a schematic block diagram of a semiconductor device including a master device and a plurality of slave devices according to an embodiment of the present disclosure. The semiconductor device 300 shown in FIG. 3 is similar to the semiconductor device 100 shown in FIG. 1. The difference is that the main device 105 includes a plurality of central processing units (CPUs) 108-1 to 108-M. In addition, the interface device 111 includes a master interface 102 and a plurality of slave interfaces 103-1 to 103-N. Each slave interface 103-1 to 103-N is coupled to each slave device 110-1 to 110-N in a one-to-one relationship. N and M are integers equal to or greater than 1. In addition, the clock generator 115 generates for driving the master device 105 having the plurality of CPUs 108-1 to 108-M, the master interface 102, the plurality of slave interfaces 103-1 to 103-N, and the plurality of One slave 110-1 to 110-N clock. The clock generator 115 may be included in the master device 105 as shown in FIG. 2.

FIG. 4 shows a schematic design diagram of a semiconductor device including a master wafer and a slave wafer according to an embodiment of the present disclosure. The semiconductor device 400 is arranged vertically to form a 3D package, and includes, for example, a master/processor/chip 1 chip 402 coupled with the master interface 404 and a slave/memory/chip 2 chip 408 coupled with the slave interface 410. The processor chip 402 and the memory chip 408 are coupled through the plurality of TSVs 406 via the processor interface 404 and the memory interface 410. In addition, the memory chip 408 includes the plurality of TSVs 412 and the plurality of connectors 414.

FIG. 5 shows a schematic design diagram of a semiconductor device including a master wafer and a plurality of slave wafers according to an embodiment of the present disclosure. The semiconductor device 500 is vertically arranged to form a 3D package, and includes, for example, a master chip 501-1 coupled to a master interface 501-2, and a plurality of first slave chips 502-1 coupled to a plurality of first slave interfaces 502-2. , And a plurality of second slave chips 503-1 coupled to the plurality of second slave interfaces 503-2. The plurality of first slave wafers 502-1 include TSV 502-4. The master interface 501-2 is coupled to the plurality of first slave interfaces 502-2 via the TSV 502-3 and to the plurality of second slave interfaces 503-2 via the TSV 503-3. In addition, the semiconductor device includes a TSV connector 504 that connects the main interface 501-2 to the connector 506.

In an embodiment, the semiconductor device (ie, 500) supports a face-to-face interface and a face-to-back interface. For example, the interface between the master chip 501-1 and the first slave chip 502-1 and/or the interface between the master chip 501-1 and the second slave chip 503-1 is a face-to-face interface. And the face-to-back interface is used for the interface between each first slave chip 502-1 and/or the interface between each second slave chip 503-1.

FIG. 6 shows a schematic 3D diagram of a semiconductor device including a master wafer and a plurality of slave wafers according to an embodiment of the present disclosure. The semiconductor device 600 includes a processor chip including a plurality of CPU core chips and a plurality of SRAM chips connected vertically to the processor chip via Glink-3D as a device interface. The read latency for the round-trip data transfer from the processor chip to the SRAM chip and back to the processor chip is equal to or less than 5 ns. The read latency value is implemented to achieve reliable data communication between the processor chip and the SRAM chip.

FIG. 7 shows a schematic 3D diagram of a semiconductor device including an example of an interface device structure according to an embodiment of the present disclosure. The semiconductor device 700 includes a CPU core chip coupled to a Glink-3D master as a master interface and a cache memory chip coupled to Glink-3D slaves as a slave interface. Glink-3D master is coupled to Glink-3D slaves via TSV. For example, during a read operation, the CPU core chip sends commands to the cache chip via the Glink-3D master and Glink-3D slaves. And then, the cache memory chip receives the command from the CPU core chip. The cache memory chip generates data according to commands and sends the data to the CPU core chip via Glink-3D slaves and Glink-3D master. Finally, the CPU core chip receives data from the cache memory chip. In addition, the data communication between the CPU core chip and the cache memory chip via the Glink-3D master and Glink-3D slaves is driven by the clock generated by the clock generator (ie, 115).

In this embodiment, Glink-3D master and Glink-3D slaves have the same structure and are connected in a one-to-one relationship. For example, each Glink-3D master and Glink-3D slaves includes multiple blocks. Each block is divided into multiple cells, such as 5×5 cells. Each cell of Glink-3D master is connected to each cell of Glink-3D slaves in a one-to-one relationship via TSV. This Glink-3D structure is used as, for example, the physical layer of the advanced microcontroller bus architecture coherent hub interface (AMBA CHI) protocol. The details of the interface device including Glink-3D master and Glink-3D slaves on the 3D semiconductor device and the corresponding implementation will be further elaborated as follows.

FIG. 8 shows a schematic diagram of an interface device including a master interface and a plurality of slave interfaces according to an embodiment of the present disclosure. The schematic 800 may be implemented using multiple electronic components (ie, flip-flop (FF), multiplexer (MUX), inverter, and buffer).

Referring to Figure 8, Glink-3D master is used as the interface of the master chip. Glink-3D slaveK and Glink-3D slaveN are used as the interface of the slaveK chip and the interface of the slaveN chip, respectively. The Glink-3D master, Glink-3D slaveK, and Glink-3D slaveN are driven by the clock clk_in generated by the clock generator (ie, 115). Glink-3D master, Glink-3D slaveK, and Glink-3D slaveN are electrically connected through one or more joints. For example, the Glink-3D master joints 806-1 to 806-3 are connected to the Glink-3D slaveN joints 808-1 to 808-3 in a one-to-one relationship using TSV.

In this embodiment, the Glink-3D master includes FF 802, DDR MUX 804, couplings 806-1 to 806-3, and read first-in first-out (first-in first-out) including multiple FFs 803-1 to 803-3. -first-out, FIFO). The FF 802 is coupled to the DDR MUX 804 and receives the command tx_data command from the host chip. The command tx_data command can be formed as, for example, a data cluster. The command tx_data command may include slave_ID used as the address of the slave chip. The DDR MUX 804 is coupled to the bonding element 806-1 and sends the command tx_data command to the Glink-3D slaveN through the bonding elements 806-1 and 808-1 in the form of a DDR data format. The FF 803-1 is coupled to the FF 803-2 and the coupling 806-3. The FF 803-3 is coupled to the FF 803-2 and the main chip and sends the data rx_data to the main chip. FF 802, DDR MUX 804, combination 806-2, and FF 803-3 are driven by clk_in generated by a clock generator (ie, 115). FF 803-1 and 803-2 are driven by a local clock generated by, for example, Glink-3D slaveN through the combination of 806-3 and 808-3.

In this embodiment, Glink-3D slaveN includes couplings 808-1 to 808-3, FFs 810 to 814, DDR MUX 816, and buffers 818 and 820. The bond 808-1 is coupled to the bond 806-1 and the FF 810 sends the command rx_data command to the slaveN chip. The bond 808-2 is coupled to the bond 806-2 and sends the clock clk to the slaveN chip. The FF 812 is coupled to the DDR MUX 816 and the slaveN chip and receives data tx_data from the slaveN chip. The FF 814 is coupled to the slaveN chip and receives the enable signal tx_en. The buffer 820 is coupled to the DDR MUX 816 and the coupling 808-3 and transmits the data tx_data in the form of the DDR data format. The buffer 818 is coupled to the coupling 808-3 and sends the local clock to the Glink 3D master through the couplings 808-3 and 806-3. FF 810 to FF 814 and DDR MUX 816 are driven by clock clk. The buffers 818 and 820 are driven by the enable signal tx_en. In addition, the slaveK chip and the corresponding Glink-3D slaveK have the same structure and data communication as the slaveN chip and Glink-3D slaveN. The difference between Glink-3D slaveN and Glink-3D slaveK is the generation of the local clock. The process of generating the local clock will be explained later according to FIG. 10.

FIG. 9 shows a schematic diagram of an interface device including a master wafer and a slave wafer during a read operation according to an embodiment of the present disclosure. The schematic diagram 900 is similar to the schematic diagram 800. The difference between the schematic diagram 900 and the schematic diagram 800 is that the schematic diagram 900 shows, for example, a slaveN chip and an SRAM 901 with a corresponding Glink-3D slaveN. In addition, it also includes a logic unit 902 and an FF 904.

Referring to FIG. 9, during a read operation, the master chip sends a command wr_data including a chip identification (ID) as the address of the slave chip N to the SRAM 901 via the Glink-3D master and Glink-3D slaveN. The logic unit 902 is coupled to Glink-3D slaveN, SRAM 901 and FF 904. FF 904 is coupled to Glink-3D slaveN. The logic unit 902 generates a signal for selecting between a chip select (CS) command, a read (read, RD) command, or a write (write, WR) command. The logic unit 902 and the corresponding FF 904 generate the enable signal tx_en. The SRAM 901 generates data tx_data according to the command. Glink-3D slaveN sends data tx_data to Glink-3D master in the form of DDR data format. The master chip reads the data tx_data according to the local clock of Glink-3D slaveN.

FIG. 10 shows a schematic diagram of a slave-to-master interface including a clock tree according to an embodiment of the present disclosure. The schematic diagram 1000 is the same as the schematic diagram 800 and the schematic diagram 900. The difference between the diagram 1000 and the diagram 800 and the diagram 900 is that, from the perspective of the slave to the main interface, the diagram 1000 shows more detailed circuits included in the data path and the clock path. In addition, the clock path has a clock tree (ie, 1019 and 1020) for delivering clocks from the Glink-3D master to each Glink-3D slave. In addition, the timing chart of the data in the form of DDR data format sent from Glink-3D slaveN and Glink-3D slaveK to Glink-3D master is provided.

In this embodiment, each of the slave interface Glink-3D slaveN and other slave interfaces (ie, Glink-3D slaveK) is also configured to use a double data rate (DDR) configuration to transfer data/other data (Ie, tx_data [31:0]) is sent to the main interface. For example, the data tx_data[31:0] is folded into data tx_data[31:16] and data tx_data[15:0]. Each of the data tx_data[31:16] and the data tx_data[15:0] is called, for example, a data cluster.

In this embodiment, the DDR configuration is generated by a DDR unit, and the DDR unit includes a first FF 1002, a second FF 1004, and a multiplexer 1006. The first FF 1002 and the second FF 1004 are represented as the FF 812 shown in FIG. 8, and the multiplexer 1006 is represented by the DDR MUX 816 shown in FIG. 8. The first FF 1002, the second FF 1004, and the multiplexer 1006 are driven by a clock 1019. The first FF 1002 is configured to generate a part of data (ie, data tx_data[31:16]) based on data/other data (tx_data[31:0]). The second FF 1004 is configured to generate another part of data (ie, data tx_data[15:0]) based on data/other data (tx_data[31:0]). The multiplexer 1006 is coupled to the first FF 1002 and the second FF 1004. The multiplexer 1006 is configured to send a part of the data tx_data[31:16] and another part of the data tx_data[15:0] to the master device via the buffer 1008. The buffer 1008 is represented by the buffer 820 shown in FIG. 8. The buffer 1008 is enabled by the enable signal tx_en. The enable signal tx_en shown in FIG. 10 is the same as the enable signal tx_en shown in FIG. 8 and FIG. 9. By enabling the buffer 1008, a part of the data tx_data[31:16] and another part of the data tx_data[15:0] are sent to the Glink-3D master through the combination parts 1011 and 1021.

In another embodiment, each of the slave interface (ie, Glink-3D slaveN) and the other slave interface (ie, Glink-3D slaveK) further includes a first strobe 1015 and a second strobe 1016. The first strobe 1015 and the second strobe 1016 are coupled to the clock path 1019. The first strobe 1015 is configured to generate the first local clock RDQS_F according to the clock clk_in generated by the clock generator (ie, 115). The second strobe 1016 is configured to generate the second local clock RDQS_R according to the clock clk_in generated by the clock generator (ie, 115). The clock path 1019 is a branch of the clock tree (ie, 1019, 1020). The clock clk_in is delivered as clk_out through the bonds 1024 and 1014. The clock path 1019 delivers the clock clk_out to the first FF 1002, the second FF 1004, the buffer 1008, the first strobe 1015, and the second strobe 1016 via the clock path 1019. The buffer 1017 delivers the first local clock RDQS_F to the Glink-3D master through the couplings 1012 and 1022. The buffer 1017 is enabled according to the enable signal tx_en. The enable signal tx_en shown in FIG. 10 is the same as the enable signal tx_en shown in FIG. 8 and FIG. 9. The buffer 1018 delivers the second local clock RDQS_R to the Glink-3D master via the couplings 1013 and 1023. The buffer 1018 is enabled according to the enable signal tx_en. The enable signal tx_en shown in FIG. 10 is the same as the enable signal tx_en shown in FIG. 8 and FIG. 9.

In this embodiment, the first local clock RDQS_F generated by the first strobe 1015 is used by the Glink-3D master to read a part of the data tx_data[31:16] generated by the first FF 1002, and the second strobe The second local clock RDQS_R generated by 1016 is used by the Glink-3D master to read another part of data tx_data[15:0] generated by the second FF 1004. For example, the Glink-3D master includes a unit block configured to read a part of data tx_data[31:16] according to a first local clock RDQS_F and another part of data tx_data[15] according to a second local clock RDQS_R :0]. Glink-3D master uses DDR data format to read part of data tx_data[31:16] and another part of data tx_data[15:0]. Therefore, the Glink-3D master combines a part of the data tx_data[31:16] with another part of the data tx_data[15:0] to generate a complete data rx_data[31:0]. The Glink-3D master then sends the complete data rx_data[31:0] to the processor.

In this embodiment, the Glink-3D master also includes a FIFO unit. The FIFO unit shown in FIG. 10 is also represented as the FIFO unit shown in FIGS. 8 and 9. The FIFO unit can be implemented to obtain the function of the unit block as described above. The FIFO unit can be implemented by multiple FFs (ie, 1031, 1032, 1051, 1041, 1042, 1061). FF 1031 and 1041 represent FF 803-1 shown in Fig. 8. FF 1032 and 1042 represent FF 803-2 shown in FIG. 8. FF 1051 and 1061 represent FF 803-3 shown in Fig. 8. Specifically, the FFs 1031 and 1041 are coupled to the coupling 1021 to receive a part of the data tx_data[31:16] and another part of the data tx_data[15:0]. The FF 1031 is coupled to the coupling 1022 via an inverter 1030 to receive the first local clock RDQS_F. The FF 1041 is coupled to the coupling 1023 to receive the second local clock RDQS_R. FF 1031 and 1041 are coupled to FF 1032 and 1042, respectively, to form a FIFO unit. The number of FFs is not limited to a specific number. The number of FFs can be implemented by any number of FFs.

In addition, the FIFO unit includes FF 1051 and 1061. FF 1051 and 1061 are configured to process a part of data tx_data[31:16] and another part of data tx_data[15:0] based on the DDR data format. FF 1051 is coupled to, for example, FF 1032, and FF 1061 is coupled to, for example, FF 1042. FF 1051 and 1061 are configured to use the clock generated by the clock generator (ie, 115) to transfer part of the data tx_data[31: 16] and another part of the data tx_data[15:0] to re-timing. The re-timing process is implemented to synchronize a part of the data tx_data[31:16] and another part of the data tx_data[15:0] with the clock clk_in. By synchronizing with the clock clk_in, a part of the data tx_data[31:16] and another part of the data tx_data[15:0] are sampled at the same frequency and the same phase using, for example, the command tx_data command generated by the processor.

For example, FF 1031 and 1041 receive a part of data tx_data[31:16] and another part of data tx_data[15:0]. The FF 1031 samples a part of the data tx_data[31:16] through the first local clock RDQS_F received from the first strobe 1015. FF 1031 sends a part of the data tx_data[31:16] to FF 1032. The FF 1051 receives a part of the data tx_data[31:16] from, for example, the FF 1032 and samples a part of the data tx_data[31:16] based on the clock clk_in. Therefore, the FF 1041 samples another part of the data tx_data[15:0] through the second local clock RDQS_R received from the second strobe 1016. FF 1041 sends another part of data tx_data[15:0] to FF 1042. The FF 1061 receives another part of the data tx_data[15:0] from, for example, the FF 1042 and samples the other part of the data tx_data[15:0] based on the clock clk_in. Finally, FFs 1051 and 1061 generate complete data rx_data[31:0] and send the complete data rx_data[31:0] to the processor. In other words, the FIFO unit of the Glink-3D master processes the data tx_data[31:0] received from, for example, the Glink-3D slaveN to generate complete data rx_data[31:0] based on the DDR data format.

In another embodiment, referring to FIG. 10, the main device (ie, the processor) further generates a steering (TA) loop. The TA loop is, for example, the interval between the data tx_data of Glink-3D slaveN and the data tx_data of Glink-3D slaveK received at the coupling 1021 by the FIFO unit of the Glink-3D master. For example, the data tx_data received by the FIFO unit of the Glink-3D master at the coupling 1021 refers to the Master RX_D. The Master RX_D received from Glink-3D slaveN contains data DN[15:0] and DN[31:16]. The Master RX_D received from Glink-3D slaveK contains data DK[15:0] and DK[31:16]. In other words, TA loop is the interval between data DN[31:16] and data DK[15:0].

In this embodiment, the TA loop is used to prevent bus competition between the response of the slave device (ie, the slaveN device) and the response of other slave devices (ie, the slaveK device). For example, during a read operation, the master device/processor uses the allocated time slot to send a command including the slave ID to the slaveN device and the slaveK device. The slaveN device and the slaveK device respectively send the data and the local clock to the processor via the Glink-3D slaveN and Glink-3D slaveK according to the allocated time slots. The slaveN device and slaveK device use the data bus according to the allocated time slot. The Glink-3D slaveN sends the data tx_data[31:0] to the Glink-3D master through the combination 1011. The Glink-3D slaveN also sends the first local clock RDQS_F and the second local clock RDQS_R to the Glink-3D master through the combination parts 1012 and 1013, respectively. The Glink-3D master receives the data DN[15:0] and DN[31:16] from the Glink-3D slaveN at the junction 1021. The Glink-3D master uses the second local clock RDQS_R to sample data DN[15:0]. The Glink-3D master uses the first local clock RDQS_F to sample the data DN[31:16].

And then, Glink-3D slaveK sends the data tx_data[31:0] to the Glink-3D master via the corresponding combination of Glink-3D slaveK. The Glink-3D slaveK also sends the first local clock RDQS_F and the second local clock RDQS_R to the Glink-3D master via the corresponding combination of the Glink-3D slaveK. After the TA loop, the Glink-3D master receives the data DK[15:0] and DK[31:16] from the Glink-3D slaveK at the junction 1021. The Glink-3D master uses the second local clock RDQS_R to sample the data DK[15:0]. The Glink-3D master uses the first local clock RDQS_F to sample the data DK[31:16].

In other words, during the transfer of data from the slaveN device and the slaveK device to the processor, by providing the time slot for the slaveN and slaveK to use the data bus, the TA loop will prevent the bus competition between the slaveN device and the slaveK device. .

In this embodiment, the TA loop is used to compensate for the round-trip-delays (RTD) difference between the slave device and other slave devices. RTD is the interval between the command sent by the Glink-3D master and the data received by the Glink-3D master. Since each slave device is produced by, for example, a different manufacturing company, each slave device has different response characteristics. Response characteristics include RTD. The RTD difference between the slave devices is compensated by the TA loop.

For example, during a read operation, the slaveN device and the slaveK device receive commands from the processor via Glink-3D slaveN and Glink-3D slaveK, respectively. Since slaveN devices and slaveK devices have different RTDs, the Glink-3D master receives data from Glink-3D slaveN and Glink-3D slaveK at different times. Although the Glink-3D master has been equipped with a pull-down function, if the RTD difference is greater than the difference between the allocated time slots of the processor to the slaveN device and the slaveK device, bus contention may occur. Therefore, by adding TA loops and RTD differences (ie, 1 loop +/-ΔRTD, 1.5 loops +/-ΔRTD), from Glink-3D slaveN (DN[15:0] and DN[31:16 ]) The interval between the time of receiving data and the time of receiving data from Glink-3D slaveK (DK[15:0] and DK[31:16]) is maintained. In this way, bus contention can be avoided.

FIG. 11 shows a schematic timing diagram of data between two slave chips having the same clock speed according to an embodiment of the present disclosure. And FIG. 12 shows a schematic timing diagram of data between two slave chips with different clock speeds according to an embodiment of the present disclosure. SlaveN devices and slaveK devices are used as examples of timing diagrams.

In this embodiment, the slave device (ie, slaveN device) and other slave devices (ie, slaveK device) generate zero data before and after the data to prevent the difference between the slave device and other slave devices due to different RTDs. Bus competition between. Referring to FIG. 11, the clock slaveK clk_B speed and the clock slaveN clk_B speed have the same speed (ie, normal/typical speed). The slaveK device is equipped with an enable signal tx_en and sends the data tx_dataK to the master device via Glink-3D slaveK. The Glink-3D slaveK delivers the data dataK to the Glink-3D master through a combination (ie, 1011). Therefore, Glink-3D slaveK sends the zero data before the data dataK and the zero data after the data dataK to the Glink-3D master through the combination (ie, 1011). Glink-3D slaveK also generates local clocks RDQS_R and RDQS_F.

On the other hand, the slaveN device is equipped with an enable signal tx_en and sends the data tx_dataN0 and tx_dataN1 to the master device via the Glink-3D slaveN. The Glink-3D slaveN delivers the data dataN0 and dataN1 to the Glink-3D master via the corresponding combination. Therefore, Glink-3D slaveN sends the zero data before dataN0 and dataN1 and the zero data after dataN0 and dataN1 to the Glink-3D master via the corresponding combination. Glink-3D slaveN also generates local clocks RDQS_R and RDQS_F. Since the data dataK is equipped with zero data after the data dataK and the data dataN0 is equipped with zero data before the dataN0, there is an interval (ie, 1T TA time) between the data dataK and the dataN0. That is to say, the zero data generated by the slaveN device and the slaveK device generates an interval (ie, 1T TA time) between the data dataK and the dataN0 to prevent the clock slaveK clk_B and the clock slaveN clk_B from having the same speed. Bus competition between slaveN devices and slaveK devices.

In another embodiment, referring to FIG. 12, the difference between the embodiment shown in FIG. 11 and the embodiment shown in FIG. 12 is that the clock slaveK clk_B speed and the clock slaveN clk_B speed have different speeds. For example, the clock slaveK clk_B is slow and the clock slaveN clk_B is fast. In other words, the clock slaveN clk_B is faster than the clock slaveK clk_B. In other words, the clock slaveN clk_B is earlier than the clock slaveK clk_B. The interval of the earlier clock is less than 1T (<400 ps for 2.5 GHz). Since the data dataK is equipped with the zero data before the data dataK and the zero data after the data dataK, and the data dataN0 is equipped with the zero data before the dataN0, there is an interval (<1T) between the clock slaveN clk_B and the clock slaveK clk_B and There is an interval (TA time) between data dataK and dataN0.

In other words, the zero data generated by the slaveN device and the slaveK device generates an interval (TA time) between the data dataK and the dataN0 to prevent the slaveN device and the slaveK from having different speeds in the clock slaveK clk_B and the clock slaveN clk_B. Bus competition between devices.

FIG. 13 shows a schematic timing diagram of data between two slave wafers with 2 TA loops according to an embodiment of the present disclosure. The timing diagram 1300 includes 2 read waiting time loops and 2 TA loops. The read waiting time is the interval between the time when the Glink-3D slave receives a command from the master device through the corresponding combination and the time when the Glink-3D slave sends data according to the command through the corresponding combination.

Specifically, for example, during a read operation, Glink-3D slaveK and Glink-3D slaveN receive the command s_cmd including the slave ID d_did and the corresponding clock clk_out. The master device sends the command NOP between the read command RD sent to the slaveK device and the preamble command PA sent to the slaveN device. The command NOP is a no-operation command. The preamble command PA is a command used to prepare data from the device. The read command RD is a read command used by the slave device to send data after the slave device has prepared the data.

In this embodiment, the slaveK device sends data (ie, tx_dataK, the preamble) at an earlier allocated time slot than the slaveN device sends data according to the time slot allocated by the master device (ie, tx_dataN, the preamble). When the enable signal tx_en (ie, 1) is activated, the data sent by the slaveK device (ie, tx_dataK, preamble) and/or the data sent by the slaveN device (ie, tx_dataN, preamble) are delivered to the corresponding slave component TX_D. Conversely, when the enable signal tx_en is deactivated (ie, 0), the data sent by the slaveK device (ie, tx_dataK, preamble) and/or the data sent by the slaveN device (ie, tx_dataN, preamble) are delivered to the corresponding The slave unit TX_D. In the case that the read waiting time has 2 loops, for example, the interval between the command NOP received by Glink-3D slaveK and the data dataK sent by Glink-3D slaveK in the corresponding slave TX_D is 2 loops . The read waiting time with 2 loops corresponds to the command NOP sent by the master device. On the other hand, when the TA has 2 loops, the data dataK sent by the Glink-3D slaveK at the corresponding slave connector TX_D and the data dataN sent by the Glink-3D slaveN at the corresponding slave connector TX_D The interval between is 2 cycles +/- ΔRTD.

In other words, the TA with 2 loops tolerates a difference of up to 2T and can be set by the master device by adding the command NOP before the preamble command PA. In addition, in the case where the RTD difference is less than 1 cycle T (400 ps for 2.5 GHz), a TA with 1 loop is sufficient.

FIG. 14 shows a schematic comparison of the first gating unit and the second gating unit before and after training according to an embodiment of the present disclosure. The block diagram 1400 shown in FIG. 14 represents the block diagram 1000 shown in FIG. 10. The difference between FIG. 14 and FIG. 10 is that the circuit diagram 1400 includes a comparison of the first strobe 1015 and the second strobe 1016 before and after training.

In this embodiment, the slave device (ie, slaveN device) and other slave devices (ie, slaveK device) train the first strobe 1015 and the second strobe 1016 to locate a part of the data at the best data sampling point (ie, DN [31:16]) and another part of the data (ie, DN[15:0]). One part of the data (ie, DN[31:16]) and another part of the data (ie, DN[15:0]) are called, for example, a data cluster. Specifically, when the semiconductor device is turned on/on, the master device selects the slave devices one by one for training. For example, the master device selects the slaveN device. The slaveN device selected by the master device manages the training sequence described below. The slaveN device sets the first strobe 1015 and the second strobe 1016 of the Glink-3D slaveN to zero. The first strobe 1015 and the second strobe 1016 are represented by the first local clock RDQS_F Initial and the second local clock RDQS_R Initial. And then, the slaveN device sends the BIST data (ie, DN[31:16] and DN[15:0]) to the master device. The master device receives the BIST data (ie, DN[31:16] and DN[15:0]) at the corresponding master combination, and the BIST data is represented by, for example, RX_D. The master device separately reports the pass/fail of the data DN[31:16] and DN[15:0] to the slaveN device. The slaveN device increments the phase of the first local clock RDQS_F Initial and the phase of the second local clock RDQS_R Initial. Continue the process of increasing the phase of the first local clock RDQS_F Initial and the phase of the second local clock RDQS_R Initial until the slaveN device receives the first pass and the last pass reported by the master device. When the master device reports that the last one passed, the slaveN device stops sending BIST data to the master device. For example, after the master device reports a pass, the last pass is obtained after the report fails. And then, the slaveN device sets the phase of the first local clock and the phase of the second local clock at an intermediate point by, for example, dividing the total pass by two. Therefore, the slaveN device sends ready data to the master device. The first pass is represented by, for example, RDQS_F Initial of the first local clock and RDQS_R Initial of the second local clock, respectively. The intermediate point is represented by, for example, RDQS_F Trained of the first local clock and RDQS_R Trained of the second local clock, respectively. The middle point represents the best data sampling point.

That is to say, the optimal data sampling point is obtained by individually increasing the phase of the first local clock of the first gate 1015 and increasing the phase of the second local clock of the second gate 1016 until the optimum sampling is obtained point.

In another embodiment, the slave device (ie, slaveN device) uses the first clock of the first strobe of the master interface Glink-3D master and the second clock of the second strobe to update the slave interface (Glink-3D slaveN) The first local clock of the first strobe and the second local clock of the second strobe are used to compensate for voltage-to-temperature (VT) changes.

For example, a semiconductor device has a normal temperature during normal processing and a high temperature during high temperature processing. The data sent from the Glink-3D slave device (ie, slaveN device) to the master device via the slave interface (ie, Glink-3D slaveN) during the high temperature period has, for example, a longer duration/period than during the normal temperature period. The slaveN device updates the phase of the first local clock (ie, RDQS_F Trained) and the phase of the second local clock (ie, RDQS_R Trained) according to the period of the data at high temperature and the period of the data at room temperature. The update process is carried out by comparing the middle point of the data at room temperature with the middle point of the data at high temperature.

That is, by updating the phase of the first local clock and the phase of the second local clock of the slave interface at different temperatures according to the first clock and the second clock of the master interface, the V-T change can be compensated. Therefore, the master interface samples the data received from the slave interface at the optimal data sampling point.

FIG. 15 shows a schematic flowchart of DLL training according to an embodiment of the present disclosure. The flowchart 1500 is executed before the DLL training starts. DLL training aims to obtain the maximum step of DLL. The maximum step of the DLL refers to the ability of the DLL to delay the clock in the slave interface (ie, Glink-3D slaveN). DLL refers to the first strobe 1015 and the second strobe 1016. DLL training is carried out under two different perspectives, the two different perspectives including an internal integrated circuit (Inter-Integrated Circuit, I2C) sequence and a slave sequence. The I2C sequence is a flowchart implemented in the I2C protocol. And the slave sequence is a flowchart executed in the slave device.

In the I2C sequence, DLL training is performed from step S1505 to step S1520. In step S1505, the DLL value is cleared/reset. And then, in step S1510, the register of each slave device is set to enable DLL training by, for example, changing the DLL training flag to 1. The register used to enable DLL training refers to the accumulator (ACC). In step S1515, the slave flag indicating the completion of the DLL training is checked. Step S1515 is performed until the slave flag indicating that the DLL training is completed is set by, for example, changing the corresponding flag to 1. Step S1515 is performed on all slave devices (ie, slaveN devices, slaveK devices). In step S1520, when the corresponding flags of all slave devices are set, the DLL training flag is reset by, for example, changing the DLL training flag to 0. By doing so, the register of each slave device that represents DLL training is disabled. That is, by performing steps S1505 to S1520, the maximum step/delay of the DLL of each slave device is obtained.

In the slave sequence, DLL training is performed through steps S1555 to S1575. In step S1555, the slave device (ie, slaveN device) checks whether the DLL training is enabled. In step S1560, if DLL training is enabled, the DLL value is increased by, for example, adding 1 to the DLL value. In step S1565, the lagging flag and the leading flag are checked. If the DLL value is the largest, the lag flag displays 0 and the advance flag displays 1; therefore, if the DLL value is not the largest, step S1560 is repeated. If the DLL value is the largest, the step continues to step S1570 by reducing the DLL value by one. The reason for reducing the DLL value by 1 is that when the condition in step S1565 is No, the maximum value represents the final value of the DLL value in the condition. Finally, in step S1575, the slave device sets a flag indicating that the DLL training is completed. In other words, the flag indicating the completion of the DLL indicates that the DLL training of the slave device (ie, the slaveN device) is completed. Therefore, the maximum DLL value is obtained. Steps S1555 to S1575 are executed by each slave device.

FIG. 16 shows a schematic flowchart of writing data cluster training according to an embodiment of the present disclosure. After obtaining the maximum DLL value according to the flowchart 1500, the DLL training is continued by writing data cluster training as shown in the flowchart 1600. Since the data-writing cluster training is to write data from the processor 105 to the slave devices (ie, slaveN devices, slaveK devices) according to the optimal clock phase, the data-writing cluster training refers to master-to-slave training. The written data cluster training is implemented under different perspectives, which include the I2C sequence, the master sequence, and the slave sequence. The purpose of data writing cluster training is to obtain the intermediate value of the DLL during data writing. By writing data according to the intermediate value of the DLL, the data is written correctly, and therefore, bit errors can be minimized. The middle value of DLL represents the best clock phase.

In the I2C sequence, write data cluster training is performed in steps S1605 to S1625. In step S1605, the corresponding register of the processor 105 is set to enable the write data cluster training. In step S1610, the register of each slave device is set to enable the write data cluster training. In step S1615, the register of each slave device corresponding to the completion of the write-in data cluster training is checked. If the register of each slave device corresponding to the completion of the write data cluster training is set, step S1620 is performed by disabling the register of each slave device. In step S1625, the register of the processor 105 is disabled. In other words, by obtaining the register of each slave device corresponding to the completion of the written data cluster training, the DLL value of each slave device used for writing data has been optimized. Therefore, bit errors can be minimized.

In the main sequence, write data cluster training is performed in steps S1630 to S1645. In step S1630, the processor 105 checks whether the write data cluster training is enabled. If the write data cluster training is enabled, then in step S1635, the BIST generator is enabled. In step S1640, the processor 105 checks whether the write data cluster training is disabled. When the write data cluster training for all slave devices has been completed, disable the write data cluster training. In step S1645, since the write data cluster training for all slave devices has been completed, the BIST generator is disabled. In other words, the cluster training is disabled by obtaining the written data, and the written data cluster training for all slave devices has been completed. Therefore, the optimal clock phase for writing data has been obtained.

In the slave sequence, write data cluster training is performed in steps S1650 to S1695. In step S1650, the register corresponding to the activation of the write data cluster training is checked. In response to the write data cluster training being enabled, in step S1655, the DLL value is set to 0. In step S1660, the BIST checker is enabled. By enabling the BIST checker, the BIST generated by the processor 105 is checked. In step S1665, the BIST is checked within X times, for example. X represents an integer value equal to or greater than 1. X can also indicate the duration of the BIST check. If the BIST has been checked X times, the BIST checker is disabled in step S1670. In step S1675, the DLL window indicating the pass value is updated. The pass value indicates that the slave device reads the BIST correctly. In step S1680, it is checked whether the DLL value reaches the maximum value. The maximum value of DLL has been obtained according to Figure 15. If the DLL value is not the maximum value, the DLL value is increased in step S1685. And then, steps S1660 to S1685 are repeated until the DLL value reaches the maximum cycle/value. In step S1690, if the DLL value reaches the maximum cycle, the DLL value is set to the middle value through the window. The middle value through the window indicates that the BIST is written to the slave device at the optimal clock phase. In step S1695, by changing the corresponding flag to 1, for example, a register indicating the completion of the write data cluster training is set. In the main sequence, the processor 105 checks this flag to determine that the write data cluster training for all slave devices has been completed.

Fig. 17 shows a schematic flow chart of reading data cluster training according to an embodiment of the present disclosure. The flowchart 1700 can be implemented after the flowchart 1600. Perform reading data cluster training to obtain the best clock phase for reading data. The reading data cluster training is implemented under different perspectives, which include the I2C sequence, the master sequence, and the slave sequence.

In the I2C sequence, read data cluster training is performed in steps S1702 to S1716. In step S1702, the maximum DLL value is read from the corresponding register of the slave device. In step S1704, the DLL value read from the corresponding register of the slave device is written to the register of the processor 105. In step S1706, a corresponding flag indicating that the read data cluster training is enabled is set to the register of the slave device. In step S1708, a corresponding flag indicating that the read data cluster training is enabled is set to the register of the processor 105. In step S1710, the slave device checks the corresponding flag indicating that the training of the read data cluster is completed. In step S1712, if the corresponding flag indicating that the training of the reading data cluster is completed is enabled, the corresponding flag of the processor 105 indicating the training of the reading data cluster is disabled. In step S1714, the corresponding flag representing the slave device of the read data cluster training is disabled. In step S1716, it is checked whether each slave device has implemented read data cluster training. If one or more slave devices have not implemented the data-reading cluster training process, steps S1706 to S1716 are repeated until all the slave devices have implemented the data-reading cluster training. That is to say, by obtaining the corresponding flag of each slave device's register has been enabled, each slave device has implemented read data cluster training.

In the main sequence, read data cluster training is performed in steps S1720 to S1748. In step S1720, the processor 105 checks the flag of the register corresponding to the read data cluster training. In step S1722, if the flag of the register corresponding to the read data cluster training is enabled, the DLL value is set to 0. In step S1724, the processor 105 sets a command for updating the value of DLL_r. In step S1726, the processor 105 sets a command for updating the value of DLL_f. In step S1728, the processor 105 resets the read FIFO. The reason why the read FIFO needs to be reset is to prevent the processor 105 from reading the wrong read data sequence from the slave device. If the read FIFO is not cleared, the data sequence in the read FIFO may not indicate the correct data sequence. In step S1730, the processor 105 sets a command for enabling tx_en. In step S1732, the processor 105 enables the BIST checker. By enabling the BIST checker, the processor is ready to read the BIST data generated by the slave device. In step S1734, the BIST data generated by the slave device is read in X times. X has been explained in the foregoing description. In step S1736, if the BIST data has been read within X times, the processor 105 disables the BIST checker. In step S1738, the processor 105 sets a command for disabling tx_en. In step S1740, the processor 105 updates the through window. Through the window has been explained in the foregoing description. In step S1742, it is checked whether the DLL value reaches the maximum cycle/value. In step S1744, if the DLL value does not reach the maximum cycle, the DLL is increased. And then, steps S1724 to S1744 are repeated until the DLL value reaches the maximum value. In step S1746, if the DLL value has reached the maximum value, the DLL is set to the middle value of the pass window of the slave device. In step S1748, a flag indicating completion of the training of the read data cluster is set.

In the slave sequence, read data cluster training is performed in steps S1750 to S1766. In step S1750, the flag corresponding to the activation of the read data cluster training is checked. In step S1752, if a flag corresponding to the activation of the read data cluster training is set, the BIST generator is activated. By enabling the BIST generator, the slave device generates BIST data and sends the BIST data to the processor 105 accordingly. In step S1754, the slave device checks whether the processor 105 sets tx_en according to the command. In step S1756, the processor 105 sets tx_en according to the command, and the slave device enables tx_en. In step S1758, the slave device checks whether the processor 105 clears tx_en according to the command. In step S1760, the processor 105 clears tx_en according to the command, and the slave device disables tx_en. In step S1762, the slave device checks whether DLL_rot or DLL_f is updated. If DLL_r or DLL_f is updated, steps S1754 to S1762 are repeated. In step S1764, if the slave device does not update DLL_r or DLL_f, a flag indicating that the read data cluster training is disabled is checked. If the flag indicating the training of the read data cluster is not disabled, steps S1762 to S1764 are repeated. In step S1766, if the flag indicating the training of the read data cluster is disabled, the BIST generator is disabled. In other words, the slave device updates DLL_r and/or DLL_f by performing read data cluster training.

In addition, examples of commands for reading data cluster training are provided as follows. Since the DLL value used in the read data cluster training is 9 bits, these 9 bits are passed to the first bit (S_CMD[0]) of the read command and the 4 bits from the master ID (S_DID[3: 0]) and the 4 bits of the master to slave ID (M_DID[3:0]) are combined to generate. On the other hand, the command is generated by combining the second bit (S_CMD[1]) of the read command and 2 bits (M_CMD[1:0]) of the write command. For example, the command generates an IDLE command by setting the bit value to {0, 0, 0}. The command generates an update DLL_r value command by setting the bit value to {0, 0, 1}. The command generates an update DLL_f value command by setting the bit value to {0,1,0}. The command generates an update DLL value command by setting the bit value to {0, 1, 1}. The command generates the tx_en enable command by setting the bit value to {1,0,1}. The command generates the tx_en disable command by setting the bit value to {1,1,0}.

FIG. 18 shows an interface method according to an embodiment of the present disclosure. In step S1805, the interface method of the semiconductor device is started by sending a command from the master interface to the slave device. In step S1810, the interface method is continued by receiving commands from the master device and/or sending data/other data to the master device by each of the slave interface and the other slave interfaces. Step S1810 includes using double data rate (DDR) configuration to send data/other data to the main interface in step S1815. Step S1815 includes steps S1820 to S1840. In step 1820, the device method is continued by generating a part of the data based on the data/other data by the first flip-flop (FF) unit. In step S1825, the device method is continued by generating another part of data from the data/other data by the second FF unit. In step S1830, the device method is continued by sending part of the data and another part of the data to the master device by the multiplexer. In step 1835, the device method is continued by generating the first local clock by the first gating unit according to the clock generated by the clock generator. In step S1840, the device method is continued by generating a second local clock by the second gating unit according to the clock generated by the clock generator. And then, in step S1845, the master interface receives data from the slave device to continue the device method. Step S1845 includes using the clock generated by the clock generator in step S1850 by the master interface to re-time a part of the data and another part of the data from the DDR unit of the slave interface and other slave interfaces.

In short, the interface device and interface method used for 3D semiconductor devices provide reliable data communication between the master device and the slave device. Reliable data communication is achieved by providing specific time slots to each slave device. The master device also provides the data waiting time between the slave devices. By doing so, bus competition between slave devices can be avoided. In addition, in order to sample the data with the best sampling phase, when the semiconductor device is turned on/on, the slave device trains the local clock. By training the local clock, the data can be sampled at the best data sampling point, so that the error rate can be reduced. In addition, the slave device also updates the local clock to compensate for the T-V change of the semiconductor device.

In another embodiment, an interface device for interfacing between a master device and a slave device is provided, wherein the master device generates a command and the slave device generates data according to the command, and the interface device includes a master interface And from the interface. The main interface is coupled to the main device. The master interface is configured to send the command to the slave device and/or receive the data from the slave device. The slave interface is coupled to the slave device. The slave interface is configured to receive the command from the master device and/or send the data to the master device. The master interface and the slave interface are driven by clocks generated by a clock generator. The master interface and the slave interface are electrically connected by one or more couplings and/or TSVs. The clock used to drive the slave interface is trained by changing the clock phase of the clock to be aligned with the command data cluster and/or the data cluster of the data.

In another embodiment, the interface device further includes other slave interfaces. The other slave interfaces are coupled to other slave devices in a one-to-one relationship. The other slave interface is configured to receive the command from the master device and/or send other data generated by the other slave device to the master device. The other slave interface is driven by the clock generated by the clock generator and is electrically connected to the master interface through the one or more coupling members and/or the TSV. Each clock used to drive each of the other slave interfaces is performed by changing the clock phase of each clock to the data cluster and/or all of the commands corresponding to each of the other slave interfaces. The data clusters of the data are aligned for training.

In another embodiment, each of the slave interface and the other slave interfaces is further configured to use a double data rate (DDR) configuration to send the data/the other data to the master interface. The DDR configuration is generated by the DDR unit. The DDR unit includes a first flip-flop (FF) unit, a second flip-flop unit, and a multiplexer. The first FF unit is configured to generate a part of data based on the data/the other data. The second FF unit is configured to generate another part of data based on the data/the other data. The multiplexer is coupled to the first FF unit and the second FF unit. The multiplexer is configured to send the part of the data and the other part of the data to the main device.

In another embodiment, each of the slave interface and the other slave interfaces further includes a first gating unit and a second gating unit. The first gating unit is configured to generate a first local clock according to the clock generated by the clock generator. The second gating unit is configured to generate a second local clock according to the clock generated by the clock generator. The first local clock generated by the first gating unit is used by the main interface to read the part of the data generated by the first FF unit. The second local clock generated by the second gating unit is used by the main interface to read the other part of the data generated by the second FF unit.

In another embodiment, the main device also generates a steering (TA) loop. The TA loop is used to prevent bus competition between the response of the slave device and the response of the other slave devices. In another embodiment, the TA loop is used to compensate for the round trip delay (RTD) difference between the slave device and the other slave devices. In another embodiment, the slave device and the other slave devices generate zero data before the data and after the data to prevent the slave device and the other slave devices from being caused by different RTDs. Competition between slave devices. In another embodiment, the master interface further includes a first-in-first-out (FIFO) unit configured to use the clock pair generated by the clock generator from the slave interface and all The part of the data and the other part of the data of the DDR unit of the other slave interface are timed again. In another embodiment, the slave device and the other slave devices train the first gating unit and the second gating unit to locate the part of the data and all the data at the optimal data sampling point. State another part of the information.

In another embodiment, an interface method for interfacing between a master device and a slave device is provided, wherein the master device generates a command and the slave device generates data according to the command, and the interface method includes: The master interface sends the command to the slave device and/or receives the data from the slave device; and the slave interface receives the command from the master device and/or sends the data to the slave device. The main device. The master interface and the slave interface are driven by clocks generated by a clock generator. The master interface and the slave interface are electrically connected by one or more couplings and/or TSVs. The clock used to drive the slave interface is trained by changing the clock phase of the clock to be aligned with the command data cluster and/or the data cluster of the data.

In another embodiment, the interface method further includes: receiving the command from the master device by another slave interface and/or sending other data generated by the other slave device to the master device. The other slave interface is driven by the clock generated by the clock generator and is electrically connected to the master interface through the one or more coupling members and/or the TSV. Each clock used to drive each of the other slave interfaces is performed by changing the clock phase of each clock to the data cluster and/or all of the commands corresponding to each of the other slave interfaces. The data clusters of the data are aligned for training.

In another embodiment, each of the slave interface and the other slave interfaces receiving the command from the master device and/or sending the data/the other data to the master device further includes : Use double data rate (DDR) configuration to send the data/the other data to the main interface. Using the double data rate (DDR) configuration to send the data/the other data to the main interface further includes: generating a part of the data according to the data/the other data by the first flip-flop (FF) unit; The second FF unit generates another part of the data according to the data/the other data; and the multiplexer sends the part of the data and the other part of the data to the main device.

In another embodiment, using the DDR configuration to send the data/the other data to the main interface further includes: generating, by the first gating unit, a first local device according to the clock generated by the clock generator. Clock; and the second gating unit generates a second local clock according to the clock generated by the clock generator. The first local clock generated by the first gating unit is used by the main interface to read the part of the data generated by the first FF unit. The second local clock generated by the second gating unit is used by the main interface to read the other part of the data generated by the second FF unit.

In another embodiment, the main device also generates a steering (TA) loop. The TA loop is used to prevent bus competition between the response of the slave device and the response of the other slave devices. In another embodiment, the TA loop is used to compensate for the round trip delay (RTD) difference between the slave device and the other slave devices. In another embodiment, the slave device and the other slave devices generate zero data before the data and after the data to prevent the slave device and the other slave devices from being caused by different RTDs. Competition between slave devices. In another embodiment, sending the command to the slave device by the master interface and/or receiving the data from the slave device further includes: using the clock pair generated by the clock generator The part of the data and the other part of the data from the DDR unit of the slave interface and the other slave interfaces are retimed. In another embodiment, the slave device and the other slave devices train the first gating unit and the second gating unit to locate the part of the data and all the data at the optimal data sampling point. State another part of the information.

The features of several embodiments have been summarized above so that those skilled in the art can better understand the following detailed description. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose as the embodiments described herein and/or achieve the implementations described herein Example of the same advantages. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and alterations in this article without departing from the spirit and scope of the present disclosure. .

100, 200, 300, 400, 500, 600, 700: semiconductor devices 101, 111: Interface devices 102, 501-2: Main interface 103, 103-1～103-N, Glink-3D slaves: slave interface 104, 406, 412, 502-3, 502-4, 503-3: silicon through hole 105, 106: master device 107, 115: clock generator 108-1～108-M: Central processing unit 110, 110-1～110-N: Slave device 120, 501-1: main chip 130: Slave chip 402: Chip 404: Interface 408: Chip 410: Interface 414, 506: connectors 502-1: The first slave chip 502-2: The first slave interface 503-1: The second slave chip 503-2: The second slave interface 504: TSV connector 800, 900, 1000: schematic diagram 802, 803-1, 803-2, 803-3, 810, 812, 814, 904, 1031, 1032, 1041, 1042, 1051, 1061: flip-flop (FF) 804, 816: Double Data Rate (DDR) Multiplexer (MUX) 806-1, 806-2, 806-3: Combination 808-1, 808-2, 808-3: combination parts 818, 820, 1008, 1017, 1018: buffer 901: SRAM 902: Logic Unit 1002: First FF 1004: second FF 1006: multiplexer 1011, 1012, 1013, 1014, 1021, 1022, 1023, 1024: combination 1015: first gate 1016: second strobe 1019: clock path 1020: clock tree 1030: inverter 1300: Timing diagram 1400: circuit diagram 1500, 1600, 1700: flow chart address wr_data, NOP, rx_data command, s_cmd, tx_data command: command clk, clk_in, clk_out, slaveK clk_B, slaveN clk_B: clock d_did: Slave ID dataK, dataN0, dataN1, DK[15:0], DK[31:16], DN[15:0], DN[31:16], Master RX_D, rx_data, rx_data[31:0], tx_data, tx_data[ 31:16], tx_data[15:0], tx_dataK, tx_dataN, tx_dataN0, tx_dataN1: data Glink-3D: Device interface Glink-3D master: main interface Glink-3D slaveK, Glink-3D slaveN: slave interface PA: pre-synchronization command RD: Read command RDQS_F: local clock RDQS_F Initial: local clock RDQS_R: local clock RDQS_R Initial: local clock RDQS_F Trained, RDQS_R Trained: phase S1505, S1510, S1515, S1520, S1555, S1560, S1565, S1570, S1575, S1605, S1610, S1615, S1620, S1625, S1630, S1635, S1640, S1645, S1650, S1655, S1660, S1665, S1670, S1675, S1675, S1685, S1690, S1695, S1702, S1704, S1706, S1708, S1710, S1712, S1714, S1716, S1720, S1722, S1724, S1726, S1728, S1730, S1732, S1734, S1736, S1738, S1740, S1742, S1744, S1746, S1748, S1750, S1752, S1754, S1756, S1758, S1760, S1762, S1764, S1766, S1805, S1810, S1815, 1820, S1825, S1830, 1835, S1840, S1845, S1850: Step slave_ID: slave chip address slaveN, slaveK: chip TX_D: From the combined piece tx_data [31:0]: data tx_en: enable signal

FIG. 1 shows a schematic block diagram of a semiconductor device including a master device and a slave device according to an embodiment of the present disclosure. FIG. 2 shows a schematic block diagram of a semiconductor device including a master device and a slave device according to an embodiment of the present disclosure. FIG. 3 shows a schematic block diagram of a semiconductor device including a master device and a plurality of slave devices according to an embodiment of the present disclosure. FIG. 4 shows a schematic design diagram of a semiconductor device including a master wafer and a slave wafer according to an embodiment of the present disclosure. FIG. 5 shows a schematic design diagram of a semiconductor device including a master wafer and a plurality of slave wafers according to an embodiment of the present disclosure. FIG. 6 shows a schematic 3D diagram of a semiconductor device including a master wafer and a plurality of slave wafers according to an embodiment of the present disclosure. FIG. 7 shows a schematic 3D diagram of a semiconductor device including an example of an interface device structure according to an embodiment of the present disclosure. FIG. 8 shows a schematic diagram of an interface device including a master interface and a plurality of slave interfaces according to an embodiment of the present disclosure. FIG. 9 shows a schematic diagram of an interface device including a master wafer and a slave wafer during a read operation according to an embodiment of the present disclosure. FIG. 10 shows a schematic diagram of a slave-to-master interface including a clock tree according to an embodiment of the present disclosure. FIG. 11 shows a schematic timing diagram of data between two slave chips having the same local clock speed according to an embodiment of the present disclosure. FIG. 12 shows a schematic timing diagram of data between two slave chips with different clock speeds according to an embodiment of the present disclosure. FIG. 13 shows a schematic timing diagram of data between two slave wafers with 2 turn-around (TA) loops according to an embodiment of the present disclosure. FIG. 14 shows a schematic comparison of the first gating unit and the second gating unit before and after training according to an embodiment of the present disclosure. FIG. 15 shows a schematic flowchart of delay lock loop (DLL) training according to an embodiment of the present disclosure. FIG. 16 shows a schematic flowchart of writing data cluster training according to an embodiment of the present disclosure. Fig. 17 shows a schematic flow chart of reading data cluster training according to an embodiment of the present disclosure. FIG. 18 shows an interface method according to an embodiment of the present disclosure.

102: Main Interface

103-1, 103-N:

105: master device

108-1, 108-M: Central Processing Unit (CPU)

110-1, 110-N: Slave device

111: Interface device

115: clock generator

300: semiconductor device

Claims (20)

An interface device for performing an interface between a master device and a slave device, wherein the master device generates a command and the slave device generates data according to the command, and the interface device includes: a master interface coupled to the master A device configured to send the command to the slave device and/or receive the data from the slave device; and a slave interface, coupled to the slave device, configured to receive the data from the master device Command and/or send the data to the master device, wherein the master interface and the slave interface are driven by a clock generated by a clock generator; the master interface and the slave interface are composed of one or more combination components And/or silicon via for electrical connection, and the clock used to drive the slave interface is performed by changing the clock phase of the clock to be aligned with the command data cluster and/or the data cluster train. The interface device according to claim 1, further comprising other slave interfaces, the other slave interfaces are coupled to other slave devices in a one-to-one relationship, and are configured to receive the command from the master device and/or be controlled by all The other data generated by the other slave device is sent to the master device, wherein the other slave interface is driven by the clock generated by the clock generator and passes through the one or more bonding members and/or the silicon via Electrically connected to the main interface, Each clock used to drive each of the other slave interfaces is performed by changing the clock phase of each clock to the data cluster and/or all of the commands corresponding to each of the other slave interfaces. The data clusters of the data are aligned for training. The interface device according to claim 2, wherein each of the slave interface and the other slave interfaces is further configured to use a double data rate (DDR) configuration to send the data/the other data to the The main interface is described. The interface device according to claim 3, wherein the double data rate configuration is generated by a double data rate unit, and the double data rate unit includes: a first flip-flop (FF) unit configured to The data/the other data generates a part of the data; the second trigger unit is configured to generate another part of the data according to the data/the other data; and a multiplexer is coupled to the first trigger unit and the The second trigger unit is configured to send the part of the data and the other part of the data to the host device. The interface device according to claim 4, wherein each of the slave interface and the other slave interfaces further includes: a first strobe unit configured to generate the clock according to the clock generated by the clock generator A first local clock; and a second gating unit configured to generate a second local clock according to the clock generated by the clock generator, The first local clock generated by the first gating unit is used by the main interface to read the part of the data generated by the first flip-flop unit, and is used by the second gating unit The generated second local clock is used by the main interface to read the other part of the data generated by the second flip-flop unit. The interface device according to claim 2, wherein the master device also generates a turnaround (TA) loop, wherein the turnaround loop is used to prevent the response of the slave device from the response of the other slave device. Bus competition. The interface device according to claim 6, wherein the turning loop is used to compensate for a round-trip delay (RTD) difference between the slave device and the other slave devices. The interface device according to claim 7, wherein the slave device and the other slave devices generate zero data before the data and after the data, so as to prevent the slave devices from being caused by different round-trip delays. The competition between the device and the other slave devices. The interface device according to claim 4, wherein the main interface further includes a first-in-first-out (FIFO) unit, and the first-in-first-out unit is configured to use the clock pair generated by the clock generator to come from the The part of the data and the other part of the data of the double data rate unit of the slave interface and the other slave interface are retimed. The interface device according to claim 5, wherein the slave device and the other slave devices train the first gating unit and the second gating unit to locate the optimal data sampling point Part of the data and the other part of the data. An interface method for performing an interface between a master device and a slave device, wherein the master device generates a command and the slave device generates data according to the command, and the interface method includes: sending the command by the master interface To the slave device and/or receive the data from the slave device; and receive the command from the master device by a slave interface and/or send the data to the master device, wherein the master interface And the slave interface is driven by a clock generated by a clock generator, wherein the master interface and the slave interface are electrically connected by one or more bonding members and/or silicon vias, and all of the slave interfaces are used to drive the slave interface. The clock is trained by changing the clock phase of the clock to be aligned with the commanded data cluster and/or the data cluster of the data. The interface method according to claim 11, further comprising: receiving the command from the master device by another slave interface and/or sending other data generated by the other slave device to the master device, wherein the other slave interface The slave interface is driven by the clock generated by the clock generator and is electrically connected to the master interface through the one or more bonding members and/or the silicon via, and is used to drive the other slave interfaces Each clock of each is achieved by changing the clock phase of each clock to be paired with each of the other slave interfaces. Training is performed in response to the command data cluster and/or the data cluster alignment of the data. The interface method according to claim 12, wherein each of the slave interface and the other slave interfaces receives the command from the master device and/or sends the data/the other data to the The host device further includes: sending the data/the other data to the host interface using a double data rate (DDR) configuration. The interface method according to claim 13, wherein the double data rate configuration is generated by a double data rate unit, and the data/the other data are sent to all using the double data rate (DDR) configuration The main interface also includes: a first trigger (FF) unit generates a part of data based on the data/the other data; a second trigger unit generates another part of data based on the data/the other data; and The multiplexer sends the part of the data and the other part of the data to the main device. The interface method according to claim 14, wherein sending the data/the other data to the main interface using the double data rate configuration further includes: The generated clock generates a first local clock; and the second gating unit generates a second local clock according to the clock generated by the clock generator, The first local clock generated by the first gating unit is used by the main interface to read the part of the data generated by the first flip-flop unit, and is used by the second gating unit The generated second local clock is used by the main interface to read the other part of the data generated by the second flip-flop unit. The interface method according to claim 12, wherein the master device also generates a steering (TA) loop, wherein the steering loop is used to prevent a response between the slave device and the response of the other slave devices. Bus competition. The interface method according to claim 16, wherein the steering loop is used to compensate for a round-trip delay (RTD) difference between the slave device and the other slave devices. The interface method according to claim 17, wherein the slave device and the other slave devices generate zero data before the data and after the data, so as to prevent the slave devices from being caused by different round-trip delays. The competition between the device and the other slave devices. The interface method according to claim 14, wherein the master interface sending the command to the slave device and/or receiving the data from the slave device further includes: using the clock generator generated The clock retimes the part of the data and the other part of the data from the double data rate unit from the slave interface and the other slave interfaces. The interface method according to claim 15, wherein the slave device and the other slave device train the first gating unit and the second gating unit Practice to locate the part of the data and the other part of the data at the best data sampling point.

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