KR20240034087A - Memory device and memory controller configured to perform re-training referring temperature and electronic device including the same - Google Patents

Abstract

The electronic device of the present disclosure includes a system-on-chip that outputs a write clock and a write data signal, and a memory device that receives a data signal based on the write clock and outputs a data strobe signal and a read data signal having a different frequency from the write clock. Includes. The memory device includes a first interval oscillator, a second interval oscillator, and a temperature sensor. The electronic device performs FIFO training when initialized and performs interval oscillator training when operating after initialization. During interval oscillator training, the memory device performs a counting operation during operation of the interval oscillator and corrects the final count value by referring to temperature information of the memory device.

Description

A memory device and a memory controller that perform retraining with reference to temperature information, and an electronic device including them {MEMORY DEVICE AND MEMORY CONTROLLER CONFIGURED TO PERFORM RE-TRAINING REFERRING TEMPERATURE AND ELECTRONIC DEVICE INCLUDING THE SAME}

The present disclosure relates to memory devices and memory controllers, and electronic devices including them, and more specifically, to performing re-training with reference to temperature information of the memory device.

In accordance with the recent trend of high performance and high capacity of memory devices such as DRAM, the operating frequency of memory devices is rapidly increasing. In addition, in accordance with the low power characteristics required for mobile devices, a standard is being adopted in which the frequencies of the write clock (WCK) required for a write operation and the read data strobe signal (RDQS) required for a read operation are different.

Accordingly, as the operating speed of the memory device increases, it becomes increasingly difficult to correct the data integrity of the data of the memory device. Accordingly, training of the memory device may be required not only during initialization of the memory device, but also during operation of the memory device.

Meanwhile, when initializing a memory device, precise training using First In First Out (FIFO) is generally performed, and less precise but rapid interval oscillator training may be used during operation of the memory device. However, there is bound to be an error (i.e., offset) between the delay times measured during FIFO training (e.g., tWCK2DQI and tWCK2DQO) and the delay times measured during interval oscillator training, and the error may change depending on temperature changes. However, if interval oscillator training is performed without reflecting changes in offset due to temperature changes, the reliability of the memory device may decrease.

The present disclosure provides a method of correcting the delay time measured during interval oscillator training so that the offset between the delay time measured during FIFO training and the delay time measured during interval oscillator training does not exceed a reference value, with reference to temperature information of a memory device. provides.

An electronic device according to an embodiment of the present disclosure includes a system-on-chip that outputs a write clock and a write data signal, and a data strobe signal that receives the data signal based on the write clock and has a frequency different from the write clock. A memory device that outputs a read data signal, wherein the memory device includes a first interval oscillator configured to simulate a difference between the path of the write clock and the path of the read data signal, the path of the write clock, and the write data signal. and a second interval oscillator configured to simulate the difference between the paths of A second delay time is obtained according to the difference between the path and the path of the write data signal, and the memory device obtains a first count value while the first interval oscillator is operating, and the second interval oscillator is operating. Obtain a second count value, obtain a third count value by correcting the first count value according to the section to which the temperature of the memory device belongs, and correct the second count value according to the section to which the temperature belongs. Obtain the fourth count value.

A memory device that communicates with a memory controller according to an embodiment of the present disclosure includes a First In First Out (FIFO) read command, a FIFO write command, and an interval oscillator based on a clock received from the memory controller and command and address signals. A command and address receiver for obtaining a start command and an interval oscillator stop command, a buffer storing read data based on the FIFO read command or write data based on the FIFO write command, receiving the interval oscillator start command and stopping the interval oscillator. An interval oscillator that operates between receiving commands, a counter that performs counting while the interval oscillator is operating, and a count value obtained from the counter when the interval oscillator stops operating, with reference to information about the temperature of the memory device. It includes a control logic circuit that corrects the count value, and a mode register that stores the corrected count value.

A method of operating an electronic device including a memory controller and a memory device according to an embodiment of the present disclosure includes generating a data strobe signal or a data signal based on the input or output of data to the FIFO (First In First Out) of the memory device. Executing a first training to align, the memory device receiving an oscillator start command, operating an interval oscillator of the memory device in response to the oscillator start command, a counter of the memory device determines that the interval oscillator is performing counting during operation, the memory device receiving an oscillator stop command, obtaining a count value from the counter when operation of the interval oscillator is stopped according to the oscillator stop command, and the memory device It includes correcting the count value according to the section to which the temperature belongs.

According to an embodiment of the present disclosure, with reference to the temperature information of the memory device, the delay time measured during interval oscillator training is such that the offset between the delay time measured during FIFO training and the delay time measured during interval oscillator training does not exceed a reference value. Correct. As a result, the reliability of the memory device can be improved.

1 shows an example configuration of an electronic device according to an embodiment of the present disclosure.
FIG. 2 is a flowchart illustrating a method of operating an electronic device according to an embodiment of the present disclosure.
FIG. 3 illustrates an example configuration of the SoC of FIG. 1 ;
FIG. 4 shows an example configuration of the memory device of FIG. 1.
FIG. 5 exemplarily shows the effective window margin calculated by the training program of FIG. 3.
6 is an example timing diagram of signals between a SoC and a memory device when executing FIFO read training.
7 is an example timing diagram of signals between a SoC and a memory device when executing FIFO write training.
Figure 8 shows an example circuit diagram of the interval oscillator of Figure 4.
FIG. 9 shows another example circuit diagram of the interval oscillator of FIG. 4.
10 is an example timing diagram of signals between a SoC and a memory device during interval oscillator training.
FIG. 11 conceptually illustrates correcting the count value of an interval oscillator according to an embodiment of the present disclosure.
FIG. 12 conceptually illustrates correcting the count value of an interval oscillator according to an embodiment of the present disclosure.
FIG. 13 conceptually illustrates correcting the count value of an interval oscillator according to an embodiment of the present disclosure.
Figure 14 is a graph showing the offset between the delay in FIFO training according to temperature change and the delay in interval oscillator training according to temperature change.
FIG. 15 is a graph conceptually illustrating correction of delay in interval oscillator training according to temperature change in FIG. 13 according to an embodiment of the present disclosure.
Figure 16 is a flowchart of interval oscillator training according to an embodiment of the present disclosure.
Figure 17 shows an example configuration of an electronic device according to an embodiment of the present disclosure.
Figure 18 shows a stacked memory device according to an embodiment of the present disclosure.
Figure 19 shows a semiconductor package according to an embodiment of the present disclosure.
Figure 20 shows a semiconductor package according to an embodiment of the present disclosure.
21 shows a semiconductor package according to an embodiment of the present disclosure.
Figure 22 shows a system to which a memory device according to an embodiment of the present disclosure is applied.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

The components described with reference to terms such as unit, module, block, ~or, ~er, etc. used in the detailed description and the functional blocks shown in the drawings are It may be implemented in the form of software, hardware, or a combination thereof. By way of example, software may be machine code, firmware, embedded code, and application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, integrated circuit cores, a pressure sensor, an inertial sensor, a microelectromechanical system (MEMS), a passive component, or a combination thereof. .

1 shows an example configuration of an electronic device 10 according to an embodiment of the present disclosure. The electronic device 10 may include a system on-chip (hereinafter referred to as SoC) 100 and a memory device 200. For example, the electronic device 10 may be a mobile device such as a smart phone, a desktop computer, a laptop computer, a workstation, a server, etc.

The SoC 100 is an application processor (AP) and can control the overall operation of the electronic device 10. The SoC 100 may execute a program according to an application supported by the electronic device 10, receive data related to program execution from the memory device 200, or transmit the results of program execution to the memory device 200. . SoC 100 may include various intellectual properties (IP). For example, SoC 100 may include a memory controller 130 and a DDR physical layer (double data rate physical layer; hereinafter referred to as DDR PHY) 140. Meanwhile, in the embodiment of FIG. 1, the memory controller 130 and the DDR PHY 140 are shown as separate components, but the DDR PHY may be understood as a part of the memory controller 130.

The memory controller 130 may control the memory device 200 through the DDR PHY (140). The memory controller 130 may generate signals to access the memory device 200. The memory controller 130 may generate data to be stored in the memory device 200. The memory controller 130 may receive data read from the memory device 200.

The DDR PHY 140 may transmit a clock (CK) and command and address signals (CMD/ADD) to the memory device 200 under the control of the memory controller 130. The DDR PHY 140 may transmit a write clock (WCK) and a data signal (DQ) to the memory device 200 under the control of the memory controller 130. The write clock WCK may be a signal for transmitting (more specifically, sampling or latching) the data signal DQ to the memory device 200. The DDR PHY 140 may receive a read data strobe signal (RDQS) and a data signal (DQ) from the memory device 200. The read data strobe signal RDQS may be a signal for receiving the data signal DQ from the memory device 200. The memory device 200 may generate a read data strobe signal (RDQS) based on the write clock (WCK) received from the DDR PHY (140).

The memory device 200 may store data or provide the stored data to the SoC 100 according to a request from the SoC 100. The memory device 200 may communicate with the SoC 100 through the DDR PHY 140. For example, the memory device 200 may include dynamic random access memory (DRAM), static random access memory (SRAM), thyristor random access memory (TRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), It may be phase change random access memory (PRAM), magnetic random access memory (MRAM), etc. Hereinafter, the memory device 200 will be described as a DRAM device (i.e., a synchronous dynamic random access memory (SDRAM) device) that operates in synchronization with the clock CK output from the SoC 100. In particular, the memory device 200 may be a low power double data rate (LPDDR) SDRAM.

The memory device 200 may receive a clock (CK) and command and address signals (CMD/ADD) from the SoC 100. The memory device 200 may acquire the command (CMD) and address (ADD) by sampling the command and address signals (CMD/ADD) based on the clock (CK). The memory device 200 may receive the data signal DQ using the write clock WCK and output the data signal DQ using the read data strobe signal RDQS.

The frequency of the write clock (WCK) may be higher than the frequency of the clock (CK). For example, the frequency of the write clock (WCK) may be an integer multiple of the frequency of the clock (CK). The SoC 100 can transmit a clock (CK) with a relatively low frequency to the memory device 200, and can transmit a write clock (WCK) with a relatively high frequency to the memory device 200 during data input and output. .

In an embodiment, upon initialization (i.e., boot-on) of the electronic device 10, the SoC 100 performs training (hereinafter referred to as FIFO training) by executing a write operation and a read operation with respect to the memory device 200. You can. FIFO training has high accuracy because it performs training using the actual paths of write data and read data, but it may not be efficient because it involves input and output of data.

In an embodiment, during normal operation after the electronic device 10 is initialized, the SoC 100 trains using the interval oscillators 271 and 272 inside the memory device 200. (hereinafter referred to as interval oscillator training) can be performed. For example, interval oscillator training may be performed periodically, aperiodically, when the temperature of the memory device 200 changes, or when the voltage of the memory device 200 changes.

In an embodiment, the interval oscillator 271 may be implemented to simulate the path difference between the write clock (WCK) and the read data signal (hereinafter, read DQ), and the interval oscillator 272 may be implemented to simulate the path difference between the write clock (WCK) and the read data signal (hereinafter, read DQ). It can be implemented to simulate the path difference of the data signal (hereinafter referred to as write DQ). For example, the interval oscillators 271 and 272 may operate during a specific period (eg, runtime) according to a command from the SoC 100, and count values may increase during runtime. The final count values at the end of interval oscillator training may correspond to the skew value of the read data strobe signal RDQS to be adjusted and/or the skew value of the data signal DQ to be adjusted. The SoC 100 may correct skew of the read data strobe signal RDQS and/or the data signal DQ based on the count values received from the memory device 200.

Meanwhile, interval oscillator training is efficient because training is performed indirectly using the interval oscillators 271 and 272, but may be less accurate than FIFO training. That is, there may be an offset or error between the delay measured through FIFO training and the delay measured through interval oscillator training, and the offset may change depending on temperature. If the results of interval oscillator training without offset correction (i.e., count values) are used for training, a problem may occur in which the accuracy of interval oscillator training is reduced. However, the electronic device 10 of the present disclosure corrects the count value according to the section to which the temperature obtained by the temperature sensor 280 belongs, and uses the corrected count value to generate a read data strobe signal (RDQS) and/or data. Correct the skew of the signal (DQ). Therefore, the accuracy of interval oscillator training can be increased.

FIG. 2 is a flowchart illustrating a method of operating an electronic device according to an embodiment of the present disclosure.

Referring to FIGS. 1 and 2 , in step S11, the electronic device 10 may perform initialization. For example, when the electronic device 10 is powered on, the SoC 100 and the memory device 200 may perform initialization according to a predetermined method. During initialization, the SoC 100 may provide a power supply voltage to the memory device 200, perform various initial setup operations, and read or set necessary information from the memory device 200.

In step S12, the electronic device 10 may perform a command/address training operation. For example, the SoC 100 and the memory device 200 may perform a command/address training operation so that the command (CMD) and address (ADD) can be latched at a desired timing by the clock (CK).

In step S13, the electronic device 10 may perform a WCK2CK Alignment Training operation. For example, the memory device 200 receives a clock (CK) and a write clock (WCK) from the SoC 100, and transmits the write clock (WCK) so that the clock (CK) and the write clock (WCK) are aligned. can be adjusted. For example, the frequency of the write clock (WCK) may be N times that of the clock (CK) (where N is a natural number).

In step S14, the electronic device 10 may perform a write clock (WCK) duty cycle training operation. for example, Write clock (WCK) duty cycle training may be performed by a duty cycle corrector (DCC) and/or duty cycle adjuster (DCA) of the DDR PHY 140. For example, the DDR PHY 140 may delay the read data strobe signal RDQS received from the memory device 200 using a gate logic-like configuration.

In step S15, the electronic device 10 may perform a read gate training operation. For example, the memory controller 130 can determine when to observe the read DQ and read data strobe signals (RDQS), and receive the read DQ and read data strobe signals (RDQS) from the memory device 200. Timing can be controlled. To this end, the SoC 100 may include components (eg, logic gates, delay circuits, etc.) that control the reception timing of the read data strobe signal RDQS.

In step S16, the electronic device 10 may perform first training (i.e., FIFO training). For example, due to the design (structure) of the memory device 200 and/or the design (structure) of the package including the memory controller 130, DDR PHY 140, and memory device 200, the data signal ( The delay of DQ) may be shorter than the delay of write clock (WCK). FIFO training may be intended to correct delays due to path differences between the write clock (WCK) and the data signal (DQ). FIFO training may include read FIFO training and write FIFO training.

In an embodiment, during read FIFO training, the SoC 100 delays the read DQ and/or read data strobe signal (RDQS) received from the memory device 200 to determine the reception timing of the read DQ and read data strobe signal (RDQS). can be controlled. Additionally, during write FIFO training, the SoC 100 may control the transmission timing of the write DQ and the write clock (WCK) by delaying the write DQ transmitted to the memory device 200. After the first training is completed, the electronic device 10 can perform normal operations.

In step S17, during normal operation of the electronic device 10, the electronic device 10 may perform second training (i.e., interval oscillator training). For example, the electronic device 10 may increase the count value while the interval oscillators 271 and 272 are operating, and the final count value after the operation of the interval oscillators 271 and 272 is terminated is the temperature. It may be corrected according to the temperature obtained by sensor 280. The corrected count value can be used to adjust the skew of the data signal (DQ) and/or the read data strobe signal (RDQS).

FIG. 3 illustrates an example configuration of the SoC of FIG. 1 ; SoC 100 may include a processor 110, on-chip memory 120, memory controller 130, and DDR PHY 140.

The processor 110 may execute various software (application programs, operating systems, file systems, device drivers, etc.) loaded into the on-chip memory 120. The processor 110 may execute a training program loaded into the on-chip memory 120. The processor 110 may include homogeneous multi-core processors or heterogeneous multi-core processors. For example, the processor 110 may include a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU). may include at least one of a processing unit).

Application programs, operating systems, file systems, device drivers, etc. for driving the electronic device 10 may be loaded into the on-chip memory 120. Referring to FIG. 3, a training program may be loaded into the on-chip memory 120. For example, the on-chip memory 120 may be an SRAM device that is implemented inside the SoC 100 and has a faster data input/output speed than the memory device 200. On-chip memory 120 may also be referred to as buffer memory.

The memory controller 130 may control the DDR PHY 140 to communicate with a memory device (FIG. 1, 200). The memory controller 130 may access the memory device 200 using direct memory access (DMA). The memory controller 130 may include a command queue 131, a command scheduler 132, a read data queue 133, and a write data queue 134.

The command queue 131 may store commands and addresses issued by the processor 110. Commands and addresses stored in the command queue 131 may be provided to the DDR PHY 140 under the control of the command scheduler 132. One or more commands and one or more addresses stored in the command queue 131 may be provided to the DDR PHY 140 in parallel. The command scheduler 132 determines the order of commands and addresses stored in the command queue 131, the time when the command(s) and address(s) are input to the command queue 131, and the command(s) from the command queue 131. And the timing at which the address(es) are output can be adjusted.

In an embodiment, under the control of a training program executed by the processor 110, the command queue 131 may generate read commands, write commands, test data, etc. for FIFO training. And, under the control of the training program executed by the processor 110, the command queue 131 generates commands for interval oscillator training (e.g., an interval oscillator start command (OSC_Start) and an interval oscillator stop command (OSC_Stop). However, it is not limited to this, and in another embodiment, the memory controller 130 or the DDR PHY 140 may use a separate circuit (not shown) to generate commands for executing FIFO training and interval oscillator training. Poetry) may also be included.

The read data queue 133 may store read data received from the memory device 200 through the DDR PHY 140 in response to a read request from the SoC 100 for the memory device 200. Read data stored in the read data queue 133 may be provided to the on-chip memory 120 and processed by the processor 110. The write data queue 134 may store write data to be stored in the memory device 200. In response to a write request from the SoC 100 to the memory device 200, write data stored in the write data queue 134 may be transmitted to the memory device 200 through the DDR PHY 140. For example, the command queue 131, command scheduler 132, read data queue 133, and write data queue 134 of the memory controller 130 are implemented in the SoC 100 in a hardware manner, a software manner, or It can be implemented using a combination of these.

The DDR PHY (140) includes a clock generator (141), a command and address generator (142), a write clock generator (143), an RDQS receiver (144), a delay circuit (145), a data receiver (146), and a delay circuit (147). , and may include a data transmitter 148. Clock generator 141, command and address generator 142, write clock generator 143, RDQS receiver 144, delay circuit 145, data receiver 146, delay circuit 147 of DDR PHY 140 , and the data transmitter 148 may be implemented within the SoC 100 using a hardware method, a software method, or a combination thereof.

The clock generator 141 may generate a clock CK that is output to the memory device 200. Although shown briefly in FIG. 2 , for example, the clock generator 141 may generate clocks (e.g., CK_t, CK_c) in a differential manner and transmit the clocks (CK_t, CK_c) to the memory device 200. . For example, the clock generator 141 may include a duty cycle corrector (DCC) (not shown) and/or a duty cycle adjuster (DCA) that adjusts the duty cycle of the clock CK.

The command and address generator 142 may receive a command or address from the command queue 131 and transmit the command and/or address to the memory device 200 . For example, the command and address generator 142 sequentially generates an interval oscillator start command (OSC_Start) and an interval oscillator stop command (OSC_Stop) at a time interval (or toggling number) defined by the JEDEC standard to the memory device ( 200). The number of command and address transmission paths between the command and address generator 142 and the memory device 200, logical states of signals transmitted through the above-described transmission paths, transmission methods, etc. may be defined in the JEDEC standard.

The write clock generator 143 may generate a write clock (WCK) output to the memory device 200. Although briefly shown in FIG. 2 , for example, the write clock generator 143 generates write clocks (e.g., WCK_t, WCK_c) in a differential manner and transmits the write clocks (WCK_t, WCK_c) to the memory device 200. Can be transmitted. For example, the write clock generator 143 may include a DCC (not shown) and/or a DCA (not shown) that adjusts the duty cycle of the write clock (WCK).

In an embodiment, the clock (CK) and the write clock (WCK) may be generated based on the same PLL (Phase Lock Loop). In this case, in order to generate a clock CK having a frequency lower than the write clock WCK, the DDR PHY 140 may further include a divider (not shown).

The RDQS receiver 144 may receive a read data strobe signal (RDQS) received from the memory device 200 during a read operation on the memory device 200.

The delay circuit 145 may align the skew of the read data strobe signal RDQS so that the data receiver 146 can latch the read DQ using the read data strobe signal RDQS at a predetermined timing. The delay circuit 145 may operate when executing the read gate training described in step S15 of FIG. 2 . For example, the delay circuit 145 may include a delay locked loop (DLL) including a plurality of delay cells. For example, a read DQ aligner (not shown) can find an optimal sampling point for latching the read DQ while delaying the read DQ based on the unit time delayed by one delay cell. Meanwhile, in FIG. 3, the delay circuit 145 is shown as being external to the RDQS receiver 144, but the delay circuit 145 may also be implemented inside the RDQS receiver 144.

The data receiver 146 may receive a read DQ from the memory device 200 during a read operation on the memory device 200. The data receiver 146 may latch the read DQ based on the input timing of the RDQS received from the delay circuit 145. The data receiver 146 may provide the received read data to the read data queue 133. Although not shown in the drawing, the DDR PHY 140 may further include a delay circuit (not shown) to delay the read DQ input to the data receiver 146. In this case, a delay circuit (not shown) can be used to obtain an optimal sampling point for latching the read DQ by operating in conjunction with the delay circuit 145.

The delay circuit 147 may align the skew of the write DQ transmitted from the DDR PHY 140 to the memory device 200 (FIG. 1, 200) so that the write DQ can be latched by the memory device 200 at a predetermined timing. Delay circuit 147 may operate during FIFO training and/or interval oscillator training. For example, the delay circuit 147 may include a DLL including a plurality of delay cells.

The data transmitter 148 may transmit write data received from the delay circuit 147 to the memory device 200 as write DQ. In an embodiment, the delay circuit 147 may be part of the data transmitter 148 rather than a separate component.

In an embodiment, the DDR PHY 140 includes a delay circuit 145 that adjusts the skew of the read data strobe signal (RDQS) and a delay circuit 147 that adjusts the skew of the write DQ to be transmitted to the memory device 200. Although shown as including one, in another embodiment, the DDR PHY 140 may include only one of the delay circuits 145 and 147.

In an embodiment, the delay circuits 145 and 147 described above may be controlled by a training program executed by the processor 110 and/or by the memory controller 130. To this end, the memory controller 130 may obtain information about the skew to be adjusted (i.e., the count value in FIG. 1) in advance from the memory device 200 through FIFO training and interval oscillator training.

In an embodiment, a training program executed by the processor 110 may calculate a valid window margin (VWM) based on the count value. The effective window margin may mean the maximum section in which the data receiver 146 can determine the read DQ output from the memory device 200 using the read data strobe signal (RDQS) output from the memory device 200. This may mean the maximum section in which the memory device 200 can determine the write DQ output from the DDR PHY 140 using the write clock (WCK) output from the SoC 100. For example, the effective window margin calculated by the training program can be stored in the on-chip memory 120.

Figure 4 shows an example configuration of the memory device of Figure 1. The memory device 200 includes a command and address receiver 201, a write clock buffer 202, an RDQS transmitter 203, a data transceiver 204, a memory cell array 210, a row decoder 221, and a column decoder 223. ), control logic circuit 230, write driver 241, input/output sense amplifier 243, write buffer 251, read buffer 253, mode register 260, interval oscillators 271, 272, counter It may include fields 273 and 274, and a temperature sensor 280. The above-described components may be implemented in hardware within the memory device 200.

The command and address receiver 201 may receive a command (CMD) and an address (ADD) by latching the command and address signals (CMD/ADD) based on the clock (CK) received from the SoC 100. The received command (CMD) may be provided to the control logic circuit 230.

In an embodiment, the command and address receiver 201 may decode an activation command, a read command, a write command, a precharge command, a mode register write command, a multi-purpose command (MPC), etc. For example, a multi-purpose command (MPC) may include a FIFO write command and a FIFO read command for FIFO training, an interval oscillator start command (OSC_Start), an interval oscillator stop command (OSC_Stop), and a mode for interval oscillator training. A command for reading the count value stored in the register 260 may also be included.

The write clock buffer 202 may receive a write clock (WCK) from the SoC (FIG. 1, 100). The SoC 100 may transmit the write clocks (WCK_t, WCK_c) to the memory device 200 in a differential manner, and the memory device 200 may include write clock buffers that respectively receive the write clocks (WCK_t, WCK_c). You can. The write clock buffer 202 may provide a write clock (WCK) received during a write operation on the memory device 200 to the data transceiver 204. In an embodiment, the write clock buffer 202 may include a phase splitter (not shown) to generate write clocks with different phases based on the received write clock (WCK). However, in other embodiments, a phase divider (not shown) may be implemented external to write clock buffer 202.

The data transceiver 204 may receive a write DQ from the SoC 100 or output a read DQ to the SoC 100. During a write operation on the memory device 200, the data transceiver 204 may latch the write DQ based on the write clock (WCK). During a read operation on the memory device 200, the data transceiver 204 may transmit a read DQ to the SoC 100 along with transmission of the read data strobe signal RDQS. For example, since the data signal DQ is a bidirectional signal, the data transceiver 204 may include a receiver (not shown) that receives the write DQ and a transmitter (not shown) that outputs the read DQ.

The memory cell array 210 may include a plurality of memory cells connected to word lines and bit lines (not shown). For example, the memory cell may be a Dynamic Random Access Memory (DRAM) cell. In this case, the DDR PHY (Figure 1, 140) and the memory device 200 are DDR (Double Data Rate), LPDDR (low power double data rate), GDDR (Graphics Double Data Rate), Wide I/O, HBM (High It can communicate based on one of the standards such as Bandwidth Memory (HMC), Hybrid Memory Cube (HMC), etc.

The row decoder 221 may decode the row address received from the control logic circuit 230. The row decoder 221 may select and activate at least one word line corresponding to the row address. The column decoder 223 may decode the column address under the control of the control logic circuit 230. The column decoder 223 may select and activate at least one column selection line corresponding to the column address. At least one bit line may be connected to the column selection line. For example, memory cells corresponding to a row address and a column address may be selected, and data input/output may be performed on the selected memory cells.

The control logic circuit 230 may control components of the memory device 200. The control logic circuit 230 may provide an address transmitted along with a multi-purpose command (MPC) to registers (not shown), the write buffer 251, or the read buffer 253 inside the memory device 200. In an embodiment, the address transmitted with the command includes the addresses of memory cells of the memory device 200, includes a code used to set the operation mode of the memory device 200, or writes for FIFO training. It may include test data stored in the buffer 251 or the read buffer 253.

In an embodiment, the control logic circuit 230 may generate signals to enable the interval oscillators 271 and 272 and the counters 273 and 274 based on the interval oscillator start command (OSC_Start). Additionally, the control logic circuit 230 may generate signals to disable the interval oscillators 271 and 272 and the counters 273 and 274 based on the interval oscillator stop command (OSC_Stop).

In an embodiment, the control logic circuit 230 may sequentially provide an enable signal and a disable signal to the interval oscillator 271 for read interval oscillator training. Additionally, the control logic circuit 230 may sequentially provide an enable signal and a disable signal to the interval oscillator 272 for write interval oscillator training. Here, the enable signal and disable signal input to each of the interval oscillators 271 and 272 may be a time interval (or number of toggling) defined by the JEDEC standard. Control logic circuit 230 may control counters 273 and 274 in a similar manner.

The value counted by the counter 273 during the operation of the interval oscillator 271 and the value counted by the counter 274 during the operation of the interval oscillator 272 may be stored in the mode register 260. The memory device 200 may transmit count values to the SoC 100 through the data transceiver 204 in response to a mode register read command received from the SoC (FIG. 1, 100).

The write driver 241 may receive write data from the write buffer 251 and write the write data to selected memory cells through the input/output line (GIO). The input/output sense amplifier 243 may detect read data output from selected memory cells through an input/output line (GIO) and provide the read data to the read buffer 253.

The write buffer 251 may receive a write read data strobe signal (RDQS) and a write DQ from the SoC 100 through the RDQS buffer 203 and the data transceiver 204. The write buffer 251 may parallelize the received write DQ and store the parallelized write data in a FIFO (not shown) within the write buffer 251. The write buffer 251 may provide write data stored in the FIFO to the write driver 241. The read buffer 253 may receive read data from the input/output sense amplifier 243. The read buffer 253 may store the received read data in a FIFO (not shown) of the read buffer 253. The read buffer 253 may serialize read data and provide the serialized read data to the data transceiver 204.

The interval oscillator 271 may be implemented to simulate the difference between the path of the write clock (WCK) and the read DQ, and the interval oscillator 272 may be implemented to simulate the difference between the path of the write clock (WCK) and the write DQ. there is. The counters 273 and 274 may increase their count values while the interval oscillators 273 and 274, respectively, operate. For example, the final count value by the first counter 273 may correspond to a skew value of the read DQ to be adjusted or a skew value of the read data strobe signal RDQS to be adjusted. For example, the final count value by the second counter 274 may correspond to the skew value of the write DQ to be adjusted. For example, the first interval oscillator 271 and the second interval oscillator 272 may not operate at the same time, and the first counter 273 and the second counter 274 may not operate at the same time.

FIG. 5 exemplarily shows the effective window margin (VWM) calculated by the training program of FIG. 3. In FIG. 5 , the horizontal axis may represent time and the vertical axis may represent the voltage level of the data signal DQ. Gray shading in FIG. 5 may represent an eye diagram of the data signal DQ.

3 to 5, a training program executed by the processor 110 may calculate an effective window margin of the data signal DQ. The training program may control the timing of the read data strobe signal RDQS and/or the timing of the read DQ by controlling the delay circuit 145 and/or the delay circuit 147. As a result, the timing (i.e., sampling point) at which the read DQ is sampled by the read data strobe signal RDQS can be adjusted. Similarly, the training program can control the delay circuit 147 to control the timing of the write DQ. As a result, the timing (i.e., sampling point) at which the write DQ is sampled by the write clock (WCK) in the memory device 200 can be adjusted.

The training program executed by the processor 110 can find effective sampling points that can effectively sample the data signal (DQ) among a plurality of sampling points, and calculate the VWM of the data signal (DQ) from the effective sampling points. there is. For example, all sampling points shown in FIG. 3 may be valid sampling points. The training circuit 149 may calculate the difference between two effective sampling points or a value smaller than the difference as the VWM of the read DQ.

FIG. 6 is an example timing diagram of signals between the SoC 100 and the memory device 200 when executing FIFO read training.

Referring to FIGS. 3, 4, and 6, the SoC 100 may issue a command for synchronization between the write clock (WCK) and the clock (CK) before issuing the FIFO read command. Afterwards, the SoC 100 may issue a FIFO read command, and the FIFO read command may be latched at time t1. After the read latency (RL) between t1 and t2 has elapsed and a slight delay time (tWCK2DQO) has elapsed, the read DQ may be output from the memory device 200. Here, the delay time may be referred to as the write clock-read DQ interval (tWCK2DQO). tWCK2DQO may be a delay time depending on the path provided to the data transceiver 204 to latch the read DQ after the write clock (WCK) is input to the memory device 200.

Mismatch between the write clock (WCK) and read DQ according to tWCK2DQO can be corrected by the delay circuit 145 of the DDR PHY 140. More specifically, the delay circuit 145 may delay the read data strobe signal (RDQS) output from the RDQS receiver 144 with reference to the count value received from the memory device 200, and as a result, the SoC ( 100), the latch timing of the read DQ can be controlled by the read data strobe signal (RDQS).

FIG. 7 is an example timing diagram of signals between the SoC 100 and the memory device 200 when performing FIFO write training.

Referring to FIGS. 3, 4, and 7, the SoC 100 may issue a FIFO write command, and the FIFO write command may be latched at time t1. After the write latency (WL) between t1 and t2 has elapsed and a slight delay time (tWCK2DQI) has elapsed, the write DQ may be input to the memory device 200. Here, the delay time can be referred to as the write clock-read DQ interval (tWCK2DQI). tWCK2DQI may be the delay time depending on the difference between the path of the write clock (WCK) and the path of the read DQ.

Mismatch between the write clock (WCK) and write DQ according to tWCK2DQI can be corrected by the delay circuit 147 of the DDR PHY 140. More specifically, the delay circuit 147 may delay the write DQ output from the data transmitter 148 by referring to the count value received from the memory device 200, and as a result, the write DQ from the memory device 200 may be delayed. The latch timing of write DQ can be controlled by the clock (WCK).

FIG. 8 shows an example circuit diagram of the interval oscillator 271 of FIG. 4. For better understanding, the control logic circuit 230 and counter 273 are also shown.

The interval oscillator 271 may include a plurality of single-ended type inverters 271_1 to 271_n. The inverters 271_1 to 271_n may be connected in series, and the output terminal of the inverter 271_n may be commonly connected to the input terminal of the counter 273 and the input terminal of the inverter 272_1. The inverters 271_1 to 271_n may operate in response to the oscillator enable signal OSC_EN received from the control logic circuit 230.

First, when initializing the electronic device (FIG. 1, 10), when the memory device (FIG. 1, 200) receives an oscillator start command (OSC_Start) from the SoC (FIG. 1, 100), the control logic circuit 230 starts the oscillator. Based on the command (OSC_Start), the oscillator enable signal (OSC_EN) and counter enable signal (CNT_EN) can be generated. The inverters 271_1 to 271_n may operate in response to the counter enable signal CNT_EN, and the counter 273 may increase the count value each time a signal is output from the inverter 271_n.

Thereafter, when the memory device 200 receives the oscillator stop command (OSC_Stop) from the SoC 100, the control logic circuit 230 may stop generating the oscillation enable signal (OSC_EN). As a result, the operation of the interval oscillator 271 is stopped, and the counter 273 can output the final count value (CNT) counted during the operation of the interval oscillator 271. The count value (CNT) may be stored in the mode register 260.

In an embodiment, the interval oscillator 272 and the counter 274 may operate similarly to the embodiment of FIG. 8. However, because the read DQ path and the write DQ path are different, the number of inverters constituting the interval oscillator 271 and the number of inverters constituting the interval oscillator 272 may be different.

FIG. 9 shows another example circuit diagram of the interval oscillator 271 of FIG. 4. For better understanding, the control logic circuit 230 and counter 273 are also shown.

The interval oscillator 271 may include a plurality of differential type inverters 271_1 to 271_n. The inverters 271_1 to 271_n may be connected in series, and the first output terminal of the inverter 271_n may be commonly connected to the input terminal CK of the counter 273 and the negative input terminal of the inverter 272_1. Additionally, the second output terminal of the inverter 271_n may be commonly connected to the input terminal (CKB) of the counter 273 and the positive input terminal of the inverter 271_1.

The operation of the interval oscillator 271 of FIG. 9 may be substantially similar to the operation of the interval oscillator of FIG. 8. The interval oscillator 271 may operate in the runtime section between the reception of the oscillator start command (OSC_Start) and the oscillator stop command (OSC_Stop), and while the interval oscillator 271 operates, the counter 273 may increase the counting value. You can. When the operation of the interval oscillator 271 ends, the counter 273 may output the final count value (CNT). The count value (CNT) may be stored in the mode register 260.

FIG. 10 is an example timing diagram of signals between the SoC 100 and the memory device 200 during interval oscillator training.

Referring to FIGS. 3, 4, and 10, when operating after initialization of the electronic device 10, the SoC 100 may issue an oscillator start command (OSC_Start), and the memory device 200 may issue an oscillator start command (OSC_Start) at time t1. The oscillator start command (OSC_Start) can be latched based on the clocks (CK_t, CK_c). Thereafter, the SoC 100 may issue an oscillator stop command (OSC_Stop), and the memory device 200 may latch the oscillator stop command (OSC_Stop) based on the clocks CK_t and CK_c at time t2. Although only one interval oscillator start command (OSC_Start) and one interval oscillator stop command (OSC_Stop) are completed in Figure 10, in order to perform read interval oscillator training and write interval oscillator training, one interval oscillator start command (OSC_Start) and one interval oscillator stop command (OSC_Stop) may be further input to the memory device 200.

During runtime, the interval oscillator 271 may operate, and the count value of the counter 273 may be stored in the mode register 260. Similarly, the interval oscillator 272 may operate during the runtime between the next interval oscillator start command (OSC_Start) and the next interval oscillator stop command (OSC_Stop), and the count value of the counter 274 is stored in the mode register 260. It can be saved in .

Thereafter, the SoC 100 may issue a mode register read command (MRR) to read the count value stored in the mode register 260, and the memory device 200 may issue a mode register read command (MRR) based on the clocks CK_t and CK_c at time t3. The mode register read command (MRR) can be latched.

After the t4 time point elapses, the free toggling period (tWCKPRE) and the read sync period (tSYNCRD) may elapse. At least a portion of the free toggling period (tWCKPRE) and the read sync period (tSYNCRD) may be included in the read latency period (RL). Then, after the delay time (tWCK2DQO) has elapsed, the read DQ may be output from the memory device 200. Here, the delay time (tWCK2DQO) may be due to the path difference between the write clock (WCK) and the read DQ. Read DQ may include a count value by the counter 273 and a count value by the counter 274.

FIG. 11 conceptually illustrates correcting the count value of an interval oscillator according to an embodiment of the present disclosure.

Referring to FIGS. 4, 8, and 11, the memory device 200 may store a table defining the correspondence between temperature sections and correction coefficients. For example, the memory device 200 may include a separate component for storing a table. Alternatively, the mode register 260 of the memory device 200 may store a table.

In an embodiment, the temperature may be divided into a plurality of sections, such as a T0 to T1 section and a T1 to T2 section, and each temperature section may have a correction factor. The correction coefficient for each section can be positive, 0, or negative.

In an embodiment, the correction coefficient may be obtained in advance during the testing phase of the electronic device (FIGS. 1 and 10). For example, a temperature coefficient may be obtained for each temperature section so that the difference (i.e., offset) between the delay obtained during FIFO training and the delay obtained during interval oscillator training does not exceed a reference value. The reference value may be a threshold value that prevents the memory device 200 from malfunctioning.

In an embodiment, the mode register 260 is configured to select a correction coefficient corresponding to the temperature range to which the temperature measured by the temperature sensor 280 falls when the count value (CNT) is received from the counter 273. It can be. The mode register 260 may be configured to reflect the selected correction coefficient to the count value (CNT) and store the corrected count value. The corrected count value may be output to the SoC 100 according to a mode register read command from the SoC 100.

Meanwhile, the above-described operation may be equally performed for the counter 274 that counts the output of the interval oscillator 272.

FIG. 12 conceptually illustrates correcting the count value of an interval oscillator according to an embodiment of the present disclosure.

The operations of the components shown in FIG. 12 are generally similar to the operations of the components shown in FIG. 11. However, in this embodiment, the memory device 200 may include a separate component for storing the table, or the control logic circuit 230 may store the table.

Referring to FIGS. 4, 8, and 12, the count value (CNT) output from the interval oscillator 271 may be input to the control logic circuit 230. The control logic circuit 230 may be configured to correct the count value (CNT) by referring to the count value (CNT) output from the interval oscillator 271, the temperature output from the temperature sensor 280, and the table. The control logic circuit 230 may provide the corrected count value to the mode register 260, and the mode register 260 may store the corrected count value. The corrected count value may be output to the SoC 100 according to a mode register read command from the SoC 100.

Likewise, the above-described operation may be equally performed for the counter 274 that counts the output of the interval oscillator 272.

FIG. 13 conceptually illustrates correcting the count value of an interval oscillator according to an embodiment of the present disclosure.

Unlike the previous embodiments of FIGS. 11 and 12, in the embodiment of FIG. 13, correction of the count value may be performed in the SoC. Referring to FIGS. 3, 8, and 13, the count value (CNT) output from the interval oscillator 271 and the temperature information obtained by the temperature sensor 280 may be stored in the mode register. The memory device 200 may transmit the count value (CNT) and temperature information to the SoC 100 in response to a mode register read command received from the SoC 100. For example, the count value (CNT) and temperature information may be stored in the on-chip memory 120.

In an embodiment, the training program executed by the processor 110 may correct the count value (CNT) based on the table and the count value (CNT) and temperature information received from the memory device 200. For example, the table may be stored in a separate storage space or memory device 200 within the SoC 100, and may be loaded into the on-chip memory 120 when a training program is executed. When correction of the count value (CNT) is completed, the training circuit 149 uses the corrected count value to control the delay circuit 145 to delay the read data strobe signal (RDQS) (read interval oscillator training). , the write DQ can be delayed by controlling the delay circuit 147 (write interval oscillator training).

Figure 14 is a graph showing the offset between the delay in FIFO training according to temperature change and the delay in interval oscillator training according to temperature change.

Referring to FIG. 14, since FIFO training is performed based on actual data input and output, relatively accurate delay can be measured. For example, as the temperature increases, the delay may tend to increase, but this is an example and is not limited thereto.

Meanwhile, interval oscillator training is fast and simple because it is based on an interval oscillator that simulates the write path and the read path, but has the disadvantage of being inaccurate. For example, the delay may tend to increase as the temperature increases, but the difference between the delay and the offset of FIFO training may further increase as the temperature increases.

As an example, the offset (Offset_a) at the temperature Ta may be within an acceptable value. In this case, even if the SoC performs training using the delay time (Da) obtained during the interval oscillator training process, there is a problem in the operation of the memory device. There will be no. However, as an example, the offset (Offset_b) and offset (Offset_c) at the temperature Tb may be outside the allowable values. In this case, when the SoC performs training using the delay times (Db, Dc) obtained during the interval oscillator training process, the memory device may not operate normally.

FIG. 15 is a graph conceptually illustrating correction of delay in interval oscillator training according to temperature change in FIG. 13 according to an embodiment of the present disclosure.

Referring to FIG. 15 along with FIGS. 11 to 13 , the temperature may be illustratively divided into a section between T0 and T1, a section between T1 and below T2, and a section between T2 and below T3.

Referring to FIGS. 3, 4, and 15, the control logic circuit 230 or the mode register 260 may correct the count value of the counter 273 according to the temperature section. For example, the delay time (Da') obtained at temperature (Ta) during interval oscillator training may be within an acceptable range. Therefore, the correction coefficient in the section (T0 to T1) to which the temperature (Ta) belongs may be '0', and the control logic circuit 230 or the mode register 260 will not correct the count value of the counter 273. You can. That is, the mode register 260 may store a count value corresponding to the delay time (tWCK2DQO or tWCK2DQI), and may provide a command value to the SoC 100 in response to a mode register read command from the SoC 100. .

If the temperature of the memory device changes from Ta to Tb and re-training is required, the SoC 100 may perform interval oscillator training. As a result of training, the counter 273 may obtain a count value corresponding to the delay time (Figure 14, Db), which may be outside the allowable range. Accordingly, the correction coefficient of the section (T1 to T2) to which the temperature (Tb) belongs may be set to 'b', and the control logic circuit 230 or mode register 260 may correct the count value of the counter 273. You can. As a result, a count value corresponding to the delay time Db' can be obtained, and the count value can be stored in the mode register 260.

If retraining is required because the temperature of the memory device changes from Tb to Tc, the SoC 100 may perform interval oscillator training. As a result of training, the counter 273 may obtain a count value corresponding to the delay time (Figure 14, Dc), which may be outside the allowable range. Accordingly, the correction coefficient of the section (T2 to T3) to which the temperature (Tc) belongs may be set to 'c', and the control logic circuit 230 or mode register 260 may correct the count value of the counter 273. You can. As a result, a count value corresponding to the delay time (Dc') can be obtained, and the count value can be stored in the mode register 260.

Figure 16 is a flowchart of interval oscillator training according to an embodiment of the present disclosure.

Referring to FIGS. 3, 4, and 16, in step S110, the memory device 200 may receive an interval oscillator start command (OSC_Start) based on the clock CK. The control logic circuit 230 may generate signals to enable the interval oscillator 271 and the counter 273 based on the interval oscillator start command (OSC_Start), and may respond to signals from the control logic circuit 230. Based on this, the interval oscillator 271 and the counter 273 can operate (S120).

In step S130, the counter 273 may count the output signal of the interval oscillator.

In step S140, the memory device 200 may receive an interval oscillator stop command (OSC_Stop) based on the clock CK. The control logic circuit 230 may generate signals to disable the interval oscillator 271 and the counter 273 based on the interval oscillator stop command (OSC_Stop), and the interval oscillator 271 and the counter 273 Operation may be stopped based on signals from the control logic circuit 230. Then, the counter 273 can output the final count value (S150).

In step S160, the control logic circuit 230 or the mode register 260 may correct the count value output from the counter 273 based on a table defining the correspondence between temperature sections and correction coefficients. For example, temperature information for referencing a table may be obtained by the temperature sensor 280 inside the memory device.

In step S170, the memory device 200 may provide a corrected count value to the SoC 100 in response to a mode register read command from the SoC 100. The SoC 100 may adjust the skew of the read data strobe signal (RDQS) and/or write DQ by referring to the corrected count value.

FIG. 17 shows an example configuration of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 10 may include a memory controller 300 and a memory device 400.

The memory device 400 may receive a clock (CK) and command and address signals (CMD/ADD) from the memory controller 300. The memory device 200 may acquire the command (CMD) and address (ADD) by sampling the command and address signals (CMD/ADD) based on the clock (CK). The memory device 200 may receive or output the data signal DQ using the data strobe signal DQS. The memory device 400 may be double data rate (DDR) SDRAM.

In an embodiment, the configuration of the memory controller 300 and the memory device 400 may be substantially similar to the configuration of the memory controller 300 and the memory device 200 of FIG. 1 . Therefore, detailed description of the specific configuration of the memory controller 300 and the memory device 400 will be omitted. However, while clocks with different frequencies (i.e., WCK and RDQS) are used during the write and read operations of the memory device 200 of FIG. 1, the write and read operations of the memory device 400 of FIG. 17 are used. The difference is that the data strobe signal (DQS) is used during operation.

In an embodiment, the memory controller 300 may perform FIFO training on the memory device 400 upon initialization, and may execute interval oscillator training on the memory device 400 upon operation of the memory device 400 after initialization. there is. Interval oscillator training may include read interval oscillator training and write interval oscillator training. Read interval oscillator training may be performed using the interval oscillator 471, and write interval oscillator training may be performed using the interval oscillator 472. You can.

The interval oscillator 471 may be implemented to simulate the difference between the path of the data strobe signal (DQS) and the path of the read DQ, and the interval oscillator 472 may be implemented to simulate the difference between the path of the data strobe signal (DQS) and the path of the write DQ. It can be implemented to mimic .

For example, the delay time according to the difference between the path of the data strobe signal (DQS) and the path of the read DQ may be tDQS2DQO. Similarly, the delay time according to the difference between the path of the data strobe signal (DQS) and the path of the write DQ may be tDQS2DQI. The configuration and operation of the interval oscillators 471 and 472 may be substantially the same as the interval oscillators described with reference to FIGS. 8 and 9.

In an embodiment, the control logic circuit (similar to control logic circuit 230 of FIG. 4) and/or the mode register (similar to mode register 260 of FIG. 4) within memory device 400 may be used to control temperature sensor 480. The count values counted during operation of the interval oscillators 471 and 472 can be corrected based on the temperature measured by . As a result, even if the temperature changes, the difference (i.e., offset) between the delay time measured during FIFO training and the delay time measured during interval oscillator training may be within an acceptable range.

Figure 18 shows a stacked memory device according to an embodiment of the present disclosure. Referring to FIG. 18 , the stacked memory device 500 may include a buffer die 510 and a plurality of core dies 520 to 550. For example, the buffer die 510 may also be referred to as an interface die, base die, logic die, master die, etc., and each of the core dies 520 to 550 may also be referred to as a memory die, slave die, etc. You can. In FIG. 18 , the stacked memory device 500 is shown to include four core dies 520 to 550, but the number of core dies may vary. For example, stacked memory device 500 may include 8, 12, or 16 core dies.

The buffer die 510 and the core dies 520 to 550 may be stacked and electrically connected through through silicon vias (TSVs). Accordingly, the stacked memory device 500 may have a three-dimensional memory structure in which a plurality of dies 510 to 550 are stacked. For example, the stacked memory device 500 may be implemented based on the HBM or HMC standards.

The stacked memory device 500 may support a plurality of functionally independent channels (or vaults). For example, as shown in FIG. 15, the stacked memory device 500 can support eight channels (CH0 to CH7). If each of the channels (CH0 to CH7) supports 128 data (DQ) transmission paths (I/O), the stacked memory device 500 can support 1024 data transmission paths (I/O). However, the present invention is not limited to this, and the stacked memory device 500 may support 1024 or more data transmission paths and 8 or more channels (eg, 16 channels). When the stacked memory device 500 supports 16 channels, each of the channels can support 64 data transmission paths.

Each of the core dies 520 to 550 may support at least one channel. For example, as shown in FIG. 18, each of the core dies 520 to 550 may support two channels (CH0-CH2, CH1-CH3, CH4-CH6, CH5-CH7). In this case, the core dies 520 to 550 may support different channels. However, the present invention is not limited to this, and at least two of the core dies 520 to 550 may support the same channel. For example, each of the core dies 520 to 550 may support the first channel CH0.

Each of the channels can constitute an independent command and data interface. For example, each channel may be independently clocked based on independent timing requirements and may not be synchronized with each other. For example, each channel can change its power state or perform a refresh based on an independent command.

Each of the channels may include a plurality of memory banks 501. Each of the memory banks 501 may include memory cells connected to word lines and bit lines, a row decoder, a column decoder, a sense amplifier, etc. For example, as shown in FIG. 12, each of the channels CH0 to CH7 may include eight memory banks 501. However, the present invention is not limited to this, and each of the channels CH0 to CH7 may include eight or more memory banks 301. Although the memory banks included in one channel are shown in FIG. 18 as being included in one core die, the memory banks included in one channel may be distributed across a plurality of core dies. For example, when each of the core dies 520 to 550 supports the first channel CH0, memory banks included in the first channel CH0 may be distributed among the core dies 520 to 550. .

In an example embodiment, one channel may be divided into two independently operating pseudo channels. For example, pseudo channels may share the channel's command and clock inputs (e.g., clock (CK) and clock enable signal (CKE)), but may decode and execute commands independently. For example, if one channel supports 128 data transmission paths, each of the pseudo channels can support 64 data transmission paths. For example, if one channel supports 64 data transmission paths, each of the pseudo channels can support 32 data transmission paths.

The buffer die 510 and core dies 520 to 550 may include a TSV area 502. TSVs configured to penetrate the dies 510 to 550 may be disposed in the TSV area 502. The buffer die 510 may transmit and receive signals and/or data with the core dies 520 to 550 through TSVs. Each of the core dies 520 to 550 may transmit and receive signals and/or data with the buffer die 510 and other core dies through TSVs. In this case, signals and/or data can be transmitted and received independently through corresponding TSVs for each channel. For example, when an external host device transmits a command and an address to the first channel (CH0) to access the memory cell of the first core die 520, the buffer die 510 transmits a command and an address to the first channel (CH0) The memory cell of the first channel CH0 can be accessed by transmitting control signals to the first core die 520 through the corresponding TSVs.

The buffer die 510 may include a physical layer (PHY, 511). The physical layer 511 may include interface circuits for communication with an external host device. For example, the physical layer 511 includes the command and address receiver 201, write clock buffer 202, RDQS transmitter 203, data transceiver 204, and control logic circuit ( 230) and the like may include interface circuits. Signals and/or data received through the physical layer 511 may be transmitted to the core dies 520 to 550 through TSVs.

In an example embodiment, buffer die 510 may include a channel controller corresponding to each of the channels. The channel controller can manage memory reference operations of the corresponding channel and determine timing requirements of the corresponding channel.

In an example embodiment, the buffer die 510 may include a plurality of pins for receiving signals from an external host device. The buffer die 510 receives a clock (CK), command and address signals (CMD/ADD), data strobe signal (DQS), and data signal (DQ) through a plurality of pins, and receives the data strobe signal (DQS) and A data signal (DQ) can be transmitted. For example, the buffer die 510 has 2 pins for receiving a clock (CK) for each channel, 14 pins for receiving command and address signals (CMD/ADD), and a data strobe signal (DQS). It may include 8 pins for transmitting a data strobe signal (DQS), and 128 pins for transmitting and receiving a data signal (DQ).

Figure 19 shows a semiconductor package according to an embodiment of the present disclosure. Referring to FIG. 19 , the semiconductor package 1000 may include a stacked memory device 1100, a system-on-chip 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer die 1110 and core dies 1120 to 1150. The buffer die 1110 may correspond to the buffer die 510 of FIG. 18, and each of the core dies 1120 to 1150 may correspond to each of the core dies 520 to 550 of FIG. 18.

Each of the core dies 1120 to 1150 may include a memory cell array. The buffer die 1110 may include a physical layer 1111 and a direct access area (DAB) 1112. The physical layer 1111 may be electrically connected to the physical layer 1210 of the system-on-chip 1200 through the interposer 1300. The stacked memory device 1100 may receive signals from the system-on-chip 1200 through the physical layer 1111, or may transmit signals to the system-on-chip 1200.

The direct access area 1112 may provide an access path for testing the stacked memory device 1100 without going through the system-on-chip 1200. Direct access area 1112 may include conductive means (e.g., ports or pins) that can communicate directly with an external test device. Test signals and data received through the direct access area 1112 may be transmitted to the core dies 1120 to 1150 through the TSVs. For testing of the core dies 1120 to 1150, data read from the core dies 1120 to 1150 may be transmitted to a test device through the TSVs and the direct access area 1112. Accordingly, a direct access test on the core dies 1120 to 1150 may be performed.

The buffer die 1110 and the core dies 1120 to 1150 may be electrically connected to each other through TSVs 1101 and bumps 1102. The buffer die 1110 may receive signals provided to each channel from the system-on-chip 1200 through bumps 1102 allocated for each channel. For example, bumps 1102 may be micro bumps.

The system-on-chip 1200 can execute applications supported by the semiconductor package 1000 using the stacked memory device 1100. For example, the system-on-chip 1200 includes a Central Processing Unit (CPU), an Application Processor (AP), a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), a Tensor Processing Unit (TPU), and a Vision Processing Unit (VPU). ), an Image Signal Processor (ISP), and a Digital Signal Processor (DSP) may be used to execute specialized operations.

System-on-chip 1200 may include a physical layer 1210 and a memory controller 1220. The physical layer 1210 may include input/output circuits for transmitting and receiving signals to and from the physical layer 1111 of the stacked memory device 1100. The system-on-chip 1200 may provide various signals to the physical layer 1111 through the physical layer 1210. Signals provided to the physical layer 1111 may be transmitted to the core dies 1120 to 1150 through the interface circuits and TSVs 1101 of the physical layer 1111.

The memory controller 1220 may control the overall operation of the stacked memory device 1100. The memory controller 1220 may transmit signals for controlling the stacked memory device 1100 to the stacked memory device 1100 through the physical layer 1210. The memory controller 1220 may correspond to the memory controller 130 of FIG. 1 .

The interposer 1300 may connect the stacked memory device 1100 and the system-on-chip 1200. The interposer 1300 connects the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the system-on-chip 1200 and may provide physical paths formed using conductive materials. . Accordingly, the stacked memory device 1100 and the system-on-chip 1200 are stacked on the interposer 1300 and can transmit and receive signals to each other.

Bumps 1103 may be attached to the top of the package substrate 1400, and solder balls 1104 may be attached to the bottom. For example, bumps 1103 may be flip-chip bumps. The interposer 1300 may be stacked on the package substrate 1400 through bumps 1103 . The semiconductor package 1000 can transmit and receive signals with other external packages or semiconductor devices through the solder ball 1104. For example, the package substrate 1400 may be a printed circuit board (PCB).

Figure 20 shows a semiconductor package according to an embodiment of the present disclosure. Referring to FIG. 20 , a semiconductor package 2000 may include a plurality of stacked memory devices 2100 and a system-on-chip 2200. The stacked memory devices 2100 and the system-on-chip 2200 may be stacked on the interposer 2300, and the interposer 2300 may be stacked on the package substrate 2400. The semiconductor package 2000 can transmit and receive signals with other external packages or semiconductor devices through the solder ball 2001 attached to the lower part of the package substrate 2400.

Each of the stacked memory devices 2100 may be implemented based on the HBM standard. However, the present invention is not limited thereto, and each of the stacked memory devices 2100 may be implemented based on GDDR, HMC, or Wide I/O standards. Each of the stacked memory devices 2100 may correspond to the stacked memory devices 300 and 1100 of FIGS. 18 and 19 .

The system-on-chip 2200 may include at least one processor, such as a CPU, AP, GPU, or NPU, and a plurality of memory controllers for controlling a plurality of stacked memory devices 2100. The system-on-chip 2200 can transmit and receive signals with a corresponding stacked memory device through a memory controller. The system-on-chip 2200 may correspond to the system-on-chip 1200 of FIG. 19.

Figure 21 shows a semiconductor package according to an embodiment of the present disclosure. Referring to FIG. 21 , the semiconductor package 3000 may include a stacked memory device 3100, a host die 3200, and a package substrate 3300. The stacked memory device 3100 may include a buffer die 3110 and core dies 3120 to 3150. The buffer die 3110 includes a physical layer 3111 for communicating with the host die 3200, and each of the core dies 3120 to 3150 may include a memory cell array. The stacked memory device 3100 may correspond to the stacked memory device 300 of FIG. 18 .

The host die 3200 may include a physical layer 3210 for communicating with the stacked memory device 3100 and a memory controller 3220 for controlling the overall operation of the stacked memory device 3100. Additionally, the host die 3200 controls the overall operation of the semiconductor package 3000 and may include a processor to execute an application supported by the semiconductor package 3000. For example, the host die 3200 may include at least one processor such as CPU, AP, GPU, or NPU.

The stacked memory device 3100 may be disposed on the host die 3200 based on TSVs 3001 and vertically stacked on the host die 3200. Accordingly, the buffer die 3110, the core dies 3120 to 3150, and the host die 3200 may be electrically connected to each other through the TSVs 3001 and bumps 3002 without an interposer. For example, bumps 3002 may be micro bumps.

Bumps 3003 may be attached to the top of the package substrate 3300, and solder balls 3004 may be attached to the bottom. For example, bumps 3003 may be flip-chip bumps. The host die 3200 may be stacked on the package substrate 3300 through bumps 3003. The semiconductor package 3000 can transmit and receive signals with other external packages or semiconductor devices through the solder ball 3004.

In another embodiment, the stacked memory device 3100 may be implemented with only core dies 3120 to 3150 without the buffer die 3110. In this case, each of the core dies 3120 to 3250 may include interface circuits for communicating with the host die 3200. Each of the core dies 3120 to 3250 may transmit and receive signals with the host die 3200 through the TSVs 3001.

Figure 22 shows a system to which a memory device according to an embodiment of the present disclosure is applied.

System 4000 may include a main processor 4100, memory 4200a, 4200b, and storage devices 4300a, 4300b, and may additionally include an image capturing device 4410 and user input. User input device 4420, sensor 4430, communication device 4440, display 4450, speaker 4460, power supply device 4470 and connecting interface ( 4480) may include one or more of the following.

The main processor 4100 can control the overall operation of the system 4000, and more specifically, the operation of other components forming the system 4000. This main processor 4100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor 4100 may include one or more CPU cores 4110 and may further include a controller 4120 for controlling the memories 4200a and 4200b and/or the storage devices 4300a and 4300b. Depending on the embodiment, the main processor 4100 may further include an accelerator 4130, which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. Such an accelerator 4130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and is physically independent from other components of the main processor 4100. It may also be implemented as a separate chip.

The memories 4200a and 4200b may be used as main memory devices of the system 4000 and may include volatile memories such as SRAM and/or DRAM. In this case, the memories 4200a and 4200b may include the memory devices described with reference to FIGS. 1 to 17 . However, the memory is not limited thereto, and the memories 4200a and 4200b may include non-volatile memory such as flash memory, PRAM, and/or RRAM. The memories 4200a and 4200b may also be implemented in the same package as the main processor 4100.

The storage devices 4300a and 4300b may function as non-volatile storage devices that store data regardless of whether power is supplied, and may have a relatively large storage capacity compared to the memories 4200a and 4200b. The storage devices 4300a and 4300b may include storage controllers 4310a and 4310b, and non-volatile memory (NVM) 4320a and 4320b that store data under the control of the storage controllers 4310a and 4310b. You can. The non-volatile memory (4320a, 4320b) may include flash memory with a 2-dimensional (2D) structure or a 3-dimensional (3D) V-NAND (Vertical NAND) structure, but may include other types of memory such as PRAM and/or RRAM. It may also contain non-volatile memory.

The storage devices 4300a and 4300b may be included in the system 4000 while being physically separated from the main processor 4100, or may be implemented in the same package as the main processor 4100. In addition, the storage devices 4300a and 4300b have a form such as a solid state device (SSD) or a memory card, and can be connected to other components of the system 4000 through an interface such as a connection interface 4480 to be described later. It can also be coupled to make it detachable. Such storage devices (4300a, 4300b) may be devices to which standard protocols such as UFS (Universal Flash Storage), eMMC (embedded multi-media card), or NVMe (non-volatile memory express) are applied, but are not necessarily limited thereto. Not really.

The photographing device 4410 can capture still images or moving images, and may be a camera, camcorder, and/or webcam.

The user input device 4420 may receive various types of data input from the user of the system 4000, and may be used through a touch pad, keypad, keyboard, mouse and/or It may be a microphone, etc.

The sensor 4430 can detect various types of physical quantities that can be obtained from outside the system 4000 and convert the sensed physical quantities into electrical signals. Such a sensor 4430 may be a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device 4440 can transmit and receive signals with other devices outside the system 4000 according to various communication protocols. Such a communication device 4440 may be implemented including an antenna, a transceiver, and/or a modem.

The display 4450 and the speaker 4460 may function as output devices that output visual information and auditory information, respectively, to the user of the system 4000.

The power supply device 4470 may appropriately convert power supplied from a battery (not shown) built into the system 4000 and/or an external power source and supply it to each component of the system 4000.

The connection interface 4480 may provide a connection between the system 4000 and an external device that is connected to the system 4000 and can exchange data with the system 4000. The connection interface 4480 is ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), and PCIe. (PCI express), NVMe, IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded Universal Flash Storage), CF (compact flash) card It can be implemented in various interface methods such as interfaces.

The above-described details are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply changed or easily changed in design. In addition, the present invention will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of the present invention as well as the claims described later.

10: Electronic device
100: SoC
200: memory device

Claims (20)

A system-on-chip that outputs write clock and write data signals; and
A memory device that receives the data signal based on the write clock and outputs a data strobe signal and a read data signal having a different frequency from the write clock,
The memory device includes a first interval oscillator configured to simulate the difference between the path of the write clock and the path of the read data signal, and a second interval oscillator configured to simulate the difference between the path of the write clock and the path of the write data signal. Including,
The system-on-chip obtains a first delay time according to the difference between the path of the write clock and the path of the read data signal, and a second delay time according to the difference between the path of the write clock and the path of the write data signal. obtain,
The memory device acquires a first count value while the first interval oscillator operates, acquires a second count value while the second interval oscillator operates, and determines the temperature of the memory device according to the section to which it belongs. An electronic device that obtains a third count value by correcting the first count value, and obtains a fourth count value by correcting the second count value according to the section to which the temperature belongs. According to claim 1,
The system-on-chip performs a first training function that adjusts the delay of the write clock based on the first delay time or adjusts the delay of the write data signal based on the second delay time when initializing the memory device. and run
When operating the memory device, the system on chip adjusts the delay of the write clock based on the third delay time corresponding to the third count value or adjusts the delay of the write clock based on the fourth delay time corresponding to the fourth count value. An electronic device that performs second training to adjust a delay of the write data signal based on the second training. According to claim 1,
The memory device obtains the first delay time in response to a First In First Out (FIFO) read command received from the system-on-chip, and obtains the second delay time in response to a FIFO write command received from the system-on-chip. Electronic devices that acquire . According to claim 1,
The memory device is an electronic device that obtains the first count value or the second count value in a section between an interval oscillator start command and an interval oscillator stop command received from the system on chip. According to claim 1,
The memory device is:
a first counter outputting the first count value;
a second counter outputting the second count value;
a temperature sensor that obtains information about the temperature of the memory device;
Control to obtain the third count value by correcting the first count value based on the information about the temperature and to obtain the fourth count value by correcting the second count value based on the information about the temperature logic circuit; and
An electronic device including a mode register storing the third count value and the fourth count value. According to claim 5,
The memory device is an electronic device that outputs the third count value and the fourth count value in response to a mode register read command received from the system on chip. According to claim 5,
The SoC is:
a read data strobe signal receiver that receives the read data strobe signal;
a first delay circuit that controls a delay of the read data strobe signal output from the read data strobe signal receiver based on the first count value;
a second delay circuit controlling a delay of the write data signal based on the second count value; and
An electronic device comprising a data transmitter that transmits the write data signal output from the second delay circuit. According to claim 1,
The first interval oscillator includes a first plurality of inverters, and the second interval oscillator includes a second plurality of inverters,
An electronic device in which the number of the first plurality of inverters and the number of the second plurality of inverters are different from each other. According to claim 2,
When performing the second training, adjusting the delay of the write clock based on the third delay time and adjusting the delay of the write data signal based on the fourth delay time are performed at different times. . According to claim 1,
The system-on-chip and the memory device are electronic devices that operate based on the LPDDR (Low Power Double Data Rate) standard. For a memory device communicating with a memory controller:
a command and address receiver that obtains a First In First Out (FIFO) read command, a FIFO write command, an interval oscillator start command, and an interval oscillator stop command based on the clock received from the memory controller and the command and address signals;
a buffer in which read data based on the FIFO read command or write data based on the FIFO write command are stored;
an interval oscillator operating between reception of the interval oscillator start command and reception of the interval oscillator stop command;
a counter that performs counting while the interval oscillator operates;
a control logic circuit that obtains a count value from the counter when the interval oscillator stops operating and corrects the count value by referring to information about the temperature of the memory device; and
A memory device including a mode register for storing the corrected count value. According to claim 11,
a clock buffer that receives a clock signal from the controller;
a data strobe signal transmitter that outputs a read data strobe signal based on the clock buffer; and
A memory device further comprising a data transceiver that receives a write data signal from the memory controller or transmits a read data signal to the memory controller. According to claim 11,
The control logic circuit enables the interval oscillator and the counter in response to the interval oscillator start command,
The control logic circuit is a memory device that disables the interval oscillator and the counter in response to the interval oscillator stop command. According to claim 11,
The interval oscillator includes a plurality of inverters connected in series,
The counter is a memory device that counts the output signal of any one of the plurality of inverters. According to claim 11,
The memory controller and the memory device operate based on the Low Power Double Data Rate (LPDDR) standard or the Double Data Rate (DDR) standard. In a method of operating an electronic device including a memory controller and a memory device:
performing first training to align a data strobe signal or data signal based on input or output of data to a First In First Out (FIFO) of the memory device;
receiving, by the memory device, an oscillator start command;
operating an interval oscillator of the memory device in response to the oscillator start command;
performing counting by a counter of the memory device while the interval oscillator operates;
receiving, by the memory device, an oscillator stop command;
Obtaining a count value from the counter when operation of the interval oscillator is stopped according to the oscillator stop command; and
A method comprising correcting the count value according to a section to which the temperature of the memory device belongs. According to claim 16,
outputting, by the memory device, the corrected count value in response to a mode register read command; and
The method further comprising the step of the memory controller performing second training to align the data strobe signal or the data signal based on the corrected count value. According to claim 16,
The steps for executing the first training are:
obtaining, by the memory device, a FIFO read command and a FIFO write command based on a clock and command and address signals;
Obtaining a first delay time based on a read operation in response to the FIFO read command; and
Obtaining a second delay time based on a write operation responsive to the FIFO write command. According to claim 18,
Before performing the first training,
executing command and address training so that the command and address signals are latched by the clock;
Executing write clock-clock alignment training to align the clock with a write clock for receiving a write data signal;
performing duty cycle training of the write clock; and
The method further includes aligning a read data strobe signal and the read data signal to output a read data signal, or performing read gate training to align the read data strobe signal and the write data signal. According to claim 16,
A method in which the memory controller and the memory device operate based on the Low Power Double Data Rate (LPDDR) standard or the Double Data Rate (DDR) standard.

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