TWI525998B - Clock reproducing and timing method, device and apparatus in a system having a plurality of devices and memory controller with flexible data alignment - Google Patents

Description

Clock regeneration and timing device, device and method thereof in system comprising a plurality of devices and a memory controller with flexible data alignment [Reference reference for related applications]

This application claims US Provisional Patent Application No. 61/013,784, issued December 4, 2007, U.S. Provisional Patent Application No. 61/019,907, issued Jan. 9, 2008, and U.S. Provisional Patent Application No. 61, Priority is given to U.S. Patent Application Serial No. 12/168,091, issued Jul. 4, 2008, and U.S. Patent Application Serial No. 12/325,074, issued Nov. 28, 2008.

The invention relates to devices. In particular, it relates to a system having a plurality of devices and a method of regenerating a clock used in such a system. Further, the present invention relates to a semiconductor device. In particular, it relates to systems having a plurality of semiconductor devices and timing and timekeeping methods for such systems.

Electronic devices use semiconductor devices, such as memory devices. Memory devices may include random access memory (RAM), flash memory (such as NAND flash devices, NOR flash devices), and other types of memory that store data or information.

The memory system on the board is designed to achieve both high density and high speed operation to meet the needs of various applications. Two design techniques that can be used to implement high-density memory systems on a board include serial cascade interconnect configurations and multi-drop bus interconnect configurations. These design techniques address density issues by allowing many memory devices to be connected to a single memory control device. One design technique is a multi-drop bus interconnect configuration in which a plurality of memory devices are connected in parallel to a memory controller. Another design technique is a series connection of a plurality of memory devices.

Various timing methods can be used in systems that include memory. Using a common source clock, the clock signal may be distorted by the parallel nature of the configuration. Also, it has several skew factors, and when many devices are connected in a multi-point manner, the operating frequency range is limited and cannot be used in high speed applications. The source synchronous time control system uses clock remodeling and retransmission to provide a higher frequency range and avoids some of the common synchronizing clock skew factors, but introduces other skew factors that do not seriously affect system performance.

In accordance with an aspect of the present invention, an apparatus for transmitting data having a period defined by a transition of an input clock signal is provided. The device includes a clock device and a synchronization circuit. The clock circuit is configured to provide a plurality of regenerative clock signals in response to the input clock signal. The phase of the complex reproduced clock signal is shifted from the data differently. The clock circuit is also configured to generate an output clock signal in response to at least one of the plurality of reproduced clock signals. The synchronization circuit synchronizes the transmission of the data with at least one of the regenerated clock signals. The transition of the output clock signal occurs during the period of the data.

For example, each of the phases of the complex regenerative clock signals are phase shifted from each other. In response to a regenerative clock signal having a different phase shift, the clock circuit can produce an output clock signal having a flexible phase shift.

The clock circuit can include: a phase locked loop (PLL) for providing the complex reproduced clock signal in response to the input clock signal, and providing the output in response to at least one of the plurality of reproduced clock signals Clock output circuit of the clock signal.

For example, the PLL is configured to be selectively enabled or disabled in response to a control signal having first and second logic states to cause the PLL to be enabled or disabled, respectively. In the case where the PLL is enabled, the PLL generates the complex regenerated clock signal in response to the input clock signal. The clock output circuit is configured to generate the output clock signal in response to at least one of the plurality of reproduced clock signals. The synchronization circuit is configured to synchronize transmission of the data with at least one of the regenerated clock signals. In the event that the PLL is disabled, the synchronization circuit is configured to synchronize the transmission of the data with the input clock signal.

Advantageously, the PLL is further configured to output the regenerated clock signals having a phase shift of a multiple of 90° from the data.

For example, the apparatus receives the input clock signal including a clock signal and its complementary clock signal. In response to the input clock signal, the clock circuit provides an internal clock signal. The PLL generates the complex regenerative clock signal in response to the internal clock signal when the PLL is enabled. The PLL synchronizes the transmission of the data with the internal clock signal when the PLL is disabled.

The apparatus can further include a keeper for maintaining identification information associated with the apparatus, the identification information being used to identify the apparatus. The control signal is provided in response to the identification information held in the holder. The control signal is one of the logic high and low that respectively causes the PLL to be enabled and disabled.

The apparatus can further include an access circuit responsive to the identification of the device based on the identification information to access the memory.

In accordance with another aspect of the present invention, an apparatus for transmitting data from a first device to a second device is provided having a period defined by a transition of a clock signal. The first device includes: a first clock circuit and a first synchronization circuit. The first clock circuit is configured to: provide a plurality of first reproduced clock signals in response to the first input clock signal, the phases of the plurality of first reproduced clock signals are differently shifted from the data, and are responsive to the plurality A first output clock signal is generated by at least one of the first regenerated clock signals. The first synchronization circuit synchronizes transmission of the data with at least one of the plurality of first reproduced clock signals, the transition of the first output clock signal occurring during the period of the data. The second device includes: a second clock circuit configured to provide a second input clock signal in response to a second input clock signal derived from the first output clock signal, the second second reproduced clock signal The phase is shifted from the data differently from each other, and a first data input circuit for receiving the data transmitted from the first device in response to the second input clock.

For example, the first clock circuit includes: a first phase-locked loop (PLL) for providing the plurality of first regenerated clock signals in response to the first input clock signal, for responding to the plurality of first regenerations A first clock output circuit of the first output clock signal is generated by at least one of the clock signals and a second PLL for providing the plurality of second reproduced clock signals in response to the second input clock signal.

The first and second PLLs are configured to be selectively enabled or disabled in response to the first and second control signals, respectively. When the first PLL is enabled, the first PLL generates the plurality of first regenerated clock signals in response to the first input clock signal. When the second PLL is enabled, the second PLL generates the plurality of second regenerated clock signals in response to the second input clock signal.

In accordance with another aspect of the present invention, a system is provided comprising: a controller and a plurality of serially connected devices whose operation is synchronized with a clock signal. Each of the devices includes: a phase locked loop (PLL) configured to be selectively enabled, the PLL, when enabled, provides a plurality of regenerated clock signals in response to the input clock signal, the regenerated clock signals A pattern of different phase shifts of the input clock signal, and a synchronization circuit for synchronizing the transmission of at least one of the data and the reproduced clock signals.

In accordance with another aspect of the present invention, a method for a plurality of devices is provided, each of the plurality of devices including a phase locked loop (PLL) that transmits data to another device in response to an input clock signal. The method includes selectively enabling the PLL in response to a control signal, the enabled PLL outputting a plurality of regenerated clock signals in response to the input clock signal, the regenerated clock signals being different phases of the input clock signal Displacement pattern.

According to another aspect of the present invention, there is provided a method for transmitting time-controlled data according to a clock signal having a period defined by a transition of the clock signal, the method comprising: selectively enabling or disabling a phase-locked loop (PLL) capable of providing a plurality of regenerated clock signals in response to the input clock signal when the PLL is enabled, the regenerative clock signals being of a different phase shift of the input clock signal and synchronizing The data is transmitted with the regenerative clock signal, and the clock transition of the regenerated clock signal is between the periods of the data.

According to another aspect of the present invention, a method for transmitting data from a first device to a second device is provided, wherein the data is time-controlled according to a clock signal having a period defined by a transition of the clock signal, The method includes: providing a plurality of regenerated clock signals in response to the first input clock signal, wherein the regenerated clock signals are of a different phase shift pattern of the first input clock signal, synchronizing the data with the regenerative time a transmission of at least one of the pulse signals, the clock transition of the regenerated clock signal being during the period of the data, the regenerative clock signal being provided as an output clock signal in response to the output from the first device The clock signal provides a plurality of regenerative clock signals that are of a different phase shift from the output clock signal of the first device and that receive the data transmitted from the first device.

According to another aspect of the present invention, a method for transmitting data according to a time-of-day signal of a clock having a period defined by a transition of the clock signal is provided. The method includes selectively enabling or disabling a phase-locked loop (PLL), providing a plurality of regenerative clock signals in response to the input clock signal when the PLL is enabled, the regenerative clock signals being the input A pattern of different phase shifts of the pulse signal and synchronization of transmission of the data with at least one of the regenerated clock signals.

In accordance with another aspect of the present invention, a method for transmitting data from a first device to a second device is provided, the data being timed based on a clock signal having a period defined by a transition of the clock signal. In the first apparatus, the method includes: providing a plurality of regenerated clock signals in response to the first input clock signal, the regenerated clock signals being of a different phase shift of the first input clock signal, and synchronizing the The data is transmitted to at least one of the regenerated clock signals, the clock transition of the regenerated clock signal being during the period of the data, the regenerative clock signal being provided as an output clock signal. In a second apparatus, the method includes: providing a plurality of regenerated clock signals in response to the output clock signal from the first device, the regenerated clock signals being different phases of the output clock signal from the first device The pattern of displacement and receiving the data transmitted from the first device.

According to another aspect of the present invention, there is provided an apparatus for communicating with a serially connected plurality of devices utilizing a source synchronous time control, the apparatus comprising: information for detecting quantity information related to the number of the series connected devices a detector, and a clock generator for generating a clock signal in response to the detected quantity information, the generated clock signal for synchronizing the device and communication between the devices.

For example, the information detector includes an identifier detector for detecting a device identifier (ID) associated with one of the series connected devices, and providing the detected device ID as the detected quantity information. To the clock generator. The identifier detector may include a bit information detector for detecting information included in one of the bits in the device ID.

The bit information detector may include a bit number determiner for determining that the least significant bit (LSB) of the device ID is "1" or "0", and providing the judgment result as the quantity information of the detection. The aligned clock signal is generated in response to the result of the determination.

The device may further include a mode detector for receiving a signal indicating the status of the ID assignment completion, determining whether the ID assignment is completed, and providing the status of the ID assignment completion to the bit determiner to determine the temporary storage. The LSB of the device ID.

For example, the clock generator generates a clock signal aligned or centrally aligned with the edge of the data in response to the device identifier assignment being completed or in progress, the device providing control input to and output from the device The strobe signal of the data, which is transmitted synchronously with the clock signal.

According to another aspect of the present invention, a method for communicating a serially connected plurality of devices utilizing source synchronous time control is provided, the method comprising: detecting quantity information related to the number of devices connected in series, and responding A clock signal is generated for the detected quantity information, and the generated clock signal is used to synchronize communication with the devices.

The method can further include: assigning a unique device identifier (ID) associated with each of the series connected devices, the assigned IDs of the devices being continuity, detection, and one of the series connected devices The associated device ID and the device ID providing the detection are used as the quantity information of the detection. The step of detecting the device ID may include detecting information included in one of the bits included in the device ID in response to the detection of the assignment of the device IDs.

According to another aspect of the present invention, a system is provided comprising: a plurality of series connection devices utilizing source synchronization time control, and a controller configured to communicate with the series connection devices, the controller comprising: for detecting a information detector for quantity information related to the number of devices connected in series, and a clock generator for generating a clock signal in response to the detected quantity information, the generated clock signal being used for synchronization The device and the communication between the devices.

According to another aspect of the present invention, a system including a memory controller and at least one semiconductor device is provided.

In accordance with another aspect of the present invention, an apparatus is provided that includes a PLL that is selectively enabled or disabled. When enabled, the PLL provides a complex regenerated clock signal with phase shifts of the reference clock signals defined by the input signal and its complementary signals by 90°, 180°, 270°, and 360°. Selectively enable or disable the PLL. Data is transmitted in response to one or a combination of complex regenerative clock signals. When disabled, the PLL does not regenerate the clock and transmits data in response to the reference clock.

In accordance with another aspect of the present invention, a memory device including a memory controller and a plurality of memory devices connected in series to a memory controller is provided. The plurality of memory devices are grouped. The memory controller provides a clock signal for synchronizing the operation of the device. A group of devices are timed by the clock signals provided by the source synchronization and the common synchronization clock structure. Each of the devices includes a PLL that is selectively enabled by an enable signal. When the PLL is enabled, it outputs a complex regenerated clock signal that is phase shifted by a multiple of 90°. Each of the devices having the enabled PLL operates with the regenerative clock signal. When the PLL is disabled, it operates with the input clock signal. The disabled PLL device results in less power consumption. In response to the regenerative clock signal provided by the enabled PLL, for the source synchronous time control, the next device for the series connection of the output clock signals is provided. The device group can be constructed in a multi-chip package. The clock phase shift provides the center or edge clock of the data to be transmitted, with the result that some skew does not constitute an attenuation factor.

In accordance with another embodiment, a semiconductor memory device having flexible operation of a flash memory (eg, a NAND flash device) is provided.

In accordance with another embodiment, a memory device including a memory controller and a plurality of memory devices connected in series to a memory controller is provided. The system operates with a source synchronous clock structure. The memory controller includes a PLL (phase-locked loop) that produces phase shifts from the input oscillating signals of 90°, 180°, 270°, and 360°. Some of these phase shift signals are used for clock alignment. The device is assigned a unique and consecutive identifier (ID) number. The least significant bit of the last device's ID number is used to determine the timing of the clock alignment: the clock generated by the memory controller that is aligned with the edge or center of the data.

According to an embodiment, the controller provides a clock aligned with the center of the material or aligned with the edge. Each of the devices connected in series can provide a clock aligned with the center or edge of the data. The provided clock system is transmitted to the next device.

For example, the memory device includes a memory or data storage element for storing data. Memory includes random access memory (RAM), flash memory (such as NAND flash devices, NOR flash devices) and other types of memory for storing data and information.

Other aspects and features of the present invention will become apparent to those skilled in the <RTIgt;

In the following detailed description of the exemplary embodiments of the invention, reference to the claims The embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is understood that other embodiments may be utilized, and may be made without departing from the scope of the invention. The following detailed description is not to be considered as limiting, and the scope of the invention is defined by the scope of the appended claims.

As mentioned above, multipoint and tandem connections are configured to address known density design techniques.

Figure 1 shows a system with a plurality of memory devices connected in a multipoint manner. The system implements a common synchronous clock structure to conform to the parallel clock distribution. In the illustrated system, memory controller 110 communicates with a plurality (N) of memory devices 120-1, 120-2, ..., and 120-N, N being an integer greater than one. The memory controller 110 and the N memory devices are connected via an n-bit data line 131 and an m-bit control line 133. The data transfer and control signals are synchronized with a common clock connected to the memory controller 110 and the common clock lines 135 of the N memory devices 120-1 through 120-N. The synchronized clock is provided by the clock source 140 to the common clock line 135. Due to the parallel nature of the busbars, the clock signal load is heavy and distorted.

An example of a series connection of multi-memory devices is "RamLink", which became an IEEE standard in 1996. RamLink actually specifies two alternative interconnection methods. One method is RingLink, which consists of a series connected device that provides a point-to-point connection between the devices, providing a high degree of scalability but long latency. Another method is SyncLink, which consists of a multipoint interconnection of a small number of devices.

The hybrid RamLink configuration is also part of the IEEE standard. The RamLink-based memory system consists of a processor or memory controller and one or more memory modules. The memory controller is typically included within the processor itself or as part of a companion wafer set of the processor. Each memory module has a slave interface that includes a link input and a link output. The memory module is configured as a RamLink signaling topology, which is called a RingLink with a unidirectional link between components. The control interface slave interface on each module interface is connected to a memory device (RAM). In this system, another RamLink signaling topology called SyncLink is used between the slave interface and the memory device. Data is transmitted between the processor and the module along a packet circulating along the RingLink. The processor and memory controller are responsible for generating all request packets and scheduling the return of the dependent response packets.

The hybrid RamLink configuration can only be operated as fast as a module-level component link. It is limited in frequency by the SyncLink link within a single module due to the multi-point bus, as shown in Figure 1. In the RingLink slave interface circuit, source sync strobing is used to control the incoming data signal. That is, the strobe signal "strobein" accompanying the entry of the data signal is used to sample the incoming data. The circuit uses a phase-locked loop (PLL) to generate a stable local clock signal from the reference clock signal.

In accordance with an embodiment of the present invention, a system is provided having a controller and a plurality of connected devices, the devices being synchronous timed. An example system with a serially connected semiconductor device will be discussed.

Figure 2 shows the overall system with flash memory. Referring to FIG. 2, memory system 140 communicates with a host system or processor (host system) 142 via memory controller 144. Memory system 140 includes a plurality of memory devices in series or in parallel. An example of a memory device is a flash device.

Figure 3 shows the configuration of a serially connected complex memory device. Referring to Fig. 3, this configuration includes N memory devices 145-1, 145-2, 145-3, ..., and 145-N connected in series, N being an integer. The N memory devices 145-1 to 145-N connected in series correspond to the memory system 140 of FIG. A memory controller (not shown) corresponding to the memory controller 144 of FIG. 2 transmits a group of data or information signals to the configured memory device. The data or information to be processed is sent to the data input Dn of the first device 145-1 and propagated through the configuration of the serially connected configuration. In one embodiment, the data output Qn of the last device 145-N is coupled to another device or system (not shown) to use the propagated material or information therein. In another embodiment, the data output Qn of the last device 145-N is coupled to the memory controller such that the memory controller can use the data returned from the last device 145-N.

The operation of the configured devices 145-1 through 145-N is shown in FIG. The device configured as shown in Fig. 4 operates in the initial mode and the normal mode shown in Fig. 4. In the initial mode, a device address (DA) or device identifier (ID) is assigned to the device. Thereafter, in the normal mode, the device specified by the ID number performs the operations specified by the command (such as data writing, data reading).

Figure 5A shows the configuration of Figure 3, showing the ID configuration. Referring to Figures 3, 4 and 5A, in the initial mode, the memory controller provides an initial ID (=0) to the first device 145-1. Each of the configured memory devices 145-1, 145-2, 145-3, ..., and 145-N stores the input ID, IDi, into its ID register and performs addition (ie, IDi+1) to generate The output ID of the next device, IDo. In the example shown, the memory devices 145-1, 145-2, 145-3, ..., and 145-N are assigned IDs of consecutive numbers "0", "1", "2", ... "N", respectively The binary numbers "000", "0001", "0010"... and "..." are represented. Each device has its most significant bit (MSB) at the top and its least significant bit (LSB) at the end. In another embodiment, the ID may become the LSB at the top and the MSB at the end. Also, the ID may be a consecutive number (such as "1") from another value. In addition, the number can be decremented from the maximum value. An example of ID assignment in a tandem-connected complex memory device is provided in International Patent Publication No. WO/2007/0109886 (October 4, 2007) and International Patent Publication No. WO/2007/0134444 (November 29, 2007) )in.

Figure 5B shows the configuration of Figure 3, showing normal mode operation. Referring to Figures 3, 4 and 5A, in the normal mode, the memory controller issues control information (CI) as a command, including specific device ID numbers, operating instructions, and others. The device controller included in each of the memory devices performs ID matching determination, and compares the input IDi with the assigned ID in the ID register. In the case where the IDs match each other, the device controller executes a command included in the CI to access the memory of the device. The operation examples of the command are memory access and data processing. Each command includes an ID number (ie, a device address) and a command operation code (hereinafter simply referred to as "OP code"), and may also include address information and/or data. If the input ID and the temporary ID do not match each other, the device will transmit the CI to the next device as the input command CO. In response to receiving the transmitted CO as CI, the next device performs a similar operation as the previous device.

Fig. 6 is a diagram showing an example command format in a memory device for serial connection as shown in Fig. 3. Referring to Figure 6, the first command format 147-1 includes an ID number and an OP code. The ID number is used to identify the selected memory device, and the OP code field contains the OP code to be executed by the selected device. The command having the first command format 147-1 can be used, for example, as a command containing an OP code that reads a scratchpad value. The second command format 147-2 includes an ID number, an OP code, and data. The command having the second command format 147-2 can be used, for example, as a command containing an OP code that writes data to the scratchpad. The third command format 147-3 includes an ID number, an OP code, and an extra address. This extra address may, for example, include a column and/or row address used to address the location in the memory unit. The command having the third command format 147-3 can be used, for example, as a command containing an OP code for reading data from a memory unit of the selected memory device. The fourth command format 147-4 includes an ID number, an OP code, an extra address, and data. The command having the fourth command format 147-4 can be used, for example, as a command containing an OP code that writes data to a memory unit of the selected memory device. Note that all four example command formats 147-1, 147-2, 147-3, and 147-4 begin with an ID number for addressing. It should be understood from the foregoing that the term "command" as used herein refers not only to the command OP code, but the command may include an ID number, an OP code, an extra address, data, or any other information related to the configuration of the memory device that controls the serial connection. . An example of a command format is disclosed in International Patent Publication WO/2008/098342 (August 21, 2008). Examples of commands and operations are disclosed in International Patent Publication No. WO/2007/036048 (April 5, 2007) and on February 21, 2008, entitled "Sequence Data Flow Control in Multiple Independent Sequences" (Serial Data) Flow Control in Multiple Independent Serial Port) is disclosed in U.S. Patent Application Serial No. 12/034,686.

For applications requiring large memory spaces (or mass storage systems), a flash memory system using a plurality of flash memory devices can be implemented. The memory controller has access to each flash memory device and can select only one flash memory at a time.

To enhance signal integrity on a large number of flash devices in flash memory systems such as USB flash drives, flash memory cards, and HDD-replaced solid state devices (SSDs), NAND flash memory can be implemented. Tandem-connected NAND flash memory is advanced and provides high performance flash devices that are connected using point-to-point serial devices.

Data can be transmitted or captured in response to a clock signal. The operation can be performed in response to the rising edge or the falling edge of the clock signal. The memory device can perform single data rate (SDR) operations or double data rate (DDR) operations, which are shown in Figures 7A and 7B, respectively. The memory device can be operated more than twice during the clock cycle.

Figure 8A shows a system with a series connected multi-memory device having a common synchronous clock structure that conforms to the parallel clock distribution topology. Referring to Fig. 8A, the memory controller 150 communicates with a plurality (N) of memory devices 152-1, 152-2, ..., and 152-N, and N is an integer greater than one. The memory controller 150 is coupled to the first memory device 152-1 to transmit control and/or data information, and propagates through the remaining memory devices in response to the common synchronization clock signal CLKcsyc1 provided by the memory controller 150. 152-2 to 152-N. The propagated information is provided from the last device 152-N to another device or device (not shown) for further processing there.

Figure 8B shows a system with a plurality of memory devices connected in series having a common synchronizing clock structure that forms a ring structure. In the illustrated example, memory controller 160 communicates with a plurality (N) of memory devices 162-1, 162-2, ..., and 162-N, N being an integer greater than one. The memory controller 160 is coupled to the first memory device 162-1 to transmit control and/or data information, and propagates through the remaining memory devices in response to the common synchronous clock signal CLKcsyc2 provided by the memory controller 150. 162-2 to 162-N. In the system, the last (Nth) memory device 162-N feeds the propagated information back to the memory controller 160, causing the system to form a circular link. If necessary, the propagated control signal is returned to the Billion Controller 160.

Figure 9 shows details of one of the memory devices shown in Figures 8A and 8B. Each of the memory devices shown in Figs. 8A and 8B has the same structure. Referring to Figure 9, device i, which represents any of the devices shown in Figures 8A and 8B, has an input circuit 172 for receiving an input signal 173 from a previous device, device (i-1), for The output signal 175 is provided to the next device, the output circuit 174 of the device (i+1), the clock circuit 176, and the memory core circuit 178. In response to the input common sync clock signal CLKcsyc 177, the clock circuit 176 passes the clock to the input circuit 172, the memory core circuit 178, and the output circuit 174 for operation thereof. The input circuit 172 and the output circuit 174 perform interface operations in response to the clock signal CLKcsyc.

Figure 10A shows the details of the system of Figure 8A. This particular example includes a memory controller 210 and serially connected complex memory devices 212-1 through 212-4. This example system has a serially connected memory device that implements a common synchronous clock structure. The example shown shows four devices, but any number of devices can be connected in series.

Referring to Fig. 10A, each of the memory devices 212-1 to 212-4 has hard-wired or pre-assigned ID numbers so that one device can be selected at a time in accordance with the ID matching judgment in the normal mode operation. The memory device has a point-to-point connection. The memory controller 210 has a plurality of outputs connected to the device to carry various information. Each device has a plurality of inputs and outputs for receiving and transmitting various information.

The memory controller 210 has data output DOC[0:3], command strobe output CSOC, data strobe output DSOC, chip select output/CEC, and reset output/RSTC. Further, the memory controller 210 has a pair of clock outputs CKOC and /CKOC. Each device has data input D[0:3], command strobe input CSI, data strobe input DSI, reset input / RST, chip enable input / CE and a pair of clock inputs CK and / CK. Moreover, each device has a data output Q[0:3], a command strobe output CSO, and a data strobe output DSO. The data output Q[0:3], the command strobe output CSO, and the data strobe output DSO of one device are respectively coupled to the data input D[0:3] of the next device, the command strobe input CSI, and the data strobe input DSI. .

The device receives a wafer enable signal /SCE (hereinafter referred to as "/SCE signal") and a reset signal /SRST (hereinafter referred to as "/SRT signal"). Further, the device receives a pair of clock signals SCLKI (hereinafter referred to as "SCLKI signal") and a complementary clock signal /SCLKI (hereinafter referred to as "/SCLKI signal"). /SCE, /SRST, SCLKI, and /SCLKI are typically provided by memory controller 210 to memory devices 212-12 through 12-4.

The data output DOC[0:3] of the memory controller 210 provides input data DI1[0:3] to the data input D[0:3] of the first device 212-1 (device 1). The first device 212-1 transmits the output data DQ[0:3] to the next device. The second device 212-2 (device 2) outputs the output data DQ[0:3] from the previous device (device 1) as input data DI2[0:3]. The command strobe input CSI and the data strobe input DSI of a device respectively receive the command strobe input signal SCSI and the data strobe input signal SDSI. Moreover, the command strobe input CSO and the data strobe output DSO of one device respectively transmit the command strobe output signal SCSO and the data strobe output signal SDSO to the next device. The data transmission is controlled by the command strobe input and data strobe input signal of each device.

Each device provides a delay type of a command strobe input signal SCSI (hereinafter referred to as "SCSI signal") and a data strobe input signal SDSI (hereinafter referred to as "SDSI signal"), that is, a command strobe output signal SCSO (hereinafter referred to as "SCSO signal") and data strobe output signal SDSO (hereinafter referred to as "SDSO signal"), to the next device. The data and SCSI and SDSI transmissions are performed in response to the SCLKI and /SCLKI signals.

Exemplary details of an architecture having a series connected device are provided in U.S. Patent Publication No. 2007/0076502 A1 (Aug. 5, 2007) and International Patent Publication No. WO/2007/036048. Other examples of architectures with devices connected in series are also provided in International Patent Publication No. WO/2008/067652 (June 12, 2008) and International Patent Publication No. WO/2008/022454 (February 28, 2008). detail.

Figure 10B shows the details of the system of Figure 8B. The connection and structure of the system shown in Fig. 10B is almost the same as that shown in Fig. 10A. The only difference is that the output data DQ4 (0:3) of the last device connected in series (ie, device 4) and the SCSO4 and SDSO4 signal systems are fed to the memory controller 220. The SCSO4 and SDSO4 signals are optionally provided to the memory controller 220. To detect valid data locations.

In a particular example, the SCK and /SCK signals are provided by the memory controller to the respective memory devices in a multipoint manner. Thus, even if the incoming data is transferred to a single component (ie, a serially connected memory device or any other serially connected memory) in a point-to-point interface, the clock signal is loaded by the multi-memory component. As a result, the actual implementation of this technique can have an operating frequency limit of, for example, 200 MHz or less.

Figure 11 shows the details of the device shown in Figures 10A and 10B. Figure 11 shows the general implementation of the device. The input and output data are n-bit parallel data.

Referring to Fig. 11, two of the devices of the system shown in 10A or 8B are shown. Referring to FIG. 11, the first device 212-i (device i) and the next device 212-(i+1) (device i+1) collectively receive the reset signal /SRST, the chip enable signal /SCE, and a pair Clock signals SCLKI and /SCLKI. The data input D[0:(n-1)] of the device i receives the input data DIi[0:(n-1)] from the previous device (device (i-1), not shown), and outputs Q from its data. [0: (n-1)] Output output data DQi[0:(n-1)]. The output data DQi[0:(n-1)] from the device i is fed as the data input D of the input data DI(i+1)[0:(n-1)] to the device (i+1). The device (i+1) outputs the output data DQ(i+1)(0:(n-1)] from its data output Q, which is transmitted to the next device, device (i+2) (not shown). The command strobe input CSI and the data strobe input DSI of i receive the command strobe input signal SCSIi and the data strobe input signal SDSIi from the previous device (device (i-1)) respectively. The device i outputs the CSO from its command strobe respectively. And the data strobe output DSO output command strobe output signal SCSOi and the data strobe output signal SDSOi. The command strobe output signal SCSOi and the data strobe output signal SDSOi from the device i are respectively fed to the device (i+1) The strobe input CSI and the data strobe input DSI are used as the command strobe input signal SCSI(i+1) and the data strobe input SDSI(i+1). The device (i+1) outputs the command strobe output signal SCSO ( i+1) and data strobe output signal SDSO(i+1) to the next device, device (i+2) (not shown).

Figure 12 depicts the common synchronization clock structure. The examples shown include two structures of interconnection. Each device has a structure as shown in Fig. 9. In the example shown, the devices have the same structure. One of the devices displays its output interface circuit in detail while the other displays its input interface in detail. Referring to Fig. 12, a device (device i) has a plurality of multiplexers (Muxs). Similarly, another device (device (i+1)) has a complex demultiplexer (DeMuxs). In the example shown, device i acts as a "transmitter." Similarly, the device (i+1) acts as a "receiver". The clock source 230 provides a common synchronous clock signal CLKcsyc to the two devices, device i and device (i+1). The data transmission from device i and the data received by device (i+1) are synchronized by clock signal CLKcsyc.

In device i, the clock signal CLKcsyc is fed to a buffer, which in turn provides a buffered output clock signal CLKb0 to the multiplexer for multiplex operation. The multiplexed data output by each multiplexer is output from the multiplexer multiplexed data (n bits) and via the differential output buffers. One of the differential output data is output from one of the devices i connected to one of the devices (i+1).

In device (i+1), the clock signal CLKcsyc is fed into the buffer, which in turn provides the buffered output clock signal CLKb1 to the demultiplexer for demultiplexing. The data received at the docking pin is provided to a corresponding input differential buffer that provides buffered output data to the corresponding demultiplexer. The multiplexed data (n bits) is provided from each solution multiplexer. The operation of the multiplexer of the multiplexer and device (i+1) of the device i is synchronized by the common synchronization clock signal CLKcsyc.

The common sync clock structure has some skew factors as shown in Fig. 12, for example:

(i) the difference between the tBUFF in the transmitting and receiving device (the clock insertion time from the clock input pad to the final clock driver set in the synchronization circuit),

(ii) the delay in the signal propagation path including tTs (transmitter output delay),

(iii) tRS (receiver input delay),

(iv) tFL (flight time between transmitter and receiver) and the difference between these delays in multiple signals, and

(v) tJITTER (clock jitter due to many factors, including power level fluctuations, transient electrical characteristics changes on the clock signal line, and noise from other signals present in the system).

Therefore, when many devices are connected in a multi-point manner, they have a limited operating frequency range.

The common synchronizing clock structure has many disadvantages stemming from signal integrity issues such as slow transition from transmission line effects and memory device loading, low noise immunity, and clock phase shifting. Thus, if many devices are driven by a common clock, a common synchronous clock structure having a single clock source as shown in Figure 1 is not suitable for high speed applications.

To improve performance, use a differential clock. A DDR dynamic random access memory (DRAM) product using a poor artery has been proposed. The parallel (multi-point) clock distribution method can be utilized by strict timing conditions and limitations on the distance between the device and the module. However, the multi-point clock is used to capture the address and control information transmitted by the SDR. In both read and write operations, the DDR data is captured using the source sync clock driven by the device providing the data.

In order to solve the problem of parallel distribution of clock structures, another way is the source synchronous clock distribution method. The source synchronous clock distribution method provides more timing margins because many skew sources in the multipoint clock structure are excluded. In the source synchronous clock structure, the clock can be adjusted by the clock regenerator, such as a phase locked loop (PLL) or a lock delay loop (DLL). In the case of a series connection device with a source synchronous clock structure, the PLL is advantageous because it has no short-term jitter accumulation and can in fact provide a jitter filtering function on the input clock. However, PLLs are more complex than DLLs and must consider the stability of the loop.

Figure 13 shows a system with a plurality of memory devices connected in series having a source synchronous clock structure conforming to the sequence of clock distributions, the system forming a ring structure. In the illustrated example system, memory controller 260 is in communication with a plurality (N) of memory devices 262-1, 262-2, ..., and 262-N. The memory controller 260 is coupled to the first memory device 262-1 to transmit control and/or profile information that propagates through the remaining memory devices 262-2 through 262-N in response to the source synchronous clock signal CLKssyc. The initial source sync clock signal CLKssyc is provided by the memory controller 260 and the device provides a synchronized clock signal to the next device. In the system, the last (Nth) memory device 262-N feeds the propagated information back to the memory controller 260, causing the system to form a circular link. The propagated control signal is returned to the memory controller 260 if necessary.

Fig. 14 shows details of one of the memory devices shown in Fig. 13. Referring to Fig. 14, device i has an input circuit 282 for receiving an input signal 283, an output circuit 284 for providing an output signal 285, a clock circuit 286, and a memory core circuit 288. The clock circuit 286 includes a clock regenerator for adjusting the delay of the incoming clock signal and generating a properly synchronized clock signal. For this purpose, there are possible implementations of various clock regenerators, such as using a PLL or DLL to adjust or synchronize the clock. In response to the input source sync clock signal CLKssyci 287, the clock circuit 286 passes the clock to the input circuit 282, the memory core circuit 288, and the output circuit 284 for their individual operation. The clock regenerator of clock circuit 286 provides an output source synchronous clock signal CLKssyco 289 synchronized with the input source synchronous clock signal CLKssyci 287 to the next device. The output clock signal CLKssyco 289 is a pattern of the regeneration of the input clock signal CLKssyci 287. Input circuit 282 and output circuit 284 perform interface operations in response to the clock provided by clock circuit 286.

Fig. 15 shows a system having a memory controller and a plurality of memory devices connected in series as shown in Fig. 13. The system has a source synchronous clock structure. In the system, the last device is connected to the controller. Referring to Fig. 15, the system includes a memory controller 310 and serially connected complex memory devices 312-1 to 312-4 having a source synchronous clock structure. Each device is similar to that of Figure 10A, but the timing is different from that of Figure 10A. Each device receives a clock signal from a previous component (a memory device, or for a first memory device or device 1 is a memory controller). Each device has a PLL (not shown) that generates an internal clock. Exemplary details of the architecture of a device having a PLL for clock synchronization are provided in International Patent Publication No. WO/2008/067636 (June 12, 2008).

In the example shown in Figure 15, the source synchronous clock structure requires a PLL in each component (such as a device) to provide an internal clock of the phase shift to capture the output clock or the output clock that provides the phase shift. If, for example, the received clock edge overlaps with the received data transition, the PLL needs to generate a 90° clock phase shift to center the received input clock SCLKI and /SCLKI signals on the data input signal D[0:3 ] The data is valid in the window. On the other hand, if the received clock edge of the SCLKI and /SCLKI signals is centered in the received data valid window, a 90° shift clock is required to generate the output clock signal SCLKO and the complementary output clock signal/SCLKO. (This will be referred to as "SCLKO signal" and "/SCLKO signal" respectively). It is assumed in the following description that the memory device operates in the latter mode.

In the write operation, the memory controller 310 transfers the write command and the write data (Q[0:3]) to the first device (device 1, 312-1) in the device serial connection. The first device 312-1 captures the input data D[0:3] with the input clock, and the input clock is aligned with the center of the incoming data from the controller 310. If the first device 312-1 is a "target" or "designation" device of the write operation, it is determined by the device ID matching to judge according to the ID device that the memory controller 310 issues as a part of the write command, and the captured The data will be written to the memory array (not shown) of that device. In this case, the retransmission of the write command and the writing of the data to the next device in the series connection of the device can be arbitrarily prevented. The ID number of the specified specific device is shown in Fig. 6, as referenced by "147-2", and the input data DI1[0:3] is the "data" of the command format 147-2.

If it is determined that the first device 312-2 is not a "target" or "designation" device of the write operation based on the ID controller that the memory controller 310 issues as part of the write command, it must be accompanied by 90. The displacement clock outputs CKO and /CKO are then transferred into the second component (device 2, 312-2). The second member (device 2, 312-2) receives the retransmitted material from the first member (device 1, 312-1) and the clock aligned with the center of the incoming data. By this method, data is delivered from the first member device 1, 312-1) to the last member (final device 312-3).

The output data DQ[0:3], SCLKO, /SCLKO, SCSO, and SDSO signals from the last device (ie, device 4) in series with the device are fed back to the memory controller 310. The SCSO and SDSO signals are provided to the memory controller 310 to detect valid data points. Unlike the parallel distribution of clocks, controller 310 does not know the true latency of the devices connected in series, so SCSO and SDSO signals are required along with SCLKO and /SCLKO as inputs.

In the read operation, the memory controller 310 issues a read command having the ID number of the designated device to the first device in series with the device. Similarly, if it is determined by the device ID match that the designated device is device 1, device 1 will process the command (ie, read) to access the memory array of that device. The reading result of the first device is transmitted to the second member (device 2, 312-2) together with the 90° displacement clock. Next, the second member (device 2, 312-2) receives the reading of the first member along with the clock aligned with the center of the input material. By this process, the read data is delivered to the memory controller 310 via the remaining devices. The format 147-3 shown in Fig. 6 provides an ID number. The access is performed according to the address included in the command format.

Figure 16 shows the two devices shown in Figure 15. Referring to Fig. 16, a device (device i) and a next device (device i+1) collectively receive a reset signal /SRST, a chip enable signal /SCE, and a pair of clock signals SCLKI and /SCKLI.

The clock inputs CK and /CK of the device i receive the input clock signals SCLKIi and /SCLKIi from the previous device (device (i-1) not shown), and respectively output the corresponding CKO and /CKO outputs from their clock outputs. Output clock signals SCLKOi and /SCLKOi. The device (i+1) receives the output clock signals SCLKOi and /SCLKOi from the device i as the input clock signals SCLKI(i+1) and /SCLKI(i+1), respectively, and outputs CKO and/or respectively from the clock thereof. The CKO outputs the corresponding output clock signals SCLKO(i+1) and /SCLKO(i+1), which are transmitted to the next device, device (i+2) (not shown).

The data input D of the device i receives the input data DIi[0:(n-1)] from the previous device (device (i-1)), and outputs the output data DQi[0:(n-1)] from its data output Q. . The output data DQi(0:(n-1)] from the device i is fed as the data input D of the input data DI(i+1)[0:(n-1)] to the device (i+1). i+1) output Q output output data DQ(i+1)[0:(n-1)] from its data output, which is transmitted to the next device, device (i+2). Command strobe input of device i The CSI and data strobe input DSI respectively receive the command strobe input signal SCSIi and the data strobe input SDSIi from the previous device (device (i-1)). The device i respectively outputs the CSO and the data strobe output DSO output from its command strobe output. The command strobe output signal SCSOi and the data strobe output signal SDSOi. The command strobe output signal SCSOi and the data strobe output signal SDSOi from the device i are respectively fed to the command strobe input CSI and data selection of the device (i+1) Input DSI as the command strobe input signal SCSI(i+1) and data strobe input signal SDSI(i+1). The device (i+1) outputs the command strobe output signal SCSO(i+1) and data respectively. The output signal SDSO(i+1) is gated to the next device, device (i+2) (not shown).

Figure 17 shows the source clocked structure with the PLL. The example shown includes two devices that are interconnected. One of them acts as a transmitter and the other acts as a receiver. Each device has a structure as shown in Fig. 14. In the example shown, the devices have the same structure. One of the devices shows its output interface circuit in detail, and the other shows its input interface circuit in detail. Referring to Fig. 17, a device 312-i, device 1 (transmitter), has a complex multiplexer (Muxs), a PLL 316, a clock multiplexer, a differential input buffer, and a complex differential output buffer.

Another device 312-(i+1) (receiver), device (i+1), includes a complex demultiplexer (DeMux) and a complex differential input buffer.

The input differential clock signal CLKi (CK and /CK) 287 passes through the differential input buffer to the PLL of device i, which provides a regenerated internal clock to the multiplexer to synchronize the operation of the multiplexer. The regenerated internal clock is also fed to the clock multiplexer, which produces the output clock in exactly the same way as the output data is generated to match the delay between the data and the clock path. An output clock is provided to drive the output clock signal transmitted to the device (i+1). The device (i+1) receives the clock and provides its solution to the multiplexer to synchronize the operation of the multiplexer.

Compared to multi-point clock structures, source-synchronized clock structures with PLLs have less skewing components. It has no significant clock insertion delay problem (tBUFF skew) because the internally regenerated clock phase is locked to the input clock. The propagation time skew (tFL) between the two devices i and (i+1) is no longer an issue since the output clock and output data follow the same path. In addition, because the filtering action of the PLL can reduce tJITTER.

The source synchronous clock structure provides a higher frequency operating range than the multi-point clock structure. For example, if the PLL jitter and phase error are well controlled, operation at frequencies exceeding 800 MHz can be achieved. In view of this, the source synchronous clock structure is suitable for use in systems with serially connected memories to provide higher data read bandwidth.

An example of a source synchronous clock structure is disclosed in "Designing High Data Rate Interfaces" in the IEEE 2004 VLSI Circuits Symposium on June 16, 2004.

Fig. 18A shows one of the series connection devices shown in Fig. 15. Referring to FIG. 18A, various input signals (such as SCLKIi, /SCLKIi, SCSIi, and SDSIi signals) and input data DIi[0:3] are provided to the i-th device "device i" 312-i in the device connected in series, and That device provides various output signals (such as SCLKOi, /SCLKOi, SCSOi, and SDSOi signals) and input data DOi[0:3]. In a particular example, the data has four bits [0:3]. The data can have another bit number.

The device 312-i includes a clock I/O circuit 401 having a phase locked loop (PLL), a data I/O circuit 403, a strobe I/O circuit 405, and a control circuit 407 having a memory core circuit. The clock I/O circuit 401 receives the SCLKIi and /SCLKIi signals at the clock inputs CK and /CK, and outputs the SCLKOi and /SCLKOi signals via the clock outputs CKO and /CKO. The clock I/O circuit 401 provides a reference clock signal Ref_clk to the data I/O circuit 403 and the strobe I/O circuit 405. The reference clock signal Ref_clk is provided as an internal clock signal. The clock I/O circuit 401 generates a complex clock signal. In a particular example, the clock I/O circuit 401 outputs clock signals of 180°, 270°, and 360° phase shifts to the data I/O circuit 403 and the strobe I/O circuit 405.

A signal SVREF of the reference voltage Vref is supplied from the memory controller (such as the memory controller 310 shown in FIG. 15) to the data I/O circuit 403 and the strobe I/O circuit 405. The data I/O circuit 403 receives the input data DIi[0:3] and outputs the output data DQi[0:3]. The strobe I/O circuit 405 receives the SCSIi and SDSIi signals and outputs the SCSOi and SDSOi signals. The control circuit 407 receives the internal command strobe input signal iCSI and the internal data strobe input signal iDSI from the strobe I/O circuit 405, and receives the data "write data" to be written from the data I/O circuit 403. The control circuit 407 provides "read data" read from its memory (not shown) to the data I/O circuit 403.

Fig. 18B shows an example of a control circuit having a memory core circuit shown in Fig. 18A. The control circuit 407 performs an ID assignment operation in the initial mode in FIGS. 4 and 5A, and performs a memory access operation in the normal mode in FIGS. 4 and 5B.

Referring to Figures 18A and 18B, the ID assignment circuit 491 performs ID assignment and ID number calculation in the initial mode. The ID of the input ID, IDi, is temporarily stored in the ID register 492. The number of calculation results (i.e., IDi+1) is provided by the device i to the next device. The ID register 492 holds the assigned ID. Thereafter, in the normal mode, the command having the format as shown in FIG. 6 is fed to the ID matching determiner 493 and the command interpreter 495. The ID matching determiner 493 determines whether the input ID number matches the assigned ID held in the ID register 491, and if it matches, provides a logical "high" ID matching signal, and the ID matches. If there is no match, the ID match signal is logic "low". In the case where the ID matching judgment is made with IDi, the device i is a designated or target device. In the case of no ID matching, device i is not a designated device. The command interpreter 495, including the OP code decoder, decodes the OP code contained in the input command in response to the "high" ID match signal and provides an interpreted command (such as write, read). In response to the interpreting command and the ID matching signal, the mode signal generator 497 provides a "primed" signal. In a particular example, the prepare signal is logic "low" when there is no ID match. When there is an ID match, the OP code is "read" (that is, the command is a data read command) and "write" (that is, the command is a data write command), and the preparation signals are logical "high" and "" respectively. low". In response to the interpreted command, for example, writing data to or receiving data from the memory core circuit 498 receiving the internal command strobe input signal iCSI and the internal data strobe input signal iDSI. An example of a command interpreter is disclosed in International Patent Publication No. WO/2008/067659 (June 12, 2008). An example of an ID match determinator is disclosed in U.S. Patent Publication No. 12/034,686.

Fig. 18C shows the details of the clock I/O circuit 401 shown in Fig. 18A. Referring to Figures 18A and 18C, the SCLKIi and /SCLKIi signals are fed to the "+" and "-" inputs of input buffer 411, which provides a reference clock input "Ref_clk input" from reference clock signal Ref_clk to PLL 413. The reference clock signal Ref_clk transitions during the SCLKIi signal transition (eg, from "high" to "low") and the /SCLKIi signal transitions in the opposite direction (eg, from "low" to "high"). The PLL 413 operates in synchronization with the transition of the reference clock signal Ref_clk.

The PLL 413 includes an oscillator and generates four phase shifts of 90°, 180°, 270°, and 360° with respect to the input reference clock signal Ref_cLk via buffers 414-1, 414-2, 414-3, and 414-4, respectively. Clock signal. The four 90°, 180°, 270°, and 360° phase shift clock signals referenced by Clk90, Clk180, Clk270, and Clk360 are hereinafter referred to as “Clk90 signal”, “Clk180 signal”, “Clk270 signal”, and “Clk360, respectively. signal". The Clk360 signal is fed to the oscillation input "Osc_loop input" of the PLL 413. The Clk360 and Clk180 signals are fed to select inputs of selectors 417 and 419, respectively. Each of the selectors 417 and 419 inputs a logic "0" and "1" signals at "0" and "1", respectively. In the selector 417, a "0" or "1" input is selected in response to the Clk360 signal, and an output signal thereof is supplied as an SCLKOi signal via the output buffer 421. Similarly, in the selector 419, a "0" or "1" input is selected in response to the Clk180 signal, and an output signal thereof is supplied as an /SCLKOi signal via the output buffer 423. The SCKO and /SCKO signals are therefore 180. Complementary differential clock signals out of phase. Selectors 417 and 419 are required to match the delay between the clock and the data path.

Fig. 18D shows the details of the data I/O circuit 403 shown in Fig. 18A. Referring to Figures 18A and 18D, the reference voltage signal SVREF is provided to the "-" input of the input buffer 425. The input data DIi[0:3] is fed to the "+" input of the input buffer 425, and the output <0:3> is fed to the data input "D of the D-type flip-flops (D-FF) 461 and 463. It is time-controlled by the positive and negative edges of the reference clock signal Ref_cLk to capture DDR data. Although the device has a four-bit data path, only the circuit for a single bit is displayed. The circuit component processing data is repeated four times in the real device. The four-bit output Din1[0:3] of the D-FF 463 contains bits 4, 5, 6, and 7 and is fed to the "0" input of the selector 465. Similarly, the four-bit output Din2[0:3] of D-FF 463 contains bits 0, 1, 2, and 3 and is fed to the "0" input of selector 467. The "1" inputs of selectors 465 and 467 receive read data as Rout1[0:3] (bits 4, 5, 6, and 7) and Rout2[0:3] (bits 0, 1, 2, and 3, respectively). ). The selectors 465 and 467 perform a selection operation based on the "prepare" signal. When the device is selected by the /SCE signal and the device is selected based on the ID matching determination, the preparation signal becomes "high" and is "low" when not selected. The selected output signals from selectors 465 and 467 are fed to the data inputs of D-FFs 469 and 471, which are clocked by Clk 180 and Clk 360 signals, respectively, for data latch operation. The output data of the internal latch of the D-FF 469, Do1[0:3] and the internal latch of the D-FF 471, Do0[0:3] are fed to the "1" and "0" inputs of the selector 473, respectively. It performs a selection operation in response to the Clk270 signal. The output from the selection of selector 473 is provided via output buffer 475 as output data DQi[0:3].

Figure 18E shows the strobe I/O circuit 405 shown in Figure 18A. Referring to Figures 18A and 18E, the reference voltage signal SVREF is supplied to the "-" inputs of the input buffers (compensators) 427 and 429. SCSIi and SDSIi are fed to the "+" inputs of input buffers 427 and 429, respectively, and their outputs are provided to the D inputs of D-FFs 431 and 433. The D-FFs 431 and 433 perform a latch operation in response to the reference clock signal Ref_clk. The D-FFs 431 and 433 output an internal command strobe input signal iCSI (hereinafter referred to as "iCSI signal") and an internal data strobe input signal iDSI (hereinafter referred to as "iDSI signal"), which are supplied to the core logic circuit 407.

The iCSI signal is fed to the D inputs of D-FFs 437 and 439 that are timed by the Clk180 and Clk360 signals, respectively. The D-FFs 437 and 439 output the iCSO1 and iCSO0 signals, which are fed to the "1" and "0" inputs of the selector 441, respectively. In response to the Clk 270 signal, the selected output signal from selector 441 is provided as an SCSOi signal via output buffer 443. The iDSI signal is fed to the D inputs of D-FFs 445 and 447 that are timed by the Clk180 and Clk360 signals, respectively. Similarly, the iDSO1 signal from D-FF 445 and the iDSO0 signal from D-FF 447 are fed to the "1" and "0" inputs of selector 449, and selector 449 selects iDSO1 and iDSO0 in response to the Clk270 signal. One. The selected output signal from selector 449 is provided as an SDSOi signal via output buffer 451.

Fig. 19 shows various signals and data of the source synchronous clock structure shown in Figs. 18A to 18E. Referring to Figures 18A through 18E and 19, each device includes a PLL that establishes a 90° phase difference between the SCLKOi and /SCLKOi signals and the output data DQi[0:3], SCSOi, and SDSOi signals to provide centering for the next device. The clock. As shown in Fig. 19, the output data DQi[0:3] has a phase difference of 90° between the SCLKOi and /SCLKOi signals.

As described above, in the normal operation mode, the preparation signal has a "logic" low (i.e., 0) or a "logic" high (i.e., 1) state depending on the ID matching judgment and the operation mode. In the no-ID matching judgment, the device i transfers only the data to the next device (i+1). The ready signal is at logic "0" and is therefore selected by selectors 465 and 467 from D-FF 461 and 463 (Dinl[0:3] (ie, bits 4, 5, 6, and 7) and Din2 [0:3). ] (ie, bits 0, 1, 2, and 3)) latch data and provide output data DQi[0:3] to the next memory device. Also, because of the "preparation" signal control (not shown), it comes from D-FF 461 and 463 (Din1[0:3] (ie, bits 4, 5, 6, and 7) and Din2[0:3] (also That is, the latch data of bits 0, 1, 2, and 3)) is not written into the write register 481. In the case of no ID matching judgment, 8-bit write data (bits 0 to 7) are not supplied to the core logic circuit 407. However, in the ID match determination and write mode, D-FF 461 and 463 (Din1[0:3] (ie, bits 4, 5, 6, and 7) and Din2 [0:3] (ie, bit) The latch data of 0, 1, 2, and 3)) is written into the memory core circuit 498 via the write register 481.

In the case of the ID matching determination and the read operation mode (the preparation signal is logic "1"), the core logic circuit 407 accesses the data storage element therein and reads the data, and writes the read data to the read register. 483. The read data (Rout1[0:3] (bits 4, 5, 6, and 7) and Rout2[0:3] (bits 0, 1, 2, and 3) are respectively selected by the selectors 465 and 467, and Finally, the output data DQi[0:3] is provided to the next device.

When a system with serially connected memory devices is used in some applications, the PLLs in all serially connected memory devices will be turned on to transfer input data to the next device because all input and output buffers are used. Therefore, if there are a large number of memory devices in the system, a large amount of power is consumed due to the PLL operation.

This example addresses this power consumption problem, such as for multi-stacked wafer-based memory with hybrid synchronous time control, such as non-electrical flash memory, which is typically packaged with multi-chip to reduce installation The area of memory on the system board. Along with this, a full source synchronous time control with alternating PLL on and off control features is introduced.

As described above, the plurality of memory devices are connected together. These devices can be grouped, with each group being distinct from other groups by the clock structure.

A system comprising a device having a series connection of PLLs is disclosed in International Patent Publication WO/2008/098367 (August 21, 2008). In the disclosed system, the PLLs in all devices are turned on, and if necessary, the PLLs of all devices are turned off to save power.

Figure 20A shows a system with a memory controller and a plurality of memory devices connected in series. In the illustrated example, the devices are grouped, with each group having a combination of a source synchronized clock structure and a common source clock structure. The last group of last devices is not connected to the source controller but is connected to other controllers or logic (not shown). Referring to Fig. 20A, the memory controller 510 communicates with a plurality of memory devices included in groups 1 to N (512-1 to 512-N). In each of the groups 1 to N, a plurality of devices (e.g., four devices) are connected in series as in Fig. 15. The memory controller 510 sends the input clock signal SCLK11 to the group 1 (512-1), along with the data and other information. Each set of 1 to N outputs its output clock signal to the next group. Group N outputs the output clock signal SCLKON connected in series.

Figure 20B shows a system with a memory controller and a plurality of memory devices connected in series, the device grouping. In the system, each group has a combination of a source synchronous clock structure and a common source clock structure, and the last device of the last group is connected to the controller. In the illustrated example, memory controller 520 is in communication with a plurality of memory devices included in groups 1, 2 through N. In each of the groups 1 to N, the plurality of devices are connected in series as in Fig. 15. The clock transmission path is similar to that of Figure 20A. The output clock signal from group N is provided to memory controller 520. Also, the propagation signal containing the data and other information is fed back from the last device of the group N back to the memory controller 520.

In the systems shown in Figures 20A and 20B, the clock structure within a group can be different from the other group. Individual devices within a group can also be timed with different clock structures than other groups. Each memory device can comprise a single die or wafer, or a multi-die or wafer in the form of a multi-chip module (MCM) or a multi-chip package (MCP).

Figure 21A shows an example system implemented in a multi-chip package (MCP) with wire bonding. Referring to Figure 21A, the system has a plurality of memory devices 531-1 through 531-4 mounted in a vertical stack on a substrate 533 which is a wire panel. The device is separated by an insulator 535. The devices 531-1 to 531-4 have a plurality of connection pads 537. The base 533 has a plurality of attachment pads 539. Pads 537 of devices 531-1 through 531-4 are connected by wires 541 to pads 539 of substrate 533 and pads of other devices. The devices 531-1 to 531-4, the base 533, and the electric wires 541 are provided in an MCP enclosure (not shown). The MPC enclosure can include a sealing medium or resin that encloses the system components on all sides, thereby providing a robust package in which the device can be secured. The base 533 has other attachment pads or terminals (not shown) on the side opposite the device. The other terminals are connected to another MCP of the memory controller to transmit or receive signals. Devices 531-1 through 531-4 are capable of communicating with other MCP devices or memory controllers. In this particular example, the system includes four wafers (i.e., four memory devices), but the system includes any number of devices.

Fig. 21B shows another example of an MCP structure having a through hole. Referring to Fig. 21B, the memory devices 551-1 to 551-3 are horizontally disposed to each other in a substrate 553 enclosure (not shown). Each device has a connecting line and a terminal on the crucible base. The terminals between the devices are connected together by a through-hole 555 to cause the device to transmit and receive signals.

Within the package, the loading effect from the wafer input to the wafer pad and associated electrostatic discharge (ESD) structures are the primary cause of interconnect capacitance. However, the load effect of the connections within the module is less severe than the connection between the package and the package on the board. The distance between the two wafers in the MCP is much shorter than the package to package connection. Therefore, the common source clock feature can be an appropriate solution within the MCP, while the source synchronous clock structure can be used for high frequency operation (eg, 200 MHz) package-to-package linkage. In this way, it is not necessary to turn on all PLLs in the MCP. High frequency operation and relatively low power consumption can be achieved at the same time.

Figure 22 shows a system with hybrid synchronized clock features based on MCP inter-MCP source synchronization time control and MCP devices within the MCP. Referring to Fig. 22, the complex numbers (N) MCP1 to MCPN (561-1 to 561-N) are connected in series and communicate with a memory controller (not shown). In this particular example, each MCP has four devices connected in series.

Each device has a data input D and a data output Q for receiving input data and transmitting output data. Each device includes a PLL for regenerating the clock signal. The memory controller sends the input data DI containing information of various data and instructions to MCP1, 562-1. And, the memory controller transmits a pair of input clock signals SCLKI and /SCKI to MCP1, and the input clock signals SCLKI and /SCKI are fed together to all devices of the MCP1. The data signal DI is fed to the data input D of the first device of the MCP1 and propagates through the MCP1 in response to the clock signals SCLKI and /SCKI.

In the specific example shown in FIG. 22, in each of MCP1 to MCPN, the PLLs of the first to third devices are turned off (ie, disabled) and the PLL of the fourth device is turned on (ie, enabled). . The logic "low" and "high" level voltages "Vss (such as 0 volts)" and "Vdd (such as positive voltage)" are provided to the PLL to be turned on or off. The last device of each MCP performs the function of clock regeneration and provides a regenerated clock signal to the next MCP. In the particular example shown in Figure 22, the clock structures in each MCP are co-synchronous timed. However, the first device of MCP2 to MCPN (562-2 to 562-N) receives the regenerative clock signal from the last device of the previous MCP, and therefore, the first device of MCP1 to MCPN is time-controlled by the source synchronization clock. The input data DI containing information of various materials and instructions is transmitted through the MCP1 to MCPN device, and the last device of the MCPN outputs the output data DQ. And, the output clock signals of SCLKO and /SCKLO are output from the last device of the MCPN.

In the system shown in Figure 22, the last device (wafer or component) of the MCP has an enabled PLL to transfer the data and the clock aligned with the center of the data to the next MCP to optimize the high frequency operation. performance. The PLL of the last device of each MCP is turned on with a logic level "high" voltage Vdd, and the PLL is enabled. The PLL of the other devices in each MCP is turned off with a logic level "low" voltage Vss, and thus the PLL is disabled.

In the system shown in Fig. 22, the devices in each MCP are in common synchronous time control. The inputs and outputs of all MCPs operate at the clock aligned with the center of the data. The MCP operates in sync with the source.

In the example shown in Fig. 22, only one PLL of each MCP is enabled. The same clock structure can also be applied to individual devices mounted directly on a printed circuit board (PCB). There is no need to regenerate the clock in each device or module. The common sync clock structure can drive more than a single device, allowing the PLLs in some devices to be turned off to conserve power.

It will be apparent to those of ordinary skill in the art that the number of devices within an MCP is not limited to four and more than one device can be connected in the MCP.

Figure 23A shows another system with a hybrid source clock structure based on a series interconnected MCP device. Referring to Fig. 23A, the complex numbers (N) MCP1 to MCPN (572-1 to 572-N) are connected in series and communicate with a memory controller (not shown). Each MCP has a plurality of devices (e.g., four) connected in series. Each device has a data input D and a data output Q for receiving input data and transmitting output data. Each device includes a PLL that regenerates the clock signal.

In the example shown in Fig. 23A, in each of MCP1 to MCPN, the PLL of the first and third devices is turned off (i.e., disabled) by the logic "low" voltage Vss, and the logic "high" voltage Vdd is used. The PLLs of the second and fourth devices are turned off (ie, enabled). Here, every second PLL is turned off.

The memory controller sends the input data DI containing information of various data and instructions to MCP1, 572-1. Moreover, the memory controller transmits a pair of input clock signals SCLKI and /SCKLI to MCP1, and the input clock signals SCLKI and /SCKLI are fed together to the first and second devices of the MCP1. The second device (enable PLL) collectively provides regenerative clock signals SCLKO2 and /SCLKO2 to the third and fourth devices. The fourth device (enable PLL) outputs the regenerated clock signal, which is supplied to the next MCP, MCP2.

In the MCP1, the third device is time-controlled by the source synchronous clock structure, and the second and fourth devices are time-controlled in a common synchronization clock structure. In each of the other MCPs, the second and fourth devices are time-controlled in a common synchronization clock structure, and the first and third devices are time-controlled by the source synchronization clock structure.

The data signal DI is fed to the data input D of the first device of the MCP1 and propagates through the devices in the MCP1 in response to the clock signals SCKLI and /SCKLI. The input data DI containing information of various materials and instructions is transmitted through the MCP1 to MCPN device, and the last device of the MCPN outputs the output data DQ. And SCLKO and /SCKLO are output from the last device of the MCPN.

Figure 23B shows another system with a hybrid source clock structure based on a series interconnected MCP device. Referring to Fig. 23B, the complex numbers (N) MCP1 to MCPN (582-1 to 582-N) are connected in series. In a particular example, each MCP includes eight complex devices connected in series. In each MCP, the PLLs of the first to third and fifth to seventh devices are turned off (i.e., disabled) by a logic "low" voltage Vss. The PLLs of the fourth and eighth devices are turned on (i.e., enabled) by a logic "high" voltage Vdd. Each enabled PLL outputs a regenerative signal to the next device in response to the input clock signal. The system of Figure 23B is an eight chip package pedestal. If the maximum operating frequency can be applied to the situation shown without signal integrity issues, any number of devices and MCPs can be connected.

In the system shown in Figures 23A and 23B, two of the devices (wafers or members) of each MCP are turned on to achieve high speed operation.

In order to achieve the above-described hybrid synchronous clock structure, a device selection method for whether or not the PLL of each wafer should be turned on is required before the start of normal operation. An exemplary method of selecting a PLL for a wafer (or component) is to use an external pin for each wafer (or component) that enters the MCP. Figures 22, 23A and 23B show how four, one, one and eight choices are made by the fixed voltages Vss and Vdd.

In the source synchronous clock structure, it is assumed that the SCLKI and /SCKLI signals are aligned in the center of the input data window, and the SCLKO and /SCKLO signals are also aligned in the center of the output data of the next series connection member. This alignment with the data is achieved by the phase shift of the PLL.

In the hybrid synchronous clock structure, the source synchronous clock structure is the same as the previous one, and the input and output data aligned with the center of the clock are transmitted. The 90° clock phase shift of the clock is performed at the output stage as shown in Figures 18A-18D and 19. This is for the overall use of source synchronization clock junctions outside the MCP It is necessary to use a common synchronous clock structure within the MCP, that is, locally.

This way. A wafer (or component) having a disabled PLL in a mixed synchronous clock structure takes an input signal in a common synchronous clock structure, and a device having a PLL enabled regenerates a clock to transmit an output data to a disable PLL Work cycle correction and 90° clock phase shift are performed before the next device.

In the example system shown in Figures 22, 23A and 23B, the first MCP receives the centrally aligned clock and data from another device, such as a memory controller. An example of a central alignment clock and data is disclosed in U.S. Patent Application Serial No. 12/325,074, filed on Nov. 28, 2008.

Fig. 24A shows one of the devices connected in series as shown in Fig. 15. This device is used in a hybrid synchronous clock structure.

In this particular example, the clock is center aligned. In this example, a PLL enable signal PLL_EN (hereinafter referred to as a "PLL_EN" signal) is provided to control the selectively enabled or disabled PLL. Enables (turns on) or disables (turns off) the PLL when the PLL_EN signal is logic high or low. In the example shown, various input data (such as SCLKIi, /SCLKIi, SCSIi and /SDSIi signals) and data DIi[0:3] are input to a device, and various input data (such as SCLKOi, /SCLKOi) are output from a device. , SCSOi and /SDSOi signals) and data DQi [0:3].

The structure of the apparatus of Fig. 24 is similar to that of Fig. 18A. The circuitry of the apparatus shown in Figure 24A further responds to the PLL_EN signal and performs the function of additional data and control signal selection. Accordingly, the components, circuits, signals, and information corresponding to the device of FIG. 18A are shown with the same reference symbols.

Referring to Fig. 24, the apparatus includes a clock I/O circuit 601 having a PLL, a data I/O circuit 603, a strobe I/O circuit 605, and a control circuit 607 having a memory core circuit. The clock I/O circuit 601 receives the SCLKI, /SCLKIi signals, and the PLL_EN signal. The clock I/O circuit 601 outputs the SCLKOi and /SCLKOi signals. The clock I/O circuit 601 provides a reference clock signal Ref_clk to the data I/O circuit 603 and the strobe I/O circuit 605. The clock I/O circuit 601 including the PLL outputs clock signals of 180°, 270°, and 360° phase shifts. A PLL_EN signal is also provided to the data I/O circuit 603 and the strobe I/O circuit 605. A reference voltage SVREF is provided to the data I/O circuit 603 and the strobe I/O circuit 605. The data I/O circuit 603 receives the input data DIi[0:3] and the 180°, 270°, and 360° phase shift clock signals. The data I/O circuit 603 provides an output data DQi[0:3]. The strobe I/O circuit 605 receives 180°, 270°, and 360° phase shift clock signals for the SCSIi and SDSIi signals. The strobe I/O circuit 605 outputs the SCSOi and SDSOi signals. The control circuit 607 receives the internal command strobe input signal iCSI and the internal data strobe input signal iDSI from the strobe I/O circuit 605, and receives the data "write data" to be written from the data I/O circuit 603. Control circuit 607 provides read data to data I/O circuit 603.

The structure of the control circuit having the memory core circuit 607 is similar to that of the control circuit having the memory core circuit 407 shown in FIG. 18B. Control circuit 607 provides a ready signal for logic "high" or "low".

Fig. 24B shows the details of the clock I/O circuit 601 shown in Fig. 24A. Referring to Figures 24A and 24B, the SCLKIi and /SCLKIi signals are fed to the "+" and "-" inputs of input buffer 611, which provides a reference clock signal Ref_clk. The reference clock signal Ref_clk and PLL_EN signals are fed to the PLL 613 including the oscillator. The PLL 613 is turned on and off in response to the logic "high" and "low" of the PLL_EN signal. Four clock signals related to the input reference clock signal Ref_clk phase shifts of 90°, 180°, 270°, and 360° are output via buffers 614-1, 614-2, 614-3, and 614-4, respectively. The PLL_EN signals are fed to select inputs of selectors 621 and 623 interposed between selectors 617 and 619 and output buffers 625 and 627, respectively. The logic "0" and "1" voltages are respectively supplied to the "0" and "1" inputs of each of the selectors 617 and 619. The "1" inputs of selectors 621 and 623 receive the selected output signals from selectors 617 and 619, respectively. A low level voltage Vss (logic "0") is provided to the "0" inputs of selectors 621 and 623. Provide 360. The phase-shifted clock signal (i.e., the Clk360 signal) is supplied to the oscillating circuit input of the PLL 613 and the selector 617. The selected outputs from selectors 621 and 623 are provided as output SCLKOi and /SCLKOi signals via output buffers 625 and 627, respectively. The clock signals of the three phase shifts of 180°, 270° and 360° are provided from the clock I/O circuit 601 (ie, the Clk180 signal, the Clk270 signal, and the Clk360 signal).

Figure 24C shows details of the data I/O circuit 603 shown in Figure 24A. Referring to Figures 24A and 24C, the reference voltage signal SVREF is provided to the "-" input of the input buffer 629. The input data DIi[0:3] is fed to the "+" input of the input buffer 629, and the output <0:3> is fed to the data input "D" of the D-FF 661 and 663 by the reference clock. The positive and negative edges of the signal Ref_clk are time-controlled to capture DDR data. Although the device has a four-bit data path, only the circuit for a single bit is displayed. The circuit component processing data is repeated four times in the real device. The four-bit output Din1[0:3] of the D-FF 661 contains bits 4, 5, 6, and 7 and is fed to the "0" input of the selector 665. Similarly, the four-bit output Din2[0:3] of D-FF 663 contains bits 0, 1, 2, and 3 and is fed to the "0" input of selector 667. The selectors 665 and 667 perform a selection operation based on the "prepare" signal. When the device is selected according to the ID matching judgment and the data reading mode and the device is enabled by the /SCE signal at the same time, the preparation signal becomes "high". The selected output signals from selectors 665 and 667 are fed to the data inputs of D-FFs 669 and 671, which are clocked by Clk 180 and Clk 360 signals, respectively, for data latch operation. The output data of the internal latch of the D-FF 669, Do1[0:3] and the internal latch of the D-FF 671, Do0[0:3] are fed to the "1" and "0" inputs of the selector 673, respectively. It performs a selection operation in response to the Clk270 signal. The selected output <0:3> from the selector 673 is fed to the "1" input of the selector 633.

The reference clock signal Ref_clk is fed to the selection input of the selector 631, and the "0" and "1" inputs receive the internal output data ido[0:3] and ido[4:7 from the outputs of the selectors 665 and 667, respectively. ]. The output signal from the selector 631 is supplied to the "0" input of the selector 633 inserted between the selector 631 and the output buffer 675. In response to the signal PLL_EN, the selector 633 selects the output signal from the selector 631 or the selector 673, and outputs the selected output data <0:3> as the output data DQi[0:3] via the output buffer 675.

Figure 24D shows details of the gated I/O circuit 605 shown in Figure 24A. Referring to Figures 24A and 24D, the reference voltage signal SVREF is provided to the "-" inputs of input buffers 641 and 643. SCSIi and SDSIi are fed to the "ten" inputs of input buffers 641 and 643, respectively, and their outputs are provided to the D inputs of D-FFs 645 and 647. The D-FFs 645 and 647 perform a latch operation in response to the reference clock signal Ref_clk. The D-FFs 645 and 647 output internal command strobe input signals iCSI (hereinafter referred to as "iCSI signals") and internal data strobe input signals iDSI (hereinafter referred to as "iDSI signals"), which are supplied to the core logic circuit 607.

The iCSI signal is fed to the D inputs of D-FFs 649, 651 and 653. The iDSI signal is fed to the D inputs of D-FFs 655, 657 and 659. D-FF 649 and 655 are time controlled by the Clk180 signal. D-FF 651 and 657 are time controlled by the Clk360 signal. D-FFs 653 and 659 are time-controlled by the inverse of the reference clock signal Ref_clk. D-FFs 649 and 651 output iCSO1 and iCSO0 signals, which are fed to the "1" and "0" inputs of selector 677, respectively. In response to the Clk 270 signal, iCSO1 or iCSO0 is selected by selector 677, and the selected output signal is provided to the "1" input of selector 687, and the "0" input receives the output signal of D-FF 653.

The D-FFs 655 and 657 output iDSO1 and iDSO0 signals, which are fed to the "1" and "0" inputs of the selector 679, respectively. In response to the Clk 270 signal, iDSO1 or iDSO0 is selected by selector 679, and the selected output signal is provided to the "1" input of selector 689, and the "0" input receives the output signal of D-FF 659.

In response to the PLL_EN signal, D-FF 687 selects the output signal of selector 677 or D-FF 653, and the selected output signal is provided as an SCSOi signal via output buffer 691. Similarly, in response to the PLL_EN signal, D-FF 689 selects the output signal of selector 679 or D-FF 653, and the selected output signal is provided as an SDSOi signal via output buffer 693.

Fig. 25 shows various signals of the devices shown in Figs. 24A to 24D. In the illustrative example of FIG. 25, in the case where the PLL_EN signal is "low", the PLL 613 is turned off (or disabled) and does not generate the Clk90 signal, the Clk180 signal, the Clk270 signal, and the Clk360 signal. Input data capture in a device that disables the PLL is performed during a period in which the SCSi signal overlaps with the reference clock signal. There is no clock phase shift between the devices that disable the PLL, but the data retention time tHOLD and the set time tSETUP are ensured by the following relationship.

tHOLD=tOUT-tINS+tDTD (1)

tSETUP=tCK×0.5-tHOLD (2)

Where tOUT is the reference clock to output buffer delay, tINS is the clock insertion delay, tDTD is the device-to-device delay, and tCK is the clock period.

As mentioned above, the time margin varies with buffer path delay and device-to-device distance, so a common synchronous clock structure is used only within the MCP or group.

Fig. 26 shows various signals of the devices shown in Figs. 24A to 24D. In this particular example, the clock is center aligned. In the example, the PLL_EN signal is logic "high" which causes the PLL to be turned on or enabled.

Referring to Figures 24A through 24D, 25 and 26, in the case where the PLL_EN signal is logic "high", PLL 613 is turned "on" and generates a C1k 90 signal, a C1k180 signal, a C1k270 signal, and a C1k360 signal.

Unlike the common sync clock structure, the source sync clock structure provides a 90° phase shift and uses a 2-input selector (as shown in Figures 24B and 24D) to match the re-generation of the delay between the clock and the data path. pulse. Since this delay matches the clock of the 90° phase shift, the set and hold time is always the same as tCK × 0.25 in the DDR operation.

This is a hybrid synchronous clock structure. The first method is based on the clock from the memory controller and between the two MPCs aligned with the center of the data. Another clock that is aligned with the edge of the data will be described here. In the case of a clock aligned with the center of the data, there is an unbalanced load between the input data and SCLKI and /SCKLI, as shown in Figures 22, 23A and 23B. Due to the effect of this unbalanced load (see "D" for CK and /CK connections), the phase difference between the clock and the data can be changed from the start of the memory controller. Therefore, this alternative provides a solution. Assume that all input data and output lines are aligned with the edge of the clock, except between the two disabled PLL components.

Figure 27 shows another system in accordance with another embodiment of the present invention. The system includes a plurality of device groups, DGP-1 to DGP-N. The system implements a hybrid synchronous clock structure with a clock aligned with the edge of the data. Each device group has the same structure as the MCP-based system shown in FIG. In the particular example shown in Figure 27, each device group includes four devices having a PLL. The PLL of the first device is turned on (enabled), and the PLLs of the second to fourth devices are turned off (disabled). The first device is time-controlled by the source synchronization clock structure, and the second to fourth devices are time-controlled by the synchronous clock structure by the regenerative clock signals SCLKO and /SCLKO outputted by the first device. The input data DI and the input clock signal have the same load effect on the input side of the MCP for SCLKI and /SCLKI, and they can be easily maintained at the same phase shift for the connected load from the controller to the first MCP.

Figure 28 shows the various signals that are communicated between the controller and the memory device.

In order to create a clock aligned with the edge of the data, the last component of each MCP provides the clock to the next MCP. Without PLL or DLL, the edge-aligned clock can be implemented with a delay path match between the output clock and the output data.

Figure 29A shows another example of a device having an interface for mixing synchronized clock structures.

In the illustrated example, various input signals (such as SCLKIi, /SCLKIi, SCSIi, and SDSIi signals) and data DIi are output to the device, and various output signals (such as SCLKOi, /SCLKOi, SCSOi, and SDSOi signals) are output from the device. Information DQi. Referring to Fig. 29A, the apparatus includes a clock I/O circuit 701 including a PLL, a data I/O circuit 703, a gate I/O circuit 705, and a control circuit 707 having a memory core circuit. The clock I/O circuit 701 receives the SCLKIi, /SCLKIi signals, and the PLL_EN signal. The clock I/O circuit 701 outputs two internally generated clock signals Clk_en1 and Clk_en2 (hereinafter referred to as "Clk_en1 clock signal and Clk_en2 clock signal" respectively to the data I/O circuit 703 and the gate I/O circuit 705. Reference clock signal SVREF to data I/O circuit 703 and strobe I/O circuit 705. Data I/O circuit 703 receives input data DIi[0:3] and provides output data DQi[0:3]. The /O circuit 705 receives the SCSIi and SDSIi signals and outputs the SCSOi and SDSOi signals. The control circuit 707 receives the internal command strobe input signal iCSI1 and the internal data strobe input signal iDSI1 from the strobe I/O circuit 705, and from the data I/O The circuit 703 receives the data "write data" to be written. The control circuit 707 provides read data to the data I/O circuit 703.

The structure of the control circuit having the memory core circuit 707 is similar to that of the control circuit having the memory core circuit 407 shown in FIG. 18B. Control circuit 707 provides a logic "high" ready signal when there is an ID match and a data read command.

Fig. 29B shows the details of the clock I/O circuit 701 shown in Fig. 29A. Referring to Figures 29A and 29B, the SCLKOi and /SCLKOi signals are fed to an input buffer 711 which provides a reference clock signal Ref_clk to the input of the PLL 713 including the oscillator. And, the PLL_EN signal is fed to the enable input "PLL_EN input" of the PLL 713. The PLL 713 produces four clock signals that are phase shifted by 90°, 180°, 270°, and 360° with respect to the reference clock signal Ref_clk. The Clk90 signal, the Clk180 signal, the Clk270 signal, and the Clk360 signal are provided by the PLL 713 via the respective buffers 714-1, 714-2, 714-3, and 714-4. The 360° phase shift clock signal Clk360 is fed into the oscillating input (Osc_loop input) of the PLL 713.

The reference clock signal Ref_clk and the 90° phase shift clock signal Clk90 signal are fed to the "0" and "1" inputs of the selector 715, respectively, and the selected input receives the PLL_EN signal. The signal from the selection of selector 715 is provided as a Clk_enl clock signal. The reference clock signal Ref_clk and the Clk_dly from the delay pattern of the buffer 755 are provided to the "0" and "1" inputs of the selector 725, respectively, and are selected by the selector 725 in response to the PLL_EN signal. The signal from the selection of selector 725 is provided as a Clk_en2 clock signal.

The reference clock signal Ref_clk is also fed to the "0" input of the selector 717, and the "1" input and the selection input of the selector 717 are pulled down (logic "0"), so the selector 717 always selects the signal input by "0". The result is the reference clock signal Ref_clk selected from it. The selected output signal of selector 717 is provided to the select inputs of selectors 719 and 720. Logic "0" and "1" are provided to the "0" and "1" inputs of selector 719, respectively. Logic "1" and "0" are provided to the "0" and "1" inputs of selector 720, respectively. The selected outputs from selectors 719 and 720 are provided through output buffers 721 and 723 as SCLKOi and /SCLKOi signals, respectively.

Figure 29C shows details of the data I/O circuit 703 shown in Figure 29A. Referring to Figures 29A and 29C, the reference voltage signal SVREF is provided to the "-" input of the input buffer (comparator) 727. The input data DIi[0:3] is fed to the "+" input of the input buffer 727, and the output <0:3> of the input buffer 727 is fed to the data input "D" of the D-FF 761 and 763, respectively. Time-controlled by the Clk_enl clock signal and its inverse pattern. In this example, the data latching operation of D-FF 763 shifts 180 degrees of the Clk_enl clock signal from the D-FF 761 phase. Although the device has a four-bit data path, only the circuit for a single bit is displayed. The circuit component processing data is repeated four times in the real device. The four-bit output Din1[0:3] of the D-FF 761 including bits 4, 5, 6, and 7 is fed to the "0" input of the selector 765. Similarly, the four-bit output Din2[0:3] of the D-FF 763 containing bits 0, 1, 2, and 3 is fed to the "0" input of the selector 767. The selectors 765 and 767 perform a selection operation based on the "prepare" signal fed to the selection inputs of the selectors 765 and 767. In this particular example, the ready signal is logic "low" when there is no ID match. When there is an ID match, in the case of data reading and data writing, the preparation signals are "high" and "low", respectively. In response to the preparation signal, the internally selected output signals Do1[0:3] and Do0[0:3] from selectors 765 and 767 are fed to the "0" and "1" inputs of selector 773, respectively, selector 773 The select input receives Clk_en2 from the clock I/O circuit 701. The output data <0:3> from the selection of the selector 773 is supplied as an output data DQi[0:3] via the output buffer 775.

Figure 29D shows details of the gated I/O circuit 705 shown in Figure 29A. Referring to Figures 29A and 29D, the reference voltage signal SVREF is provided to the "-" inputs of the input buffers (comparators) 737 and 739, the "+" inputs of which receive the SCSIi and SDSIi signals, respectively. The outputs of input buffers 737 and 739 are provided to the D inputs of D-FF 741 and 781 and 743 and 783. The Clk_en1 clock signal is supplied to the clock input of D-FF 741 and 743 and the reverse clock input of D-FF 781 and 783, respectively. In response to the Clk_en1 clock signal, D-FFs 741 and 743 respectively output iCSI1 and iDSI1 signals, which are supplied to control circuit 707. The iCSI1 and iDSI1 signals are fed to the "0" inputs of selectors 791 and 793, respectively. Additional internal command strobes and data strobe input signals iSCSI2 and iSDSI2 are provided from D-FF781 and 783 to the "1" inputs of selectors 791 and 793, respectively. The Clk_en2 clock signal is fed to the select inputs of selectors 791 and 793. The selector 791 selects the iCSI1 signal or the iCSI2 signal in response to the Clk_en2 clock signal, and the selected output signal of the selector 791 is supplied as an SCSOi signal via the output buffer 751. The selector 793 selects the iDSI1 signal or the iDSI2 signal in response to the Clk_en2 clock signal, and the selected output signal of the selector 793 is supplied as an SDSOi signal via the output buffer 753.

The control circuit having the memory core circuit 707 has the same structure as that of the 18B.

Referring to Figures 29A through 29D, in the write operation (the ready signal is logic "0"), the latch data from D-FF 761 and 763 (Din1[0:3] (ie, bits 4, 5, 6 and 7) and Din2[0:3] (i.e., bits 0, 1, 2, and 3) are written to the write register 795. After the ID is matched, 8-bit write data (bits 0 to 7) is supplied to the control circuit 707 to store the write data in the core unit included therein. In the normal operation read mode (the preparation signal is logic "1"), after the ID is matched, the control circuit 707 accesses the data storage element therein and reads the data, and writes the read data to the read register. 797. Selecting data (Rout1[0:3] (bits 4, 5, 6, and 7) and Rout2[0:3] (bits 0, 1, 2, and 3)) are selected by selectors 765 and 767, respectively, and Finally, the output data DQi[0:3] is provided to the next memory device. In the read operation, latch data from D-FF 761 and 763 (Din1[0:3] (ie, bits 4, 5, 6, and 7) and Din2[0:3] (ie, bit 0, 1) , 2, and 3)) are not written to the write register 795. Therefore, 8-bit write data (bits 0 to 7) is not supplied to the control circuit 707.

Fig. 30 shows various signals of the devices of the 29A to 29D. Figure 30 depicts the operation of the enabling PLL device in the case of an edge-aligned clock in a hybrid synchronous clock structure. The PLL is enabled by the "high" PLL_EN signal.

Referring to Figures 29A-29D and 30, when the PLL_EN signal is supplied by the logic "high" level voltage Vdd, the PLL 713 starts generating the clock signal of the internal phase shift, and one of them is used (90° phase shift clock signal Clk90) The input data latched on the data input side is a circuit including D-FFs 761 and 763 of the data I/O circuit 703. The clock signal aligned with the edge of the data does not have a time margin if there is no clock phase shift, so a 90° phase shift clock signal is required to be supplied to each input latch, as shown in Figures 29C and 29D. In this case, the phase difference between the input data (DQi, SCSOi, and SDSOi) and the SCLKIi and /SCLKIi signals is extremely important, so the delayed clock "Clk_dly" is used to transmit the output data, and the current pulse and input data arrive at the next step. The input latch level of the device gives the next device time margin. The SCLKOi and /SCLKOi signals of the last component (or device) of each MCP are fed to other MCPs, while the output clocks of the first component (or device) in the same MCP are connected to the other in a common time-controlled manner into the same MCP. member.

In the case where the PLL_EN signal is logic "low" (Vss), the PLL 713 is disabled and the reference clock signal Ref_clk is used to latch the input data and transmit the output data to a component with edge alignment timing. When the delay between the clock and the output data is matched, the clock is aligned with the edge of the output data. In the next component, the input data is captured by the SCLKOi and /SCLKOi signals with a one-cycle delay between the two components, as shown in FIG. Figure 31 shows the various signals of the device. Figure 31 depicts the operation of the disable PLL device for edge-aligned clock conditions in a hybrid synchronous clock structure. The PLL is disabled by the "low" PLL_EN signal.

Using mixed time control, the power consumption from the PLL can be reduced and high speed operation can be provided by the MCP and the grouping device.

A second alternative to implementing a fully source synchronized clock structure has no hybrid synchronous time control.

Since only the source synchronizes the clock structure, there is a way to reduce the power consumption from the PLL. Data capture and transmission can be achieved using alternate PLL on and off (or off and on) operations. In this case, only the source synchronization clock structure is considered, so that full speed performance can be obtained compared to the other first two cases. And, another advantage is that it can be applied to all packet-linked systems, including ring-type linking systems, not limited to MCPs. For a single component package, this technique can be applied without the limitations of the first two cases.

Figure 32 depicts an example of a system with a fully source synchronized clock structure. In the illustrated example, the system includes 14 devices 797-1 through 799-14, each having a -PLL. Each device has an ID register that holds the associated ID of the binary code. In this particular example, the ID is a four-digit binary number. Since no ID is assigned to devices 797-1 to 799-14, its ID register holds the initial ID (i.e., "0000"). The PLL_EN signal of each device according to the LSB (ie, "0") of the initial ID is logic "high". Therefore, the PLLs of all devices are enabled ("on").

Figure 33A shows an example of a plurality of devices having a series connection of a fully source synchronized clock structure that alternates between an edge aligned clock and a central aligned clock. In this particular example, the system uses a clock that is aligned with the edge of the data. Referring to Fig. 33A, in the initial mode, devices 790-1 to 799-14 are assigned ID numbers "0000" to "1101", respectively. The PLL_EN signal of each device is either logic "high" or logic "low" depending on the LSB assigned to the ID of the device. In the particular example shown in Figure 33A, the LSBs of the first, third, ... devices are "0" and their PLL_EN signals are logic "high." The second and fourth ... devices have an LSB of "1" and their PLL_EN signal is logic "low".

Figure 33B shows another example of a plurality of devices having a series connection of fully source synchronized clock structures that alternate between center-aligned clock and edge-aligned clocks. In this particular example, the system uses the clock aligned with the center of the data. Referring to Fig. 33B, in the initial mode, devices 797-1 to 799-14 are assigned ID numbers "0000" to "1101", respectively. The PLL_EN signal of each device is either logic "low" or logic "high" depending on the LSB assigned to the ID of the device. In this particular example, the PLL_EN signals of the first, third, ... devices are logic "low." The second, fourth... device's PLL_EN signal is logic "high." In each of the systems shown in Figs. 32, 33A and 33B, the number N of devices is 14 (even), but the number of devices connected in series is not limited thereto. Also shown in Figures 33A and 33B, the N/2 device is enabled (turned on) and the other N/2 devices are disabled (turned off).

Figure 34A shows one of the devices with a fully source synchronous timed interface. Referring to Figure 34A, the apparatus includes a clock I/O circuit 801 including a PLL, a data I/O circuit 803, a strobe I/O circuit 805, and a control circuit 807 having a memory core circuit. The clock I/O circuit 801 receives the SCLKIi, /SCLKIi signals and outputs the SCLKOi, /SCLKOi signals. The clock I/O circuit 801 provides two internally generated clock signals Clk_in1 and Clk_in2 (hereinafter referred to as "Clk-in1 clock signal and Clk_in2 clock signal" respectively to the data 1/O circuit 803 and the gate I/O circuit 805. The reference clock signal SVREF is supplied to the data I/O circuit 803 and the strobe I/O circuit 805. The data I/O circuit 803 receives the input data DIi (0:3) and provides the output data DQi (0:3). The SCSIi and SDSIi signals are received by the I/O circuit 805 and the SCSOi and SDSOi signals are output. The control circuit 807 provides read data to the data I/O circuit 803. The control circuit 807 receives the internal command strobe input from the strobe I/O circuit 805. Signal iCSI1 and internal data strobe input signal iDSI1, and receive data to be written from data I/O circuit 803. Control circuit 807 provides read data to data I/O circuit 803. Control circuit 807 provides PLL_EN signal to clock The I/O circuit 801, the data I/O circuit 803, and the strobe I/O circuit 805. Further, the control circuit 807 supplies an ID assignment completion signal to the clock I/O circuit 801.

Figure 34B shows a control circuit 807 having a memory core circuit shown in Figure 34A. Referring to Figures 34A and 34B, the ID assignment circuit 371 performs ID assignment and ID calculation in the initial mode. The number (IDi) of the input ID is temporarily stored in the ID register 372. The number of calculation results (i.e., ID+1) is provided by the device i as the output IDo to the next device. The ID register 372 maintains the assigned ID.

ID register 372 provides a one-bit signal 374 representing the logic state of the least significant bit (LSB) assigned to IDi to inverter 376 whose inverted output signal is output as a PLL_EN signal. Therefore, in response to the "0" or "1" of the LSB of the assigned IDi, the PLL_EN signal has a logic state of "high" or "low". And, the ID assignment circuit 371 outputs the ID assignment completion signal 379 after the ID assignment is completed. In the initial mode, the ID register 372 is reset first and the LSBs of all ID registers 372 are "0". Therefore, the PLL_EN signal is logic "high" and the PLLs of all devices are enabled (on), as shown in Figure 32. After the temporary ID, in response to the LSB of the even ID, the PLL_EN signal is logic "high" and responds to the LSB of the odd ID, and the PLL_EN signal is logic "low". In response to the "high" PLL_EN signal, the PLLs of the first, third, and fifth devices are enabled (turned on), and in response to the "low" PLL_EN signal, the PLLs of the second, fourth, ... devices To disable (close), as shown in Figure 33A.

Thereafter, in the normal mode, the command having the format as shown in FIG. 6 is fed to the ID matching determiner 373 and the command interpreter 375. The ID match determiner 373 determines whether the input ID number matches the allocation ID held in the ID register 372, and if they match, provides a logical "high" ID match signal. If there is no match, the ID match signal is logic "low". In response to the "high" ID match signal, the command interpreter 375, including the OP code decoder, decodes the OP code contained in the input command and provides an interpreted command (such as write or read). In response to the interpretation command and the ID match signal, the mode signal generator 377 provides a "prepare" signal. In this particular example, the ready signal is logic "low" when there is no ID match, and is "high" when there is an ID match and the OP code is "read" (ie, the command is a data read command). In response to the interpreting command, for example, writing data to or reading data from a memory core circuit 378 having a data storage or memory component (not shown). The memory core circuit 378 receives the internal command strobe input signal iCSI1 and the internal data strobe input signal iDSI1 from the strobe I/O circuit 805.

Figure 34C shows the clock I/O circuit 801 shown in Figure 34A. Referring to Figures 34A and 34C, a PLL_EN signal is provided to PLL 813. The SCLKIi and /SCLKIi signals are fed to the "+" and "-" inputs of the input buffer 811, and the input buffer 811 provides the reference clock input Ref_clk to the reference clock input "Ref_clk input" of the PLL 813. The PLL 813 includes an oscillator and provides four clock signals having phase shifts of 90°, 180°, 270°, and 360° with respect to the reference clock signal Ref_clk via the buffer buffers 814_1, 814_2, 814_3, and 814_4, respectively. The four phase-shifted clock signals referred to by Clk90, Clk180, Clk270, and Clk360 are hereinafter referred to as "Clk90 signal", "Clk180 signal", "Clk270 signal", and "Clk360 signal", respectively. The Clk360 signal is fed to the oscillation input "Osc_loop input" of the PLL 813. The Clk360 signal, reference clock signal Ref_clk and PLL_EN signals are fed to "1", "0" and select input of selector 817, respectively, and the output signal of selector 718 is fed to the select inputs of selectors 819 and 820.

The "0" and "1" inputs of the selector 819 receive the logic "0" and "1" signals, respectively. The "0" and "1" inputs of the selector 820 receive the logic "1" and "0" signals, respectively. The output signal of the selector 819 is supplied as an SCLKOi signal via the output buffer 821. Similarly, the output signal of selector 820 is provided as an /SCLKOi signal via output buffer 8213. The SCLKOi and /SCLKOi signals are therefore 180° out-of-phase complementary differential clock signals.

The ID assignment completion signal 379 and the PLL_EN signal are fed to an AND gate 853, the logic output signal of which is fed to the selection input of the selector 815. The reference clock signals Ref_clk and Clk80 signals are fed to the "0" and "1" inputs of the selector 815, respectively, and the selected output signals are provided as Clk_in1 clock signals. Further, the PLL signal is fed to the selection input of the selector 824, and the "1" and "0" inputs respectively receive and receive the Clk 270 signal and the reference clock signal Ref_clk. The selected output signal of selector 824 is provided as a Clk_in2 clock signal.

Figure 34D shows details of the data I/O circuit 803 shown in Figure 34A. Referring to Figures 34A and 34D, the reference voltage signal SVREF is provided to the "-" input of the input buffer 825. The input data DIi[0:3] is fed to the "+" input of the input buffer 825, and the output data <0:3> of the input buffer 825 is fed to the data input "D" of the D-FF 861 and 863. Time-controlled by the positive and negative edges of the Clk_in1 clock signal to capture DDR data. Although the device has a four-bit data path, only the circuit for a single bit is displayed. The circuit component processing data is repeated four times in the real device. The four-bit output Din1[0:3] of the D-FF 861 including bits 4, 5, 6, and 7 is fed to the "0" input of the selector 865. Similarly, the four-bit output Din2[0:3] of the D-FF 863 containing bits 0, 1, 2, and 3 is fed to the "0" input of the selector 867. The selectors 865 and 867 perform a selection operation based on the "prepare" signal fed to the selection inputs of the selectors 865 and 867. The selected output signals from selectors 865 and 867 are fed to the data inputs of D-FFs 881 and 883, respectively, which are subjected to C1k_in1 negative and positive edge timing for internal data latching operations.

The internal latch output data Do1_d[0:3] from the internal selection output data Do1[0:3] and D-FF881 of the selector 865 are fed to the "1" and "0" inputs of the selector 885, respectively. The internal latch output data Do0_d[0:3] from the internal selection output data Do0 (0:3) and D-FF 883 of the selector 867 are fed to the "1" and "0" inputs of the selector 887, respectively. The select inputs of drivers 885 and 887 receive the PLL_EN signal. The select output signals <0:3> of selector 885 are fed to the "1" input of selector 888, and the select output signal of selector 887 is <0:3> To the "0" input of the selector 888, the select input of the selector 888 receives the internal clock signal C1k_in2. In response to the internal clock signal C1k_in2, the select output data <0:3> of the selector 888 is provided via the output buffer 802. Output data DQi[0:3].

In the write operation, latch data from D-FF861 and 863 (Din1[0:3] (ie, bits 4, 5, 6, and 7) and Din2[0:3] (ie, bits 0, 1, 2 and 3)) are provided to the write register 795. In the read operation, the control circuit 807 having the memory core circuit accesses the data storage element therein and reads the data, and writes the read data into the read register 897. Selecting data (Routl[0:3] (bits 4, 5, 6, and 7) and Rout2[0:3] (bits 0, 1, 2, and 3)) are selected by selectors 865 and 867, respectively, and Finally, the output data DQi[0:3] is provided to the next memory device.

Figure 34E shows details of the gated I/O circuit 805 shown in Figure 34A. Referring to Figures 34A and 34E, the reference voltage signal SVREF is supplied to the "-" inputs of the input buffers (comparators) 827 and 829. The SCSIi and SDSIi signals are fed to the "ten" inputs of input buffers 827 and 829, respectively. The output of buffer 827 is provided to the D inputs of D-FFs 831 and 835. The output of buffer 829 is provided to the D inputs of D-FFs 833 and 837. The Clk_inl clock signal is supplied to the clock inputs of D-FFs 831 and 833 and to the reverse clock inputs of D-FFs 835 and 837.

In response to the positive edge of the Clk_inl clock signal, D-FFs 831 and 833 perform a latch operation. In response to the negative edge of the Clk_inl clock signal, D-FFs 835 and 837 perform a latch operation. Therefore, D-FFs 835 and 837 are 180° phase shifts of the Clk_inl clock signal. The D-FFs 831 and 833 output an internal command strobe input signal iCSI1 (hereinafter referred to as "iCSI1 signal") and an internal data strobe input signal iDSI1 (hereinafter referred to as "iDSI1 signal"), which are supplied to the control circuit 807. The D-FF8 35 and 837 output another internal command strobe input signal iCSI2 (hereinafter referred to as "iCSI2 signal") and an internal data strobe input signal iDSI2 (hereinafter referred to as "iDSI2 signal").

The iCSI1 and iDSI1 signals are fed to the D inputs of D-FFs 862 and 864, respectively, which are time-controlled by the negative edge of the Clk_inl clock signal. The iCSI2 and iDSI2 signals are fed to the D inputs of D-FFs 866 and 868, respectively, which are clocked by the positive edge of the Clk_in1 clock signal. The iCSI1 signal and the iCSI1_d output signal from the D-FF 862 are fed to the "1" and "0" inputs of the selector 871. The iCSI2 signal from the D-FF 866 and the iCSI2_d output signal are fed to the "1" and "0" inputs of the selector 873. The iDSI1 signal from the D-FF 864 and the iDSI1_d output signal are fed to the "1" and "0" inputs of the selector 875. The iDSI2 signal from the D-FF 868 and the iDSI2_d output signal are fed to the "1" and "0" inputs of the selector 877. The PLL_EN signal is fed to the select inputs of selectors 871, 873, 875, and 877. The selection output signals of the selectors 871 and 873 are fed to the "1" and "0" inputs of the selector 891, respectively. The selection output signals of selectors 875 and 877 are fed to the "1" and "0" inputs of selector 893, respectively. The Clk_in2 clock signal is fed to the select inputs of selectors 891 and 893. The selected output signal from selector 891 is provided as an SCSOi signal via output buffer 843. The output signal from the selection of selector 893 is provided as an SDSOi signal via output buffer 851.

Figure 35A shows various signals of the device shown in Figures 34A through 34E. Referring to Figures 34A to 34E and 35A, in the case where the LSB of the allocation ID is "0", the output signal 374 from the ID register 372 is logic "low" and the output signal of the inverter 376 is "high". Causes the PLL_EN signal to be logic high. When the LSB of the allocation ID is "1", the output signal 374 from the ID register 372 is logic "high" and the PLL_EN signal is logic "low". In response to a PLL_EN signal having a logic "high" or "low", PLL 813 is disabled or enabled.

All memory components have a "0000" ID number as a preset value before the device ID is assigned. Thus, all of the PLLs of all components (or devices) are enabled and they begin the ID assignment operation with all PLLs as shown in Figure 32 turned on. The LSB of the ID is used to determine if the PLL is on (enabled) or off (disabled). If the LSB is "0", the PLL is turned on. Otherwise, in the case where the LSB is equal to "1", the PLL is turned on and off.

The switching between the central alignment time control and the edge alignment time control requires hundreds of cycles in the power-up sequence operation. However, it does not affect the true performance of the component operation. Also, depending on the last device ID number (i.e., the total number of components (or devices) of the ring type connection), the final output may be data aligned with the edge of the data or data aligned with the center of the data.

During the power-up sequence, device address (DA) or device identifier (ID) assignment operations are automatically performed for each device with the enabled PLL. Therefore, for this operation, even if the PLL in all components is on, the input side of each member has the reference clock signal Ref_clk instead of the logic zero state of the ID assignment completion signal 379 as shown in FIG. 34C. Phase shift clock signal. Since the input data already has a clock from the memory controller aligned with the center of the data and the previous component (or device) produces a clock that is aligned with the center of the data. This exception only occurs before the ID assignment. This is controlled by the ID assignment completion signal 379. If it is "low", it will be connected to the "0" input of "Ref_clk". If it is "high", it will be connected to the "1" input of the 90° phase shift clock. The timing relationship between the center-aligned clock and the edge-aligned clock in the memory controller needs to be controlled to support this source synchronization mode. Comparing the case of all open PLLs, this provides a 50% reduction in power consumption when compared to the case of all open PLLs. An example of a centrally-aligned clock and edge-aligned clock control in a memory controller is disclosed in U.S. Patent Application Serial No. 12/325,074, filed on Nov. 28, 2008.

Figure 36A shows another example of a control circuit 807 having a memory core circuit in Figure 34A. Referring to Figures 34A and 36A, the ID assignment circuit 391 performs ID assignment and ID calculation in the initial mode. The number (IDi) of the input ID is temporarily stored in the ID register 392. The number of calculation results (i.e., ID+1) is provided by the device i as the output IDo to the next device. The ID register 392 maintains the assigned ID.

The ID register 392 provides a one-bit signal 394 representing the logic state of the least significant bit (LSB) assigned to IDi to the inverter 396, the inverted output signal of which is provided to the NAND gate. 395. The ID assignment circuit 391 provides an ID assignment completion signal 399 to the NAND gate 395, the logic output signal of which is provided as a PLL_EN signal. The PLL_EN signal and ID assignment completion signal 399 is fed to the AND gate 853. And, the PLL_EN signal is fed to the PLL 813, the AND gate 853, and the selectors 817 and 824.

Thereafter, in normal operation, the control circuit shown in Fig. 36A performs an operation similar to that of the control circuit 807 shown in Fig. 34B.

Figure 37A is a timing diagram of the apparatus shown in Figures 34A, 34C through 34E and 36. Figure 37B is a timing diagram of the apparatus shown in Figures 34A, 34C through 34E and 36 of the disable PLL.

Referring to Figures 34A, 34C through 34E, 37A and 37B, when PLL 813 is on, the data is latched by a 90° phase shift in the input stage. Output signals, such as the SCSOi and SDSOi signals and DQi[0:3], are aligned with the center clock with a 90° phase difference. By shifting the clock, the next device can capture the input data without any clock phase change from the PLL. This is why alternate PLL turn-on (enable) and turn-off (disable) are feasible in a fully source synchronous clock structure.

In a system having the apparatus shown in Figures 34A through 34E, 36A and 36B, the edge alignment output data is provided from a device having a disabled PLL and is enabled and connected to the previous device. Realign the next device. The two timing relationships are repeated in the proposed full source synchronous clock structure (as shown in Figures 35A and 35B and 37A and 37B).

For example, in a system having a controller and a plurality of connected devices, a time synchronization device such as a source synchronization method is used. The source synchronous clock structure provides a higher frequency operating range than the common source synchronous clock structure, such as over 800 MHz, if good control of PLL jitter and phase error. In view of this, a source synchronous clock structure will be employed in systems with serially connected memories to provide higher data read and write ranges and bandwidths.

If, for example, a clock system is well designed and the PLL jitter and phase error are well controlled, the pulse system can allow a higher frequency operating range than the operating range of the common source clock signal.

Figure 38 shows another example of a system having a memory controller 1410 and a plurality of devices connected in series. U.S. Provisional Patent Application No. 60/902,003, entitled "Non-Volatile Memory System", and International Patent Publication No. WO/2008/109981, filed on Feb. 16, 2007. An example of a source synchronization clock method is described in more detail in the 18th of the month. The system includes complex (N) devices 1420-1, 1420-1...1420-N that are connected in series, with N being an integer greater than one.

In the particular example shown in FIG. 38, the memory controller 1410 has a data link DOC[0:7] for the data/address/command, a command strobe output link CSOC, a data strobe output link DSOC, The chip enables the output connection / CEC, the reference voltage link VREF, and the reset output link / RSTC. Further, the memory controller 1410 has a pair of clock output connections CKOC and /CKOC. Each device has a data input D, a command strobe input CSI, a data strobe input DSI, a reset input / RST, a wafer enable input / CE, and a pair of clock inputs CK and / CK. Moreover, each device has a data output Q, a command strobe output CSO, and a data strobe output DSO. The data output Q, the command strobe output CSO, and the data strobe output DSO of one device are respectively coupled to the data input D, the command strobe input CSI, and the data strobe input DSI of the next device. The devices 1420-1 to 1420-N receive the wafer enable signal "/CE", the reset signal "/RST", and the reference voltage "Vref" in parallel from the memory controller 1410. Provide and transmit data in the form of sequence data or parallel data.

The data output DOC[0:7] of the memory controller 1410 provides input data DI1[0:7] to the data input D of the first device 1420-1. The first device 1420-1 provides output data DO1[0:7] to the second device 1420-2. The second device 1420-2 receives the output data DO1[0:7] transmitted from the first device 1420-1 as its input data DI2[0:7]. Each of the other devices performs the same function.

The command strobe input CSI and the data strobe input DSI of one device respectively receive the CSI signal and the DSI signal. Moreover, the command strobe output CSO and the data strobe output DSO of one device respectively transmit the CSO signal and the DSO signal to the next device. Data transmission is controlled by command strobe input and data strobe input in each device. Each device provides a delayed version of the CSI signal and the DSI signal (ie, the CSO signal and the DSO signal) to the next device. In response to the clock signals CK and /CK, the transmission of data, CSI and DSI is performed.

Exemplary details of an architecture having devices connected in series are provided in U.S. Patent Application Publication No. 2007/0076502 (Aug. 5, 2007) and International Patent Publication No. WO/2007/036048. Further example details of an architecture with devices connected in series are provided in International Patent Publications WO/2008/067652 and WO/2008/022454.

The last device (memory device 1420-N) provides output data DO (0:7), command strobe output CSO, data strobe output DSO, and a pair of output clock signals CKO and /CKO to memory controller 1410, respectively. Individual receiving connections are DIC, CSIC, DSIC, CKIC, and /CKIC.

Figure 39 shows an example of a source synchronous clock system including a plurality of devices connected in series. The system includes a controller (not shown) that produces a controller output signal 1510 and series complex devices 1520-1, 1520-2, ..., 1520-N, where N is an integer. In the example of Fig. 39, each of the devices 1520-1, 1520-2, ..., 1520-N includes a PLL 1522 as a clock remodeling device. In Fig. 39, the PLL 1522 of all devices is turned on before the device identifier (ID) is assigned. The PLL 1522 reshapes the clock shape, regardless of the type of clock input, causing each device to generate its own clock. The PLL 1522 enables each of the devices 1520-1, 1520-2, ..., 1520-N to transmit a clearer or better clock signal to the next device. Using the generated clock signal, the output is synchronized to an outgoing signal 1530 and sent to control. All inputs and outputs are controlled by the device's internal PLL 1522.

The controller output signal 1510, which is considered to be the incoming signal by the first device 1520-1, transmits the first device 1520-1 that is connected in series with the memory device. The differential clock (CK and /CK) is used to create an internal reference clock to be input to the PLL 1522. A 90° phase shift clock is then provided, along with the duty cycle correction of the phase shift clock. The data is then captured with an input clock that has been centrally aligned from the controller to perform data capture in the input stage without additional data or clock remodeling by the PLL. The PLL 1522 is used to regenerate the internal clock to provide data from the 90° clock shift of the input clocks CK and /CK. Thus, all devices on the source synchronous clock system produce a clock aligned with the center of the output data.

The PLL 1522 in the first device 1520-1 generates a clock and transmits it to the second device 1520-2. The result of the reading of the first device 1520-1 (if in the data reading operation) or the passing of the incoming data (if it is a transfer operation) is transmitted to the second device 1520-2, along with a 90° shifted clock output. The second device 1520-2 receives the input clock and also generates a new clock based on the input clock received from the first device 1520-1. For example, the second device 1520-2 can receive the data passed from the first device 1520-1, or the result of the reading of the first device, along with the clock aligned with the center of the incoming data. By this flow, data is passed from the first device 1520-1 to the last device 1520-N to provide outgoing data 1530 from a plurality of serially connected memory devices that are considered by the controller as controller input data.

Using the reshaped clock signal, the output in the outgoing signal 1530 is synchronized and sent to the controller. In this case, the clock is also sent to determine which point is the valid output point. The phases of the CK and CKO signals at the input and output of a set of serially connected memory devices are different. Even if the PLL frequency is the same, the frequency does not change. In this example, the PLL acts only as a phase shifter. In the example of Figure 39, the CKO and /CKO signals are sent or returned to the controller, along with the DO signal. In another example, the DO can be sent to another controller. Unlike parallel time control, the output immediate pulse signal is independent of the input.

Without the PLL 1522, the clock train is provided to a simple drive and can change or distort the duty cycle at the output of several connected devices. In fact, in the case of a large number of connected devices, the clock may degrade and become a stable signal. As double data rates (DDRs) become more popular, work cycles become important and can even be critical. One disadvantage of using a PLL is higher power consumption. Even devices with low power PLLs consume more power than devices without PLLs. However, a PLL is required to ensure high frequency operation.

For example, the PLL can contribute about 10% of the total power consumption of the memory device. Assuming the device uses 25mW, the PLL accounts for 2.5mW. In a system with 10 devices, the total power consumption of the PLL is the same as the power consumption of the entire device. Thus, embodiments of the present invention allow for the use of a greater number of devices within the same power consumption threshold.

Embodiments of the present invention include a memory controller that can be implemented in the context of a source synchronous time control method as in the system of Figures 38 or 39. In some embodiments of such a system, only the PLL of every second device is turned on during operation after the initial setup and configuration phases.

According to an embodiment of the present invention, a maximum of 50% of the PLL is in operation, which saves power while ensuring high frequency operation. For example, in a system with three series devices, one of the devices is turned off and the second device is turned on to save some power. In another embodiment, having a 2 device off and 1 device on is more power efficient than a similar configuration with a PLL with alternate device shutdown. In many other cases, about 50% of the device is turned off when each alternating device is off.

Each PLL needs to be turned on before turning the alternate PLL on and off, as shown in Figure 39, which depicts the device PLL during phase configuration prior to operation. This is the state before the ID is assigned, since it is not known here which devices are odd devices, and those are even devices. All device IDs are initially set to 0000. Therefore, in the pre-ID allocation state, all devices have an ID of 0000 and the PLL of each device is turned on, as shown in FIG.

Serial connection is disclosed in International Patent Publication No. WO/2007/109886 (October 4, 2007), WO/2007/134444 (November 29, 2007), WO/2008/074126 (June 26, 2008). An example of ID assignment in a device.

During ID generation, even if each memory device has a unique ID number, it does not affect the clock shape of the center-aligned clock until the last device transmits its ID to the controller. Some fixed time latency is considered in each memory device and controller to avoid faults in the clock and data operations. Therefore, there is no clock remodeling during ID assignment. All devices are enabled even after the ID is assigned to each memory device. After the final ID number is taken from the last device, if the controller should change its clock, the controller begins to reshape the shape of the clock. Between the ID assignment and the timely remodeling, there is enough time to prevent malfunctions. With this extra waiting time, there is no failure caused by sudden changes in the relationship between the time and the data.

Although all devices having a PLL are turned on in the initial setting phase, as shown in Fig. 39, this setting is small compared to the overall operation time of the device. In one example, less than 1 to 5% of the overall time is spent in the set phase. Even in the case where the power is turned on and off frequently, the power consumption in the setting phase is only a small problem.

Figures 40A and 40B show alternate PLL turn-on control in two different operational embodiments. According to some examples of alternate PLL turn-on control, approximately 50% of the PLL power consumption can be saved after the power-on operation. The power-on operation includes, for example, ID generation or distribution of serially connected memory devices.

Different clocks are transmitted for the first case (Fig. 40A) and the second case (Fig. 40B). Figure 40A depicts that the PLL of this device (even device) is on when the least significant bit (LSB) assigned to the ID of the device is "0". Fig. 40B depicts that when the LSB of the allocation ID is "1", the PLL of this device (odd device) is on. In the specific example shown in Figures 40A and 40B, the device ID assigned to each device is a binary code. In Fig. 40A, the plurality of devices 1620-1, 1620-2, 1620-3, 1620-4, ..., 1620-N are connected in series. The odd devices 1620-1, 1620-3... have an open PLL 1622, while the even devices 1620-2, 1620-4... have a closed PLL 1632. When the PLL 1622 of the device having the even ID number ("0000", "0010"...) is turned on, the clock aligned with the center of the data is transmitted to the next device. When the PLL 1632 of the device having the odd ID number ("0001", "0001"...) is off, the clock aligned with the edge of the data is sent to the next device.

In Fig. 40B, the odd devices 1640-1, 1640-3... have a closed PLL 1642, while the even devices 1640-2, 1640-4... have an open PLL 1652. In this case, when the PLL 1642 of the device having the even ID number ("0000", "0010", ...) is off, the clock aligned with the edge of the data is sent to the next device. Also, when the PLL 1652 of the device having the odd ID number ("0001", "0001"...) is turned on, the clock aligned with the center of the data is transmitted to the next device.

Depending on the alternate PLL control mode, the memory controller will expect different clock and data timing relationships based on the detection that would occur before any normal operation begins.

Fig. 41A is a flow chart showing an example of the clock alignment judgment of the ID number of the last device in the series connection device, as in case 1 or the first case described in relation to Fig. 40A. In step 1711, the state of all devices is reset. The PLL of all devices is turned on as shown in Fig. 39. In step 1712, a clock aligned with the center of the data is transmitted from the memory controller, and a clock aligned with the center of the data is received at the memory controller, such as from the last memory body member (last device 1620- N). In step 1713, a unique identifier or ID is assigned to each of the series connected devices 1620-1 through 1620-N. For example, the device ID can be assigned serially. In step 1714, the memory controller receives the ID number assigned to the last device 1620-N. In step 1715, the memory controller determines whether the least significant bit (LSB) of the ID number of the last device is "1".

As shown in step 1716 in FIG. 41A, if the LSB of the ID of the last device is "1" (eg, "1101" (odd ID): "Yes" in step 1715), the data is provided from the memory controller. The edge is aligned with the clock and the clock from the edge of the data is provided from the last device 1620-N to the memory controller. In step 1717, if the LSB of the ID of the last device is "0" (such as "1100" (even ID): "No" in step 1715), the clock from the memory controller is aligned with the edge of the data to The first device 1620-1, and from the last device (such as the device assigned the ID "1100") provides a clock aligned with the center of the data to the memory controller.

Fig. 41B is a flow chart showing another example of the clock alignment judgment of the ID number of the last device in the series connection device, as in the case 2 or the second case described in relation to Fig. 40A. In step 1721, the state of all devices is reset. The PLL of all devices is turned on as shown in Fig. 39. In step 1722, a clock aligned with the center of the data is sent from the memory controller to the first device 1640-1, and the controller receives a clock aligned with the center of the data, such as from a memory body member ( Last device 1640-N). In step 1723, a unique identifier or ID is assigned to each of the series connected devices. In step 1724, the memory controller receives the ID number assigned to the last device 1640-N. In step 1725, the memory controller determines whether the LSB of the received ID number is "1". As shown in step 1726, if the LSB of the ID of the last device is "1" (eg, "1101" (odd ID): "Yes" in step 1725), the last device 1640-N is provided with the center of the data. Clock to memory controller. If the LSB of the received ID is "0" (such as "1100" (even ID): "No" in step 1725), then the memory component (such as the device of ID "1100") is provided with the edge of the data. Pulse to memory controller.

In the method of Figure 41B, particularly in steps 1726 and 1727, the use of a centrally aligned clock in the memory controller is implicit. When resetting the ID number, the center alignment clock is used in the controller. Once the ID number is assigned to the memory device, the pulse will not change.

The flowchart of Fig. 41A is for Case 1, in which an even LSB (LSB = 0) device has an open PLL. The flowchart of Fig. 41B is for Case 2, in which device with LSB = 1, PLL = On. In each case, the number of connected devices is considered. Depending on the number of devices, as well as the situation, choose edge alignment or center alignment clock. The steps in the method only consider the LSB of the ID number assigned to the last device of the series connected device. There are four different situations and the controller has different clock controls for different situations. There are only two different operations or outputs for these four cases: edge alignment or center alignment.

Presently preferred embodiments include a single alternating on/off pattern for a PLL (e.g., one on, one off, one on, one off, etc.) of a plurality of series memory devices. In other embodiments, other patterns may be implemented, but high frequency operation may not be provided. Depending on the ID assignment status, each device can determine the received ID assignment command and whether to turn its PLL on or off based on the LSB of the device's ID number.

The timing alignment varies depending on the number of devices. In the case where the PLL of the even LSB is turned on, and the device string includes an even number of devices, the last device has an edge-aligned clock. For an odd number of devices, the last device has a centrally aligned clock. In the case where the PLL of the odd LSB is turned on, and the device string includes an even number of devices, the last device has a center aligned clock. For an odd number of devices, the last device has an edge-aligned clock. Therefore, the final clock alignment can vary depending on the situation.

Figure 42 shows the ID generation timing in the example power-on sequence. The timing diagram depicts the relative states of the signals that are compared to each other in the power-on sequence, including VCC/VCCQ, /RST, /CE, Ck, /CK, CSI, DSI, and DI. Also, the array signals DSO and DO are displayed. In the particular example shown in Figure 42, N is the device address (in this example, N = 30); "Dev" represents the device number and "CTRL" represents the controller.

A memory controller in accordance with an embodiment of the present invention has features that determine which clock alignment should be assigned. This is based on which of the alternate PLL configurations (odd or even) is turned on, and according to the total number of connected devices in series. Embodiments of the present invention control whether a center alignment or edge alignment clock is transmitted and is performed in an automated manner.

The memory controller according to an embodiment of the present invention can determine which clock to transmit to the memory and which clock to receive from the memory according to the logical configuration of the serially connected memory device. Embodiments of the present invention can be used in conjunction with a fully source synchronous time control method with alternate PLL control. Some PLLs are turned on or off, depending on their location or ID assignment. There is a need for a new type of memory controller in accordance with an embodiment of the present invention.

Figures 43A and 43B show a circuit diagram of an example of a memory controller having data alignment with clock flexibility for the first case (case 1 described above in connection with Figures 40A and 41A). The logical combination is only an example, so that those skilled in the art can easily manufacture different types of circuit configurations. For Case 1, the controller should generate a clock that is aligned with the edge of the data.

Referring to Figures 43A and 43B, Clock_out 1901 and /Clock_out 1902 are synchronized with Clk360_out 1903 to provide a clock alignment with the data center from the memory controller. DO (command/address/data) 1904, CSO (command strobe output) 1905, and DSO (data strobe output) 1906 signals are synchronized with Clk270_out 1907. A clock generator 1910, a PLL 1912, and a complex output buffer having a clock oscillator 1911 generate a clock signal. The internally generated clock signal "Clk_src" 1913 is supplied by the clock oscillator 1911 to the reference clock input "Ref_clock" of the PLL 1912, which generates a plurality of 90°, 180°, 270°, and 360° phase shift clock signals. The 180°, 270°, and 360° phase shift clock signals are provided as Clk180_out 1909, Clk270_out 1907, and Clk360_out 1903 via separate output buffers. Clk180_out 1909, Clk270_out 1907, and Clk360_out 1903 are synchronized with the internally generated clock signal 1913. Clk360_out 1903 and Clk270_out 1907 are provided to mode detection logic circuit 1980 including two selectors 1981 and 1982, each having a "0" and "1" input and selection input. The "0" and "1" inputs of the selector 1981 receive Clk360_out 1903 and Clk270_out 1907, respectively. The "1" input of the selector 1982 receives Clk270_out 1907, and the "0" input of the selector 1982 is a pull-down. The selection input of the selector 1982 is a pull-up and therefore, the "1" input to the output Clk270_out is always selected as the selected 270 clock signal 1983.

Control logic circuit 1924 has various input and output connections. The internal command strobe in the input Icsi of control logic circuit 1924 receives the internal command strobe in signal "icsi" 1925 from D-type flip-flop (D-FF) 1939. Similarly, the internal data strobe in the input Idsi receives the internal data strobe from the D-FF 1957 signal "idsi" 1915. The clock input Iclk receives Clk360_out 1903. The control logic circuit 1924 provides an "ID_assignment_status" signal 1933 from its "Power_up_seq_done" output and a latch ID signal "latch_ID" 1927 from its Oltid output. The "ID_assignment_status" signal 1933 represents a state in which the ID assignment is complete or in progress. The ID assignment status is in the power on sequence.

The "ID_assignment_status" signal 1933 is fed to the selection input of the selector 1981. The output signal from the selection of selector 1981 is provided to the selection inputs of selectors 1921 and 1922, each of which has a "0" and "1" input and selection input. The logic "0" and "1" signals are respectively supplied to the "0" and "1" inputs of the selector 1921. The logic "1" and "0" signals are respectively supplied to the "0" and "1" inputs of the selector 1922. The select inputs of selectors 1921 and 1922 receive the selected output signal from selector 1981. The select output signals of selectors 1921 and 1922 are provided as Clock_out 1901 and /Clock_out 1902 via respective output buffers 1923 and 1926.

Clk360_out 1903 is also provided to command/address/data generator 1928, which provides octet data for bits 0 through 7. The four-bit system of the even-numbered bits [0, 2, 4, 6] and the four-bit system of the odd-numbered bits [1, 3, 5, 7] are supplied to the data D input of the D-FFs 1929 and 1936, respectively. Clk180_out 1909 provides clock input to D-FF 1929 and reverse clock input to D-FF 1936. The even bits [0, 2, 4, 6] and the odd bits [1, 3, 5, 7] are latched in the D-FFs 1929 and 1936, respectively. D-FF 1929 and 1936 provide the input of the even data bit "Even_d" and the odd data bit "Odd_d" to the "1" and "0" of the selector 1937, respectively. "Odd_d" is 180° phase shifted from "Even_d". In response to the selected 270 clock signal 1983, the selector 1937 selects even or odd data bits. The selected data bits are provided as a DO (Command/Address/Profile) 1904 via output buffer 1938.

Control logic circuit 1924 provides command strobe output and data strobe output signals from its outputs CSO_SRC and DSO_SRC, respectively, which are coupled to command strobe output circuit 1941 and data strobe output circuit 1946. The internally generated command strobe output signal in response to Clk360_out 1903 is fed to the D inputs of the two D-FFs 1942 and 1943 of the command strobe output circuit 1941. Clk180_out 1909 provides clock input to D-FF 1942 and reverse clock input to D-FF 1943. The output signals of the D-FFs 1942 and 1943 are supplied to the "1" and "0" inputs of the selector 1944 as "icso_1" and "icso_2" signals, respectively. The "icso_2" signal and the "icso_1" signal are 180° phase shifted. In response to the selected 270 clock signal 1983, the selector 1944 selects one of the "icso_1" and "icso_2" signals, and the selected signal is provided as the CSO 1905 via the output buffer 1945.

The data strobe output circuit 1946 has the same structure as the command strobe output circuit 1941 including two D-FFs and a selector. The data strobe output signal generated in response to C1k360_out 1903 is supplied from control logic circuit 1924 to the D inputs of two D-FFs 1947 and 1948 of data strobe output circuit 1946. C1k180_out 1909 provides clock input to D-FF 1947 and reverse clock input to D-FF 1948. The "idso_1" and "idso_2" output signals from D-FF 1947 and 1948 are fed to the "1" and "0" inputs of selector 1949. The "idso_2" signal and the "idso_1" signal are 180° phase shifted. In response to the selected 270 clock signal 1983, the selector 1949 selects one of the "idso_1" and "idso_2" signals, and the selected signal is provided as a DSO (Data Selection Output) 1905 via the output buffer 1951.

The last (Nth) device 1420-N (see Figure 38) sends the CKO and /CKO signals to the memory controller 1410. The CKO and /CKO signals are provided as "+" and "-" inputs to Clock_in 1934 and Clock_in #1935 to the differential input buffer 1952, which provides a reference clock signal Ref_clk 1953. The reference clock signal 1953 is fed to the reference clock input "Ref_clk" of the PLL 1970 and the "0" input of the selector 1960. The PLL 1970 outputs four clock signals with phase shift and reference clock signal 1953 of 90°, 180°, 270°, and 360°. The 90° phase clock signal is supplied as a "1" input from "Clk90_in" to selector 1960 via the output buffer. The 360° phase clock signal is supplied as "Osc_1oop Input" from "Clk360_in" to PLL 1970 via the output buffer. The "Latch_ID" signal 1927 is provided to the component ID register 1920, which receives the internal data signal 1968 of the octet "Idata[0:7]" from the data register 1940. The component ID register 1920 stores the input data in response to the "Latch_ID" signal 1927. The component ID register 1920 outputs the least significant bit (LSB) of its temporarily stored ID to the AND gate 1950, which receives the "ID_assignment_status" signal 1933. The AND gate 1950 provides a logic output signal to the select input of the selector 1960 to select the clock signal "Clk90_in" of the reference clock signal 1953 or 90° phase shift. The selected clock signal 1959 from selector 1960 provides clock inputs to D-FFs 1939 and 1957.

The last (Nth) device 1420-N (see Figure 38) transmits a DI signal 1931, a DSI signal 1932, and a CSI signal 1916 to the memory controller 1410. The DI signal "data/address/command input" 1931, the DSI signal "data strobe input" 1932, and the CSI signal "command strobe input" 1916 to the memory controller 1410. The reference voltage "Vref" 1917 is generated internally in the memory controller 1410 itself or externally from a power generator (not shown). The reference voltage Vref is supplied to the "-" input of the differential input buffer 1954, and the "+" input thereof receives the CSI 1916. Input buffer 1954 outputs a differential buffer output signal to the D input of D-FF 1939, which outputs an "ics1" signal 1925 to control logic circuit 1924 in response to selected clock signal 1959.

The DSI signal 1932 and the reference voltage Vref signal are supplied to the "+" and "-" inputs of the differential input buffer 1955, and the differential input buffer output signal is fed to the D input of the D-FF 1957. The data signal "D" 1931 and the reference voltage Vref signal are supplied to the "+" and "-" inputs of the differential input buffer 1956, and the differential input buffer output signal 1967 is fed to the latch circuits 1961 and 1963. . Circuit 1961 includes four D-FFs 1965-6, 1965-4, ..., 1965-0 connected in series. The Q output of the D-FF is coupled to the D input of the next D-FF. Similarly, circuit 1963 includes four D-FFs 1965-7, 1965-5, ..., 1965-1 connected in series.

The output signal of D-FF 1957 is provided as an internal data strobe in signal "idsi" 1915. The "idsi" signal 1915 is provided to the control logic circuit 1924 and to the data strobe in circuit 1962 having eight AND gates 1958-7, 1958-6, ..., 1958-0. The clock signal 1959 from the selection of selector 1960 is provided to D-FF 1965-6, 1965-4, ... 1965-0 and D-FF 1965-7, 1965-5, ... 1965-1 Reverse clock input. The differential input buffer output signal 1967 from input buffer 1956 is fed to the D input of D-FF 1965-6 in response to the selected input signal 1959 and sequentially transmitted to the D-FF connected in circuit 1961. And, the differential input buffer output signal 1967 from the input buffer 1956 is fed to the D input of the D-FF 1965-7 in response to the inverted version of the selected input signal 1959 and sequentially transmitted to the connected D- in the circuit 1963. FF. Thus, the data in circuit 1963 is transmitted with a 180° phase shift of circuit 1961. The output signals i7 and i6 of D-FF 1965-7 and 1965-6 are fed to AND gates 1958-7 and 1958-6, respectively. Similarly, the output signals of D-FF 1965-5 and 1965-4, ..., 1965-1, and 1965-0 are fed to the individual AND gates of the data strobes in circuit 1962. Each of the AND gates 1958-7, 1958-6, ..., 1958-0 receives the "idsi" signal 1915. The logic output signal of each of the AND gates 1958-7, 1958-6, ..., 1958-0 is supplied to the data register 1940, which outputs the internal data signal "Idata[0:7]" 1968.

The memory controller does not obtain any input from the output of the last device until the ID number of the last device on the serial device is obtained. After transmitting the initial ID number (such as "0000"), the input of the memory controller receives the input data stream. The judgment of the completion of the ID assignment is performed by the falling edge of the DSI (Data Strobe Input).

Once the memory controller obtains the ID number from the last device connected in series with the memory device, in response to the "Latch_ID" signal 1927, the ID number is stored in the component ID register 1920 and the data register 1940 via D埠1931, such as Shown in Figure 43B. While this operation is being performed, DSI 1932 is also received to inform the start and end points of the memory controller ID number. From the falling edge of the DSI signal, the "ID_assignment_status" signal 1933 determines the transition point based on the delay in which one of the ID numbers is transmitted to the member ID register 1920. Control logic circuit 1924, which receives "idsi" signal 1915 from D-FF 1957, provides an "ID_assignment_status" signal 1933. For ID generation of the memory device, DSI and DSO are used to generate the ID number and transmit the ID number to the next memory device. When the "ID_assignment_status" signal 1933 is in the high state, the memory controller recognizes the end of the ID generation operation, that is, the completion of the device ID assignment.

When the "ID_assignment_status" signal is low, the PLLs of all devices are turned on to initially assign the ID number to all of them. When the "ID_assignment_status" signal is high, all IDs are assigned, and the PLL is turned on only to odd or even devices. Therefore, this is controlled by the ID assignment status signal.

In the initial state, the memory controller does not know the information needed to determine the situation in which the serially controlled device is in. Therefore, the CKO, /CKO, and DO signals are supplied to the memory controller as CK, /CK, and DI as shown in Fig. 43B. The device is not assigned an ID number until the power is turned on. After the power is turned on, the first operation is to reset the device ID so that each device has a zero state ID (such as "0000").

As shown in FIG. 43B, the "ID_assignment_status" signal 1933 and the LSB (stored in the component ID register 1920) assigned to the ID of the last memory device are supplied to the AND gate 1950. In response to the output of the AND gate 1950, the clock selector 1960 selects the clock that the memory controller will provide. In the example of Figure 43B, the output Clk90_in of PLL 1970, which is a phase shifter and pulse remodeling, is coupled to the input of clock selector 1960. In an embodiment, components 1960 and 1970 can all be considered part of the clock configurator. When the AND gate 1950 detects that the ID assignment is complete, if the "ID_assignment_status" signal 1933 is detected as high, the output is the LSB of the component ID register 1920. When the ID assignment is not complete, the clock selector 1960 selects the reference clock signal Ref_clk 1953. The selector 1960 provides the selected clock signal 1959.

In the case of ID assignment, all of the PLLs of the memory device are turned on during ID generation, and the source sync clock from the last device connected in series with the memory device is aligned with the center of the data. As shown in Figures 43A and 43B, the memory controller provides a central alignment signal or edge alignment signal depending on whether the ID assignment has been completed.

Referring back to Figure 43A, the memory controller includes a mode detection logic circuit 1980 to detect whether the ID assignment is complete and to generate a clock signal in response to the detection. In the example of FIG. 43A, mode detection logic circuit 1980 outputs a center-aligned clock aligned with Clk360_out 1903 in response to mode detection logic detecting that the ID assignment has not been completed. The mode detection logic circuit 1980 responds to the mode detection logic detecting that the ID assignment is complete and the output is aligned with the edge of the Clk 270_out 1907, and thus the system is in the normal mode of operation.

Figures 44 and 45 show timing diagrams during ID assignment (production) operations. In the disclosure, the "/" symbol is used to represent a complementary signal (such as /clock).

Figure 46 shows a timing diagram of clock generation in accordance with an exemplary embodiment, along with control outputs that are synchronized with Clock_out and /Clock_out without phase differences, such as CSO/DSO and DO. With the high state of "ID_assignment_status", the clock generation path selector selects the "1" input connected to "Clk270_out" so that there is no phase difference between the clock and data control and data (CSO/DSO/DO). This happens during normal operation after ID assignment.

During the normal operation after the ID assignment, the input clock alignment with the data is determined by the LSB (Least Significant Bit) of the last component ID stored in the "Component ID Register". If the LSB of the ID is "0", the timing relationship between the clock and data control and the data will not change. This is the same as the timing before the ID generation shown in Fig. 45. Except for the state change of "ID_assignment_status", its state changes in response to the data strobe in the signal.

As can be seen, if the last device connected in series with the memory device has "0" as the LSB of the ID, it means that the last device has an open PLL. Figure 47 shows a timing diagram of the clock at the center of the data according to an exemplary embodiment, since the last device has an open PLL. In an alternative case, if the LSB of the ID is "1", it means that the last device has a closed PLL. Therefore, an edge alignment clock is generated therefrom (see the first case of Fig. 40A).

As described earlier, the memory controller according to an embodiment of the present invention may vary depending on the circumstances in which the alternate PLL is turned on/off. Figures 43A and 43B show a memory controller that is matched to the embodiment of the case 1 herein.

49A and 49B depict a memory controller that is matched to the embodiment of the case 2 herein in accordance with another embodiment of the present invention. The structure of the memory controller shown in Figs. 49A and 49B is similar to that of Figs. 43A and 43B. The memory controller modeless detection logic shown in Figures 49A and 49B has an additional inverter 2521 to reverse the LSB of the ID provided by the component ID register 2520. The timing diagram for the second case during ID generation can be similar to the first case because all memory devices have an open PLL (see Figure 39).

In the memory controllers of Figs. 49A and 49B, in the case of the matching case 2, the clock is aligned with the center of the data in both the ID assignment completion and the normal operation. Before the ID is assigned, the LSB even number "on" should be used to reset all IDs, because in the reset phase, as in case 1, all PLLs are turned on, so there is no need to worry about different operation types. In case 2, only odd PLLs are turned on.

Referring to FIGS. 49A and 49B, the clock generator 2510 has a clock oscillator 2511 and a PLL 2512. The internally generated clock signal "Clk_src" is supplied by the clock oscillator 2511 to the reference clock input "Ref_clk" of the PLL 2512 which generates a plurality of 90°, 180°, 270° and 360° phase shift clock signals. The 180°, 270°, and 360° phase shift clock signals are provided as Clk180_out 2508, Clk270_out 2507, and Clk360_out 2503 via separate output buffers. Clk180_out 2508, Clk270_out 2507, and Clk360_out 2503 are synchronized with the internally generated clock signal "Clk_src". The Clk360_out 2503 is provided to select inputs including two selectors 2513 and 2514. The "0" and "1" logic signals are fed to the "0" and "1" inputs of the selector 2513 and the "1" and "0" inputs of the other selector 2514, respectively. In response to Clk360_out 2503, selectors 2513 and 2514 provide complementary output signals that are provided as "Clock out" 2501 and "Clock out #" 2502 via separate output buffers, respectively.

Clk360_out 2503 is also provided to command/address/data generator 2580, which provides octet data for bits 0 through 7. The even bits [0, 2, 4, 6] of the data are supplied to the D-FF controlled by Clk180_out 2508. The odd bits [1, 3, 5, 7] of the data are supplied to another D-FF controlled by the inverse version of Clk180_out 2508. The two D-FFs provide an even data bit "Even_d" and an odd data bit "Odd_d" to the "1" and "0" inputs of the selector 2523. "Odd_d" and "Even_d" are 180° phase shifted. In response to Clk 270_out 2507, selector 2523 selects even or odd data bits. The selected data bits are provided as DO (command/address/data) 2504 via the output buffer.

Control logic circuit 2530 receives Clk360_out 2503, internal command strobe from "icsi" 2534 of D-FF 2561, and internal data strobe from "idsi" 2565 of D-FF 2563. Control logic circuit 2530 provides command strobe output and data strobe output signals from its outputs CSO_SRC and DSO_SRC, respectively, which are coupled to command strobe output circuit 2541 and data strobe output circuit 2551. The internally generated command strobe output signal is fed to the two D-FFs of the command strobe output circuit 2541. The two D-FFs are time-controlled by Clk180_out 2508 and its inverse type, and provide output signals as "icso_1" and "icso_2" to the selector 2524, respectively. In response to Clk270_out 2507, selector 2524 selects one of the "icso_1" and "icso_2" signals, and the selected signal is provided as CSO 2505 via the output buffer.

The internally generated data strobe output signal is supplied from control logic circuit 2530 to the two D-FFs of data strobe output circuit 2551. The two D-FFs are time-controlled by Clk180_out 2508 and its inverse type, and provide output signals as "idso_1" and "idso_2" to the selector 2525, respectively. In response to Clk270_out 2507, selector 2525 selects one of the "idso_1" and "idso_2" signals, and the selected signal is provided as a DSO (data strobe output) 2506 via the output buffer.

The CSI 2536 and the reference voltage "Vref" 2537 are compared by the differential input buffer. Vref is generated internally in the memory controller itself or externally from a power generator (not shown). In response to the clock signal output 2559 from the selection of selector 2560, the D-FF2561 latches the differential buffer output signal. The output signal of D-FF 2561 is provided as an "icsi" signal 2534 to control logic 2530.

Similarly, the DS1 signal 2532 and the reference voltage Vref signal are compared by the differential input buffer and the differential buffer output signal is latched by the D-FF 2563 in response to the clock signal output 2559 from the selection. The output signal of D-FF 2563 provides data strobe in "idsi" signal 2565 to control logic circuit 2530 and circuit 2590 having eight AND gates.

Also, the differential input buffer compares "DI" 2531 with the reference voltage Vref and provides a differential buffer output signal to the two data latch circuits 2591 and 2592, each including four D-FFs connected in series. In each of the data latch circuits, the Q output of one D-FF is connected to the D output of the next D-FF. In response to the selected clock signal output 2559, the latch and the data of the differential buffer output signal are sequentially transmitted via the serial connection D-FF in each of the two data latch circuits 2591 and 2592. The D-FF of circuit 2592 performs data transfer in response to the selected clock signal output 2559 and its inverse pattern. Thus, the data transfer in circuit 2592 has a 180° phase shift from circuit 2591. For example, the output signal i7 of the first D-FF in circuit 2592 is 180° out of phase with the output signal i6 of the first D-FF in circuit 2591. Output signals i7, i6, ..., and i1 are fed to the individual AND gates of the data strobe in circuit 2590. The eight AND gates of the data strobe in circuit 2590 collectively receive the "idsi" signal 2565, and the logic outputs of the eight AND gates are provided to the data register 2540, which outputs the internal data signal "Idata[0:7] "."

Control logic circuit 2530 receives "icsi" signal 2534 from its Icsi input from D-FF 2561 and 2563 and receives an "idsi" signal 2565 at its Idsi input. Control logic circuit 2530 receives Clk360_out 2503 from its Iclk input from clock generator 2510. The control logic circuit 2530 provides an "ID_assignment_status" signal 2533 from its Power_up_seq_done output and a latch ID signal "Latch_ID" from its OItid output. The "ID_assignment_status" signal 2533 represents the completion of the ID assignment.

In Fig. 49A, similar to Fig. 43A, clock_out 2501 and /Clock_out 2502 are synchronized with Clk360_out 2503 to provide clock synchronization from the memory controller. This synchronization is not affected by the state of the "ID_assignment_status" signal 2533. DO (command/address/data) 2504, CSO (command strobe output) 2502, and DSO (data strobe output) 2506 signals are synchronized with Clk270_out 2507. The clock generator 2510 provides signals Clk360_out 2503 and Clk270_out 2507, for example, by a PLL. Similarly, the clock synchronization is not affected by the state of the "ID_assignment_status" signal 2533, as opposed to the controller of Case 1. The memory controller of Fig. 49A does not require the mode detection logic circuit 1980 as shown in Fig. 43A because the clock output does not change regardless of the mode change (ID assignment mode or normal operation mode).

In Fig. 49B, the operation is similar to that of Fig. 43B. Once the memory controller obtains the ID number from the last device connected to the memory device via the D埠2531 to the data register 2540, in response to the "Latch_ID" signal from the control logic circuit 2530, the temporarily stored ID number is stored in the component ID. In the register 1920. While this operation is being performed, DSI 2532 is also received to inform the start and end points of the memory controller ID number. From the falling edge of the DSI signal, the "ID_assignment_status" signal 2533 determines the transition point based on the delay in which the ID number is transmitted to one of the members ID register 2520. For ID generation of the memory device, DSI and DSO are used to generate the ID number and transmit the ID number to the next memory device. When the "ID_assignment_status" signal 2533 is in the high state, the memory controller recognizes the end of the ID generation operation.

As shown in Fig. 49B, the "ID_assignment_status" signal 2533 and the LSB of the last memory device are all supplied to the AND gate 2550, which operates as a comparator. In response to the output of the AND gate 2550, the selector 2560 operating as a clock configurator configures the clock to be provided by the memory controller. The PLL 2570 can communicate with the selector 2560. In one embodiment, both selector 2560 and PLL 2570 can be considered part of the clock configurator. The PLL 2570 of Fig. 49B performs the function of generating a phase shift clock like the PLL 1970 of Fig. 43B. The reference clock signal "Ref_clk" and the 90° phase shift clock signal "Clk90_in" are fed to the selector 2560. The selector 2560 outputs the selected clock signal 2559 in response to an input signal fed from the output of the AND gate 2550 to its selection input. When the LSB of the ID stored in the component ID register 2520 is low, the output signal of the inverter 2521 is high, and then the AND gate 2550 detects that the ID allocation is completed, for example, by detecting the "ID_assignment_status" signal 2533. High. In response to the "high" output signal of AND gate 255, selector 2560 selects Clk90_in as the selected clock signal 2559. When the ID assignment is not complete (i.e., the logic state of the "ID_assignment_status" signal 2533 is low), the clock configurator produces the opposite output (i.e., provides the reference clock signal "Ref_clk") as the selected clock signal 2559. This logic determines the timing of the clock that is expected to be received from the last device or memory member.

For Case 2, automatic detection of Case 2 is possible because the PLL of the first device is off. For case 1, if the PLL of the first device is on, it must be checked to determine whether the ID assignment is in progress; it can only be determined whether the situation 1 exists after the ID assignment is completed.

As described above, the controller can change the type of signal generation in response to the detection of Case 1 or Case 2. A series connected device group typically does not have a hybrid setting; each device in the connected device sequence has the same settings. In the presently preferred embodiment, all devices are controlled according to Case 1 or Case 2, but there is no mixture of the two modes in the same connected device sequence.

Typically, the user makes a decision on use case 1 or case 2; the controller simply detects which of the embodiments is to be performed. The controller may include a logical implementation of both cases, but it only implements one condition at a time depending on the user's choice.

The user can decide on the controller implementation. The embodiments in Figures 43A and 43B and the embodiments in Figures 49A and 49B are equal in terms of power consumption. Two different embodiments can be combined into one controller or can be implemented as different controllers. The user uses the matching controller depending on the method used (such as odd PLL on or off). The controller must match the embodiment of the alternate PLL supply.

Normally, there is no need to switch from one method to another in real time. After the power is turned on, the method is fixed. The selection can be stored in memory or can be re-enabled each time the unit is powered on. However, when the power is turned on, the device ID of all connected devices must be reset. The main purpose is to reduce power consumption. If an embodiment is implemented, there is no need to switch to another embodiment.

The controller can receive or retrieve configuration information from each device, but it only requires configuration information from the last device, as all connected devices will have the same configuration. Based on the configuration information, the controller can detect the configuration and respond to the appropriate clock signal that will be sent.

There is no limit to the number of devices that can be connected together in one of these configurations. One limitation of the known parallel time control method is that even if the device is daisy chained, an infinite number of devices cannot be connected due to clock driveability and signal integrity. In accordance with an embodiment of the invention, any number of devices can be connected together.

The controller can determine the configuration information based on the LSB of the ID of the last device and the number of connected devices. The controller can read the configuration of the last device to determine if it is Case 1 or Case 2.

Figure 50 shows a timing diagram (output signal, second case) generated from the clock of the memory controller after ID generation, according to an exemplary embodiment. For the second case, the timing of the output signal after the ID allocation is substantially similar to the timing of the ID allocation period except "ID_assignment_status". Since the output signal of the memory controller is not controlled by the state in which the ID allocation is completed.

After the ID of the second case is generated, the timing chart (Fig. 51) having the LSB = 0 of the ID is substantially similar to the timing chart (Fig. 48) having the LSB = 1 of the ID. The 52nd picture (the second case) having the LSB=1 of the ID is the same as the 47th picture (the first case) having the LSB=0 of the ID. In the second case, the multiplexer control of the LSB of the ID is performed after the LSB of the ID is reversed. The differences are shown in Figures 43A and 43B and Figures 49A and 49B.

Embodiments of the invention may be described as providing flexible clockwise control of the memory controller (the clock aligned with the center of the data and the clock aligned with the edge of the data). Using the ID number of the last device, the clock alignment control can be determined. Before and after the ID assignment, and the LSB=0 and 1 of the ID may produce different timing diagrams. The edge alignment method uses the same delay path as the clock and data control. The clock structure can be operated with SDR and DDR interfaces.

The embodiments described herein have been referred to a plurality of devices connected in series. Each of the devices in the series connected device group may be a unique physical device, or may be a logical device including a plurality of parallel connected physical devices. The stacked devices connected in series are each assigned to its own ID number and are represented by different devices, as shown in Figures 40A and 40B.

For example, if three parallel connection devices are provided in the middle of a plurality of series connection devices, the three parallel connection devices are considered a logic device in terms of powering or controlling the PLL in accordance with an embodiment of the present invention. It is therefore possible to have devices connected in parallel, but each group of parallel connections is considered a logic device. To turn on the PLL of a logic device (including multiple parallel connections), it is only necessary to turn on one of the plurality of parallel connections. Other PLLs can be turned on, but power consumption is unnecessarily increased.

According to one embodiment of the invention, the PLLs of the alternate series connection devices are turned on, whether the devices are logical devices or physical devices, regardless of the total number of devices. Embodiments of the invention illustrate a method of controlling a device connection.

An alternative to the on/off/on/off (or off/on/off/on) method of alternating PLL power supply is possible, but additional circuitry may be required. The maximum frequency may be limited by this other method. For example, if all PLLs are off except one, system operation is not feasible.

Using the source synchronous signaling method, the connection is only from one device to another, which can be regarded as a point-to-point connection. Point-to-point links ensure high frequency operation.

This technique can be applied to non-electrical devices such as flash devices. Flash devices include any type of flash device, such as NAND flash or NOR flash.

In the above example, the device is a memory device. The memory device can be any of electrical or non-electrical memory. Also, the device can be any semiconductor device whose operation is synchronized with the clock signal.

Electronic devices that use semiconductor devices can include a variety of electrical devices, such as digital still and video cameras, personal digital assistants, mobile computers, sound and music devices, and cell phones.

In the above examples, the devices, components, and circuits are connected to each other as shown for simplicity of explanation. In the practical application of the present invention, components, circuits, and the like can be directly connected to each other. Also, components, circuits, and the like may be indirectly connected to each other via other components and circuits or the like required for operation of the device or device. Thus, in a real configuration, devices, components, and circuits are coupled directly or indirectly to one another.

The above and illustrated examples of the invention are intended to be illustrative only. A person skilled in the art can make changes, modifications, and variations to the specific embodiments without departing from the scope of the invention, which is defined by the scope of the appended claims.

110. . . Memory controller

120-1~120-N. . . Memory device

131. . . Data line

133. . . Control line

135. . . Common clock line

140. . . Memory system

142. . . Main system or processor (host system)

144. . . Memory controller

145-1~145-N. . . Memory device

147-1. . . First command format

147-2. . . Second command format

147-3. . . Third command format

147-4. . . Fourth command format

150. . . Memory controller

152-1~152-N. . . Memory device

160. . . Memory controller

162-1~162-N. . . Memory device

172. . . Input circuit

173. . . input signal

174. . . Output circuit

175. . . output signal

176. . . Clock circuit

178. . . Memory core circuit

177. . . Common synchronization clock signal

210, 220. . . Memory controller

212-1~212-4. . . Memory device

230. . . Clock source

260. . . Memory controller

262-1~262-N. . . Memory device

282. . . Input circuit

283. . . input signal

284. . . Output circuit

285. . . output signal

286. . . Clock circuit

287. . . Input source sync clock signal

288. . . Memory core circuit

289. . . Output source synchronous clock signal

310. . . Memory controller

312-1~312-4. . . Memory device

316. . . PLL

371. . . ID distribution circuit

372. . . ID register

373. . . ID match determinator

375. . . Command interpreter

376. . . Inverter

377. . . Mode signal generator

378. . . Memory core circuit

379. . . ID assignment completion signal

391. . . ID distribution circuit

392. . . ID register

394. . . One-bit signal

396. . . Inverter

399. . . ID assignment completion signal

395. . . Reverse gate

401. . . Clock I/O circuit

403. . . Data I/O circuit

405. . . Gating I/O circuit

407. . . Control circuit

411. . . Input buffer

413. . . PLL

414-1~414-4. . . buffer

417, 419. . . Selector

421, 423. . . Output buffer

425. . . Input buffer

429, 472. . . Input buffer

431, 433. . . D-type flip-flop

441. . . Selector

443. . . Output buffer

445, 447. . . D-type flip-flop

449. . . Selector

451. . . Output buffer

461, 463, 469, 471. . . D-type flip-flop

465, 467, 473. . . Selector

475. . . Output buffer

481. . . Write register

483. . . Read register

491. . . ID distribution circuit

492. . . ID register

493. . . ID match determinator

495. . . Command interpreter

497. . . Mode signal generator

498. . . Memory core circuit

510, 520. . . Memory controller

512-1~512-N. . . Memory device group

531-1~531-4. . . Memory device

533. . . Base

535. . . Insulator

537. . . Connection pad

541. . . wire

551-1~551-3. . . Memory device

553. . . Base

555. . .矽 through hole

561-1~561-N, 572-1~572-N, 582-1~582-N. . . Multi-chip package

601. . . Clock I/O circuit

603. . . Data I/O circuit

605. . . Gating I/O circuit

607. . . Control circuit

611. . . Input buffer

613. . . PLL

614-1~614-4. . . buffer

617, 619, 621, 623. . . Selector

625, 627. . . Output buffer

629. . . Input buffer

641, 643. . . Input buffer

645,647. . . D-type flip-flop

649, 651, 653, 655, 657, 659. . . D-type flip-flop

661, 663, 669, 671. . . D-type flip-flop

663, 665, 667, 673, 677, 679, 687, 689. . . Selector

675. . . Output buffer

691, 693. . . Output buffer

701. . . Clock I/O circuit

703. . . Data I/O circuit

705. . . Gating I/O circuit

707. . . Control circuit

711. . . Input buffer

713. . . PLL

714-1~714-4. . . buffer

715, 717, 719, 720, 725. . . Selector

721, 723. . . Output buffer

727. . . Input buffer

737, 739. . . Input buffer

741, 743, 781, 783. . . D-type flip-flop

751, 753. . . Output buffer

755. . . buffer

761, 763. . . D-type flip-flop

765, 767, 773, 781, 783, 791, 793. . . Selector

775. . . Output buffer

795. . . Write register

797. . . Read register

799-1~799-14. . . Device

801. . . Clock I/O circuit

803. . . Data I/O circuit

805. . . Gating I/O circuit

807. . . Control circuit

811. . . Input buffer

815, 817, 819, 820, 824, 865, 867, 871, 873, 875, 877, 885, 887, 888, 891. . . Selector

821, 823, 843, 851, 890. . . Output buffer

825, 827, 829. . . Input buffer

831, 833, 835, 837, 861, 862, 863, 864, 866, 868, 881, 883. . . D-type flip-flop

853. . . Gate

895. . . Write register

897. . . Read register

1410. . . Memory controller

1420-1~1420-N. . . Memory device

1510. . . Controller output signal

1520-1~1520-N. . . Device

1522. . . PLL

1530. . . Outgoing signal

1620-1~1620-N. . . Device

1622, 1632. . . PLL

1640-1~1640-N. . . Device

1642, 1652. . . PLL

1911. . . Clock oscillator

1910. . . Clock generator

1912. . . PLL

1915, 1916, 1925, 1927, 1931, 1932, 1933. . . signal

1920. . . Component ID register

1921, 1922, 1937, 1944, 1949, 1960, 1981. . . Selector

1923, 1926, 1938, 1945, 1951. . . Output buffer

1924. . . Control logic

1929, 1936, 1939, 1942, 1943, 1947, 1948, 1957, 1965-7~1965-0. . . D-type flip-flop

1928. . . Command/address/data generator

1940. . . Data register

1941. . . Command strobe output circuit

1946. . . Data strobe output circuit

1950, 1958-7~1958-0. . . Gate

1952, 1954, 1955, 1956. . . Differential input buffer

1953. . . Reference clock signal

1959. . . Select clock signal

1961, 1963 latch circuit

1962. . . Circuit

1967. . . Differential input buffer output signal

1968. . . Internal data signal

1970. . . PLL

1980. . . Pattern detection logic

1981, 1982. . . Selector

2510. . . Clock generator

2511. . . Clock oscillator

2512, 2570. . . PLL

2513, 2514, 2523, 2524, 2525, 2560. . . Selector

2520. . . Component ID register

2521. . . Inverter

2530. . . Control logic

2533. . . signal

2541. . . Command strobe output circuit

2550. . . Gate

2551. . . Data strobe output circuit

2559. . . Clock signal output

2561, 2563. . . D-type flip-flop

2565. . . Data register

2580. . . Command/address/data generator

2590. . . Circuit

2591, 2592. . . Data latch circuit

Embodiments of the present invention are discussed with reference to the accompanying drawings in which:

Figure 1 is a block diagram of a prior art system having a plurality of memory devices connected in a multipoint manner;

2 is a block diagram of an overall system with flash memory to which embodiments of the present invention may be applied;

Figure 3 is a block diagram showing the configuration of a serially connected complex memory device to which an embodiment of the present invention can be applied;

Figure 4 is a flow chart showing the operation of the apparatus shown in Figure 3;

5A is a block diagram showing a configuration of a third diagram of an operation of assigning a device identifier (ID);

Figure 5B is a block diagram showing the configuration of Figure 3 of the normal mode operation;

Figure 6 is a block diagram of an example command format used in the configuration shown in Figure 2;

Figure 7A is a timing diagram of single data rate (SDR) operation;

Figure 7B is a timing diagram of dual data rate (DDR) operation;

Figure 8A is a block diagram of an example of a system having a serially connected complex memory device having a common synchronous clock structure;

Figure 8B is a block diagram of another example of a system having a serially connected complex memory device having a common synchronous clock structure;

Figure 9 is a block diagram of one of the memory devices shown in Figure 8A;

10A is a block diagram showing an example of a system having a memory controller and a plurality of memory devices connected in series;

10B is a block diagram of another example of a system having a memory controller and a plurality of memory devices connected in series;

Figure 11 is a block diagram of the two devices shown in Figures 10A and 10B;

Figure 12 is a block diagram of two devices containing a common synchronized clock structure having a common clock source;

Figure 13 is a block diagram of a system having a serially coupled complex memory device containing a source synchronous clock structure;

Figure 14 is a block diagram of one of the memory devices shown in Figure 13;

Figure 15 is a block diagram of a system having a serially connected complex memory device containing a source synchronous clock structure;

Figure 16 is a block diagram of the two devices shown in Figure 15;

Figure 17 is a block diagram of two devices having a source synchronous clock structure;

Figure 18A is a block diagram of one of the series connection devices shown in Figure 15;

Figure 18B is a block diagram of a control circuit having a memory core circuit of the apparatus shown in Figure 18A;

Figure 18C is a block diagram of the clock I/O circuit of the device shown in Figure 18A;

Figure 18D is a block diagram of the data I/O circuit of the device shown in Figure 18A;

Figure 18E is a block diagram of the strobe I/O circuit of the device shown in Figure 18A;

Figure 19 is a timing diagram of the source synchronous clock structure shown in Figures 18A to 18E;

Figure 20A is a block diagram of a system having a source synchronous clock structure and a common synchronous clock having a memory controller and a plurality of memory devices connected in series;

Figure 20B is a block diagram of another system having a memory controller and a serially connected complex memory device including a source synchronous clock structure and a common synchronous clock;

21A is a cross-sectional view showing an example of a multi-chip package (MCP) having wire bonding;

21B is a cross-sectional view showing another example of an MCP structure having a through hole;

Figure 22 is a block diagram of a system having a hybrid synchronous clock structure for an MCP device;

Figure 23A is a block diagram of another system for an MCP device having an alternate hybrid synchronous clock structure;

Figure 23B is a block diagram of another system for another MCP device having another alternate hybrid synchronous clock structure;

Figure 24A is a block diagram of a memory device that receives central alignment data to capture input data and optionally provides a centrally aligned source synchronized clock output;

Figure 24B is a block diagram of the clock I/O circuit shown in Figure 24A;

Figure 24C is a block diagram of the data I/O circuit shown in Figure 24A;

Figure 24D is a block diagram of the gated I/O circuit shown in Figure 24A;

Figure 25 is a timing diagram of the apparatus shown in Figures 24A through 24D of the phase-locked loop (PLL) operation of the disable phase;

Figure 26 is a timing diagram of the apparatus shown in Figures 24A through 24D of the PLL operation enabled;

Figure 27 is a block diagram of a system having an alternate clock structure for an MCP device that synchronizes a clock structure with a source and a synchronous clock.

Figure 28 is a timing chart showing the relationship between the controller and the source sync signal of the first memory device;

Figure 29A is a block diagram of a memory device capable of receiving input data using an edge-aligned clock or a centrally aligned clock;

Figure 29B is a block diagram of the clock I/O circuit of the device shown in Figure 29A;

Figure 29C is a block diagram of the data I/O circuit of the device shown in Figure 29A;

Figure 29D is a block diagram of the strobe I/O circuit of the device shown in Figure 29A;

Figure 30 is a timing diagram of the apparatus shown in Figures 29A through 29D of the PLL operation enabled;

Figure 31 is a timing diagram of the apparatus shown in Figures 29A through 29D of the disabled PLL operation;

Figure 32 is a block diagram of an exemplary system having a plurality of devices having a source synchronous clock structure prior to ID assignment;

Figure 33A is a block diagram of an example system having a plurality of devices after ID allocation;

Figure 33B is a block diagram of another example system having a plurality of devices after ID allocation;

Figure 34A is a block diagram of one of the memory devices used with the source sync clock;

Figure 34B is a block diagram of the control circuit with the memory core circuit shown in Figure 34A;

Figure 34C is a block diagram of the clock I/O circuit shown in Figure 34A;

Figure 34D is a block diagram of the data I/O circuit shown in Figure 34A;

Figure 34E is a block diagram of the strobe I/O circuit shown in Figure 34A;

Figure 35A is a timing diagram of the apparatus shown in Figures 34A through 34E with the enabled PLL;

Figure 35B is a timing diagram of the apparatus shown in Figures 34A through 34E with the disable PLL;

Figure 36A is a block diagram of another example of a control circuit having a memory core circuit shown in Figure 34A;

Figure 36B is a block diagram of another example of the clock I/O circuit shown in Figure 34A;

Figure 37A is a timing diagram of the apparatus shown in Figures 34A, 34D through 34E, 36A and 36B of the enabling PLL;

Figure 37B is a timing diagram of the apparatus shown in Figures 34A, 34D through 34E, 36A and 36B with the disable PLL;

Figure 38 shows another example of a system having a controller and a plurality of devices connected in series by a source synchronous time control method;

Figure 39 shows an example of a source synchronous time control system comprising a plurality of devices connected in series;

Figure 40A shows an example of a full source synchronous time control method in a series connected device with alternating PLL turn-on control;

Figure 40B shows another example of a full source synchronous time control method in a series connected device with alternating PLL turn-on control;

Figure 41A is a flow chart showing an example of clock alignment determination of the ID number of the last device in the series connection device;

Figure 41B is a flow chart showing another example of the clock alignment determination of the ID number of the last device in the series connection device.

Figure 42 shows the timing of the ID generation in the example power-on sequence;

43A and 43B are diagrams showing an exemplary memory controller logic configuration in accordance with an embodiment of the present invention to support flexible data alignment;

Figures 44 and 45 show timing diagrams of the signals of the memory controller shown in Figures 43A and 43B;

Figure 46 is a timing diagram showing clock generation from a memory controller after ID generation, according to an exemplary embodiment;

Figure 47 is a timing diagram showing the clock generation from the memory controller after the ID is generated and the least significant bit (LSB) of the ID = 0, according to an exemplary embodiment;

Figure 48 is a timing diagram showing clock generation from a memory controller after ID generation and LSB = 1 of the ID, according to an exemplary embodiment;

49A and 49B are diagrams showing another example of a memory controller logic configuration in accordance with an embodiment of the present invention to support flexible data alignment;

Figure 50 is a timing diagram showing clock generation from a memory controller after ID generation, according to an exemplary embodiment;

Figure 51 is a timing diagram showing clock generation from a memory controller after ID generation and LSB = 0 of an ID, according to an exemplary embodiment;

Figure 52 shows a timing diagram of clock generation from a memory controller after ID generation and LSB = 1 of the ID, in accordance with an exemplary embodiment.

401‧‧‧clock I/O circuit

403‧‧‧Data I/O Circuit

405‧‧‧Gating I/O Circuitry

407‧‧‧Control circuit

Claims (37)

An apparatus for transmitting data having a period defined by a transition of an input clock signal, the apparatus comprising: a clock circuit comprising: a phase locked loop (PLL) for providing the response to the input clock signal a plurality of reproduced clock signals, the phase of the complex reproduced clock signal being shifted from the data differently, wherein the PLL is configured to be selectively enabled or disabled in response to a control signal having the first and second logic states And a clock output circuit for generating the output clock signal in response to at least one of the plurality of reproduced clock signals, wherein in the case where the PLL is enabled, the PLL is configured to respond to the input Generating the complex regenerative clock signal, and the clock output circuit is configured to generate the output clock signal in response to at least one of the plurality of regenerated clock signals; and synchronizing circuitry for the PLL Synchronizing the data with at least one of the regenerative clock signals when enabled and the synchronization circuit is configured to synchronize the transmission of the data with the input clock signal when the PLL is disabled When the output transition pulse signals occur during the week of that information. The device of claim 1, wherein the clock circuit is further configured to provide an internal clock signal in response to the input clock signal comprising a clock signal and its complementary clock signal. The device of claim 2, wherein the PLL Further configured to generate the complex regenerative clock signal in response to the internal clock signal when the PLL is enabled. The apparatus of claim 2, wherein the synchronization circuit is further configured to synchronize transmission of the data with the internal clock signal when the PLL is disabled. The apparatus of claim 4, wherein the PLL is further configured to output the regenerated clock signals having a phase shift of a multiple of 90° of the data. The apparatus of claim 2, wherein the clock output circuit is configured to generate the output clock signal comprising a clock signal and its complementary clock signal. The apparatus of claim 1, wherein the control signal comprises: a logic signal having a high logic state for enabling the PLL. The device of claim 1, wherein the control signal comprises: a logic signal having first and second logic states for enabling and disabling the PLL, respectively. The device of claim 1, further comprising: a memory for storing data; and an access circuit for accessing the memory. The device of claim 9, wherein the access circuit is configured to write data in the memory in response to the write signal. The apparatus of claim 10, wherein the synchronization circuit is configured to synchronize transmission of data input to the apparatus with transmission of the regenerated clock signal. The device of claim 10, wherein the access circuit is further configured to read the data stored in the memory in response to the read signal. The apparatus of claim 12, wherein the synchronization circuit is configured to synchronize transmission of the read data from the access circuit with the regenerative clock. The device of claim 13, further comprising: a holder for maintaining identification information associated with the device, the identification information being used to identify the device, the access circuit configured to respond to the identification The memory is accessed by the identification of the device. The device of claim 14, further comprising: an identification information provider for providing identification information to the holder, the control signal being provided in response to the identification information held in the holder, the control The signal is one of the logic high and low that respectively causes the PLL to be enabled and disabled. The device of claim 14, further comprising: the identification information provider configured to: Providing identification information to the holder, and providing a completion signal when the supply of the identification information is completed; and the logic circuit configured to provide a logic signal as a control signal in response to the completion signal and the identification information held in the holder The identification information includes a binary number, the control signal is one of a logic high and a logic low in response to the least significant bit of the binary number, and the PLL is enabled in response to the logic high and low of the control signal respectively And disabling; reading data from the memory in response to the data read signal to provide to the second data latch circuit. The device of claim 16, wherein the synchronization circuit is configured to: capture incoming data in response to the first internal clock signal; and synchronize any of the incoming data and the read data And transmission of the second internal clock signal. An apparatus for transmitting data from a first device to a second device, the data having a period defined by a transition of a clock signal: the first device comprising: a first clock circuit comprising: a phase locked loop (PLL) Providing a plurality of first regenerated clock signals in response to the first input clock signal, the phase of the plurality of first regenerated clock signals being shifted from the data differently from each other, wherein the PLL is configured to respond to having the first And the second logic state control signal is selectively enabled or disabled, and a clock output circuit responsive to at least one of the plurality of first reproduced clock signals to generate the output clock signal, wherein in the case where the PLL is enabled, the PLL is configured to respond to the first Generating a clock signal to generate the plurality of first reproduced clock signals, and wherein the clock output circuit is configured to generate the output clock signal in response to at least one of the plurality of first reproduced clock signals; and the first synchronization a circuit for synchronizing the transmission of the data with at least one of the plurality of first reproduced clock signals when the PLL is enabled and configuring the synchronization circuit to synchronize the data when the PLL is disabled And the transmission of the first input clock signal, the transition of the first output clock signal occurs during the period of the data, the second device comprising: a second clock circuit configured to be derived from the first a second input clock signal of the output clock signal provides a plurality of second reproduced clock signals, the phase of the plurality of second reproduced clock signals is different from the data, and the first data input circuit is configured to respond In the first The receiving of the information transmitted from the first clock signal input means. The device of claim 18, wherein: the PLL of the first clock circuit is a first PLL, and the second clock circuit comprises: a second PLL for responding to the second input The plurality of second regenerated clock signals are provided by the pulse signals. The apparatus of claim 19, wherein the second PLL is configured to be selectively enabled or disabled in response to the second control signal. The device of claim 20, wherein: when the second PLL is enabled, the second PLL generates the plurality of second regenerated clock signals in response to the second input clock signal. The device of claim 21, wherein the first data input circuit of the second device is configured to receive the data transmitted from the first device in response to the second clock signal. The device of claim 22, wherein the first device further comprises a second data input circuit for receiving input data synchronized with the first input clock signal, the first synchronization circuit configuration Synchronizing the transmission of the data with at least one of the plurality of first regenerated clock signals. The device of claim 23, wherein: the first input clock signal comprises a clock signal and a complementary clock signal thereof; and the first output clock signal comprises a clock signal and a complementary clock signal thereof . The device of claim 24, wherein: the first clock circuit is configured to provide a first internal time in response to the first input clock signal including the one clock signal and its complementary clock signal a pulse signal; and the first output clock circuit is configured to provide a clock signal and A second internal clock signal of the complementary clock signal. The apparatus of claim 25, wherein the first PLL is further configured to generate the plurality of first regenerated clock signals in response to the first internal clock signal when the first PLL is enabled. The apparatus of claim 26, wherein the first synchronization circuit is further configured to synchronize transmission of the data with the first internal clock signal when the first PLL is disabled. The apparatus of claim 27, wherein the first data input circuit of the second device is configured to receive the data transmitted from the first device in response to the second internal clock signal. The device of claim 28, wherein the first device further comprises: a first identification information provider for providing identification information to the first holder, in response to being held in the first holder The first control signal is provided by the identification information, and the first control signal is one of logic high and low respectively causing the first PLL to be enabled and disabled. A system for transmitting data synchronized with a clock signal reproduced by a device, comprising: a controller; and a plurality of serially connected devices, the operations of which are synchronized with a clock signal, each of the devices comprising: phase lock The loop (PLL) is configured to be selectively enabled, and when enabled, the PLL provides a plurality of regenerative clock signals in response to the input clock signal, The regenerative clock signals are of a different phase shift of the input clock signal; and a synchronization circuit for synchronizing the transmission of at least one of the data and the regenerated clock signals, and in each group, At least one of the devices receives the regenerative output clock from the previous device, the other device receives the common clock signal, and the PLL of the device that outputs the regenerated clock signals is enabled, and the PLL of the other device is Disabled. The system of claim 30, wherein the devices are constructed in a multi-chip package (MCP), and a group of the devices are in a package. The system of claim 31, wherein the source synchronized clock structure is applied between the MCPs of the devices. The system of claim 32, wherein each group includes at least first and second devices, the first device further comprising a data input circuit for receiving input data synchronized with the input clock signal, the synchronization The circuit is configured to synchronize the transmission of the data with the regenerated clock signal. A method for a plurality of devices, each of the plurality of devices comprising a phase locked loop (PLL) responsive to an input clock signal - a device transmitting data to another device, the method comprising: assigning a device identifier to the plurality of devices; Providing a control signal having a level of the device identifier according to the device, Selectively enabling the PLL in response to the control signal having a first level and selectively disabling the PLL in response to the control signal having a second level, the enabled PLL outputting in response to the input clock signal The plurality of clock signals are reproduced, and the reproduced clock signals are different phase shift patterns of the input clock signals. The method of claim 34, wherein the providing step further comprises: providing the control signal having the first and second levels of the device identifier according to the device, in response to the first and second The PLL is selectively enabled or disabled for each of the devices. A method for transmitting time-controlled data according to a clock signal having a period defined by a transition of the clock signal, the method comprising: selectively responding to a control signal having first and second logic states A phase-locked loop (PLL) can be disabled or disabled; in the case where the PLL is enabled, a plurality of regenerated clock signals are generated by the PLL in response to the input clock signal, and the regenerated clock signals are the input clock a pattern of different phase shifts of the signal; generating an output clock signal in response to the complex reproduced clock signal; and synchronizing transmission of the data with at least one of the reproduced clock signals; and wherein the PLL is disabled Next, when synchronizing the data with the input The transmission of pulse signals. A method for transmitting data from a first device to a second device, wherein the data is time-controlled according to a clock signal having a period defined by a transition of the clock signal, the method comprising: at the first device, And providing a plurality of first regenerated clock signals by a phase locked loop (PLL) in response to the first input clock signal, wherein the regenerated clock signals are of a different phase shift pattern of the first input clock signal, wherein the PLL group Generating, in response to the control signal having the first and second logic states, selectively enabling or disabling, and generating the first output clock signal in response to at least one of the plurality of first reproduced clock signals, Wherein in the case where the PLL is enabled, the PLL is configured to generate the plurality of first reproduced clock signals in response to the first input clock signal, and to respond to at least one of the plurality of first reproduced clock signals Generating the output clock signal to synchronize the transmission of the data with at least one of the regenerated clock signals when the PLL is enabled and to synchronize the data with the first input when the PLL is disabled Pulse signal The clock transition of the regenerated clock signal is during the period of the data, the regenerative clock signal being provided as the output clock signal, and in response to the output from the first device, the second device The pulse signal provides a plurality of second regenerative clock signals, the regenerative clock signals being from the first device A pattern of different phase shifts of the output clock signal is received, and the data transmitted from the first device is received.