TW202215244A - Interface device and interface method for 3d semiconductor device - Google Patents

Abstract

An interface device and an interface method for interfacing between a master device and a slave device is provided. The master device generates command and the slave device generates data according to the command. The interface device includes a master interface and a slave interface. The master interface is coupled to the master device and configured to send the command to the slave device and/or receive the data from the slave device. The slave interface is coupled to the slave device and configured to receive the command from the master device and/or send the data to the master device. The master interface and the slave interface are driven by a clock generated by a clock generator. The master interface and the slave interface are electrically connected by one or plurality of bonds and/or TSVs.

Description

Interface device and interface method for three-dimensional semiconductor device

The present disclosure relates to a technique for a three-dimensional (3D) semiconductor device, and more particularly, to an interface device and an interface method for the 3D semiconductor device.

In recent years, electronic devices, such as personal computers (PCs) or smart phones, have been developed in terms of packaging, so that the size of the electronic devices has become compact and the production cost can be reduced accordingly. One of the key factors in the development of electronic devices is 3D semiconductor technology. Various semiconductor devices including a CPU and a memory can be integrated into a single chip by vertically interconnecting a central processing unit (CPU) with the memory. This structure is generally referred to as a 3D integrated circuit (3D integrated circuit, 3D IC). On the other hand, in order to maintain reliable data transfer/communication, the interconnection between one CPU/memory and other CPU/memory needs to be regulated by an interface device. However, interface devices for 3D integrated circuits are still under development.

The present invention provides an interface device and an interface method for a 3D semiconductor device. The interface device and the interface method provide reliable data communication between a master device and a slave device.

In an embodiment, the present invention provides an interface device for interfacing between a master device and a slave device. The master device generates commands and the slave device generates data according to the commands, and the interface device includes a master interface and a slave interface. The host interface is coupled to the host device. The master interface is configured to send the command to the slave device and/or receive the data from the slave device. The slave interface is coupled to the slave device. The slave interface is configured to receive the command from the master device and/or send the data to the master device. The master interface and the slave interface are driven by a clock generated by a clock generator. The master interface and the slave interface are electrically connected by one or more bonding elements. The clock used to drive the slave interface is trained by changing the clock phase of the clock to align with the data clusters of the command and/or the data clusters of the data.

In an embodiment, the present invention provides an interface method for interfacing between a master device and a slave device. The master device generates a command and the slave device generates data according to the command, and the interface method includes: sending the command to the slave device by the master interface and/or receiving the data from the slave device; and receiving the command from the master device and/or sending the data to the master device by a slave interface. The master interface and the slave interface are driven by a clock generated by a clock generator. The master interface and the slave interface are electrically connected by one or more bonding elements. The clock used to drive the slave interface is trained by changing the clock phase of the clock to align with the data clusters of the command and/or the data clusters of the data.

In order to make the above content easier to understand, several embodiments with accompanying drawings will be explained in detail below.

The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of elements and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which the first feature is formed Embodiments in which additional features may be formed between and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may reuse reference numbers and/or letters in various instances. This re-use is for the purpose of brevity and clarity and is not itself indicative of the relationship between the various embodiments and/or configurations discussed.

Also, for ease of description, for example, "beneath", "below", "lower", "above" may be used herein. )", "upper" and other spatially relative terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present disclosure discloses an interface device and an interface method for a 3D semiconductor device. Interface devices provide reliable data communication between master and slave devices. The reliable data communication is produced by distributing the data latency provided by the master device to each slave device according to the clock generated by the clock generator. Each slave has a local clock generated from the clock of the clock generator. Each slave can adjust its local clock, thus avoiding data races between slaves. Furthermore, by avoiding data races between each slave device, bit errors can be minimized or avoided, thus eliminating the need for error correction modules and methods. Therefore, the data communication speed can be improved.

Additionally, each slave device can train each slave device's local clock by sending built-in-self-test (BIST) data to the master device when the electronics are powered on. By accurately generating a local clock, each slave device can provide accurate data with low or zero error rates. By doing so, error correction is not required and the data communication speed can be increased accordingly. In order to avoid data races between each slave and to train each slave's local clock, the implementation of the interface device and interface method will be detailed in accordance with the examples provided below (especially considering the implementation of the slave-to-master interface ).

FIG. 1 shows a schematic block diagram of a semiconductor device including a master device and a slave device according to an embodiment of the present disclosure. The semiconductor device 100 is implemented in, for example, the following 3D packages: chip-on-wafer-on-substrate (CoWoS), system-on-integrated-chip (SoIC), wafer-to-wafer ( wafer-on-wafer, WoW) and other 3D packaging integration.

Referring to FIG. 1 , a semiconductor device 100 includes a master wafer 120 , a slave wafer 130 and a clock generator 115 . Master wafer 120 is coupled to slave wafer 130 by through-silicon-via (TSV) 104 . The host wafer 120 includes a host device 105 and a host interface 102 coupled to the host device 105 . On the other hand, slave wafer 130 includes slave device 110 and slave interface 103 coupled to slave device 110 . The master device 105 is coupled to the slave device 110 via the master interface 102 and the slave interface 103 . The master interface 102 and the slave interface 103 are coupled through the TSV 104 and integrated together as the interface device 101 . The interface device 101 is adapted to connect the master device 105 and the slave device 110 vertically, which forms a 3D semiconductor device. The structure of the interface device 101 is called Glink-3D. In addition, the clock generator 115 generates a clock for driving the master device 105 , the master interface 102 , the slave interface 103 and the slave device 110 . The clock generated by the clock generator 115 is used for the master interface 102 and the slave interface 103 in the forward and reverse directions.

In an embodiment, the master device 105 and the slave device 110 are implemented, for example, as a processor and a memory (ie, static random access memory (SRAM)), respectively. The clock generator 115 is implemented by, for example, an oscillator. The connection between the master interface 102 and the slave interface 103 is implemented by TSVs with parallel bus bars for transmission at sampling rates up to 5.0 Gbps or double data rate (DDR) of 2.5 GHz material. Parallel busbars are also used for coupling between the slave device 110 and the slave interface 103 and also between the master device 105 and the master interface 102 . In an embodiment, the latency between the master device 105 and the slave device 110 is set to be 1 ns to 2 ns. The data transfer between the master device 105 and the slave device 110 has a little bit error or no bit error (no BER).

2 shows a schematic block diagram of a semiconductor device including a master device and a slave device according to an embodiment of the present disclosure. The semiconductor device 200 shown in FIG. 2 is similar to the semiconductor device 100 shown in FIG. 1 . The difference is that the clock generator 107 is implemented inside the master device 106 rather than being implemented as an external clock generator as shown in FIG. 1 .

3 shows a schematic block diagram of a semiconductor device including a master device and a plurality of slave devices according to an embodiment of the present disclosure. The semiconductor device 300 shown in FIG. 3 is similar to the semiconductor device 100 shown in FIG. 1 . The difference is that the main device 105 includes a plurality of central processing units (CPUs) 108-1 to 108-M. In addition, the interface device 111 includes a master interface 102 and a plurality of slave interfaces 103-1 to 103-N. Each slave interface 103-1 through 103-N is coupled to each slave device 110-1 through 110-N in a one-to-one relationship. N and M are integers equal to or greater than 1. In addition, the clock generator 115 generates for driving the master device 105 having the plurality of CPUs 108-1 to 108-M, the master interface 102, the plurality of slave interfaces 103-1 to 103-N, and the plurality of clocks from devices 110-1 to 110-N. The clock generator 115 may be included to the master device 105 as shown in FIG. 2 .

4 shows a schematic design diagram of a semiconductor device including a master wafer and a slave wafer according to an embodiment of the present disclosure. Semiconductor device 400 is vertically aligned to form a 3D package and includes, for example, a master/processor/die 1 die 402 coupled with a master interface 404 , a slave/memory/die 2 die 408 coupled with a slave interface 410 . The processor chip 402 and the memory chip 408 are coupled through the plurality of TSVs 406 via the processor interface 404 and the memory interface 410 . Additionally, the memory chip 408 includes the plurality of TSVs 412 and the plurality of connectors 414 .

5 shows a schematic design diagram of a semiconductor device including a master wafer and a plurality of slave wafers according to an embodiment of the present disclosure. Semiconductor device 500 is vertically aligned to form a 3D package and includes, for example, a master die 501-1 coupled to a master interface 501-2, a plurality of first slave dies 502-1 coupled to a plurality of first slave interfaces 502-2 , and a plurality of second slave wafers 503-1 coupled to a plurality of second slave interfaces 503-2. The plurality of first slave wafers 502-1 includes a TSV 502-4. The master interface 501-2 is coupled to the plurality of first slave interfaces 502-2 via TSV 502-3 and to the plurality of second slave interfaces 503-2 via TSV 503-3. In addition, the semiconductor device includes a TSV connector 504 that connects the main interface 501 - 2 to the connector 506 .

In an embodiment, the semiconductor device (ie, 500 ) supports a face-to-face interface and a face-to-back interface. For example, the interface between the master chip 501-1 and the first slave chip 502-1 and/or the interface between the master chip 501-1 and the second slave chip 503-1 is a face-to-face interface. And the face-to-back interface is used for the interface between each of the first slave chips 502-1 and/or the interface between each of the second slave chips 503-1.

6 shows a schematic 3D diagram of a semiconductor device including a master wafer and a plurality of slave wafers according to an embodiment of the present disclosure. The semiconductor device 600 includes a processor die including a plurality of CPU core die and a plurality of SRAM die connected vertically to the processor die via Glink-3D as a device interface. The read latency for round-trip data transfers from the processor die to the SRAM die and back to the processor die is 5 ns or less. This read latency value is implemented to enable reliable data communication between the processor die and the SRAM die.

7 shows a schematic 3D diagram of a semiconductor device including an example of an interface device structure according to an embodiment of the present disclosure. Semiconductor device 700 includes a CPU core die coupled to a Glink-3D master as a master interface and a cache die coupled to Glink-3D slaves as a slave interface. Glink-3D master is coupled to Glink-3D slaves via TSV. For example, during a read operation, the CPU core chip sends commands to the cache chip via the Glink-3D master and Glink-3D slaves. And then, the cache chip receives the command from the CPU core chip. The cache chip generates data on command and sends the data to the CPU core chip via Glink-3D slaves and Glink-3D master. Finally, the CPU core chip receives data from the cache memory chip. In addition, the data communication between the CPU core chip and the cache chip via the Glink-3D master and Glink-3D slaves is driven by the clock generated by the clock generator (ie, 115).

In this embodiment, the Glink-3D master and Glink-3D slaves have the same structure and are connected in a one-to-one relationship. For example, each Glink-3D master and Glink-3D slaves includes multiple blocks. Each block is divided into multiple cells, eg, 5×5 cells. Each cell of the Glink-3D master is connected to each cell of the Glink-3D slaves in a one-to-one relationship via TSV. This Glink-3D structure is used, for example, as a physical layer for the advanced microcontroller bus architecture coherent hub interface (AMBA CHI) protocol. The details of the interface device including the Glink-3D master and the Glink-3D slaves on the 3D semiconductor device and the corresponding embodiments will be further described below.

FIG. 8 shows a schematic diagram of an interface device including a master interface and a plurality of slave interfaces according to an embodiment of the present disclosure. The schematic diagram 800 may be implemented using multiple electronic components (ie, flip-flops (FFs), multiplexers (MUXs), inverters, and buffers).

Referring to Figure 8, use Glink-3D master as the interface of the master chip. Glink-3D slaveK and Glink-3D slaveN are used as the interface of slaveK chip and the interface of slaveN chip respectively. Glink-3D master, Glink-3D slaveK, and Glink-3D slaveN are driven by the clock clk_in generated by the clock generator (ie, 115). The Glink-3D master, Glink-3D slaveK and Glink-3D slaveN are electrically connected through one or more bonding pieces. For example, Glink-3D master bonds 806-1 to 806-3 are connected to Glink-3D slaveN bonds 808-1 to 808-3 in a one-to-one relationship using TSVs.

In this embodiment, the Glink-3D master includes FF 802, DDR MUX 804, bonds 806-1 through 806-3, and a read first-in first-out including multiple FFs 803-1 through 803-3 -first-out, FIFO). FF 802 is coupled to DDR MUX 804 and receives the command tx_data command from the master die. The command tx_data command can be formed, for example, as a data cluster. The command tx_data command may include the slave_ID used as the slave address. DDR MUX 804 is coupled to bond 806-1 and processes the command tx_data command to Glink-3D slaveN in DDR data format through bonds 806-1 and 808-1. FF 803-1 is coupled to FF 803-2 and bond 806-3. FF 803-3 is coupled to FF 803-2 and the master chip and sends data rx_data to the master chip. FF 802, DDR MUX 804, bond 806-2, and FF 803-3 are driven by clk_in generated by the clock generator (ie, 115). FFs 803-1 and 803-2 are driven by local clocks generated, for example, by Glink-3D slaveN through bonds 806-3 and 808-3.

In this embodiment, Glink-3D slaveN includes bonds 808-1 to 808-3, FFs 810 to 814, DDR MUX 816, and buffers 818 and 820. Bond 808-1 is coupled to bond 806-1 and FF 810 sends the command rx_data command to the slaveN die. Bond 808-2 is coupled to bond 806-2 and sends the clock clk to the slaveN die. FF 812 is coupled to DDR MUX 816 and the slaveN die and receives data tx_data from the slaveN die. FF 814 is coupled to the slaveN die and receives the enable signal tx_en. Buffer 820 is coupled to DDR MUX 816 and bond 808-3 and transmits data tx_data in DDR data format. Buffer 818 is coupled to bond 808-3 and sends the local clock to Glink 3D master through bonds 808-3 and 806-3. FF 810 to FF 814 and DDR MUX 816 are driven by clock clk. Buffers 818 and 820 are driven by enable signal tx_en. In addition, the slaveK chip and the corresponding Glink-3D slaveK have the same structure and data communication as the slaveN chip and the Glink-3D slaveN. The difference between Glink-3D slaveN and Glink-3D slaveK is the generation of the local clock. The process of generating the local clock will be explained later with reference to FIG. 10 .

9 shows a schematic diagram of an interface device including a master wafer and a slave wafer during a read operation according to an embodiment of the present disclosure. Diagram 900 is similar to diagram 800 . The difference between diagram 900 and diagram 800 is that diagram 900 shows, for example, one slaveN die and SRAM 901 with a corresponding Glink-3D slaveN. In addition, logic unit 902 and FF 904 are also included.

9, during a read operation, the master chip sends a command wr_data including a chip identification (ID) as the address of the slave chip N to the SRAM 901 via Glink-3D master and Glink-3D slaveN. Logic unit 902 is coupled to Glink-3D slaveN, SRAM 901 and FF 904. FF 904 is coupled to Glink-3D slaveN. The logic unit 902 generates signals for selecting between a chip select (CS) command, a read (RD) command or a write (write, WR) command. The logic unit 902 and the corresponding FF 904 generate the enable signal tx_en. The SRAM 901 generates data tx_data according to the command. Glink-3D slaveN sends data tx_data to Glink-3D master in DDR data format. The master chip reads the data tx_data according to the local clock of the Glink-3D slaveN.

FIG. 10 shows a schematic diagram of a slave-to-master interface including a clock tree according to an embodiment of the present disclosure. Diagram 1000 is the same as diagram 800 and diagram 900 . Diagram 1000 differs from diagram 800 and diagram 900 in that diagram 1000 shows more detailed circuitry included in the data path and clock path from a slave-to-master interface perspective. Additionally, the clock path has a clock tree (ie, 1019 and 1020) for delivering the clock from the Glink-3D master to each Glink-3D slave. In addition, timing diagrams of data in the form of DDR data format sent from Glink-3D slaveN and Glink-3D slaveK to Glink-3D master are provided.

In this embodiment, each of the slave interface Glink-3D slaveN and the other slave interfaces (ie, Glink-3D slaveK) is also configured to transfer data/other data using a double data rate (DDR) configuration (ie, tx_data[31:0]) sent to the main interface. For example, data tx_data[31:0] is collapsed into data tx_data[31:16] and data tx_data[15:0]. Each of the data tx_data[31:16] and the data tx_data[15:0] is called, for example, a data cluster.

In this embodiment, the DDR configuration is generated by a DDR unit including a first FF 1002 , a second FF 1004 and a multiplexer 1006 . The first FF 1002 and the second FF 1004 are represented as FF 812 shown in FIG. 8 , and the multiplexer 1006 is represented by DDR MUX 816 shown in FIG. 8 . The first FF 1002 , the second FF 1004 and the multiplexer 1006 are driven by the clock 1019 . The first FF 1002 is configured to generate a portion of the data (ie, data tx_data[31:16]) from the data/other data (tx_data[31:0]). The second FF 1004 is configured to generate another part of the data (ie, data tx_data[15:0]) from the data/other data (tx_data[31:0]). A multiplexer 1006 is coupled to the first FF 1002 and the second FF 1004 . The multiplexer 1006 is configured to send a portion of the data tx_data[31:16] and another portion of the data tx_data[15:0] via the buffer 1008 to the master device. Buffer 1008 is represented by buffer 820 shown in FIG. 8 . The buffer 1008 is enabled by the enable signal tx_en. The enable signal tx_en shown in FIG. 10 is the same as the enable signal tx_en shown in FIGS. 8 and 9 . By enabling the buffer 1008, a part of the data tx_data[31:16] and another part of the data tx_data[15:0] are sent to the Glink-3D master through the combiners 1011 and 1021 .

In another embodiment, each of the slave interface (ie, Glink-3D slaveN) and the other slave interfaces (ie, Glink-3D slaveK) further includes a first gate 1015 and a second gate 1016 . The first gate 1015 and the second gate 1016 are coupled to the clock path 1019 . The first gate 1015 is configured to generate the first local clock RDQS_F according to the clock clk_in generated by the clock generator (ie, 115 ). The second gate 1016 is configured to generate the second local clock RDQS_R according to the clock clk_in generated by the clock generator (ie, 115 ). Clock path 1019 is a branch of the clock tree (ie, 1019, 1020). Clock clk_in is delivered as clk_out through bonds 1024 and 1014 . Clock path 1019 delivers clock clk_out to first FF 1002 , second FF 1004 , buffer 1008 , first gate 1015 and second gate 1016 via clock path 1019 . The buffer 1017 delivers the first local clock RDQS_F to the Glink-3D master through the bonds 1012 and 1022 . The buffer 1017 is enabled according to the enable signal tx_en. The enable signal tx_en shown in FIG. 10 is the same as the enable signal tx_en shown in FIGS. 8 and 9 . The buffer 1018 delivers the second local clock RDQS_R to the Glink-3D master via the bonds 1013 and 1023 . The buffer 1018 is enabled according to the enable signal tx_en. The enable signal tx_en shown in FIG. 10 is the same as the enable signal tx_en shown in FIGS. 8 and 9 .

In this embodiment, the first local clock RDQS_F generated by the first gate 1015 is used by the Glink-3D master to read a portion of the data tx_data[31:16] generated by the first FF 1002, and is used by the second gate The second local clock RDQS_R generated by 1016 is used by the Glink-3D master to read another part of the data tx_data[15:0] generated by the second FF 1004 . For example, the Glink-3D master includes a unit block configured to read a part of the data tx_data[31:16] according to the first local clock RDQS_F and read another part of the data tx_data[15] according to the second local clock RDQS_R :0]. Glink-3D master uses DDR data format to read part of data tx_data[31:16] and another part of data tx_data[15:0]. Therefore, the Glink-3D master combines a part of the data tx_data[31:16] with another part of the data tx_data[15:0] to generate the complete data rx_data[31:0]. The Glink-3D master then sends the complete data rx_data[31:0] to the processor.

In this embodiment, the Glink-3D master also includes a FIFO unit. The FIFO unit shown in FIG. 10 is also denoted as the FIFO unit shown in FIGS. 8 and 9 . A FIFO unit can be implemented to obtain the functionality of the unit block as previously described. A FIFO unit may be implemented by multiple FFs (ie, 1031, 1032, 1051, 1041, 1042, 1061). FFs 1031 and 1041 represent FF 803-1 shown in FIG. 8 . FFs 1032 and 1042 represent FF 803-2 shown in FIG. 8 . FFs 1051 and 1061 represent FF 803-3 shown in FIG. 8 . Specifically, FFs 1031 and 1041 are coupled to bond 1021 to receive a portion of data tx_data[31:16] and another portion of data tx_data[15:0]. FF 1031 is coupled to bond 1022 via inverter 1030 to receive the first local clock RDQS_F. The FF 1041 is coupled to the bond 1023 to receive the second local clock RDQS_R. FFs 1031 and 1041 are coupled to FFs 1032 and 1042, respectively, to form FIFO units. The number of FFs is not limited to a specific number. The number of FFs can be implemented by any number of FFs.

In addition, the FIFO unit includes FFs 1051 and 1061 . The FFs 1051 and 1061 are configured to process a part of the data tx_data[31:16] and another part of the data tx_data[15:0] based on the DDR data format. FF 1051 is coupled to, for example, FF 1032, and FF 1061 is coupled to, for example, FF 1042. FFs 1051 and 1061 are configured to use the clock generated by the clock generator (ie, 115) to transfer a portion of the data tx_data[31: 16] and another part of the data tx_data[15:0] to re-time. The reclocking process is performed to synchronize a part of the data tx_data[31:16] and another part of the data tx_data[15:0] with the clock clk_in. One part of the data tx_data[31:16] and another part of the data tx_data[15:0] are sampled at the same frequency and the same phase using a command tx_data command, eg generated by the processor, by synchronizing with the clock clk_in.

For example, FFs 1031 and 1041 receive a portion of data tx_data[31:16] and another portion of data tx_data[15:0]. The FF 1031 samples a portion of the data tx_data[31:16] by the first local clock RDQS_F received from the first gate 1015 . FF 1031 sends a part of data tx_data[31:16] to FF 1032. FF 1051 receives a portion of data tx_data[31:16] from eg FF 1032 and samples a portion of data tx_data[31:16] based on clock clk_in. Therefore, the FF 1041 samples another part of the data tx_data[15:0] by the second local clock RDQS_R received from the second gate 1016 . FF 1041 sends another part of data tx_data[15:0] to FF 1042. FF 1061 receives another portion of data tx_data[15:0] from eg FF 1042 and samples another portion of data tx_data[15:0] based on clock clk_in. Finally, FFs 1051 and 1061 generate the complete data rx_data[31:0] and send the complete data rx_data[31:0] to the processor. That is, the FIFO unit of the Glink-3D master processes the data tx_data[31:0] received from eg the Glink-3D slaveN to generate the complete data rx_data[31:0] based on the DDR data format.

In another embodiment, referring to FIG. 10 , the master device (ie, the processor) further generates a turnaround (TA) loop. The TA loop is, for example, the interval between the data tx_data of the Glink-3D slaveN and the data tx_data of the Glink-3D slaveK received at the junction 1021 by the FIFO unit of the Glink-3D master. For example, the data tx_data received at the junction 1021 by the FIFO unit of the Glink-3D master refers to the Master RX_D. The Master RX_D received from Glink-3D slaveN contains data DN[15:0] and DN[31:16]. The Master RX_D received from Glink-3D slaveK contains data DK[15:0] and DK[31:16]. That is, the TA loop is the interval between the data DN[31:16] and the data DK[15:0].

In this embodiment, the TA loop is used to prevent bus competition between responses from slave devices (ie, slaveN devices) and responses from other slave devices (ie, slaveK devices). For example, during a read operation, the master/processor sends commands including the slave ID to the slaveN and slaveK devices using the allocated time slot. The slaveN device and the slaveK device respectively send the data and the local clock to the processor through the Glink-3D slaveN and Glink-3D slaveK according to the allocated time slot. The slaveN device and slaveK device use the data bus according to the assigned time slot. The Glink-3D slaveN sends the data tx_data[31:0] to the Glink-3D master through the coupling 1011. The Glink-3D slaveN also sends the first local clock RDQS_F and the second local clock RDQS_R to the Glink-3D master through the coupling elements 1012 and 1013, respectively. Glink-3D master receives data DN[15:0] and DN[31:16] from Glink-3D slaveN at bond 1021 . The Glink-3D master uses the second local clock RDQS_R to sample the data DN[15:0]. The Glink-3D master uses the first local clock RDQS_F to sample the pair and data DN[31:16].

And then, the Glink-3D slaveK sends the data tx_data[31:0] to the Glink-3D master via the corresponding combination of the Glink-3D slaveK. The Glink-3D slaveK also sends the first local clock RDQS_F and the second local clock RDQS_R to the Glink-3D master via the corresponding combination of the Glink-3D slaveK. After the TA loop, the Glink-3D master receives data DK[15:0] and DK[31:16] from the Glink-3D slaveK at the junction 1021 . The Glink-3D master uses the second local clock RDQS_R to sample the data DK[15:0]. The Glink-3D master uses the first local clock RDQS_F to sample the pair and data DK[31:16].

That is, the TA loop prevents bus contention between slaveN and slaveK devices by providing slaveN and slaveK with time slots to use the data bus during data transfer from slaveN and slaveK devices to the processor .

In this embodiment, the TA loop is used to compensate the round-trip delay (RTD, round-trip-delays) difference between the slave device and other slave devices. RTD is the interval between the command sent by the Glink-3D master and the data received by the Glink-3D master. Since each slave device is produced, for example, by a different manufacturing company, each slave device has different response characteristics. Response characteristics include RTD. RTD differences between slaves are compensated by the TA loop.

For example, during a read operation, slaveN devices and slaveK devices receive commands from the processor via Glink-3D slaveN and Glink-3D slaveK, respectively. Since the slaveN device and the slaveK device have different RTDs, the Glink-3D master receives data from Glink-3D slaveN and Glink-3D slaveK at different times. Although the Glink-3D master is already equipped with pull-down functionality, bus contention may occur if the RTD difference is greater than the difference in the allocated time slots allocated by the processor to slaveN devices and slaveK devices. Therefore, by summing the TA loop and the RTD difference (ie, 1 loop +/- ΔRTD, 1.5 loop +/- ΔRTD), slave N (DN[15:0] and DN[31:16] from Glink-3D ]) The interval between when data is received and when data is received from Glink-3D slaveK (DK[15:0] and DK[31:16]) is maintained so that bus competition is avoided.

11 shows a schematic timing diagram of data between two slave wafers having the same clock speed according to an embodiment of the present disclosure. And FIG. 12 shows a schematic timing diagram of data between two slave wafers with different clock speeds according to an embodiment of the present disclosure. slaveN devices and slaveK devices are used as examples of timing diagrams.

In this embodiment, the slave device (ie, the slaveN device) and other slave devices (ie, the slaveK device) generate zero data before and after the data to prevent the slave device and other slave devices due to different RTDs. competition between busbars. Referring to FIG. 11 , the clock slaveK clk_B speed is the same speed as the clock slaveN clk_B speed (ie, normal/typical speed). The slaveK device is equipped with the enable signal tx_en and sends the data tx_dataK to the master via the Glink-3D slaveK. The Glink-3D slaveK delivers the data dataK to the Glink-3D master through the bond (ie, 1011). Therefore, the Glink-3D slaveK sends the zero data before the data dataK and the zero data after the data dataK to the Glink-3D master through the combiner (ie, 1011). Glink-3D slaveK also generates local clocks RDQS_R and RDQS_F.

On the other hand, the slaveN device is equipped with the enable signal tx_en and sends the data tx_dataN0 and tx_dataN1 to the master device via the Glink-3D slaveN. The Glink-3D slaveN delivers the data dataN0 and dataN1 to the Glink-3D master via the corresponding connectors. Therefore, the Glink-3D slaveN sends the zero data before the data dataN0 and dataN1 and the zero data after the data dataN0 and dataN1 to the Glink-3D master through the corresponding combination. Glink-3D slaveN also generates local clocks RDQS_R and RDQS_F. Since data dataK is equipped with zero data after data dataK and data dataN0 is equipped with zero data before data dataN0, there is a gap (ie, 1T TA time) between data dataK and data dataN0. That is, the zero data generated by the slaveN device and the slaveK device creates a gap (ie, 1T TA time) between the data dataK and the data dataN0 to prevent, in the case where the clock slaveK clk_B and the clock slaveN clk_B have the same speed, Bus competition between slaveN devices and slaveK devices.

In another embodiment, referring to FIG. 12 , the difference between the embodiment shown in FIG. 11 and the embodiment shown in FIG. 12 is that the clock slaveK clk_B speed and the clock slaveN clk_B speed have different speeds. For example, the clock slaveK clk_B is slow and the clock slaveN clk_B is fast. In other words, the clock slaveN clk_B is faster than the clock slaveK clk_B. In other words, the clock slaveN clk_B is earlier than the clock slaveK clk_B. The earlier clocks are less than 1T apart (<400 ps for 2.5 GHz). Since data dataK is equipped with zero data before data dataK and zero data after data dataK, and data dataN0 is equipped with zero data before data dataN0, there is a gap (<1T) between clock slaveN clk_B and clock slaveK clk_B and in There is a gap (TA time) between the data dataK and the data dataN0.

That is, the zero data generated by the slaveN device and the slaveK device creates an interval (TA time) between the data dataK and the data dataN0 to prevent the slaveN device and the slaveK in the case where the clock slaveK clk_B and the clock slaveN clk_B have different speeds Bus competition between devices.

13 shows a schematic timing diagram of data between two slave wafers with 2 TA loops according to an embodiment of the present disclosure. Timing diagram 1300 includes 2 read latency loops and 2 TA loops. The read latency is the interval between the time when the Glink-3D slave receives a command from the master device via the corresponding bond and the time when the Glink-3D slave sends data according to the command via the corresponding bond.

Specifically, for example, during a read operation, Glink-3D slaveK and Glink-3D slaveN receive the command s_cmd including the slave ID d_did and the corresponding clock clk_out. The master device sends the command NOP between the read command RD sent to the slaveK device and the preamble command PA sent to the slaveN device. The command NOP is a no-operation command. The preamble command PA is a command for the slave device to prepare data. The read command RD is a read command for the slave device to send data after the slave device has prepared the data.

In this embodiment, the slaveK device transmits data (ie, tx_dataK, preamble) at an earlier allocated time slot than the slaveN device transmits data (ie, tx_dataN, preamble) according to the time slot allocated by the master. When the enable signal tx_en (ie, 1) is activated, data sent by the slaveK device (ie, tx_dataK, preamble) and/or data sent by the slaveN device (ie, tx_dataN, preamble) are delivered to the corresponding slave bond TX_D. Conversely, when the enable signal tx_en is deactivated (ie, 0), the data sent by the slaveK device (ie, tx_dataK, the preamble) and/or the data sent by the slaveN device (ie, tx_dataN, the preamble) are delivered to the corresponding of the slave binding piece TX_D. In the case of read latency with 2 loops, for example the interval between the command NOP received by Glink-3D slaveK and the data dataK sent by Glink-3D slaveK on the corresponding slave bond TX_D is 2 loops . The read latency with 2 loops corresponds to the command NOP sent by the master. On the other hand, in the case where TA has 2 loops, the data dataK sent by Glink-3D slaveK at the corresponding slave joint TX_D and the data dataN sent by Glink-3D slaveN at the corresponding slave joint TX_D The interval between is 2 loops +/- ΔRTD.

That is, TA with 2 loops tolerates a difference of up to 2T and can be set by the master adding a command NOP before the preamble command PA. Also, in cases where the RTD difference is less than 1 period T (400 ps for 2.5 GHz), a TA with 1 loop is sufficient.

FIG. 14 shows a schematic comparison of the first gating unit and the second gating unit before and after training according to an embodiment of the present disclosure. The block diagram 1400 shown in FIG. 14 represents the block diagram 1000 shown in FIG. 10 . The difference between Figure 14 and Figure 10 is that the circuit diagram 1400 includes a comparison of the first gating 1015 and the second gating 1016 before and after training.

In this embodiment, the slave device (ie, the slaveN device) and other slave devices (ie, the slaveK device) train the first gate 1015 and the second gate 1016 to locate a portion of the data (ie, the DN) at the best data sampling point [31:16]) and another part of the data (ie, DN[15:0]). A portion of the data (ie, DN[31:16]) and another portion of the data (ie, DN[15:0]) are referred to, for example, as a data cluster. Specifically, when the semiconductor device is activated/turned on, the master device selects the slave devices one by one for training. For example, the master device selects the slaveN device. The slaveN device selected by the master device manages the training sequence as described below. The slaveN device sets the first gate 1015 and the second gate 1016 of the Glink-3D slaveN to zero, and the first gate 1015 and the second gate 1016 are represented by the first local clock RDQS_F Initial and the second local clock RDQS_R Initial. And then, the slaveN device sends the BIST data (ie, DN[31:16] and DN[15:0]) to the master device. The master device receives BIST data (ie, DN[31:16] and DN[15:0]) at the corresponding master junctions, for example, represented by RX_D. The master device reports the pass/fail of the data DN[31:16] and DN[15:0] to the slaveN device alone. The slaveN device increments the phase of the first local clock RDQS_F Initial and the phase of the second local clock RDQS_R Initial. The process of incrementing the phase of the first local clock RDQS_F Initial and the phase of the second local clock RDQS_R Initial continues until the slaveN device receives the first pass and the last pass reported by the master. When the master device reports the last pass, the slaveN device stops sending BIST data to the master device. For example, after the master reports a pass, the last pass is obtained after a failure is reported. And then, the slaveN device sets the phase of the first local clock and the phase of the second local clock at an intermediate point by, for example, dividing the total pass by 2. Therefore, the slaveN device sends ready data to the master device. The first pass is represented by, for example, RDQS_F Initial of the first local clock and RDQS_R Initial of the second local clock, respectively. The middle point is represented by, for example, RDQS_F Trained of the first local clock and RDQS_R Trained of the second local clock, respectively. The middle point represents the best data sampling point.

That is, the optimal data sampling point is obtained by individually incrementing the phase of the first local clock of the first gate 1015 and the phase of the second local clock of the second gate 1016 until the optimal sample is obtained point.

In another embodiment, the slave device (ie, the slaveN device) uses the first clock of the first gate of the master interface Glink-3D master and the second clock of the second gate to update the slave interface (Glink-3D slaveN) The first gated first local clock and the second gated second local clock to compensate for voltage-to-temperature (V-T) changes.

For example, semiconductor devices have normal temperatures during normal processing and high temperatures during high temperature processing. The data sent from the slave (ie, slaveN device) via Glink-3D to the master via the slave interface (ie, Glink-3D slaveN) during high temperature has eg longer duration/period than during normal temperature. The slaveN device updates the phase of the first local clock (ie, RDQS_F Trained) and the phase of the second local clock (ie, RDQS_R Trained) according to the period of the data at high temperature and the period of the data at normal temperature. The update process is carried out by comparing the midpoint of the data at room temperature with the midpoint of the data at high temperature.

That is, by updating the phase of the first local clock and the phase of the second local clock of the slave interface at different temperatures according to the first clock and the second clock of the master interface, the V-T change can be compensated for. Therefore, the master interface samples the data received from the slave interface at the optimal data sampling point.

FIG. 15 shows a schematic flowchart of DLL training according to an embodiment of the present disclosure. Flowchart 1500 is performed before DLL training begins. DLL training aims to obtain the maximum steps of the DLL. The maximum step of the DLL refers to the ability of the DLL to delay the clock in the slave interface (ie, Glink-3D slaveN). DLL refers to the first gate 1015 and the second gate 1016 . DLL training is performed under two different perspectives, including the Inter-Integrated Circuit (I2C) sequence and the slave sequence. The I2C sequence is a flowchart implemented in the I2C protocol. And a slave sequence is a flowchart implemented in a slave device.

In the I2C sequence, DLL training is performed from step S1505 to step S1520. In step S1505, the DLL value is cleared/reset. And then, in step S1510, each slave's register is set to enable DLL training by, for example, changing the DLL training flag to 1. The register used to enable DLL training refers to the accumulator (ACC). In step S1515, the slave flag indicating the completion of DLL training is checked. Step S1515 is carried out until the slave flag indicating the completion of DLL training is set by changing the corresponding flag to 1, for example. Step S1515 is performed for all slave devices (ie, slaveN devices, slaveK devices). In step S1520, when the corresponding flags of all slave devices are set, the DLL training flag is reset by, for example, changing the DLL training flag to 0. By doing so, the registers for each slave that represent DLL training are disabled. That is, by carrying out steps S1505 to S1520, the maximum step/delay of the DLL of each slave device is obtained.

In the slave sequence, DLL training is performed through steps S1555 to S1575. In step S1555, the slave device (ie, the slaveN device) checks whether DLL training is enabled. In step S1560, if DLL training is enabled, the DLL value is increased by, for example, adding 1 to the DLL value. In step S1565, the lag flag and the lead flag are checked. If the DLL value is the largest, the lag flag displays 0 and the lead flag displays 1, so if the DLL value is not the largest, step S1560 is repeated. If the DLL value is the largest, the step continues to step S1570 by decreasing the DLL value by one. The reason for decrementing the DLL value by 1 is that when the condition in step S1565 is NO, the maximum value represents the last value of the DLL value in the condition. Finally, in step S1575, the slave device sets a flag indicating completion of DLL training. That is, a flag indicating that the DLL is complete indicates that the DLL training of the slave device (ie, the slaveN device) is complete. Therefore, the maximum DLL value is obtained. Steps S1555 to S1575 are performed by each slave device.

FIG. 16 shows a schematic flowchart of write data cluster training according to an embodiment of the present disclosure. After obtaining the maximum DLL value according to flowchart 1500 , DLL training continues by writing data cluster training as shown in flowchart 1600 . Since write data cluster training is to write data from processor 105 to slave devices (ie, slaveN devices, slaveK devices) according to the optimal clock phase, write data cluster training refers to master-to-slave training. Write cluster training is performed under different perspectives including I2C sequence, master sequence and slave sequence. The purpose of the write data cluster training is to obtain the intermediate value of the DLL during the write data. By writing the data according to the intermediate value of the DLL, the data is correctly written, and therefore, bit errors can be minimized. The median value of the DLL represents the optimal clock phase.

In the I2C sequence, write data cluster training is performed in steps S1605 to S1625. In step S1605, the corresponding register of the processor 105 is set to enable the writing data cluster training. In step S1610, the registers of each slave device are set to enable write data cluster training. In step S1615, the register of each slave device corresponding to the completion of the writing data cluster training is checked. If the register of each slave device corresponding to the completion of the write data cluster training is set, step S1620 is performed by disabling the register of each slave device. In step S1625, the registers of the processor 105 are disabled. That is, by obtaining the registers of each slave corresponding to the completion of the write data cluster training, the DLL value of each slave for writing data has been optimized. Therefore, bit errors can be minimized.

In the main sequence, write data cluster training is carried out in steps S1630 to S1645. In step S1630, the processor 105 checks whether the write data cluster training is enabled. If write-data cluster training is enabled, then in step S1635, the BIST generator is enabled. In step S1640, the processor 105 checks whether the write data cluster training is disabled. Disables write-cluster training when write-cluster training is complete for all slaves. In step S1645, the BIST generator is disabled since the write data cluster training for all slave devices has been completed. That is, with get-write-cluster training disabled, write-cluster training for all slaves has been completed. Therefore, the optimum clock phase for writing the data has been obtained.

In the slave sequence, write data cluster training is performed in steps S1650 to S1695. In step S1650, the register corresponding to which write data cluster training is enabled is checked. In response to the write data cluster training being enabled, the DLL value is set to 0 in step S1655. In step S1660, the BIST checker is enabled. The BIST generated by the processor 105 is checked by enabling the BIST checker. In step S1665, the BIST is checked, for example, within X times. X represents an integer value equal to or greater than 1. X may also indicate the duration of the check BIST. If the BIST has been checked X times, the BIST checker is disabled in step S1670. In step S1675, the DLL window representing the pass value is updated. A pass value indicates that the BIST was correctly read by the slave. In step S1680, it is checked whether the DLL value reaches the maximum value. The maximum value of DLL has been obtained according to Figure 15. If the DLL value is not the maximum value, the DLL value is increased in step S1685. And then, steps S1660 to S1685 are repeated until the DLL value reaches the maximum cycle/value. In step S1690, if the DLL value reaches the maximum cycle, the DLL value is set to the middle value through the window. The median value through the window indicates that the BIST is written to the slave at the optimum clock phase. In step S1695, the register indicating the completion of the writing data cluster training is set by changing the corresponding flag to 1, for example. During the main sequence, the processor 105 checks this flag to determine that write cluster training for all slaves has been completed.

FIG. 17 shows a schematic flowchart of reading data cluster training according to an embodiment of the present disclosure. Flowchart 1700 may be performed after flowchart 1600 . Read cluster training is performed to obtain the optimal clock phase for the reads. Read clustering training is performed under different perspectives including I2C sequence, master sequence, and slave sequence.

In the I2C sequence, read data cluster training is performed in steps S1702 to S1716. In step S1702, the maximum DLL value is read from the corresponding register of the slave device. In step S1704, the DLL value read from the corresponding register of the slave device is written to the register of the processor 105. In step S1706, a corresponding flag indicating that read data cluster training is enabled is set to the register of the slave device. In step S1708, a corresponding flag indicating that read data cluster training is enabled is set to a register of the processor 105. In step S1710, the slave device checks the corresponding flag indicating that the training of the read data cluster is completed. In step S1712, if the corresponding flag indicating that the training of the read data cluster is completed is enabled, the corresponding flag of the processor 105 indicating the training of the read data cluster is disabled. In step S1714, the corresponding flags representing slaves that read data cluster training are disabled. In step S1716, it is checked whether each slave device has performed read data cluster training. If one or more slave devices have not performed the process of reading data cluster training, steps S1706 to S1716 are repeated until all slave devices have performed read data cluster training. That is, each slave has performed read data cluster training by obtaining the corresponding flag of each slave's register has been enabled.

In the main sequence, read data cluster training is carried out in steps S1720 to S1748. In step S1720, the processor 105 checks the flag of the register corresponding to the training of the read data cluster. In step S1722, if the flag of the register corresponding to the read data cluster training is enabled, the DLL value is set to 0. In step S1724, the processor 105 sets a command for updating the value of DLL_r. In step S1726, the processor 105 sets a command for updating the value of DLL_f. In step S1728, the processor 105 resets the read FIFO. The reason the read FIFO needs to be reset is to prevent the processor 105 from reading an erroneous sequence of read data from the slave. If the read FIFO is not cleared, the data sequence in the read FIFO may not represent the correct data sequence. In step S1730, the processor 105 sets a command for enabling tx_en. In step S1732, the processor 105 enables the BIST checker. By enabling the BIST checker, the processor prepares to read the BIST data generated by the slave device. In step S1734, the BIST data generated by the slave device is read X times. X has been set forth in the foregoing description. In step S1736, if the BIST material has been read within X times, the processor 105 disables the BIST checker. In step S1738, the processor 105 sets a command for disabling tx_en. In step S1740, the processor 105 updates the pass window. The pass-through window has been explained in the foregoing description. In step S1742, it is checked whether the DLL value reaches the maximum cycle/value. In step S1744, if the DLL value has not reached the maximum cycle, the DLL is increased. And then, steps S1724 to S1744 are repeated until the DLL value reaches the maximum value. In step S1746, if the DLL value has reached the maximum value, the DLL is set to the middle value of the pass-through window of the slave device. In step S1748, a flag indicating that the training of the read data cluster is completed is set.

In the slave sequence, read data cluster training is carried out in steps S1750 to S1766. In step S1750, a flag corresponding to read data cluster training enable is checked. In step S1752, if a flag corresponding to read data cluster training enable is set, the BIST generator is enabled. By enabling the BIST generator, the slave device generates BIST data and sends the BIST data to the processor 105 accordingly. In step S1754, the slave device checks whether the processor 105 sets tx_en according to the command. In step S1756, the processor 105 sets tx_en according to the command, and enables tx_en from the device. In step S1758, the slave device checks whether the processor 105 clears tx_en according to the command. In step S1760, the processor 105 clears tx_en according to the command, and disables tx_en from the slave device. In step S1762, the slave device checks whether DLL_rot or DLL_f is updated. If DLL_r or DLL_f is updated, steps S1754 to S1762 are repeated. In step S1764, if the slave device has not updated DLL_r or DLL_f, a flag indicating that read data cluster training is disabled is checked. If the flag indicating read data cluster training is not disabled, steps S1762 to S1764 are repeated. In step S1766, if the flag indicating read data cluster training is disabled, the BIST generator is disabled. That is, the slave device updates DLL_r and/or DLL_f by performing read data cluster training.

Additionally, examples of commands for reading data cluster training are provided below. Since the DLL value used in the read data cluster training is 9 bits, these 9 bits are passed to the first bit of the read command (S_CMD[0]), the 4 bits from the slave to the master ID (S_DID[3: 0]) and the 4 bits of the master to slave ID (M_DID[3:0]) are combined to generate. On the other hand, the command is generated by combining the second bit (S_CMD[1]) of the read command with 2 bits (M_CMD[1:0]) of the write command. For example, the command generates an IDLE command by setting the bit values to {0,0,0}. The command generates an update DLL_r value command by setting the bit values to {0,0,1}. The command generates an update DLL_f value command by setting the bit values to {0,1,0}. The command generates an update DLL value command by setting the bit values to {0,1,1}. The command generates the tx_en enable command by setting the bit values to {1,0,1}. The command generates the tx_en disable command by setting the bit values to {1,1,0}.

FIG. 18 illustrates an interface method according to an embodiment of the present disclosure. In step S1805, the interface method of the semiconductor device is started by sending a command from the master interface to the slave device. In step S1810, the interface method continues by receiving commands from the master device and/or sending data/other data to the master device by each of the slave interface and other slave interfaces. Step S1810 includes sending the data/other data to the host interface using a double data rate (DDR) configuration in step S1815. Step S1815 includes steps S1820 to S1840. In step 1820, the device method continues by generating a portion of the data from the data/other data by the first flip-flop (FF) unit. In step S1825, the device method is continued by generating another part of the data from the data/other data by the second FF unit. In step S1830, the device method continues by sending one part of the data and another part of the data to the master by the multiplexer. In step 1835, the device method continues by generating, by the first gating unit, a first local clock from the clock generated by the clock generator. In step S1840, the device method continues by generating a second local clock by the second gating unit according to the clock generated by the clock generator. And then, in step S1845, the device method is continued by receiving data from the slave device by the master interface. Step S1845 includes using the clock generated by the clock generator in step S1850 by the master interface to re-clock a portion of the data and another portion of the data from the DDR cells of the slave interface and other slave interfaces.

In summary, an interface device and interface method for 3D semiconductor devices provides reliable data communication between a master device and a slave device. Reliable data communication is achieved by providing specific time slots to each slave device. The master device also provides data latency between slave devices. By doing so, bus contention between slave devices can be avoided. Furthermore, in order to sample the data with the optimal sampling phase, the slave device trains the local clock when the semiconductor device is turned on/on. By training the local clock, the data can be sampled at the optimal data sampling point, thus reducing the error rate. In addition, the slave device also updates the local clock to compensate for T-V changes in the semiconductor device.

In another embodiment, an interface device is provided for interfacing between a master device and a slave device, wherein the master device generates commands and the slave device generates data according to the commands, the interface device includes a master interface and from the interface. The host interface is coupled to the host device. The master interface is configured to send the command to the slave device and/or receive the data from the slave device. The slave interface is coupled to the slave device. The slave interface is configured to receive the command from the master device and/or send the data to the master device. The master interface and the slave interface are driven by a clock generated by a clock generator. The master interface and the slave interface are electrically connected by one or more bonding elements and/or TSVs. The clock used to drive the slave interface is trained by changing the clock phase of the clock to align with the data clusters of the command and/or the data clusters of the data.

In another embodiment, the interface device further includes other slave interfaces. The other slave interfaces are coupled to other slave devices in a one-to-one relationship. The other slave interface is configured to receive the command from the master device and/or send other data generated by the other slave device to the master device. The other slave interfaces are driven by the clock generated by the clock generator and are electrically connected to the master interface through the one or more bonds and/or the TSV. Each clock used to drive each of the other slave interfaces is generated by changing the clock phase of each clock to the data cluster and/or all of the commands corresponding to each of the other slave interfaces. The data clusters of the above data are aligned for training.

In another embodiment, the slave interface and the other slave interfaces are each further configured to send the data/the other data to the master interface using a double data rate (DDR) configuration. The DDR configuration is generated by DDR cells. The DDR unit includes a first flip-flop (FF) unit, a second flip-flop unit, and a multiplexer. The first FF unit is configured to generate a portion of the data from the data/the other data. The second FF unit is configured to generate another portion of data from the data/the other data. The multiplexer is coupled to the first FF unit and the second FF unit. The multiplexer is configured to send the portion of the data and the other portion of the data to the master device.

In another embodiment, each of the slave interface and the other slave interfaces further includes a first gating unit and a second gating unit. The first gating unit is configured to generate a first local clock according to the clock generated by the clock generator. The second gating unit is configured to generate a second local clock according to the clock generated by the clock generator. The first local clock generated by the first gating unit is used by the host interface to read the part of the data generated by the first FF unit. The second local clock generated by the second gating unit is used by the main interface to read the other part of the data generated by the second FF unit.

In another embodiment, the master device also generates turnaround (TA) loops. The TA loop is used to prevent bus competition between responses from the slave device and responses from the other slave devices. In another embodiment, the TA loop is used to compensate for round trip delay (RTD) differences between the slave device and the other slave devices. In another embodiment, the slave and the other slaves generate zero data before the data and after the data to prevent the slave and the other slaves from being caused by different the RTDs competition between slave devices. In another embodiment, the master interface further includes a first-in, first-out (FIFO) unit configured to use the clock pair generated by the clock generator from the slave interface and all The part of the data and the other part of the data of the DDR cells of the other slave interface are re-clocked. In another embodiment, the slave device and the other slave devices train the first gating unit and the second gating unit to locate the portion of data and all data at optimal data sampling points another part of the information.

In another embodiment, there is provided an interface method for interfacing between a master device and a slave device, wherein the master device generates a command and the slave device generates data according to the command, the interface method comprising: sending, by a master interface, the command to the slave device and/or receiving the data from the slave device; and receiving, by a slave interface, the command from the master device and/or sending the data to the slave device master device. The master interface and the slave interface are driven by a clock generated by a clock generator. The master interface and the slave interface are electrically connected by one or more bonding elements and/or TSVs. The clock used to drive the slave interface is trained by changing the clock phase of the clock to align with the data clusters of the command and/or the data clusters of the data.

In another embodiment, the interface method further comprises: receiving, by the other slave interface, the command from the master device and/or sending other data generated by the other slave device to the master device. The other slave interfaces are driven by the clock generated by the clock generator and are electrically connected to the master interface through the one or more bonds and/or the TSV. Each clock used to drive each of the other slave interfaces is generated by changing the clock phase of each clock to the data cluster and/or all of the commands corresponding to each of the other slave interfaces. The data clusters of the above data are aligned for training.

In another embodiment, each of the slave interface and the other slave interfaces receiving the command from the master device and/or sending the data/the other data to the master device further comprises : Send the data/the other data to the main interface using a double data rate (DDR) configuration. Sending the data/the other data to the host interface using a double data rate (DDR) configuration further includes: generating, by a first flip-flop (FF) unit, a portion of the data according to the data/the other data; by The second FF unit generates another part of the data according to the data/the other data; and sends the part of the data and the other part of the data to the host device by a multiplexer.

In another embodiment, sending the data/the other data to the host interface using the DDR configuration further comprises: generating, by a first gating unit, a first local based on the clock generated by the clock generator a clock; and generating, by a second gating unit, a second local clock according to the clock generated by the clock generator. The first local clock generated by the first gating unit is used by the host interface to read the part of the data generated by the first FF unit. The second local clock generated by the second gating unit is used by the main interface to read the other part of the data generated by the second FF unit.

In another embodiment, the master device also generates turnaround (TA) loops. The TA loop is used to prevent bus competition between responses from the slave device and responses from the other slave devices. In another embodiment, the TA loop is used to compensate for round trip delay (RTD) differences between the slave device and the other slave devices. In another embodiment, the slave and the other slaves generate zero data before the data and after the data to prevent the slave and the other slaves from being caused by different the RTDs competition between slave devices. In another embodiment, sending, by the master interface, the command to the slave device and/or receiving the data from the slave device further comprises: using the clock pair generated by the clock generator The portion of data and the other portion of data from the DDR cells of the slave interface and the other slave interfaces are reclocked. In another embodiment, the slave device and the other slave devices train the first gating unit and the second gating unit to locate the portion of data and all data at optimal data sampling points another part of the information.

The features of several embodiments have been outlined above in order that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or implementing the embodiments described herein example of the same advantages. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure .

100, 200, 300, 400, 500, 600, 700: Semiconductor devices 101, 111: Interface Devices 102, 501-2: Main interface 103, 103-1～103-N, Glink-3D slaves: slave interface 104, 406, 412, 502-3, 502-4, 503-3: TSV 105, 106: Master device 107, 115: Clock generator 108-1～108-M: Central Processing Unit 110, 110-1～110-N: slave device 120, 501-1: Main wafer 130: From Wafer 402: Wafer 404: interface 408: Wafer 410: Interface 414, 506: Connectors 502-1: First slave wafer 502-2: First slave interface 503-1: Second slave wafer 503-2: Second slave interface 504:TSV connector 800, 900, 1000: Schematic 802, 803-1, 803-2, 803-3, 810, 812, 814, 904, 1031, 1032, 1041, 1042, 1051, 1061: Flip Flop (FF) 804, 816: Double Data Rate (DDR) Multiplexer (MUX) 806-1, 806-2, 806-3: Bonding pieces 808-1, 808-2, 808-3: Bonding pieces 818, 820, 1008, 1017, 1018: Buffer 901:SRAM 902: Logic Unit 1002: First FF 1004: Second FF 1006: Multiplexer 1011, 1012, 1013, 1014, 1021, 1022, 1023, 1024: Joints 1015: First Strobe 1016: Second Strobe 1019: Clock Path 1020: Clock Tree 1030: Inverter 1300: Timing Diagram 1400: Circuit Diagram 1500, 1600, 1700: Flowchart address wr_data, NOP, rx_data command, s_cmd, tx_data command: command clk, clk_in, clk_out, slaveK clk_B, slaveN clk_B: clock d_did: from ID dataK, dataN0, dataN1, DK[15:0], DK[31:16], DN[15:0], DN[31:16], Master RX_D, rx_data, rx_data[31:0], tx_data, tx_data[ 31:16], tx_data[15:0], tx_dataK, tx_dataN, tx_dataN0, tx_dataN1: data Glink-3D: Device Interface Glink-3D master: main interface Glink-3D slaveK, Glink-3D slaveN: slave interface PA: Preamble command RD: read command RDQS_F: local clock RDQS_F Initial: local clock RDQS_R: local clock RDQS_R Initial: local clock RDQS_F Trained, RDQS_R Trained: Phase S1505、S1510、S1515、S1520、S1555、S1560、S1565、S1570、S1575、S1605、S1610、S1615、S1620、S1625、S1630、S1635、S1640、S1645、S1650、S1655、S1660、S1665、S1670、S1675、S1680、 S1685、S1690、S1695、S1702、S1704、S1706、S1708、S1710、S1712、S1714、S1716、S1720、S1722、S1724、S1726、S1728、S1730、S1732、S1734、S1736、S1738、S1740、S1742、S1744、S1746、 Steps slave_ID: slave chip address slaveN, slaveK: chip TX_D: slave binding tx_data[31:0]: data tx_en: enable signal

FIG. 1 shows a schematic block diagram of a semiconductor device including a master device and a slave device according to an embodiment of the present disclosure. 2 shows a schematic block diagram of a semiconductor device including a master device and a slave device according to an embodiment of the present disclosure. 3 shows a schematic block diagram of a semiconductor device including a master device and a plurality of slave devices according to an embodiment of the present disclosure. 4 shows a schematic design diagram of a semiconductor device including a master wafer and a slave wafer according to an embodiment of the present disclosure. 5 shows a schematic design diagram of a semiconductor device including a master wafer and a plurality of slave wafers according to an embodiment of the present disclosure. 6 shows a schematic 3D diagram of a semiconductor device including a master wafer and a plurality of slave wafers according to an embodiment of the present disclosure. 7 shows a schematic 3D diagram of a semiconductor device including an example of an interface device structure according to an embodiment of the present disclosure. FIG. 8 shows a schematic diagram of an interface device including a master interface and a plurality of slave interfaces according to an embodiment of the present disclosure. 9 shows a schematic diagram of an interface device including a master wafer and a slave wafer during a read operation according to an embodiment of the present disclosure. FIG. 10 shows a schematic diagram of a slave-to-master interface including a clock tree according to an embodiment of the present disclosure. 11 shows a schematic timing diagram of data between two slave dies with the same local clock speed according to an embodiment of the present disclosure. 12 shows a schematic timing diagram of data between two slave wafers with different clock speeds, according to an embodiment of the present disclosure. 13 shows a schematic timing diagram of data between two slave wafers with 2 turn-around (TA) loops according to an embodiment of the present disclosure. FIG. 14 shows a schematic comparison of the first gating unit and the second gating unit before and after training according to an embodiment of the present disclosure. FIG. 15 shows a schematic flowchart of delay lock loop (DLL) training according to an embodiment of the present disclosure. FIG. 16 shows a schematic flowchart of write data cluster training according to an embodiment of the present disclosure. FIG. 17 shows a schematic flowchart of reading data cluster training according to an embodiment of the present disclosure. FIG. 18 illustrates an interface method according to an embodiment of the present disclosure.

102: Main interface

103-1, 103-N:

105: Master device

108-1, 108-M: Central Processing Unit (CPU)

110-1, 110-N: Slave

111: Interface Devices

115: Clock generator

300: Semiconductor Devices

Claims (20)

An interface device for interfacing between a master device and a slave device, wherein the master device generates a command and the slave device generates data according to the command, the interface device comprising: a master interface, coupled to the master device, configured to send the command to the slave device and/or receive the data from the slave device; and A slave interface, coupled to the slave device, is configured to receive the command from the master device and/or transmit the data to the master device, wherein the master interface and the slave interface are driven by a clock generated by a clock generator; The master interface and the slave interface are electrically connected by one or more bonding elements and/or TSVs, The clock used to drive the slave interface is trained by changing the clock phase of the clock to align with the data clusters of the command and/or the data clusters of the data. The interface device of claim 1, further comprising other slave interfaces coupled in a one-to-one relationship to other slave devices, configured to receive the command from the master device and/or to be other data generated by the other slave devices are sent to the master device, where the other slave interfaces are driven by the clock generated by the clock generator and electrically connected to the master interface through the one or more bonds and/or the TSV, Each clock used to drive each of the other slave interfaces is generated by changing the clock phase of each clock to the data cluster and/or all of the commands corresponding to each of the other slave interfaces. The data clusters of the above data are aligned for training. The interface device of claim 2, wherein the slave interface and the other slave interfaces are each further configured to send the data/the other data to the the main interface. The interface device of claim 3, wherein the double data rate configuration is generated by a double data rate unit comprising: a first flip-flop (FF) unit configured to generate a portion of the data according to the data/the other data; a second trigger unit configured to generate another part of the data according to the data/the other data; and A multiplexer, coupled to the first flip-flop unit and the second flip-flop unit, is configured to send the portion of the data and the other portion of the data to the master device. The interface device of claim 2, wherein each of the slave interface and the other slave interfaces further comprises: a first gating unit configured to generate a first local clock according to the clock generated by the clock generator; and a second gating unit configured to generate a second local clock according to the clock generated by the clock generator, The first local clock generated by the first gating unit is used by the main interface to read the part of the data generated by the first flip-flop unit, and the second gating unit is used to read the part of the data generated by the first trigger unit. The generated second local clock is used by the master interface to read the other part of the data generated by the second flip-flop unit. The interface device of claim 2, wherein the master device further generates a turnaround (TA) loop, wherein the turnaround loop is used to prevent communication between responses from the slave device and responses from the other slave devices Bus competition. The interface device of claim 6, wherein the steering loop is used to compensate for differences in round trip delay (RTD) between the slave device and the other slave devices. The interface device of claim 7, wherein the slave device and the other slave devices generate zero data before the data and after the data to prevent the slaves from being caused by different round-trip delays competition between the device and the other slave devices. The interface device of claim 3, wherein the master interface further includes a first-in, first-out (FIFO) unit configured to use the clock pair generated by the clock generator from the clock The portion of the data and the other portion of the data for the double data rate units of the slave interface and the other slave interfaces are reclocked. The interface device of claim 5, wherein the slave device and the other slave devices train the first gating unit and the second gating unit to locate the first gating unit at an optimal data sampling point part of the information and said part of the information. An interface method for interfacing between a master device and a slave device, wherein the master device generates a command and the slave device generates data according to the command, the interface method comprising: sending, by a master interface, the command to the slave device and/or receiving the data from the slave device; and receiving said command from said master device and/or sending said data to said master device by a slave interface, wherein the master interface and the slave interface are driven by a clock generated by a clock generator, wherein the master interface and the slave interface are electrically connected by one or more bonding elements and/or TSVs, wherein the clock used to drive the slave interface is trained by changing the clock phase of the clock to align with the data clusters of the command and/or the data clusters of the data. The interface method according to claim 11, further comprising: receiving, by other slave interfaces, the command from the master device and/or sending other data generated by the other slave devices to the master device, wherein the other slave interfaces are driven by the clock generated by the clock generator and are electrically connected to the master interface through the one or more bonds and/or the TSV, wherein each clock used to drive each of the other slave interfaces is by changing the clock phase of each clock to the data cluster and/or the command corresponding to each of the other slave interfaces The data clusters of the data are aligned for training. The interface method of claim 12, wherein each of the slave interface and the other slave interfaces receives the command from the master device and/or sends the data/the other data to the The master device also includes sending the data/the other data to the master interface using a double data rate (DDR) configuration. The interface method of claim 13, wherein sending the data/the other data to the host interface using a double data rate (DDR) configuration further comprises: generating a part of the data according to the data/the other data by the first flip-flop (FF) unit; generating another part of the data according to the data/the other data by the second flip-flop unit; and The portion of the data and the other portion of the data are sent to the master by a multiplexer. The interface method of claim 14, wherein using the double data rate configuration to send the data/the other data to the host interface further comprises: generating, by a first gating unit, a first local clock from the clock generated by the clock generator; and generating a second local clock by a second gating unit according to the clock generated by the clock generator, The first local clock generated by the first gating unit is used by the main interface to read the part of the data generated by the first flip-flop unit, and the second gating unit is used to read the part of the data generated by the first trigger unit. The generated second local clock is used by the master interface to read the other part of the data generated by the second flip-flop unit. The interface method of claim 12, wherein the master device further generates a turnaround (TA) loop, wherein the turnaround loop is used to prevent communication between responses from the slave device and responses from the other slave devices Bus competition. The interface method of claim 16, wherein the steering loop is used to compensate for differences in round trip delay (RTD) between the slave device and the other slave devices. The interface method of claim 17, wherein the slave and the other slaves generate zero data before the data and after the data to prevent the slaves from being caused by different round-trip delays competition between the device and the other slave devices. The interface method of claim 13, wherein sending, by the master interface, the command to the slave device and/or receiving the data from the slave device further comprises: using a clock generated by the clock generator The clock reclocks the portion of data and the other portion of data from the double data rate units of the slave interface and the other slave interfaces. The interface method of claim 15, wherein the slave device and the other slave devices train the first gating unit and the second gating unit to locate the first gating unit at an optimal data sampling point part of the information and said part of the information.

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