TWI736414B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

Info

Publication number
TWI736414B
TWI736414B TW109130848A TW109130848A TWI736414B TW I736414 B TWI736414 B TW I736414B TW 109130848 A TW109130848 A TW 109130848A TW 109130848 A TW109130848 A TW 109130848A TW I736414 B TWI736414 B TW I736414B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
substrate
distance
package
conductive
Prior art date
Application number
TW109130848A
Other languages
English (en)
Other versions
TW202119571A (zh
Inventor
陳碩懋
鄭心圃
許峯誠
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202119571A publication Critical patent/TW202119571A/zh
Application granted granted Critical
Publication of TWI736414B publication Critical patent/TWI736414B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81457—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81466—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81493—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/814 - H01L2224/81491, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/83488—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本揭露實施例提供一種封裝結構及其形成方法。封裝結構包括封裝基板及在封裝基板上方的中介層基板。中介層基板具有面向封裝基板的第一表面及與第一表面相對的第二表面。封裝結構還包括設置在第一表面上的第一半導體裝置及設置在第二表面上的第二半導體裝置。導電結構設置在中介層基板與封裝基板之間。第一半導體裝置位於導電結構之間。第一半導體裝置的第一側與最相鄰的導電結構相距一第一距離，以及第一半導體裝置的第二側與最相鄰的導電結構相距一第二距離，第一側相對於第二側，並且第一距離大於第二距離。

Description

封裝結構及其形成方法
本發明實施例係關於一種半導體封裝技術，特別係有關於一種晶片封裝結構及其形成方法。
積體電路(Integrated circuits，IC)通過半導體裝置製造技術的進步而被實際做出。通過可以在相同尺寸的晶片上安裝越來越多元件的技術進步的推動下，晶片的尺寸、速度和容量取得了巨大的進步。半導體製造製程的不斷進步，導致半導體裝置具有更精細的特徵及/或更高的整合度。功能密度(即，每一晶片區域內互連裝置的數目)通常增加，而特徵尺寸(即，可以使用製造製程產出的最小構件)則減小。一般而言，這種尺寸縮小的製程通過生產效率增加及製造成本降低而提供好處。
晶片封裝(package)不僅為半導體裝置提供免受環境汙染的保護，也為封裝在其中的半導體裝置提供連接介面。已經開發出利用更少面積或更低高度的更小的封裝結構來封裝半導體裝置。
雖然現有的封裝技術通常已足以滿足其預期目的，但它們仍無法在所有方面令人滿意。
本揭露一些實施例提供一種封裝結構，包括封裝基板、中介層基板、第一半導體裝置、第二半導體裝置、以及複數個導電結構。中介層基板設置在封裝基板上方，並且具有面向封裝基板的第一表面及與第一表面相對的第二表面。第一半導體裝置設置在中介層基板的第一表面上。第二半導體裝置設置在中介層基板的第二表面上。複數個導電結構設置在中介層基板與封裝基板之間，用以將中介層基板接合到封裝基板。第一半導體裝置位於導電結構之間。其中，第一半導體裝置的第一側在第一方向上與最相鄰的導電結構相距第一距離，以及第一半導體裝置的第二側在第一方向上與最相鄰的導電結構相距第二距離，第一側相對於第二側，並且第一距離大於第二距離。
本揭露一些實施例提供一種封裝結構，包括封裝基板、中介層基板、兩個第一半導體裝置、第二半導體裝置、以及複數個導電結構。中介層基板設置在封裝基板上方，並且具有面向封裝基板的第一表面及與第一表面相對的第二表面。兩個第一半導體裝置設置在中介層基板的第一表面上。第二半導體裝置設置在中介層基板的第二表面上。複數個導電結構設置在中介層基板與封裝基板之間，用以將中介層基板接合到封裝基板。兩個第一半導體裝置位於導電結構之間。其中，兩個第一半導體裝置中的每一者以下列方式配置：第一半導體裝置的第一側在第一方向上與最相鄰的導電結構相距第一距離，以及第一半導體裝置的第二側在第一方向上與最相鄰的導電結構相距第二距離，第一側相對於第二側，並且第一距離大於第二距離。
本揭露一些實施例提供一種形成封裝結構的方法。所述方法包括在中介層基板的第一表面上設置第一半導體裝置及複數個導電結構，使得第一半導體裝置位於導電結構之間。其中，第一半導體裝置的第一側在第一方向上與最相鄰的導電結構相距第一距離，以及第一半導體裝置的第二側在第一方向上與最相鄰的導電結構相距第二距離，第一側相對於第二側，並且第一距離大於第二距離。所述方法更包括將中介層基板堆疊在封裝基板上方，使得中介層基板的第一表面面向封裝基板，並且通過導電結構將中介層基板接合到封裝基板。此外，所述方法還包括在中介層基板的與第一表面相對的第二表面上設置第二半導體裝置。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下描述具體的構件及其排列方式的實施例以闡述本揭露。當然，這些實施例僅作為範例，而不該以此限定本揭露的範圍。例如，在說明書中敘述了一第一特徵形成於一第二特徵之上或上方，其可能包含第一特徵與第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於第一特徵與第二特徵之間，而使得第一特徵與第二特徵可能未直接接觸的實施例。另外，在本揭露不同範例中可能使用重複的參考符號及/或標記，此重複係為了簡化與清晰的目的，並非用以限定所討論的各個實施例及/或結構之間有特定的關係。
再者，空間相關用語，例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用語，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用語意欲包含使用中或操作中的裝置之不同方位。設備可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
說明書中的用語「基本上(substantially)」，例如「基本上平坦」或「基本上共平面」等可為本領域技術人員所能理解。在一些實施例中，形容詞基本上可以被去除。在適用的情況下，用語「基本上」還可以包括「全部(entirely)」、「完全(completely)」、「所有(all)」等的實施例。在適用的情況下，用語「基本上」還可以涉及90%或更高，例如95%或更高，特別是99%或更高，包括100%。此外，例如「基本上平行」或「基本上垂直」之類的用語應解釋為不排除相較於特定佈置的微小偏差，並且例如可包括高達10°的偏差。用語「基本上」不排除「完全」，例如「基本上不含(substantially free)」Y的組合物可以是完全不含Y。
與特定距離或尺寸結合使用的用語，例如「約」，應解釋為不排除相較於特定距離或尺寸的微小偏差，並且例如可包括高達10%的偏差。使用於數值X的用語「約」可能表示X±5或10%。
以下描述本揭露的一些實施例。可以在這些實施例中描述的階段之前、之中及/或之後提供額外的操作。在不同的實施例中，可以替換或消除所述的某些階段。可以在封裝結構中加入附加特徵。在不同的實施例中，可以替換或消除所述的某些特徵。儘管下文中以特定順序執行的操作來討論一些實施例，但是也可以其他的邏輯順序來執行這些操作。
本揭露的實施例可以涉及3D封裝或3D-IC裝置。也可以包括其他特徵或製程。例如，可以包括測試結構以幫助對3D封裝或3D-IC裝置進行驗證測試。測試結構可以包括例如形成在重分佈層(redistribution layer)中或基板上的測試墊(pads)，其允許對3D封裝或3D-IC裝置進行測試、探針及/或探針卡等的使用。可以對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構以及方法可以與結合已知良好的晶粒的中間驗證的測試方法一起使用，從而提高產率並降低成本。
第1A圖至第1E圖是根據一些實施例的形成一封裝結構的製程的各個階段的剖視圖。如第1A圖所示，根據一些實施例，在載體基板100上方形成封裝基板102。載體基板100可以是玻璃基板、半導體基板或其他合適的基板。在後續的階段去除載體基板100之後(如第1E圖所示)，封裝基板102可用於提供封裝結構中的半導體裝置(將在後面描述)與外部電子裝置之間的電連接。
封裝基板102可用於佈線(routing)。在一些實施例中，封裝基板102是重分佈基板(redistribution substrate)。在一些替代實施例中，封裝基板102是積層基板(build-up substrate)，包括核心(core)及在核心的相反側的積層(build-up layers)。在一些替代實施例中，封裝基板102是玻璃基板。在本揭露實施例的後續討論中，以重分佈基板作為封裝基板102的說明性示例，然而根據示範實施例所揭露的教導也可以容易地適用於積層基板或玻璃基板。如第1A圖所示，封裝基板102包括多個層疊的絕緣層104以及被絕緣層104包圍的多個導電特徵106。導電特徵106可以包括導線、導電通孔(vias)及/或導電墊。在一些實施例中，一些導電通孔是相互堆疊的，上方的導電通孔與下方的導電通孔基本上對準，從而具有較短的佈線長度。然而，在某些佈線受限的情況下，一些導電通孔為交錯排列的(staggered)通孔，上方的導電通孔與下方的導電通孔未對準。
絕緣層104可以包括或由一或多種聚合物材料製成。聚合物材料可以包括聚苯噁唑(polybenzoxazole，PBO)、聚醯亞胺(polyimide，PI)、環氧基樹脂、一或多種其他合適的聚合物材料或其組合。在一些實施例中，聚合物材料是光敏性的。因此，可以使用光微影製程在絕緣層104中形成具有期望圖案的開口。
在一些其他實施例中，部分或全部的絕緣層104包括或由聚合物材料以外的介電材料製成。介電材料可以包括氧化矽、碳化矽、氮化矽、氮氧化矽、一或多種其他合適的材料或其組合。
導電特徵106可以包括在水平方向上提供電連接的導線，以及在垂直方向上提供電連接的導電通孔。導電特徵106可以包括或由銅、鋁、金、鈷、鈦、鎳、銀、石墨烯、一或多種其他合適的導電材料或其組合製成。在一些實施例中，導電特徵106包括多個子層。例如，每個導電特徵106包含多個子層，包括Ti/Cu、Ti/Ni/Cu、Ti/Cu/Ti、Al/Ti/Ni/Ag、其他合適的多個子層或其組合。
封裝基板102的形成可以涉及多個沉積或塗布製程、多個圖案化製程及/或多個平坦化製程。
沉積或塗布製程可用於形成絕緣層及/或導電層。沉積或塗布製程可以包括旋轉塗布製程、電鍍製程(electroplating process)、化學鍍製程(electroless process)、化學氣相沉積(chemical vapor deposition，CVD)製程、物理氣相沉積(physical vapor deposition，PVD)製程、原子層沉積(atomic layer deposition，ALD)製程、一或多種其他適用的製程或其組合。
圖案化製程可用於圖案化所述形成的絕緣層及/或形成的導電層。圖案化製程可以包括光微影製程、能量束鑽孔製程(例如，雷射束鑽孔製程、離子束鑽孔製程或電子束鑽孔製程)、蝕刻製程、機械鑽孔製程、一或多種其他適用的製程或其組合。
平坦化製程可用於為所述形成的絕緣層及/或形成的導電層提供平坦的頂表面，以利於後續的製程。平坦化製程可以包括機械研磨製程、化學機械研磨(chemical mechanical polishing ，CMP)製程、一或多種其他適用的製程或其組合。
如第1A圖所示，根據一些實施例，封裝基板102還包括形成在其上的導電元件108。每個導電元件108可以暴露於絕緣層104的最頂表面處或從所述最頂表面突出，並且可以電連接到導電特徵106中的一者。導電元件108可用於電耦接、保持或接收導電結構，這將在後面描述。
導電元件108可以包括或由銅、鋁、金、鈷、鈦、錫、一或多種其他合適的材料或其組合製成。可以使用電鍍製程、化學鍍製程、放置製程(placement process)、印刷製程、物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程、一或多種其他適用的製程或其組合來形成導電元件108。
如第1B圖所示，根據一些實施例，提供要被設置在封裝基板102(參見第1A圖)上方的中介層基板(interposer substrate)110。中介層基板110可以是半導體基板，其可以進一步是晶體矽基板，儘管它也可以包括例如矽鍺、碳化矽等其他半導體材料。儘管未示出，中介層基板110可以進一步包括形成於其中的絕緣層及導電層。在各種實施例中，中介層基板110可以包括或可以不包括形成在其中或其上的被動裝置(例如，電阻器、電容器、電感器等)及/或主動裝置(例如，電晶體、二極體等)。在一些其他實施例中，中介層基板110可以是有機基板，包括多個層疊的絕緣層及被絕緣層包圍的多個導電特徵(與上述第1A圖所示的封裝基板102類似)，或者中介層基板110可以是玻璃基板。
根據一些實施例，如第1B圖所示，在中介層基板110的一側上形成互連結構層112(有時稱為重分佈層(RDL))，其用於電連接到中介層基板110的內部電路(未示出)或中介層基板110上方的裝置。儘管未圖示，互連結構層112可以包括複數個介電層。金屬線路形成在介電層中。導電通孔形成在上方和下方的金屬線路之間，並且互連上方和下方的金屬線路。電連接件(有時也稱為墊區域(pad regions))可以形成在互連結構層112的頂表面處或從所述頂表面突出，以接收或互連到外部裝置(將在後面描述)。根據一些實施例，介電層由氧化矽、氮化矽、碳化矽、氮氧化矽、其組合及/或其多層形成。或者，介電層可以包括一或多個具有低k值的低k介電層。互連結構層112的金屬線路、導電通孔及電連接件(統稱為導電特徵)的材料可以與第1A圖所示的導電特徵106的材料相同或相似。
根據一些實施例，如第1B圖所示，多個半導體裝置126和半導體裝置127(為了簡單起見，僅示出一個半導體裝置126和一個半導體裝置127)通過覆晶接合(flip-chip bonding)方法接合到中介層基板110。在一些實施例中，每個半導體裝置126/127是堆疊或設置在中介層基板110的一表面110B上方，並且通過導電結構128接合到中介層基板110的一些暴露的墊區域(例如，由互連結構層112的一些導電特徵構成)。導電結構可以包括導電柱、焊球、可控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊(micro bumps)、一或多種其他合適的接合結構(bonding structures)或其組合。
在一些實施例中，導電結構128可以包括或由例如銅、鋁、金、鎳、銀、鈀、其類似物或其組合的金屬材料製成。可以使用電鍍製程、化學鍍製程、放置製程、印刷製程、物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程、光微影製程、一或多種其他適用的製程或上述之組合來形成導電結構128。
在一些其他實施例中，導電結構128由含錫材料製成。含錫材料可以進一步包括銅、銀、金、鋁、鉛、一或多種其他合適的材料或其組合。在一些其他實施例中，導電結構128是不含鉛的。另外，可以執行回焊製程以便將含錫材料塑形為期望的凸塊或球形。
在一些實施例中，如第1B圖所示，形成底部填充元件(underfill element)130以包圍和保護導電結構128，並且強化每個半導體裝置126/127與中介層基板110之間的連接。底部填充元件130可以包括或由絕緣材料製成，例如底部填充材料(underfill material)。底部填充材料可以包括環氧樹脂、樹脂、填料材料、應力釋放劑(stress release agent，SRA)、助黏劑、另一種合適的材料或其組合。在一些實施例中，將液態的底部填充材料分配到每個半導體裝置126/127與中介層基板110之間的間隙中，以強化導電結構128乃至整個封裝結構的強度。在分配之後，固化底部填充材料以形成底部填充元件130。底部填充元件130還可以為封裝結構提供熱傳導路徑。在本實施例中，底部填充元件130填滿每個半導體裝置126/127與中介層基板110之間的整個間隙，並且覆蓋每個半導體裝置126/127的所有下表面。在一些其他實施例中，未形成底部填充元件130，或者底部填充元件130僅覆蓋每個半導體裝置126/127的部分下表面。
根據一些實施例，每個半導體裝置126/127包括半導體晶片、一或多個主動裝置(例如，電晶體、二極體、光二極體等)、一或多個被動裝置(例如，電阻器、電容器、電感器等)、包括封裝基板和安裝在其上的一或多個半導體晶片或晶粒的一封裝模組(例如，參見第6圖)、或上述之組合。半導體晶片可以包括任何類型的功能性積體電路，例如處理器、邏輯電路、記憶體、類比電路、數位電路、混合信號電路、或其類似物。在一些實施例中，半導體裝置126和半導體裝置127是提供不同功能的不同類型的電子裝置。例如，半導體裝置126是處理器裝置，而半導體裝置127是記憶體裝置，但是也可以使用其他組合。在一些其他實施例中，半導體裝置126和半導體裝置127是相同類型的電子裝置。
在一些實施例中，半導體裝置126和半導體裝置127具有不同的尺寸。舉例來說，如第1B圖所示，每個半導體裝置126在垂直於表面110B的方向D3上的高度H1大於每個半導體裝置127在方向D3上的高度H2。然而，在一些其他實施例中，半導體裝置126和半導體裝置127可以具有相同的尺寸(例如，高度)。
根據一些實施例，如第1B圖所示，在中介層基板110上方形成保護層132以包圍和保護半導體裝置126和半導體裝置127。在一些實施例中，保護層132通過底部填充元件130與個別的半導體裝置126/127下方的導電結構128分開。然而，本揭露的實施例不以此為限。在一些其他實施例中，未形成底部填充元件130。在這些情況下，保護層132可以與個別的半導體裝置126/127下方的導電結構128直接接觸。
在一些實施例中，保護層132包括或由絕緣材料製成，例如模製材料(molding material)。模製材料可以包括聚合物材料，例如其中散布有填料的環氧基樹脂。在一些實施例中，模製材料(例如，液體模製材料)被分配到中介層基板110的表面110B上方及/或每個半導體裝置126/127上方。在一些實施例中，然後使用熱處理來固化液體模製材料，並將其轉變成保護層132。
在一些實施例中，在保護層132上施行平坦化製程，以部分地去除保護層132。在一些實施例中，如第1B圖所示，在平坦化製程之後，半導體裝置126的頂表面126A被露出並且與保護層132的頂表面132A基本上齊平。這有助於從半導體裝置126快速散熱並且避免過熱發生。另外，在平坦化製程之後，半導體裝置127的頂表面127A與保護層132的頂表面132A之間分開一間隙G(即，半導體裝置127被保護層132的一部分132B覆蓋)。由於被部分132B覆蓋和壓住，在回焊製程或熱處理期間可能發生在半導體裝置127的翹曲可以減少。平坦化製程可以包括機械研磨製程、化學機械研磨(CMP)製程、蝕刻製程、乾式研磨製程、一或多種其他適用的製程或其組合。
如第1C圖所示，根據一些實施例，將第1B圖中的所得結構倒置，並使得保護層132側固定在切割膠帶T上。根據一些實施例，之後，在中介層基板110的與安裝有半導體裝置126和半導體裝置127的表面110B相對的另一表面110A上形成導電結構116。在一些實施例中，每個導電結構116形成在暴露於表面110A上的一墊區域(由中介層基板110中的一個導電層構成)上並與其電連接。導電結構116可用於將中介層基板110接合(例如，電連接)到封裝基板102，這將在後面描述。導電結構116可以包括導電柱、焊球、可控塌陷晶片連接(C4)凸塊、微凸塊、一或多種其他合適的接合結構或其組合。導電結構116的結構、材料及形成方法可以與第1B圖所示的導電結構128的結構、材料及形成方法相同或相似。在導電結構116是包括或由含錫材料製成的例子中，可以執行回焊製程以便將含錫材料塑形為期望的凸塊或球形。
根據一些實施例，如第1C圖所示，將多個半導體裝置118(為了說明，示出了兩個半導體裝置118)堆疊或設置在中介層基板110上方。在一些實施例中，每個半導體裝置118是功能性積體電路(IC)晶片，其可以包括一或多個應用處理器、邏輯電路、記憶體裝置、電源管理積體電路、類比電路、數位電路、混合信號電路、一或多個其他合適的功能性積體電路、或上述之組合。在一些其他實施例中，每個半導體裝置118包括一或多個被動裝置，例如電阻器、電容器、電感器等，或者每個半導體裝置118包括一或多個主動裝置，例如二極體、電晶體等。在一些其他實施例中，每個半導體裝置118包括一封裝模組，其包括封裝基板和安裝在封裝基板上的一或多個半導體晶片或晶粒(例如，參見第6圖)。或者，在一些其他實施例中，每個半導體裝置118可以是僅具有金屬佈線的半導體晶粒(即，不含功能性晶片、裝置或模組)，以用於佈線(routing)。
在一些實施例中，半導體裝置118是提供不同功能的不同類型的電子裝置。舉例來說，一些半導體裝置118可以是記憶體裝置，而一些其他半導體裝置118可以是電容器。然而，也可以使用半導體裝置118的其他組合。在一些其他實施例中，半導體裝置118是相同類型的電子裝置。
另外，儘管圖中所示的半導體裝置118具有相同的尺寸(例如，在方向D3上的高度相同)，在一些其他實施例中，它們也可以具有不同的尺寸。在一些實施例中，如第1C圖所示，半導體裝置118的高度小於導電結構116的高度。然而，本揭露不以此為限，並且在一些其他實施例中，導電結構116的高度可以小於半導體裝置118的高度(將在後面描述)。
如第1C圖所示，每個半導體裝置118可以通過導電結構120接合到暴露於中介層基板110的表面110A處的一些墊區域，所述墊區域未被導電結構116所佔據。在一些其他實施例中，半導體裝置118可以在安裝導電結構116之前附接到中介層基板110。在一些實施例中，半導體裝置118可以通過形成在中介層基板110上方的另一互連結構層(如同上述互連結構層112)互連到中介層基板110。導電結構120可以包括導電柱、焊球、可控塌陷晶片連接(C4)凸塊、微凸塊、一或多種其他合適的接合結構或其組合。導電結構120的結構、材料及形成方法可以與上述導電結構116的結構、材料及形成方法相同或相似。
在一些實施例中，如第1C圖所示，形成底部填充元件122以包圍和保護在每個半導體裝置118下方的導電結構120，並且強化半導體裝置118與中介層基板110之間的連接。底部填充元件122可以進一步為封裝結構提供熱傳導路徑。底部填充元件122的結構、材料及形成方法可以與第1B圖所示的底部填充元件130的結構、材料及形成方法相同或相似。
接下來，參見第2圖，其是根據一些實施例的第1C圖中的區域X的俯視圖，示出了一個半導體裝置118和相鄰的導電結構116的佈置。導電結構116排列成具有正交的行和列的陣列。在一些實施例中，導電結構116在沿著一第一方向D1排列的每兩個相鄰的導電結構116之間具有均勻的間距P1，並且在沿著一第二方向D2(垂直於第一方向D1)排列的每兩個相鄰的導電結構116之間具有均勻的間距P2。間距P1可以等於間距P2，但是本揭露實施例不以此為限。在一些其他實施例中，間距P1可以大於或小於間距P2。另外，在一些不同的例子中，在第一方向D1與第二方向D2之間可以形成大於0度且小於90度的角度。
在一些實施例中，當沿著垂直於中介層基板110的表面110A的方向D3觀察時(如第1B圖中的箭頭所示)，一個半導體裝置118是被數個導電結構116包圍或環繞，如第2圖所示。半導體裝置118具有彼此相對且垂直於第一方向D1的第一側1181和第二側1182，並且具有彼此相對且垂直於第二方向D2的第三側1183和第四側1184。
在一些實施例中，如第2圖所示，在第一方向D1上從第一側1181到最相鄰的導電結構116的距離S1大於在第一方向D1上從第二側1182到最相鄰的導電結構116的距離S2。距離S1可以大於或等於兩倍的間距P1並且小於三倍的間距P1(即，2P1≦S1＜3P1)。另外，距離S2可以大於或等於間距P1並且小於兩倍的間距P1(即，P1≦S2＜2P1)。舉例來說，在間距P1為約130μm的例子中，距離S1大於或等於260μm並且小於390μm，以及距離S2大於或等於130μm並且小於260μm。然而，在不同的例子中也可以使用其他合適的數值。
在一些實施例中，如第2圖所示，在第二方向D2上從第三側1183到最相鄰的導電結構116的距離S3等於在第二方向D2上從第四側1184到最相鄰的導電結構116的距離S4。距離S3和距離S4中的每一者可以大於或等於間距P2並且小於兩倍的間距P2(即，P2≦S3＜2P2及P2≦S4＜2P2)。舉例來說，在間距P2為約130μm的例子中，距離S3和距離S4均大於或等於130μm並且小於260μm。然而，在不同的例子中也可以使用其他合適的數值。
應當理解的是，將半導體裝置118的一側(例如，第一側1181)與其最相鄰的導電結構116之間的距離設計成大於半導體裝置118的其他側(例如，第二側1182、第三側1183或第四側1184)與其最相鄰的導電結構116之間的距離，並且特別是大於每兩個相鄰的導電結構116之間的間距的兩倍(如上所述)，這是可利於通過第一側1181將(底部填充元件122的)底部填充材料注射到每個半導體裝置118與中介層基板110之間的間隙。另外，在半導體裝置118的一側(例如，第一側1181)留下較大的空間還有助於通過該側逸散自半導體裝置118產生的熱量。另一方面，將半導體裝置118的其他側(例如，第二側1182、第三側1183或第四側1184)與其最相鄰的導電結構116之間的距離設計成大於每兩個相鄰的導電結構116之間的間距(如上所述)，這有助於避免半導體裝置118發生短路或橋接到相鄰的導電結構116。
另外，將半導體裝置118的每一側與其最相鄰的導電結構116之間的距離設計成小於每兩個相鄰的導電結構116之間的間距的兩倍或三倍(如上所述)，這有助於在中介層基板110上方為導電結構116保留更大的安裝空間。
再回到第1C圖，根據一些實施例，在半導體裝置118和導電結構116(以及底部填充元件122)設置在中介層基板110上方之後，沿著切割槽G進行分割(singulation)製程(也稱為鋸切製程)，以形成多個單獨的封裝結構。在第1C圖中，示出其中一個封裝結構(例如，晶圓上晶片(chip-on-wafer，CoW)封裝結構)。之後，通過使用拾取和放置工具(未圖示)從切割膠帶T上去除每個封裝結構。
如第1D圖所示，根據一些實施例，通過拾取和放置工具放置第1C圖中的所得封裝結構，使得半導體裝置118側面向封裝基板102以及半導體裝置118堆疊在中介層基板110上方。之後，中介層基板110通過上述導電結構116接合(例如，電連接)到封裝基板102上方的導電元件108。在一些其他實施例中，未形成導電元件108，並且中介層基板110通過導電結構116接合到封裝基板102的暴露的墊區域(由一些導電特徵106構成)。在一些實施例中，在高溫下將中介層基板110和封裝基板102彼此擠壓。結果，中介層基板110通過導電結構116接合到封裝基板102。在一些實施例中，使用熱壓(thermal compression)製程來實現上述接合製程。
在一些實施例中，如第1D圖所示，在中介層基板110下方的每個半導體裝置118與封裝基板102之間分開一間隙G1。在一些實施例中，間隙G1(在方向D3上)可以大於約20μm，但是本揭露不以此為限。根據一些實施例，如第1D圖所示，形成底部填充元件124以包圍和保護介於中介層基板110與封裝基板102之間的導電結構116。在一些實施例中，底部填充元件124還包圍和保護安裝在中介層基板110上的半導體裝置118。在一些實施例中，一部分的底部填充元件124在每個半導體裝置118與封裝基板102之間的間隙G1中，以為封裝結構提供額外的熱傳導路徑。底部填充元件124的材料及形成方法可以與第1B圖所示的底部填充元件130的材料及形成方法相同或相似。
之後，根據一些實施例，如第1E圖所示，去除載體基板100以暴露封裝基板102的表面。在一些實施例中，在形成封裝基板102之前，在載體基板100上方預先形成一離型膜(未圖示)。離型膜是暫時性接合材料，其有助於載體基板100與封裝基板102之間的分離操作。
在一些實施例中，如第1E圖所示，然後在原來由載體基板100所覆蓋的封裝基板102的表面上方形成導電凸塊134。每個導電凸塊134可以電連接到封裝基板102的導電特徵106中的一者。導電凸塊134可用於將封裝基板102接合到另外的外部電子元件200(例如，半導體基板、封裝基板、印刷電路板(printed circuit board，PCB))或主機板(motherboard)等，如第1E圖所示。導電凸塊134可以是或者包括例如含錫焊料凸塊的焊料凸塊(solder bumps)。含錫焊料凸塊可以進一步包括銅、銀、金、鋁、鉛、一或多種其他合適的材料或其組合。在一些實施例中，含錫焊料凸塊是不含鉛的。
在一些實施例中，在去除載體基板100之後，將焊球(或焊接元件)設置在暴露的導電特徵106上。然後，執行回焊製程以將焊球熔化並轉變成導電凸塊134。在一些其他實施例中，在設置焊球之前，在暴露的導電特徵106上方形成凸塊下金屬(under bump metallization，UBM)元件。在一些其他實施例中，焊接元件是被電鍍到暴露的導電特徵106上。之後，使用回焊製程熔化焊接元件以形成導電凸塊134。
結果，完成了形成如第1E圖所示的所得封裝結構(包括基板上晶圓上晶片(chip-on-wafer-on-substrate，CoWoS)封裝結構)的製程。在一些實施例中，在封裝基板102(例如，重分佈基板)可視為一積體扇出型(integrated fan-out，InFo)封裝基板的情況下，其中封裝基板102下方的相鄰的電連接件(例如，導電凸塊134)之間的平均距離大於封裝基板102上方的相鄰的電連接件(例如，導電結構116)之間的平均距離，第1E圖所示的所得封裝結構也可以稱作積體扇出型(InFo)封裝結構。在第1E圖的封裝結構中，半導體裝置118、半導體裝置126和半導體裝置127可以通過中介層基板110中的一些導電層(而不需額外的線路基板)彼此通信。因此，RC延遲及/或信號雜訊可以顯著減小(例如，通過直接安裝在中介層基板110上的被動元件)，以及信號傳輸速度可以提高。結果，改善了整體封裝結構的電性能(例如，電源完整性(power integrity))。
另外，如第1E圖所示，半導體裝置126的頂表面126A從保護層132露出。在操作中的半導體裝置126(例如，處理器裝置)可能產生大量的熱量的情況下，這有助於快速散熱並避免過熱。此外，保護層132具有覆蓋半導體裝置127的頂表面127A的一部分132B。在一些實施例中，部分132B基本上覆蓋半導體裝置127的整個頂表面127。由此，保護層132的部分132B可以減少由回焊製程或熱處理中使用的高溫所引起的半導體裝置127的彎折或翹曲。結果，封裝結構中的半導體裝置的性能和可靠度也得到改善。因此，也改善了封裝結構的整體性能(包括電性和機械性能)及可靠度。
可以對本揭露的實施例做出許多變化及/或修改。第3A圖是根據一些實施例的封裝結構的剖視圖。應當理解的是，第3A圖中的大部分結構與第1E圖中的相同，因此在此僅描述不同的部分。根據一些實施例，如第3A圖所示，中介層基板110下方的兩個半導體裝置118在第一方向D1上並排佈置(即，兩者之間沒有導電結構116)。
第3B圖是根據一些實施例的第3A圖中的區域Y的俯視圖，示出了兩個半導體裝置118和相鄰的導電結構116的佈置。如第3B圖所示，導電結構116排列成具有正交的行和列的陣列，其中，在沿著一第一方向D1排列的每兩個相鄰的導電結構116之間具有均勻的間距P1，並且在沿著一第二方向D2(垂直於第一方向D1)排列的每兩個相鄰的導電結構116之間具有均勻的間距P2，類似於第2圖所示的導電結構116的佈置。兩個半導體裝置118被數個導電結構116包圍或環繞。每個半導體裝置118具有面向另一個相鄰的半導體裝置118的第一側1181，並且具有面向導電結構116的三個其他側(例如，第二側1182、第三側1183和第四側1184)。每個半導體裝置118和相鄰的導電結構116的佈置可以與第2圖所示的一個半導體裝置118和相鄰的導電結構116的佈置相似，因此在此不再重複贅述。
根據一些實施例，如第3B圖所示，將兩個(第一)半導體裝置118的第一側1181之間的距離或間隙S5設計成大於從每個半導體裝置118的第二側1182到最相鄰的導電結構116的距離S2，並且大於從每個半導體裝置118的第三側1183到最相鄰的導電結構116的距離S3，並且大於從每個半導體裝置118的第四側1184到最相鄰的導電結構116的距離S4。間隙S5可以大於或等於兩倍的間距P1(或間距P2)並且小於三倍的間距P1(或間距P2)。舉例來說，在每兩個相鄰的導電結構116之間的間距為約130μm的例子中，間隙S5大於或等於260μm並且小於390μm。然而，在不同的例子中也可以使用其他合適的數值。
應當理解的是，將兩個(第一)半導體裝置118的第一側1181之間的間隙S5設計成大於每個半導體裝置118的其他側(例如，第二側1182、第三側1183或第四側1184)與其最相鄰的導電結構116之間的距離，並且特別是大於每兩個相鄰的導電結構116之間的間距的兩倍(如上所述)，這是可利於通過兩個相鄰的半導體裝置118之間的間隙將(底部填充元件122的)底部填充材料注射到每個半導體裝置118與中介層基板110之間的間隙。另外，在半導體裝置118的一側(例如，第一側1181)留下較大的空間還有助於通過該側逸散自半導體裝置118產生的熱量。
可以對本揭露的實施例做出許多變化及/或修改。第4A圖是根據一些實施例的封裝結構的剖視圖。應當理解的是，第4A圖中的大部分結構與第1E圖中的相同，因此在此僅描述不同的部分。根據一些實施例，如第4A圖所示，在封裝基板102的面向中介層基板110的上表面102A上形成多個凹槽136(為了說明，示出了兩個凹槽136)。如第4A圖所示，每個凹槽136可以在基本上垂直於上表面102A的方向D3上具有適當的深度，以便容納在中介層基板110下方的一個半導體裝置118(在中介層基板110堆疊在封裝基板102上方之後，如第1D圖所示)。在一些實施例中，凹槽136在方向D3上的(最大)深度不會超過封裝基板102在方向D3上的厚度的50%，以保持封裝基板102的足夠的結構強度。在一些其他實施例中，一個凹槽136上可以收容一個以上的半導體裝置118。
在一些實施例中，如第4A圖所示，一半導體裝置118(例如，圖中所示左邊的一者)的一部分延伸到封裝基板102的一對應的凹槽136中，並且所述半導體裝置118的底部與凹槽136的底表面136A之間分開一間隙(例如，大於約20μm)。一部分的底部填充元件124在所述半導體裝置118與凹槽136的底表面136A之間的間隙中，以為封裝結構提供額外的熱傳導路經。
在一些實施例中，如第4A圖所示，另一半導體裝置118(例如，圖中所示右邊的一者)的一部分也延伸到封裝基板102的一對應的凹槽136中，並且所述半導體裝置118還通過半導體裝置118與暴露於所述凹槽136的底表面136A上的墊區域(由一些導電特徵106構成)之間的導電結構138在底表面136A處電連接到封裝基板102。在中介層基板110堆疊在封裝基板102上方之後，導電結構138使得所述半導體裝置118(以及所連接的中介層基板110及/或其上的半導體裝置126和半導體裝置127)與封裝基板102之間能夠電連接在一起。導電結構138可以包括導電柱、焊球、可控塌陷晶片連接(C4)凸塊、微凸塊、一或多種其他合適的接合結構或其組合。在一些實施例中，導電結構138的結構、材料及形成方法可以與第1C圖所示的導電結構120的結構、材料及形成方法相同或相似。
在一些實施例中，在將中介層基板110堆疊在封裝基板102上方之前，導電結構138形成在半導體裝置118的與導電結構120相對的表面上，並且電連接到半導體裝置118的暴露的墊區域或電極。導電結構138還電連接到半導體裝置118的內部電路。舉例來說，數個導電貫穿通孔可以在半導體裝置118中形成並且穿透半導體裝置118，以互連在半導體裝置118的相對表面上的導電結構120和導電結構138。
在一些實施例中，如第4A圖所示，底部填充元件124還包圍和保護在半導體裝置118與對應的凹槽136的底表面136A之間的導電結構138，並且強化半導體裝置118與封裝基板102之間的連接。舉例來說，底部填充元件124可以填滿半導體裝置118、導電結構138及凹槽136的底表面136A之間的間隙。這也有助於為封裝結構提供額外的熱傳導路徑。
第4B圖是根據一些實施例的第4A圖中的區域Z的俯視圖，示出了一個半導體裝置和封裝基板102的對應的凹槽136的佈置。在一些實施例中，當沿著垂直於上表面102A的方向D3(參見第4A圖)觀察時，凹槽136具有與所收容的半導體裝置118的形狀相對應的形狀，如第4B圖所示。另外，凹槽136是以半導體裝置118的每一側與凹槽136的相鄰壁136B間隔一均勻的距離S6的方式配置。距離S6可以大於或等於沿著第一方向D1排列的每兩個相鄰的導電結構116之間的間距P1(參見第4A圖)或者沿著第二方向D2排列的每兩個相鄰的導電結構116之間的間距P2，並且可以小於兩倍的間距P1(即，P1≦S6＜2P1)。這有助於允許半導體裝置118容易地進入對應的凹槽136(當P1≦S6)並且在封裝基板102上方為導電結構116保留更大的安裝空間(當S6＜2P1)。在間距P1(或間距P2)為約130μm的例子中，距離S6大於或等於130μm並且小於260μm。然而，在不同的例子中也可以使用其他合適的數值。
在一些實施例中，在將中介層基板110設置在封裝基板102上方之前形成凹槽136。可以使用濕式或乾式蝕刻製程、能量束鑽孔製程(例如，雷射束鑽孔製程、離子束鑽孔製程或電子束鑽孔製程)、機械鑽孔製程、一或多種其他適用的製程或其組合來形成凹槽136。
在第4A圖所示的實施例中，由於凹槽136形成在封裝基板102上以容納半導體裝置118，導電結構116在方向D3上的高度H3可以小於使用沒有凹槽的封裝基板102的高度。這是因為導電結構116的高度不再需要大於半導體裝置118在方向D3上的厚度。結果，可以得到更薄的整體封裝結構。
另外，與中介層基板110結合的至少一半導體裝置118還可以電連接到下方的封裝基板102，從而為中介層基板110提供了與封裝基板102互連的額外的佈線(除了導電結構116之外)。結果，第4A圖中的整體封裝結構的電性能可以進一步得到改善。
第5圖是根據一些實施例的封裝結構的剖視圖。應當理解的是，第5圖中的大部分結構與第4A圖中的相同，除了一金屬板結構107從封裝基板102的一凹槽136(例如，圖中所示左邊的一者)的底表面136A露出，並且位於相應的半導體裝置118下方之外。在一些實施例中，金屬板結構107是預先形成在封裝基板102中，並且在形成所述凹槽136之後從凹槽136的底表面136A露出。金屬板結構107可以配置作為蝕刻停止件，以控制形成的凹槽136的深度。在一些實施例中，與用於佈線的封裝基板102中的導電特徵106相反，金屬板結構107被電性接地(例如，沒有耦接到晶片封裝結構中的其他電子裝置)。當中介層基板110堆疊在封裝基板102上方時，金屬板結構107可以配置作為屏蔽板(shielding plate)，以減少外部信號對上方的半導體裝置118的干擾。在一些實施例中，半導體裝置118的底表面與金屬板結構107的頂表面107A(以及凹槽136的底表面136A)之間分開一間隙，例如大於約20μm。在一些實施例中，金屬板結構107具有與半導體裝置118的截面形狀相對應的截面形狀(在圖中所示的D1-D2截面中)。另外，金屬板結構107的尺寸W1(在D1-D2截面中)可以等於或大於半導體裝置118的尺寸W2。在一些實施例中，金屬板結構107的材料可以與第1A圖所示的導電特徵106的材料相同或相似。在一些實施例中，金屬板結構107與導電特徵106中的一者是在同一製程步驟形成。
可以對本揭露的實施例做出許多變化及/或修改。舉例來說，第1圖至第5圖中所示的封裝結構中的半導體裝置118、半導體裝置126和半導體裝置127中的至少一者可以是或者包括一封裝模組(例如，如第6圖所示)。
根據一些實施例，如第6圖所示，一封裝模組包括互連結構500以及形成在互連結構500上的一或多個半導體晶粒502和半導體晶粒504。在各種實施例中，半導體晶粒502/504可以是上述任何類型的半導體裝置。半導體晶粒502/504可以通過覆晶接合、打線接合(wire bonding)及/或任何其他適用的接合方法接合到互連結構500。在一些實施例中，互連結構500是中介層基板，其可承載半導體晶粒502/504並且提供半導體晶粒502/504與中介層基板110(參見第1圖至第5圖)之間的電連接。在這些例子中，互連結構500具有與中介層基板110相似的結構。根據一些實施例，如第6圖所示，封裝模組還包括形成在互連結構500上方的保護層506，用以包圍和保護半導體晶粒502和半導體晶粒504。保護層506的材料及形成方法可以與第1B圖所示的保護層132的材料及形成方法相同或相似。
本揭露一些實施例形成一種封裝結構，包括封裝基板、位於封裝基板上方的中介層基板、位於中介層基板與封裝基板之間的一或多個第一半導體裝置、以及位於中介層基板上方的一或多個第二半導體裝置。第一和第二半導體裝置可以通過中介層基板中的一些導電特徵彼此通信。因此，信號傳輸效率顯著提高。
另外，複數個導電結構設置於中介層基板與封裝基板之間。底部填充材料用於包圍及保護導電結構。每個第一半導體裝置被配置為使得從第一半導體裝置的一側到其最相鄰的導電結構的距離大於從第一半導體裝置的其他側到其最相鄰的導電結構的距離，從而可以便於底部填充材料的注射及促進第一半導體裝置的散熱。結果，封裝結構的生產製程得到了改善，也提高了封裝結構的可靠度和性能。
根據本揭露的一些實施例，提供一種封裝結構，包括封裝基板、中介層基板、第一半導體裝置、第二半導體裝置、以及複數個導電結構。中介層基板設置在封裝基板上方，並且具有面向封裝基板的第一表面及與第一表面相對的第二表面。第一半導體裝置設置在中介層基板的第一表面上。第二半導體裝置設置在中介層基板的第二表面上。複數個導電結構設置在中介層基板與封裝基板之間，用以將中介層基板接合到封裝基板。第一半導體裝置位於導電結構之間。其中，第一半導體裝置的第一側在第一方向上與最相鄰的導電結構相距第一距離，以及第一半導體裝置的第二側在第一方向上與最相鄰的導電結構相距第二距離，第一側相對於第二側，並且第一距離大於第二距離。在一些實施例中，導電結構中在第一方向上的每兩個相鄰的導電結構之間存在一間距，其中，第一距離大於或等於兩倍的所述間距，並且第二距離大於或等於所述間距。在一些實施例中，第一半導體裝置的第三側在不同於第一方向的第二方向上與最相鄰的導電結構相距第三距離，以及第一半導體裝置的第四側在第二方向上與最相鄰的導電結構相距第四距離，其中，第三側相對於第四側，並且第三距離等於第四距離。在一些實施例中，導電結構中在第二方向上的每兩個相鄰的導電結構之間存在一間距，其中，第三距離和第四距離中的每一者大於或等於所述間距。在一些實施例中，封裝基板具有面向中介層基板的第一表面的上表面，其中，第一半導體裝置與封裝基板的上表面之間分開一間隙。在一些實施例中，封裝基板具有面向中介層基板的第一表面的上表面及形成在上表面上的凹槽，其中，凹槽配置以容納第一半導體裝置。在一些實施例中，導電結構中的每兩個相鄰的導電結構之間存在一間距，其中，當沿著垂直於封裝基板的上表面的方向觀察時，第一半導體裝置的每一側與凹槽的相鄰壁之間的距離大於或等於所述間距。在一些實施例中，第一半導體裝置延伸到凹槽中，並且在凹槽的底表面處進一步電連接到封裝基板。在一些實施例中，一金屬板結構從凹槽的底表面露出，並且位於第一半導體裝置下方。
根據本揭露的一些實施例，提供一種封裝結構，包括封裝基板、中介層基板、兩個第一半導體裝置、第二半導體裝置、以及複數個導電結構。中介層基板設置在封裝基板上方，並且具有面向封裝基板的第一表面及與第一表面相對的第二表面。兩個第一半導體裝置設置在中介層基板的第一表面上。第二半導體裝置設置在中介層基板的第二表面上。複數個導電結構設置在中介層基板與封裝基板之間，用以將中介層基板接合到封裝基板。兩個第一半導體裝置位於導電結構之間。其中，兩個第一半導體裝置中的每一者以下列方式配置：第一半導體裝置的第一側在第一方向上與最相鄰的導電結構相距第一距離，以及第一半導體裝置的第二側在第一方向上與最相鄰的導電結構相距第二距離，第一側相對於第二側，並且第一距離大於第二距離。在一些實施例中，導電結構中在第一方向上的每兩個相鄰的導電結構之間存在一間距，其中，第一距離大於或等於兩倍的所述間距，並且第二距離大於或等於所述間距。在一些實施例中，兩個第一半導體裝置中的每一者更以下列方式配置：第一半導體裝置的第三側在不同於第一方向的第二方向上與最相鄰的導電結構相距第三距離，以及第一半導體裝置的第四側在第二方向上與最相鄰的導電結構相距第四距離，其中，第三側相對於第四側，並且第三距離等於第四距離。在一些實施例中，導電結構中在第二方向上的每兩個相鄰的導電結構之間存在一間距，其中，第三距離和第四距離中的每一者大於或等於所述間距。在一些實施例中，導電結構中的每兩個相鄰的導電結構之間存在一間距，其中，兩個第一半導體裝置並排佈置，並且兩個第一半導體裝置的第一側之間的間隙大於或等於兩倍的所述間距。在一些實施例中，封裝基板具有面向中介層基板的第一表面的上表面及形成在上表面上的凹槽，其中，凹槽配置以容納兩個第一半導體裝置中的至少一者。
根據本揭露的一些實施例，提供一種形成封裝結構的方法。所述方法包括在中介層基板的第一表面上設置第一半導體裝置及複數個導電結構，使得第一半導體裝置位於導電結構之間。其中，第一半導體裝置的第一側在第一方向上與最相鄰的導電結構相距第一距離，以及第一半導體裝置的第二側在第一方向上與最相鄰的導電結構相距第二距離，第一側相對於第二側，並且第一距離大於第二距離。所述方法更包括將中介層基板堆疊在封裝基板上方，使得中介層基板的第一表面面向封裝基板，並且通過導電結構將中介層基板接合到封裝基板。此外，所述方法還包括在中介層基板的與第一表面相對的第二表面上設置第二半導體裝置。在一些實施例中，導電結構中在第一方向上的每兩個相鄰的導電結構之間存在一間距，其中，第一距離大於或等於兩倍的所述間距，並且第二距離大於或等於所述間距。在一些實施例中，在將中介層基板堆疊在封裝基板上方之前，所述方法更包括從第一半導體裝置的第一側分配底部填充材料，以包圍和保護第一半導體裝置與中介層基板的第一表面之間的接合點。在一些實施例中，在將中介層基板堆疊在封裝基板上方之前，所述方法更包括在封裝基板的上表面上形成凹槽，其中，在將中介層基板堆疊在封裝基板上方之後，第一半導體裝置延伸到凹槽中。在一些實施例中，在形成封裝基板的凹槽之後，一金屬板結構從凹槽的底表面露出，並且位於第一半導體裝置下方。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
100:載體基板 102:封裝基板 102A:上表面 104:絕緣層 106:導電特徵 107:金屬板結構 107A:頂表面 108:導電元件 110:中介層基板 110A, 110B:表面 112:互連結構層 116:導電結構 118:半導體裝置 1181:第一側 1182:第二側 1183:第三側 1184:第四側 120:導電結構 122:底部填充元件 124:底部填充元件 126:半導體裝置 126A:頂表面 127:半導體裝置 127A:頂表面 128:導電結構 130:底部填充元件 132:保護層 132A:頂表面 132B:部分 134:導電凸塊 136:凹槽 136A:底表面 136B:相鄰壁 138:導電結構 200:外部電子元件 500:互連結構 502, 504:半導體晶粒 506:保護層 C:切割槽 D1:第一方向 D2:第二方向 D3:方向 G, G1:間隙 T:切割膠帶 H1, H2, H3:高度 W1, W2:尺寸 S1, S2, S3, S4, S6:距離 S5:間隙 P1, P2:間距 X, Y, Z:區域
第1A圖至第1E圖是根據一些實施例的形成一封裝結構的製程的各個階段的剖視圖。 第2圖是根據一些實施例的第1C圖中的區域X的俯視圖。 第3A圖是根據一些實施例的封裝結構的剖視圖。 第3B圖是根據一些實施例的第3A圖中的區域Y的俯視圖。 第4A圖是根據一些實施例的封裝結構的剖視圖。 第4B圖是根據一些實施例的第4A圖中的區域Z的俯視圖。 第5圖是根據一些實施例的封裝結構的剖視圖。 第6圖是根據一些實施例的封裝模組的剖視圖。
116:導電結構 118:半導體裝置 1181:第一側 1182:第二側 1183:第三側 1184:第四側 S1, S2, S3, S4:距離 P1, P2:間距 X:區域 D1:第一方向 D2:第二方向

Claims (10)

  1. 一種封裝結構，包括：一封裝基板；一中介層基板，設置在該封裝基板上方，其中，該中介層基板具有面向該封裝基板的一第一表面及與該第一表面相對的一第二表面；一第一半導體裝置，設置在該中介層基板的該第一表面上；一第二半導體裝置，設置在該中介層基板的該第二表面上；以及複數個導電結構，設置在該中介層基板與該封裝基板之間，用以將該中介層基板接合到該封裝基板，其中，該第一半導體裝置位於該些導電結構之間，其中，該第一半導體裝置的一第一側在一第一方向上與最相鄰的導電結構相距一第一距離，以及該第一半導體裝置的一第二側在該第一方向上與最相鄰的導電結構相距一第二距離，其中，該第一側相對於該第二側，並且該第一距離大於該第二距離。
  2. 如請求項1之封裝結構，其中，該些導電結構中在該第一方向上的每兩個相鄰的導電結構之間存在一間距，其中，該第一距離大於或等於兩倍的該間距，並且該第二距離大於或等於該間距。
  3. 如請求項1之封裝結構，其中，該封裝基板具有面向該中介層基板的該第一表面的一上表面及形成在該上表面上的一凹槽，其中，該凹槽配置以容納該第一半導體裝置。
  4. 如請求項3之封裝結構，其中，該些導電結構中的每兩個相鄰的導電結構之間存在一間距，其中，當沿著垂直於該封裝基板的該上表面的一方向觀察時，該第一半導體 裝置的每一側與該凹槽的一相鄰壁之間的一距離大於或等於該間距。
  5. 如請求項3之封裝結構，其中，該第一半導體裝置延伸到該凹槽中，並且在該凹槽的一底表面處進一步電連接到該封裝基板。
  6. 如請求項3之封裝結構，其中，一金屬板結構從該凹槽的一底表面露出，並且位於該第一半導體裝置下方。
  7. 一種封裝結構，包括：一封裝基板；一中介層基板，設置在該封裝基板上方，其中，該中介層基板具有面向該封裝基板的一第一表面及與該第一表面相對的一第二表面；兩個第一半導體裝置，設置在該中介層基板的該第一表面上；一第二半導體裝置，設置在該中介層基板的該第二表面上；以及複數個導電結構，設置在該中介層基板與該封裝基板之間，用以將該中介層基板接合到該封裝基板，其中，該兩個第一半導體裝置位於該些導電結構之間，其中，該兩個第一半導體裝置中的每一者以下列方式配置：該第一半導體裝置的一第一側在一第一方向上與最相鄰的導電結構相距一第一距離，以及該第一半導體裝置的一第二側在該第一方向上與最相鄰的導電結構相距一第二距離，其中，該第一側相對於該第二側，並且該第一距離大於該第二距離。
  8. 如請求項7之封裝結構，其中，該些導電結構中在該第一方向上的每兩個相鄰的導電結構之間存在一間距，其中，該第一距離大於或等於兩倍的該間距，並且該第二距離大於或等於該間距。
  9. 一種形成一封裝結構的方法，包括： 在一中介層基板的一第一表面上設置一第一半導體裝置及複數個導電結構，使得該第一半導體裝置位於該些導電結構之間，其中，該第一半導體裝置的一第一側在一第一方向上與最相鄰的導電結構相距一第一距離，以及該第一半導體裝置的一第二側在該第一方向上與最相鄰的導電結構相距一第二距離，其中，該第一側相對於該第二側，並且該第一距離大於該第二距離；將該中介層基板堆疊在一封裝基板上方，使得該中介層基板的該第一表面面向該封裝基板，並且通過該些導電結構將該中介層基板接合到該封裝基板；以及在該中介層基板的與該第一表面相對的一第二表面上設置一第二半導體裝置。
  10. 如請求項9之形成一封裝結構的方法，其中，在將該中介層基板堆疊在該封裝基板上方之前，該形成一封裝結構的方法更包括從該第一半導體裝置的該第一側分配一底部填充材料，以包圍和保護該第一半導體裝置與該中介層基板的該第一表面之間的接合點。
TW109130848A 2019-09-09 2020-09-09 封裝結構及其形成方法 TWI736414B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962897461P 2019-09-09 2019-09-09
US62/897,461 2019-09-09
US16/984,369 US11610864B2 (en) 2019-09-09 2020-08-04 Chip package structure and method of forming the same
US16/984,369 2020-08-04

Publications (2)

Publication Number Publication Date
TW202119571A TW202119571A (zh) 2021-05-16
TWI736414B true TWI736414B (zh) 2021-08-11

Family

ID=74850144

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109130848A TWI736414B (zh) 2019-09-09 2020-09-09 封裝結構及其形成方法

Country Status (2)

Country Link
US (1) US11610864B2 (zh)
TW (1) TWI736414B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3109466B1 (fr) * 2020-04-16 2024-05-17 St Microelectronics Grenoble 2 Dispositif de support d’une puce électronique et procédé de fabrication correspondant
US11770115B2 (en) * 2020-10-16 2023-09-26 Qualcomm Incorporated Tunable circuit including integrated filter circuit coupled to variable capacitance, and related integrated circuit (IC) packages and fabrication methods
US11973040B2 (en) * 2021-04-23 2024-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer with warpage-relief trenches
US11855034B2 (en) * 2021-05-28 2023-12-26 Advanced Semiconductor Engineering, Inc. Electronic device package and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017059141A1 (en) * 2015-10-02 2017-04-06 Qualcomm Incorporated PACKAGE-ON-PACKAGE (PoP) DEVICE COMPRISING A GAP CONTROLLER BETWEEN INTEGRATED CIRCUIT (IC) PACKAGES
US20180190582A1 (en) * 2017-01-03 2018-07-05 Micron Technology, Inc. Semiconductor package with embedded mim capacitor, and method of fabricating thereof
WO2019132963A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Quantum computing assemblies

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US10468351B2 (en) * 2014-08-26 2019-11-05 Xilinx, Inc. Multi-chip silicon substrate-less chip packaging
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017059141A1 (en) * 2015-10-02 2017-04-06 Qualcomm Incorporated PACKAGE-ON-PACKAGE (PoP) DEVICE COMPRISING A GAP CONTROLLER BETWEEN INTEGRATED CIRCUIT (IC) PACKAGES
US20180190582A1 (en) * 2017-01-03 2018-07-05 Micron Technology, Inc. Semiconductor package with embedded mim capacitor, and method of fabricating thereof
WO2019132963A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Quantum computing assemblies

Also Published As

Publication number Publication date
TW202119571A (zh) 2021-05-16
US11610864B2 (en) 2023-03-21
US20210074682A1 (en) 2021-03-11

Similar Documents

Publication Publication Date Title
KR102127796B1 (ko) 반도체 패키지 및 방법
KR102131759B1 (ko) 통합 팬-아웃 패키지 및 통합 팬-아웃 패키지 형성 방법
US9852969B2 (en) Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
TWI736414B (zh) 封裝結構及其形成方法
TWI620254B (zh) 半導體封裝及其形成方法
US9728527B2 (en) Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) Multiple bond via arrays of different wire heights on a same substrate
TWI739579B (zh) 封裝結構及其形成方法
TWI733339B (zh) 封裝結構及其形成方法
TW202220123A (zh) 半導體裝置封裝以及形成半導體裝置封裝的方法
US11063015B2 (en) Semiconductor device package and method of manufacturing the same
TWI742749B (zh) 封裝結構及其形成方法
US11404394B2 (en) Chip package structure with integrated device integrated beneath the semiconductor chip
TWI730629B (zh) 封裝結構及其形成方法
TWI757864B (zh) 封裝結構及其形成方法
CN112466862A (zh) 封装结构及其形成方法
US11810830B2 (en) Chip package structure with cavity in interposer
TWI796114B (zh) 半導體晶粒封裝及其形成方法
KR102411802B1 (ko) 휨 제어를 갖는 칩 패키지 구조물 및 그 형성 방법
US20240014197A1 (en) Semiconductor package and method of manufacturing the same
US20240021531A1 (en) Semiconductor package
TW202410365A (zh) 半導體裝置與其形成方法