TWI732678B - 晶片封裝體及其製造方法 - Google Patents
晶片封裝體及其製造方法 Download PDFInfo
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- TWI732678B TWI732678B TW109131822A TW109131822A TWI732678B TW I732678 B TWI732678 B TW I732678B TW 109131822 A TW109131822 A TW 109131822A TW 109131822 A TW109131822 A TW 109131822A TW I732678 B TWI732678 B TW I732678B
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- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 239000000758 substrate Substances 0.000 claims abstract description 173
- 239000004065 semiconductor Substances 0.000 claims abstract description 77
- 239000010410 layer Substances 0.000 claims description 371
- 238000002161 passivation Methods 0.000 claims description 61
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- 239000000463 material Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 25
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- 238000000034 method Methods 0.000 claims description 21
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- 239000003292 glue Substances 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
一種晶片封裝體包含半導體基板、支撐件、天線層與重佈線層。半導體基板具有傾斜側壁與凸出傾斜側壁的導電墊。支撐件位於半導體基板上,且具有背對半導體基板的頂面與鄰接頂面的傾斜側壁。天線層位於支撐件的頂面上。重佈線層位於支撐件的傾斜側壁上,且接觸導電墊的側壁與天線層的一端。
Description
本案是有關於一種晶片封裝體與一種晶片封裝體的製造方法。
在無線通訊裝置中,天線作為無線電波收發無線電訊號的部件,為無線通訊裝置中重要的組件之一。隨著無線通訊技術的發展,無線通訊裝置朝著重量輕、體積小的趨勢設計。然而,一般而言,天線還是需以外接的方式電性連接電路板上的晶片,因此在電子裝置中(例如手機)仍須佔據一定的設置空間,不利於微小化設計。
本發明之一技術態樣為一種晶片封裝體。
根據本發明一實施方式,一種晶片封裝體包含半導體基板、支撐件、天線層與重佈線層。半導體基板具有傾斜側壁與凸出傾斜側壁的導電墊。支撐件位於半導體基板上,且具有背對半導體基板的頂面與鄰接頂面的傾斜側壁。天線層位於支撐件的頂面上。重佈線層位於支撐件的傾斜側壁上,且接觸導電墊的側壁與天線層的一端。
在本發明一實施方式中,上述晶片封裝體更包含屏蔽層。屏蔽層位於半導體基板與支撐件之間。
在本發明一實施方式中,上述支撐件具有相對頂面的底面,屏蔽層接觸此底面。
在本發明一實施方式中,上述天線層接觸支撐件的頂面。
在本發明一實施方式中,上述半導體基板具有鄰接傾斜側壁的底面,晶片封裝體更包含平坦層。平坦層覆蓋半導體基板的傾斜側壁與底面,且覆蓋導電墊的底面。平坦層具有底面與鄰接此底面的傾斜側壁,且平坦層的傾斜側壁的斜率與支撐件的傾斜側壁的斜率大致相同。
在本發明一實施方式中,上述重佈線層位於平坦層的傾斜側壁與底面上。
在本發明一實施方式中,上述天線層的傳輸頻率在20 GHz至60 GHz的範圍中,且半導體基板為射頻裝置。
在本發明一實施方式中,上述晶片封裝體更包含保護層。保護層覆蓋支撐件、天線層與重佈線層遠離半導體基板的一端。
在本發明一實施方式中,上述保護層的材料包含玻璃、熔融石英(Fused silica)、石英玻璃、藍寶石或上述材料之組合。
在本發明一實施方式中,上述保護層為黏膠。
在本發明一實施方式中,上述支撐件、半導體基板與保護層之間有空腔,且支撐件圍繞此空腔。
在本發明一實施方式中,上述半導體基板具有頂面。半導體基板的頂面鄰接半導體基板的傾斜側壁。晶片封裝體更包含屏蔽層。屏蔽層位於半導體基板的頂面上。
在本發明一實施方式中,上述晶片封裝體更包含接合層。接合層位於支撐件與半導體基板之間。
本發明之一技術態樣為一種晶片封裝體的製造方法。
根據本發明一實施方式,一種晶片封裝體的製造方法包含形成天線層於支撐件的頂面上;將支撐件接合於半導體基板的頂面,其中半導體基板的頂面具有導電墊;蝕刻半導體基板的底面,使半導體基板具有傾斜側壁,且導電墊凸出傾斜側壁;執行切割製程,使支撐件具有傾斜側壁;以及形成重佈線層於支撐件的傾斜側壁上,使得重佈線層接觸導電墊的側壁與天線層的一端。
在本發明一實施方式中,上述形成該天線層包含濺鍍導電層於該支撐件的頂面上;以及圖案化該導電層,以形成天線層。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含形成屏蔽層於支撐件的底面上。
在本發明一實施方式中,上述形成該屏蔽層包含濺鍍導電層於支撐件的底面上;以及圖案化導電層,以形成屏蔽層。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含形成平坦層於半導體基板的傾斜側壁與底面上與導電墊的底面上。
在本發明一實施方式中,上述執行切割製程使平坦層同步形成傾斜側壁,其中平坦層的傾斜側壁的斜率與支撐件的傾斜側壁的斜率大致相同。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含設置保護層於支撐件與天線層上。
在本發明上述實施方式中,由於晶片封裝體包含支撐件與位於支撐件的頂面上的天線層,且半導體基板具有凸出其傾斜側壁的導電墊,因此重佈線層可形成於支撐件的傾斜側壁上,進而接觸導電墊的側壁與天線層的一端。此外,天線層是形成於支撐件的頂面上,並利用支撐件接合於半導體基板的頂面而整合於晶片封裝體中,因此實現了天線的微小化以及內含天線之晶片封裝體。
根據本發明一實施方式,一種晶片封裝體包含第一基板、天線層、第一鈍化層與重佈線層層。第一基板具有相對的第一表面與第二表面。天線層位於第一基板的第一表面上。第一鈍化層覆蓋天線層。重佈線層位於第一基板的第二表面上,且電性連接天線層。重佈線層還具有與天線層分開的屏蔽區段。屏蔽區段與天線層重疊。
在本發明一實施方式中,上述重佈線層延伸至第一基板的側面與第一鈍化層的側面。
在本發明一實施方式中,上述晶片封裝體更包含第二基板。第一鈍化層位於第一基板與第二基板之間,且重佈線層延伸至第二基板的凹部。
在本發明一實施方式中,上述晶片封裝體更包含金屬層與第二鈍化層。金屬層位於第二基板背對第一鈍化層的表面上。第二鈍化層覆蓋金屬層。
在本發明一實施方式中,上述第二基板的材質為玻璃、熔融石英(Fused silica)或石英玻璃。
在本發明一實施方式中,上述晶片封裝體更包含第二鈍化層。第二鈍化層覆蓋該重佈線層。
在本發明一實施方式中,上述晶片封裝體更包含積體電路元件。積體電路元件具有導電結構,且導電結構位於重佈線層上。
在本發明一實施方式中,上述第一基板的材質為玻璃、熔融石英(Fused silica)或石英玻璃。
在本發明一實施方式中,上述晶片封裝體更包含導電通道。導電通道位於第一基板中,且導電通道的兩端分別接觸天線層與重佈線層。
根據本發明一實施方式,一種晶片封裝體的製造方法包含形成天線層於第一基板的第一表面上,其中第一基板具有背對第一表面的第二表面;形成第一鈍化層以覆蓋天線層;以及形成重佈線層於第一基板的第二表面上,其中重佈線層電性連接天線層。重佈線層還具有與天線層分開的屏蔽區段。屏蔽區段與天線層重疊。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含接合第二基板於第一基板,使第一鈍化層位於第一基板與第二基板之間。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含形成金屬層於第二基板背對第一鈍化層的表面上;以及形成第二鈍化層以覆蓋金屬層。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含移除第一基板與第一鈍化層的邊緣部分,以形成溝槽,其中天線層的側面從溝槽露出,且溝槽延伸至第二基板中,使第二基板具有凹部。
在本發明一實施方式中,上述形成重佈線層於第一基板的第二表面上更包含形成重佈線層於天線層的側面與第二基板的凹部上。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含形成第二鈍化層以覆蓋重佈線層。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含設置具有導電結構的積體電路元件於重佈線層上。
在本發明一實施方式中,上述晶片封裝體的製造方法更包含形成導電通道於第一基板中,其中導電通道的兩端分別接觸天線層與重佈線層。
以下將以圖式揭露本發明之複數個實施方式,為明確說明,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之晶片封裝體100的剖面圖。晶片封裝體100包含半導體基板110、支撐件120、天線層130與重佈線層140。半導體基板110具有傾斜側壁111與導電墊112,且導電墊112凸出傾斜側壁121。支撐件120位於半導體基板110上,且具有背對半導體基板110的頂面122與鄰接頂面122的傾斜側壁121。天線層130位於支撐件120的頂面122上。重佈線層140位於支撐件120的傾斜側壁121上,且接觸導電墊112的側壁與天線層130的一端132。
在本實施方式中,晶片封裝體100可用於高頻訊號的傳輸,例如5G通訊。天線層130的傳輸頻率可在20 GHz至60 GHz的範圍中,且半導體基板110可以為射頻裝置。半導體基板110的材質可以包含矽,且具有功能層115。舉例來說,功能層115的材質可以包含氮化鎵(GaN)。此外,半導體基板110還可的頂面114還可依序覆蓋絕緣層116與鈍化層117(Passivation layer),但並不用以限制本揭露。重佈線層140的材質可以包含銅、銀或鋁,天線層130的材質可以包含銅或銀,皆可採用物理氣相沉積法(例如濺鍍方式)形成。因此,天線層130可直接接觸支撐件120的頂面122。
由於晶片封裝體100包含支撐件120與位於支撐件120的頂面122上的天線層130,且半導體基板110具有凸出其傾斜側壁111的導電墊112,因此重佈線層140可形成於支撐件120的傾斜側壁121上,進而接觸導電墊112的側壁與天線層130的一端132。此外,天線層130是形成於支撐件120的頂面122上,並利用支撐件120接合於半導體基板110的頂面114而整合於晶片封裝體100中,因此實現了天線的微小化以及內含天線之晶片封裝體100。
在本實施方式中,晶片封裝體100更包含屏蔽層150。屏蔽層150位於半導體基板110與支撐件120之間。支撐件120具有相對頂面122的底面123。屏蔽層150可採用物理氣相沉積法(例如濺鍍方式)形成於支撐件120的底面123上。因此,屏蔽層150可直接接觸支撐件120的底面123。屏蔽層150可避免射頻訊號(RF)干擾半導體基板110。
半導體基板110具有鄰接傾斜側壁111且與頂面114相對的底面113。晶片封裝體100更包含平坦層160。平坦層160覆蓋半導體基板110的傾斜側壁111與底面113,且覆蓋導電墊112的底面。平坦層160具有底面161與鄰接此底面161的傾斜側壁162,且平坦層160的傾斜側壁162的斜率與支撐件120的傾斜側壁121的斜率大致相同。重佈線層140位於平坦層160的傾斜側壁162與底面161上。也就是說,重佈線層140可從支撐件120的傾斜側壁121經平坦層160的傾斜側壁162延伸至平坦層160的底面161,因此具有鈍角θ。
此外,晶片封裝體100還可包含鈍化層180與導電結構190。鈍化層180覆蓋重佈線層140與平坦層160,可具有開口以設置導電結構190於重佈線層140的底面上。導電結構190可以為錫球或導電柱,並不用以限制本揭露。導電結構190可電性連接其他電子裝置(如電路板)。
在本實施方式中,晶片封裝體100更包含保護層170。保護層170覆蓋支撐件120、天線層130與重佈線層140遠離半導體基板110的一端142。保護層170的材料可包含玻璃、熔融石英(Fused silica)、石英玻璃、藍寶石或上述材料之組合。
此外,晶片封裝體100更包含接合層102a、102b。接合層102a位於支撐件120與半導體基板110之間。接合層102b位於支撐件120與保護層170之間。
應瞭解到,已敘述過的元件連接關係、材料與功效將不再重複贅述,合先敘明。在以下敘述中,將說明晶片封裝體100的製造方法。
第2圖至第9圖繪示第1圖之晶片封裝體100的製造方法在各階段的剖面圖。參閱第2圖,首先於支撐件120的頂面122形成天線層130。形成天線層130的步驟可包含於支撐件120的整個頂面122先形成(例如以濺鍍方式)導電層,接著圖案化此導電層,以形成天線層130。圖案化的步驟可包含曝光、顯影與蝕刻等步驟。此外,可於支撐件120的底面123形成屏蔽層150。形成屏蔽層150的步驟可包含於支撐件120的整個底面123先形成(例如以濺鍍方式)導電層,接著可圖案化此導電層,便可形成屏蔽層150。經由上述步驟,可產生第2圖的結構。
參閱第3圖,使用接合層102a將支撐件120接合於半導體基板110的頂面114,接著可將保護層170設置於支撐件120與天線層130上。舉例來說,可使用接合層102b將保護層170接合於支撐件120的頂面122。在另一實施方式中,可先使用接合層102b將保護層170接合於支撐件120的頂面122,接著才使用接合層102a將支撐件120接合於半導體基板110的頂面114,並不用以限制本揭露。第3圖至第9圖的半導體基板110為尚未經切割步驟的晶圓,以方便製造。
待第3圖的結構完成後,可減薄半導體基板110,例如研磨半導體基板110的底面113。如此一來,便可得到第4圖的結構。
參閱第5圖,接著,蝕刻半導體基板110的底面113,使半導體基板110具有朝向缺口O的傾斜側壁111,且導電墊112凸出傾斜側壁111且從缺口O裸露。
參閱第6圖,待第5圖的結構形成後,可形成平坦層160於半導體基板110的傾斜側壁111與底面113上與導電墊112的底面上。
參閱第7圖,接著,可執行切割製程,使支撐件120具有傾斜側壁121。此切割製程可採用刀具切割。在執行切割製程時,平坦層160可同步形成傾斜側壁162。由於可利用單一刀具執行此切割步驟,因此平坦層160的傾斜側壁162的斜率與支撐件120的傾斜側壁121的斜率可大致相同。半導體基板110的導電墊112的側壁也會具有如傾斜側壁121、162的斜率。這樣的設計,對於後續重佈線層140(見第8圖)的穩固性有所助益。此外,天線層130的一端132也會在此切割製程裸露。
參閱第8圖,待第7圖的結構形成後,可形成重佈線層140於支撐件120的傾斜側壁121上、導電墊112的側壁上、平坦層160的傾斜側壁162上及平坦層160的底面161上,使得重佈線層140接觸導電墊112的側壁與天線層130的一端132,實現半導體基板110與天線層130的電性連接。
參閱第9圖,在後續製程中,可形成鈍化層180覆蓋重佈線層140與平坦層160。接著,可圖案化鈍化層180,使在平坦層160的底面161上的鈍化層180形成裸露重佈線層140的開口。接著,可設置導電結構190於開口中的重佈線層140上。導電結構190可用來電性連接其他電子裝置(如電路板)。之後,便可沿線L執行切割步驟,而得到第1圖的晶片封裝體100。
第10圖繪示第1圖之晶片封裝體100的上視圖,其省略保護層170與接合層102b。第11圖繪示第1圖之晶片封裝體100的下視圖,其省略鈍化層180。第1圖可視為第10圖與第11圖沿線段1-1的剖面圖。同時參閱第10圖與第11圖,天線層130的一端132與屏蔽層150電性連接不同重佈線層140,例如天線層130的一端132接觸第10圖左側的重佈線層140,而屏蔽層150接觸第10圖上下兩側的重佈線層140。這樣的配置,可利用不同的重佈線層140與其下方的導電結構190操作天線層130與屏蔽層150。另外,第10圖的天線層130的圖案僅為示意,並不用以限制本揭露。
第12圖繪示根據本發明另一實施方式之晶片封裝體100a的剖面圖。晶片封裝體100a包含半導體基板110、支撐件120、天線層130、重佈線層140與保護層170a。與第1圖實施方式不同的地方在於,保護層170a為黏膠,可取代第1圖的保護層170與接合層102b,以節省材料與製造成本。
第13圖繪示根據本發明另一實施方式之晶片封裝體100b的剖面圖。晶片封裝體100a包含半導體基板110、支撐件120a、天線層130a、重佈線層140、屏蔽層150a與保護層170a。與第1圖實施方式不同的地方在於,支撐件120a、半導體基板110與保護層170a之間有空腔C,且支撐件120a圍繞此空腔C。此外,天線層130a的一部分朝向空腔C,另一部分朝向支撐件120a。在本實施方式中,屏蔽層150a位於半導體基板110的頂面114上,因此空腔C位於屏蔽層150a與天線層130a之間。
第14圖至第25圖繪示根據本發明一實施方式之晶片封裝體200(見第25圖)的製造方法在各階段的剖面圖。同時參閱第14圖與第15圖,天線層220可用沉積方式(Deposition)形成於第一基板210的整個第一表面211上,並經圖案化製程而得到第15圖的天線層220。在本實施方式中,天線層220的材質可以為銅,但並不以此為限。第一基板210的材質可以為玻璃、熔融石英(Fused silica)或石英玻璃,其內部可不具有線路與導電接點。
參閱第16圖,待天線層220形成後,可形成鈍化層230以覆蓋天線層230。在此步驟中,可接合第二基板240於第一基板210,使鈍化層230位於第一基板210與第二基板240之間。第二基板240的材質可與第一基板210相同,例如玻璃、熔融石英或石英玻璃。此外,鈍化層230可先形成於第一基板210或第二基板240才執行上述接合步驟,並不用以限制本發明。
同時參閱第17圖與第18圖,待第二基板240接合於第一基板210後,可形成金屬層250於第二基板240背對鈍化層230的整個表面上,例如以沉積方式形成。接著,經圖案化製程而得到第18圖的金屬層250。金屬層250可材質可以為銅,但不以此為限。金屬層250的設置為選擇性的,在一些實施方式中,晶片封裝體可不具有金屬層250。
參閱第19圖,待圖案化金屬層250後,可形成另一鈍化層260以覆蓋金屬層250。第一基板210具有背對第一表面211的第二表面213。
同時參閱第20圖與第21圖,接著,可將第19圖的結構翻轉180度,並研磨第一基板210的第二表面213,以減薄第一基板210。待第一基板210減薄後,可採用刀具切割的方式,移除第一基板210與鈍化層230的邊緣部分,以形成溝槽T。在本實施方式中,天線層220的側面從溝槽T露出,且溝槽T延伸至第二基板240中,使第二基板240具有凹部242。
參閱第22圖,接著,形成重佈線層270於第一基板210的第二表面213上、天線層220的側面上與第二基板240的凹部242上。如此一來,重佈線層270可與天線層220電性連接。在本實施方式中,重佈線層270可用濺鍍的方式形成,其材質可以為銅,但不以此為限。重佈線層270可經圖案化而具有與天線層220分開的屏蔽區段272。屏蔽區段272與天線層220重疊,具有屏蔽效果。
同時參閱第23圖與第24圖,待重佈線層270形成後,可形成另一鈍化層280以覆蓋重佈線層270。鈍化層280圍繞重佈線層270。鈍化層280可經圖案化形成開口O1。接著可選擇性地形成金屬表層275(Metal finish)於開口O1中的重佈線層270上,在一些實施方式中,金屬表層275可以省略。
接著參閱第25圖,可設置導電結構294於鈍化層280上,以及設置具有導電結構292的積體電路元件290於開口O1中的重佈線層270上。積體電路元件290可經導電結構292與重佈線層270電性連接天線層220,也可經導電結構292電性連接重佈線層270的屏蔽區段272。此外,積體電路元件290與鈍化層280之間還可設置填充層295(Under fill),以提供絕緣與保護功能。經由以上步驟,可形成第25圖的晶片封裝體200。在一實施方式中,晶片封裝體200可省略填充層295。在另一實施方式中,晶片封裝體200還可省略積體電路元件290的配置。
在本實施方式中,晶片封裝體200的重佈線層270從第一基板210的第二表面213延伸至第一基板210的側面、第一鈍化層230的側面及第二基板240的凹部242。晶片封裝體200對於毫米波(mm-wave)裝置的要求可提供更佳的效能,例如較短的傳輸線、整合的積體電路元件290與天線層220、及能使用較佳的基板材料(如石英玻璃)取代印刷電路板(PCB)。
在另一實施方式中,第16圖的天線層220可形成在第二基板240朝向第一鈍化層230的表面而非第一基板210的第一表面211。如此一來,經過第17圖至第25圖的步驟後,第25圖的天線層220會位在第二基板240上。
已敘述過的元件連接關係、材料與功效將不再重複贅述,合先敘明。在以下敘述中,將說明其他形式的晶片封裝體的製造方法。
第26圖至第34圖繪示根據本發明一實施方式之晶片封裝體200a(見第34圖)的製造方法在各階段的剖面圖。參閱第26圖,於第一基板210a中形成穿孔H。穿孔H可用鑽孔(Drilling)的方式形成。參閱第27圖,接著可對第一基板210a施以金屬化(Metallization)製程,以形成天線層220a於第一基板210a的整個第一表面211上、形成導電通道V於第一基板210a中及形成重佈線層270a於第一基板210a的整個第二表面213上。如此一來,可得到第27圖的結構。在本實施方式中,天線層220a、導電通道V與重佈線層270a可以為一體成型,具有相同的材料(例如銅),但並不用以限制本發明。第一基板210a的材質可以為玻璃、熔融石英(Fused silica)或石英玻璃,其內部可不具有線路與導電接點。
同時參閱第28圖與第29圖,待前述金屬化製程後,可圖案化覆蓋第一基板210a之整個第一表面211的天線層220a而得到第28圖的天線層220a,接著可形成鈍化層230a以覆蓋天線層220a。
同時參閱第30圖與第31圖,接著,可將第29圖的結構翻轉180度,重佈線層270可經圖案化而具有與導電通道V分開的屏蔽區段272a。屏蔽區段272a與天線層220a重疊,具有屏蔽效果。待圖案化重佈線層270後,可形成另一鈍化層280a以覆蓋重佈線層270a。鈍化層280可經圖案化形成開口O2。
同時參閱第32圖與第33圖,接著可選擇性地形成金屬表層275(Metal finish)於開口O2中的重佈線層270a上,在一些實施方式中,金屬表層275可以省略。待金屬表層275形成後,可設置導電結構294於鈍化層280a上。
參閱第34圖,待設置導電結構294後,可設置具有導電結構292的積體電路元件290於開口O2中的重佈線層270a上。積體電路元件290可經導電結構292、重佈線層270a與導電通道V電性連接天線層220,也可經導電結構292電性連接重佈線層270a的屏蔽區段272a。導電通道V的兩端可分別接觸天線層220a與重佈線層270a。此外,積體電路元件290與鈍化層280之間還可設置填充層295(Under fill),以提供絕緣與保護功能。經由以上步驟,可形成第34圖的晶片封裝體200a。在一實施方式中,晶片封裝體200a可省略填充層295。在另一實施方式中,晶片封裝體200a還可省略積體電路元件290的配置。
在本實施方式中,晶片封裝體200a的重佈線層270a可經由第一基板210中的導電通道V電性連接在第一基板210之第一表面211的天線層220a。晶片封裝體200a對於毫米波(mm-wave)裝置的要求可提供更佳的效能,例如較短的傳輸線、整合的積體電路元件290與天線層220a、及能使用較佳的基板材料(如石英玻璃)取代印刷電路板(PCB)。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100,100a,100b:晶片封裝體
102a,102b:接合層
110:半導體基板
111:傾斜側壁
112:導電墊
113:底面
114:頂面
115:功能層
116:絕緣層
117:鈍化層
120,120a:支撐件
121:傾斜側壁
122:頂面
123:底面
130,130a:天線層
132:一端
140:重佈線層
142:一端
150,150a:屏蔽層
160:平坦層
161:底面
162:傾斜側壁
170,170a:保護層
180:鈍化層
190:導電結構
200,200a:晶片封裝體
210,210a:第一基板
211:第一表面
213:第二表面
220,220a:天線層
230,230a:鈍化層
240:第二基板
242:凹部
250:金屬層
260:鈍化層
270,270a:重佈線層
272,272a:屏蔽區段
275:金屬表層
280,280a:鈍化層
290:積體電路元件
292,294:導電結構
295:填充層
1-1:線段
C:空腔
L:線
O:缺口
O1,O2:開口
H:穿孔
T:溝槽
V:導電通道
θ:鈍角
本案之態樣當結合附圖閱讀時將自以下實施方式中最佳地理解。應注意,根據行業中的標準實踐,各個特徵不必按比例繪製。實際上,為了論述清晰起見,各個特徵的尺寸可任意增加或減小。
第1圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
第2圖至第9圖繪示第1圖之晶片封裝體的製造方法在各階段的剖面圖。
第10圖繪示第1圖之晶片封裝體的上視圖,其省略保護層與接合層。
第11圖繪示第1圖之晶片封裝體的下視圖,其省略鈍化層。
第12圖繪示根據本發明另一實施方式之晶片封裝體的剖面圖。
第13圖繪示根據本發明另一實施方式之晶片封裝體的剖面圖。
第14圖至第25圖繪示根據本發明一實施方式之晶片封裝體的製造方法在各階段的剖面圖。
第26圖至第34圖繪示根據本發明一實施方式之晶片封裝體的製造方法在各階段的剖面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記)
無
國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記)
無
100:晶片封裝體
102a、102b:接合層
110:半導體基板
111:傾斜側壁
112:導電墊
113:底面
114:頂面
115:功能層
116:絕緣層
117:鈍化層
120:支撐件
121:傾斜側壁
122:頂面
123:底面
130:天線層
132:一端
140:重佈線層
142:一端
150:屏蔽層
160:平坦層
161:底面
162:傾斜側壁
170:保護層
180:鈍化層
190:導電結構
θ:鈍角
Claims (35)
- 一種晶片封裝體,包含:一半導體基板,具有一傾斜側壁與凸出該傾斜側壁的一導電墊;一支撐件,位於該半導體基板上,且具有背對該半導體基板的一頂面與鄰接該頂面的一傾斜側壁;一天線層,位於該支撐件的該頂面上;以及一重佈線層,位於該支撐件的該傾斜側壁上,且接觸該導電墊的一側壁與該天線層的一端。
- 如請求項1所述的晶片封裝體,更包含:一屏蔽層,位於該半導體基板與該支撐件之間。
- 如請求項2所述的晶片封裝體,其中該支撐件具有相對該頂面的一底面,該屏蔽層接觸該底面。
- 如請求項1所述的晶片封裝體,其中該天線層接觸該支撐件的該頂面。
- 如請求項1所述的晶片封裝體,其中該半導體基板具有鄰接該傾斜側壁的一底面,該晶片封裝體更包含:一平坦層,覆蓋該半導體基板的該傾斜側壁與該底面,且覆蓋該導電墊的一底面,該平坦層具有一底面與鄰接該 底面的一傾斜側壁,且該平坦層的該傾斜側壁的斜率與該支撐件的該傾斜側壁的斜率大致相同。
- 如請求項5所述的晶片封裝體,其中該重佈線層位於該平坦層的該傾斜側壁與該底面上。
- 如請求項1所述的晶片封裝體,其中該天線層的傳輸頻率在20GHz至60GHz的範圍中,該半導體基板為一射頻裝置。
- 如請求項1所述的晶片封裝體,更包含:一保護層,覆蓋該支撐件、該天線層與該重佈線層遠離該半導體基板的一端。
- 如請求項8所述的晶片封裝體,其中該保護層的材料包含玻璃、熔融石英(Fused silica)、石英玻璃、藍寶石或上述材料之組合。
- 如請求項8所述的晶片封裝體,其中該保護層為黏膠。
- 如請求項8所述的晶片封裝體,其中該支撐件、該半導體基板與該保護層之間有一空腔,且該支撐件圍繞該空腔。
- 如請求項1所述的晶片封裝體,其中該半導體基板具有一頂面,該半導體基板的該頂面鄰接該半導體基板的該傾斜側壁,該晶片封裝體更包含:一屏蔽層,位於該半導體基板的該頂面上。
- 如請求項1所述的晶片封裝體,更包含:一接合層,位於該支撐件與該半導體基板之間。
- 一種晶片封裝體的製造方法,包含:形成一天線層於一支撐件的一頂面上;將該支撐件接合於一半導體基板的一頂面,其中該半導體基板的該頂面具有一導電墊;蝕刻該半導體基板的一底面,使該半導體基板具有一傾斜側壁,且該導電墊凸出該傾斜側壁;執行一切割製程,使該支撐件具有一傾斜側壁;以及形成一重佈線層於該支撐件的該傾斜側壁上,使得該重佈線層接觸該導電墊的一側壁與該天線層的一端。
- 如請求項14所述的晶片封裝體的製造方法,其中形成該天線層包含:濺鍍一導電層於該支撐件的該頂面上;以及圖案化該導電層,以形成該天線層。
- 如請求項14所述的晶片封裝體的製造方法,更包含:形成一屏蔽層於該支撐件的一底面上。
- 如請求項16所述的晶片封裝體的製造方法,其中形成該屏蔽層包含:濺鍍一導電層於該支撐件的該底面上;以及圖案化該導電層,以形成該屏蔽層。
- 如請求項14所述的晶片封裝體的製造方法,更包含:形成一平坦層於該半導體基板的該傾斜側壁與該底面上與該導電墊的一底面上。
- 如請求項18所述的晶片封裝體的製造方法,執行該切割製程使該平坦層同步形成一傾斜側壁,其中該平坦層的該傾斜側壁的斜率與該支撐件的該傾斜側壁的斜率大致相同。
- 如請求項14所述的晶片封裝體的製造方法,更包含:設置一保護層於該支撐件與該天線層上。
- 一種晶片封裝體,包含: 一第一基板,具有相對的一第一表面與一第二表面;一天線層,位於該第一基板的該第一表面上;一第一鈍化層,覆蓋該天線層;以及一重佈線層,位於該第一基板的該第二表面上,且電性連接該天線層,其中該重佈線層還具有與該天線層分開的一屏蔽區段,該屏蔽區段與該天線層重疊,該重佈線層延伸至該第一基板的側面與該第一鈍化層的側面。
- 如請求項21所述的晶片封裝體,更包含:一第二基板,其中該第一鈍化層位於該第一基板與該第二基板之間,且該重佈線層延伸至該第二基板的一凹部。
- 如請求項22所述的晶片封裝體,更包含:一金屬層,位於該第二基板背對該第一鈍化層的表面上;以及一第二鈍化層,覆蓋該金屬層。
- 如請求項22所述的晶片封裝體,其中該第二基板的材質為玻璃、熔融石英(Fused silica)或石英玻璃。
- 如請求項20所述的晶片封裝體,更包含:一第二鈍化層,覆蓋該重佈線層。
- 如請求項25所述的晶片封裝體,更包含:一積體電路元件,具有一導電結構,且該導電結構位於該重佈線層上。
- 如請求項21所述的晶片封裝體,其中該第一基板的材質為玻璃、熔融石英(Fused silica)或石英玻璃。
- 如請求項21所述的晶片封裝體,更包含:一導電通道,位於該第一基板中,且該導電通道的兩端分別接觸該天線層與該重佈線層。
- 一種晶片封裝體的製造方法,包含:形成一天線層於一第一基板的一第一表面上,其中該第一基板具有背對該第一表面的一第二表面;形成一第一鈍化層以覆蓋該天線層;接合一第二基板於該第一基板,使該第一鈍化層位於該第一基板與該第二基板之間;以及形成一重佈線層於該第一基板的該第二表面上,其中該重佈線層電性連接該天線層,該重佈線層還具有與該天線層分開的一屏蔽區段,該屏蔽區段與該天線層重疊。
- 如請求項29所述的晶片封裝體的製造方法,更包含: 形成一金屬層於該第二基板背對該第一鈍化層的表面上;以及形成一第二鈍化層以覆蓋該金屬層。
- 如請求項29所述的晶片封裝體的製造方法,更包含:移除該第一基板與該第一鈍化層的邊緣部分,以形成一溝槽,其中該天線層的一側面從該溝槽露出,且該溝槽延伸至該第二基板中,使該第二基板具有一凹部。
- 如請求項31所述的晶片封裝體的製造方法,其中形成該重佈線層於該第一基板的該第二表面上更包含:形成該重佈線層於該天線層的該側面與該第二基板的該凹部上。
- 如請求項29所述的晶片封裝體的製造方法,更包含:形成一第二鈍化層以覆蓋該重佈線層。
- 如請求項29所述的晶片封裝體的製造方法,更包含:設置具有一導電結構的一積體電路元件於該重佈線層上。
- 如請求項29所述的晶片封裝體的製造方法,更包含:形成一導電通道於該第一基板中,其中該導電通道的兩端分別接觸該天線層與該重佈線層。
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