TWI720737B - Microcontroller circuit and control method thereof - Google Patents

Abstract

A microcontroller circuit controlling a display panel and including a memory, a CPU, an image driver, a charge pump and a control circuit is provided. The memory is configured to store a program code. The CPU executes the program code to generate an image driving signal. The image driver receives an operation voltage and drives the display panel according to the image driving signal. The charge pump charges a capacitor according to a charging signal. The voltage of the capacitor serves as the operation voltage. The control circuit generates the charging signal according to the operation voltage. In a normal mode, the control circuit determines whether the charge time of the capacitor exceeds a charging standard value. When the charge time of the capacitor exceeds the charging standard value, the CPU executes a detection procedure of the program code.

Description

Microcontroller circuit and control method

The present invention relates to a microcontroller circuit, in particular to a microcontroller circuit for driving a display panel.

In a general display device, there is usually a display panel and a microcontroller circuit. The microcontroller circuit is used to generate an image signal. The display panel presents a picture according to the image signal. When assembling the display panel and the microcontroller circuit, two adjacent pins of the display panel may be short-circuited, so that the picture cannot be displayed normally. In addition, when the size of the display panel is too large, the image signal generated by the microcontroller circuit may not be sufficient to drive the display panel, so that the display panel cannot display images normally. However, when the display panel cannot display the picture normally, the tester cannot immediately know the cause of the abnormality, and it takes a lot of time to detect.

The present invention provides a microcontroller circuit for controlling a display panel, and includes a memory, a central processing unit, an image driver, a charge pump, and a control circuit. The memory is used to store a program code. The central processing unit executes the program code to generate an image driving signal. The image driver receives an operating voltage and drives the display panel according to the image driving signal. The charge pump charges a capacitor according to a charging signal. The voltage of the capacitor is used as the operating voltage. The control circuit generates a charging signal according to the operating voltage. In a normal mode, the control circuit determines whether the charging time of the capacitor is greater than a charging standard value. When the charging time of the capacitor is greater than the charging standard value, the central processing unit executes a detection procedure of the program code.

The present invention further provides a control method, which is suitable for a microcontroller circuit. The microcontroller circuit is coupled to a display panel. The control method of the present invention includes: executing a program code to generate an image driving signal; charging a capacitor, where the voltage of the capacitor is used as an operating voltage; providing an operating voltage to an image driver, where the image driver is driven according to the image driving signal Display panel; and judging whether the charging time of the capacitor is greater than a charging standard value. When the charging time of the capacitor is greater than the charging standard value, a detection procedure of the program code is executed.

The control method of the present invention can be implemented by the microcontroller circuit of the present invention, which is a hardware or firmware that can perform specific functions, or it can be recorded in a recording medium by means of program codes and combined with specific hardware. Implementation. When the program code is loaded and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes a microcontroller circuit for implementing the present invention.

In order to make the purpose, features and advantages of the present invention more comprehensible, embodiments are specifically cited below, and detailed descriptions are made in conjunction with the accompanying drawings. The specification of the present invention provides different examples to illustrate the technical features of different embodiments of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes, and is not intended to limit the present invention. In addition, part of the repetition of the drawing symbols in the embodiments is for simplifying the description, and does not mean the relevance between different embodiments.

Figure 1 is a schematic diagram of the display device of the present invention. As shown in the figure, the display device 100 includes a display panel 110 and a microcontroller circuit 120. The present invention does not limit the type of the display device 100. In a possible embodiment, the display device 100 is an electronic device with a display function, such as an electronic watch.

The display panel 110 presents a frame according to an image signal S _I. The invention does not limit the type of the display device 110. In a possible embodiment, the display panel 110 is a liquid crystal display panel (LCD panel), such as a twisted nematic (TN) liquid crystal display panel or a super-twisted nematic (STN) liquid crystal display panel. ) Liquid crystal display panel. In other embodiments, the display panel 110 is a passive matrix liquid crystal display panel.

The microcontroller circuit 120 provides the image signal S _I to the display panel 110, and includes a memory 121, a central processing unit (CPU) 122, an image driver 123, a charge pump 124, and a control circuit 125 . In one possible embodiment, the microcontroller circuit 120 is a micro control unit (MCU).

In this embodiment, the memory 121 is used to store a program code PRC. The invention does not limit the type of the memory 121. In a possible embodiment, the memory 121 is a non-volatile memory, such as a flash memory.

The central processor 122 reads and executes the code PRC, to generate a video drive signal S _D. In a possible embodiment, the central processing unit 122 has input and output pins D ₀ to D ₇ . The input and output pins D ₀ ~ D ₇ are used to receive data S _DT . In this example, the data S _DT is a parallel data. In other embodiments, the data S _DT is a series of data. The central processing unit 122 uses a single input/output pin (such as D ₀ ) to receive serial data.

In other embodiments, the central processing unit 122 further has an input and output pin INT ₀ for receiving the interrupt signal LCDPO_INT. When the interrupt signal LCDPO_INT is enabled, the central processing unit 122 executes an interrupt procedure of the program code PRC. In a possible embodiment, when the microcontroller circuit 120 is operating in a test mode, if the interrupt signal LCDPO_INT is enabled, the CPU 122 receives data S _{through the input and output pins D 0} ~ D _{7 DT} , and generate a charging standard value based on the data S _DT. In this example, the central processing unit 122 may output the charging standard value _{through the input and output pins D 0} to D _7. However, when the microcontroller circuit 120 is operating in a normal mode, if the interrupt signal LCDPO_INT is enabled, it means that the display panel 110 is working abnormally. Therefore, the central processing unit 122 enters a detection mode according to the interrupt procedure of the program code PRC. In the detection mode, the central processing unit 122 performs a detection procedure. The detection procedure may be an obstacle removal procedure to find out where the abnormality occurs, or a warning procedure to notify the user.

Video driver 123 receives an operating voltage VLCD, and generate an image based on the video signal S _I drive signal S _D. The present invention does not limit the circuit structure of the image driver 123. In one possible embodiment, the image 123 comprising a drive voltage generating circuit which generates a plurality of output voltage VLCD according to the operating voltage, and the driving based on the video signal S _D, to select one of a video signal S _I from such output voltage. In one possible embodiment, the image driver 123 is a common/segment (COM/SEG) driver.

The charge pump 124 charges a capacitor C according to a charging signal CMP_OUT to provide an operating voltage VLCD. In a possible embodiment, the voltage of the capacitor C is used as the operating voltage VLCD. The present invention does not limit the circuit structure of the charge pump 124. Any structure that can charge the capacitor C according to the charging signal CMP_OUT can be used as the charge pump 124. In a possible embodiment, when the charging signal CMP_OUT is at a first level, the charge pump 124 charges the capacitor C. When the charging signal CMP_OUT is at a second level, the charge pump 124 stops charging the capacitor C. In other embodiments, the charge pump 124 further receives a clock signal LCDCLK from the central processing unit 122.

The control circuit 125 generates a charging signal CMP_OUT according to the operating voltage VLCD. For example, when the operating voltage VLCD is lower than a target value (such as 5V), the control circuit 125 enables the charging signal CMP_OUT, such as setting the charging signal CMP_OUT to the first level. At this time, the charge pump 124 charges the capacitor C according to the charging signal CMP_OUT to increase the operating voltage VLCD. However, when the operating voltage VLCD reaches the target value, the control circuit 125 disables the charging signal CMP_OUT, such as setting the charging signal CMP_OUT to the second level. At this time, the charge pump 124 stops charging the capacitor C according to the charging signal CMP_OUT. The first level is relative to the second level. For example, when the first level is a high level, the second level is a low level. When the first level is a low level, the second level is a high level.

In this embodiment, the control circuit 125 determines whether the display panel 110 is abnormal according to the charging time of the capacitor C. For example, when the assembler connects the display panel 110 with the microcontroller circuit 120, it may be caused by a short circuit between the pins of the integrated circuit (IC) or an overload caused by the oversize of the display device 110, which will cause the capacitor C's charging time is too long. When the charging time of the capacitor C is greater than a charging standard value, the display panel 110 cannot work normally or presents a blurred image. Therefore, the control circuit 125 enables the interrupt signal LCDPO_INT to notify the central processing unit 122.

At this time, the central processing unit 122 executes a specific program of the program code PRC according to the interrupt signal LCDPO_INT. In a possible embodiment, the specific program is used to issue a warning message to notify the assembly personnel of the abnormal occurrence. In another possible embodiment, the specific program is used to issue a test signal to command the image driver 123 to enter a test mode. In the detection mode, the image driver 123 sequentially detects whether a short circuit occurs between each pin of the display panel 110 and another pin.

In other embodiments, when a trigger event occurs, the microcontroller circuit 120 enters a test mode. In the test mode, the control circuit 125 detects the charging time of the capacitor C to generate data S _DT . The central processing unit 122 _{learns the charging time of the capacitor C according to the data S DT} , and then defines a charging standard value according to the charging time of the capacitor C. In a possible embodiment, the trigger event is caused by the tester. In this example, the tester may press a button (not shown) to make the microcontroller circuit 120 enter a test mode. In another possible embodiment, when the central processing unit 122 executes a test procedure of the program code PRC, the microcontroller circuit 120 also enters a test mode.

Figure 2 is a possible embodiment of the control circuit of the present invention. As shown in the figure, the control circuit 200 includes comparators 210 and 260, a counter 220, an edge detector 230, a storage circuit 240, and a switch 250. The comparator 210 compares the operating voltage VLCD with a reference voltage Vref ₁ to generate the charging signal CMP_OUT. In this embodiment, when the operating voltage VLCD is less than the reference voltage Vref ₁ , it indicates that the operating voltage VLCD has not reached a target value, so the comparator 210 outputs a high-level charging signal CMP_OUT to command the charge pump 124 to charge the capacitor C . However, when the operating voltage VLCD is greater than the reference voltage Vref ₁ , it indicates that the operating voltage VLCD has reached the target value, so the comparator 210 outputs a low-level charging signal CMP_OUT to command the charge pump 124 to stop charging the capacitor C. In one possible embodiment, the comparator 210 is integrated in the charge pump 124.

The counter 220 is used to count the charging time of the capacitor C. In this embodiment, the counter 220 calculates the duration of the charging signal CMP_OUT at a high level. The present invention does not limit the counting method of the counter 220. In a possible embodiment, the counter 220 is triggered by the rising edge of the charging signal CMP_OUT to count the number of pulses of the clock signal LCDCLK from a preset value. In this example, the counter 220 stops counting according to the falling edge of the charging signal CMP_OUT. The invention does not limit the type of the counter 220. In one possible embodiment, the counter 220 is an up counter or a down counter.

The edge detector 230 is used to detect the falling edge of the charging signal CMP_OUT. When the edge detector 230 detects the falling edge of the charging signal CMP_OUT, it means that the charge pump 124 stops charging the capacitor C. Therefore, the edge detector 230 reads the count value of the counter 220. The invention does not limit the circuit structure of the edge detector 230. In one possible embodiment, the edge detector 230 has a latch for latching the count value of the counter 220. In another possible embodiment, the edge detector 230 stores the count value of the counter 220 in the storage circuit 240. For convenience of illustration, the micro-controller circuit 120 when operating in a test mode, the count value of the counter 220 is represented by the symbol CNT _T. When microcontroller circuit 120 operates in a normal mode, the count value of the counter 220 is represented by the symbol CNT _N.

In other embodiments, each time the edge detector 230 detects the falling edge of the charging signal CMP_OUT, the edge detector 230 generates the enabling signal S _EN . In a possible embodiment, when the microcontroller circuit 120 is operating in the test mode, the central processing unit 122 turns on the switch 250. Therefore, the enable signal S _{EN is} used as the interrupt signal LCDPO_INT to interrupt the central processing unit 122. At this time, the central processing unit 122 reads the count value CNT _T stored in the storage circuit 240, and generates a charging standard value ST _C according to the count value CNT _T. In a possible embodiment, the central processing unit 122 _{adds a preset value to the count value CNT T} , and uses the added result as the charging standard value ST _C. The central processing unit 122 may store the charging standard value ST _C in the storage circuit 240. In other embodiments, the central processing unit 122 may _{store the charging standard value ST C} in the memory 121. In some embodiments, the central processing unit 122 is coupled to the counter 220 to directly read the count value CN _{T of the} counter 220. However, when the microcontroller circuit 120 is operating in the normal mode, the central processing unit 122 does not turn on the switch 250. In this example, the enable signal S _{EN is} used to trigger the comparator 260.

In the normal mode, when the comparator 260 is enabled trigger signal S _EN, the comparator 260 comparing the count value of the counter 220 and the charging standard value CNT _N ST _C. When the count value of the counter 220 is larger than the charging standard value CNT _N ST _C, C represents the capacitance of the charging time is too long. Therefore, the comparator 260 enables the interrupt signal LCDPO_INT to notify the central processing unit 122. In a possible embodiment, the central processing unit 122 executes a specific program of the program code PRC according to the interrupt signal LCDPO_INT, such as a notification program to notify the user, or executes a detection program to detect abnormalities, or executes a Troubleshooting procedures. However, when the count value of the counter CNT _N 220 does not exceed the value of the charging standard ST _C, C represents the capacitance of the normal charging time. Therefore, the comparator 260 does not enable the interrupt signal LCDPO_INT. At this time, the central processor 122 continues to generate the drive signal S _D to the video driver 123 images.

In the present embodiment, comparator 260 is coupled to the storage circuit 240 for reading the count value of the charging standard value CNT _N ST _C, but not to limit the present invention. In one possible embodiment, when the edge detector 230 detects the falling edge of the charging signal CMP_OUT, edge detector 230 reads the count value of the counter CNT _N 220, and the count value CNT _N directly to the comparator 260 . In another possible embodiment, the comparator 260 is directly coupled to counter 220 to read the count value CNT _N. In some embodiments, the comparator 260 is coupled to the memory 121 for reading the charging standard value ST _C. In other embodiments, the comparator 260 is coupled to the central processing unit 122 to receive the charging standard value ST _C.

In one possible embodiment, when the count value of the counter 220 is larger than the charging standard value CNT _N ST _C, the magnitude comparator 260 to set a flag (not shown) is a first specific value, such as 1. In this example, when the central processing unit 122 receives the enabled interrupt signal LCDPO_INT, the central processing unit 122 reads the value of the flag. When the value of the flag is equal to a set value (such as 1), the central processing unit 122 executes a detection procedure. In another possible embodiment, when the count value of the counter 220 is larger than the charging standard value CNT _N ST _C, the target value of the flag comparator 260 is set to a second specific value such as 0. In this example, since the value of the flag is not equal to the set value, even if the interrupt signal LCDPO_INT is enabled, the CPU 122 does not execute the detection procedure.

In other embodiments, the storage circuit 240 further has a mode register (not shown). In this example, when the mode register stores a value of 1, it means that the microcontroller circuit 120 is operating in the test mode. Therefore, the microcontroller circuit 120 turns on the switch 250. However, when the mode register stores a value of 0, it means that the microcontroller circuit 120 is operating in the normal mode. Therefore, the microcontroller circuit 120 does not turn on the switch 250.

In a possible embodiment, the microcontroller circuit 120 further includes a button (not shown). When the user toggles the button to the right, the central processing unit 122 stores the value 1 in the mode register. When the user toggles the button to the left, the central processing unit 122 stores the value 0 in the mode register. In some embodiments, the mode register may be provided in the memory 121.

Figure 3 is another possible embodiment of the control circuit of the present invention. FIG. 3 is similar to FIG. 2 except that the control circuit 300 in FIG. 3 further includes a voltage divider circuit 305. The voltage divider circuit 305 processes the operating voltage VLCD to generate a process voltage V _P. In this example, the comparator 310 compares the processing voltage V _P and the reference voltage Vref ₂ to generate the charging signal CMP_OUT. Since the characteristics of the counter 320, the edge detector 330, the storage circuit 340, and the comparator 360 are similar to those of the counter 220, the edge detector 230, the storage circuit 240, and the comparator 260 in FIG. 2, they will not be described again.

FIG. 4A is a schematic diagram of the charging signal CMP_OUT and the interrupt signal LCDPO_INT in the normal mode of the present invention. Taking the control circuit 200 in FIG. 2 as an example, the rising edge 413 of the charging signal CMP_OUT triggers the counter 220. Therefore, the counter 220 starts to adjust a count value CNT _T according to the rising edge of the clock signal LCDCLK. At this time, since the charging signal CMP_OUT is at a high level, the charge pump 124 charges the capacitor C.

When the charging signal CMP_OUT changes from a high level to a low level, the charge pump 124 stops charging the capacitor C. At this time, the counter 220 stops counting according to the falling edge 414 of the charging signal CMP_OUT. Assume that the count value of the counter 220 is 56. Since the count value (56) of the counter 220 is greater than the charging standard value (50), the comparator 260 enables the interrupt signal LCDPO_INT. Therefore, the central processing unit 122 executes an interrupt procedure, such as an abnormality detection procedure or a notification procedure.

FIG. 4B is a schematic diagram of the charging signal CMP_OUT and the interrupt signal LCDPO_INT of the present invention in the test mode. Taking the control circuit 200 in FIG. 2 as an example, the counter 220 is triggered by the rising edge 411 of the charging signal CMP_OUT. Thus, counter 220 according to the clock signal rising edge LCDCLK, adjusting a start count value CNT _N. At this time, since the charging signal CMP_OUT is at a high level, the charge pump 124 charges the capacitor C.

When the charging signal CMP_OUT changes from a high level to a low level, the charge pump 124 stops charging the capacitor C. At this time, the counter 220 stops counting according to the falling edge 412 of the charging signal CMP_OUT. Assume that the count value of the counter 220 is 50. The edge detector 230 enables the interrupt signal LCDPO_INT according to the falling edge 412. Therefore, the central processing unit 122 reads the count value of the counter 220 (for example, 50). In a possible embodiment, the central processing unit 122 directly uses the count value of the counter 220 (for example, 50) as a charging standard value.

Figure 5 is a possible schematic diagram of the image driver of the present invention. In this embodiment, the image driver 500 is a COM/SEG driver, and includes a COM/SEG digital signal generator 510, a voltage generating circuit 520, and a driver 530. The COM/SEG digital signal generator 510 generates a digital signal S _{DG according to the image driving signal S D.} The voltage generating circuit 520 generates processing voltages V1 to V3 according to the operating voltage VLCD. The invention does not limit the structure of the voltage generating circuit 520. In a possible embodiment, the voltage generating circuit 520 is a voltage divider circuit, which includes resistors R ₁ ˜R ₄ . The resistors R ₁ to R _{4 are} connected in series between the operating voltage VLCD and the ground voltage VSS to generate the processing voltages V1 to V3. The invention does not limit the number of resistors. In other embodiments, when the voltage generating circuit 520 has more resistances, more processing voltages can be generated.

The driver 530 generates common signals COM ₀ ~COM _M and segment signals SEG ₀ ~SEG _N according to the digital signal S _DG . In a possible embodiment, the driver 530 selectively uses the processing voltages V1 to V3 as the common signals COM ₀ to COM _M and the segment signals SEG ₀ to SEG _{N according to the digital signal S DG} . In other words, _{the voltage of any one of the common signals COM 0} to COM _M and the segment signals SEG ₀ to SEG _N is equal to one of the processing voltages V1 to V3. In this embodiment, the common signals COM ₀ to COM _M and the segment signals SEG ₀ to SEG _N constitute the image signal S _I.

Figure 6 is a schematic diagram of a possible flow of the control method of the present invention. The control method of the present invention is applicable to a microcontroller circuit. The microcontroller circuit is coupled to a display panel for controlling the picture presented by the display panel. First, it is determined whether a trigger event has occurred (step S611). The invention does not limit the types of trigger events. In one possible embodiment, the microcontroller circuit determines the state of a button. When the tester presses the button, it means that a trigger event has occurred. Therefore, the microcontroller circuit enters a test mode (step S612). When the trigger event does not occur, the microcontroller circuit enters a normal mode (step S613). In a possible embodiment, in the test mode, the microcontroller circuit defines a charging standard value. In the normal mode, the microcontroller circuit compares the charging time of a capacitor with the charging standard value. When the charging time of the capacitor is longer than the charging standard value, it means that the display panel is abnormal. Therefore, the microcontroller circuit executes a specific program, such as an abnormality detection program.

FIG. 7 is a schematic diagram of a possible flow of the microcontroller circuit of the present invention operating in the test mode. First, reset a count value (step S711). In a possible embodiment, the microcontroller circuit resets the count value according to the level change of a charging signal, wherein the charging signal is used to charge a specific capacitor. In this example, when a charging signal changes from a first level (such as a low level) to a second level (a high level), the microcontroller circuit resets a counter to start counting from an initial value .

Next, it is determined whether a charging signal is at the second level (step S712). When the charging signal is at the second level, it means that the capacitor C is continuously charging. Therefore, the count value is increased (step S713), and the process returns to step S712. When the charging signal is not at the second level, the capacitor C is no longer charged. Therefore, the count value is latched and an interrupt request is generated (step S714). In a possible embodiment, the microcontroller circuit generates a charging standard value according to the count value latched in step S714. The invention does not limit how the microcontroller circuit generates the charging standard value. In a possible embodiment, the microcontroller circuit adds the count value to a preset value, and then uses the added result as the charging standard value.

In other embodiments, step S712 further determines whether the count value is less than a maximum value. In this example, as long as the charging signal is not at the second level or the count value is not less than the maximum value, step S714 is executed. However, if the charging signal is at the second level and the count value is less than the maximum value, step S713 is executed.

FIG. 8 is a schematic diagram of a possible flow of the microcontroller circuit of the present invention operating in the normal mode. First, a count value is reset (step S811). In one possible embodiment, when a charging signal changes from a first level (such as a low level) to a second level (a high level), a counter is reset. Therefore, the counter starts counting from an initial value (such as 0).

It is determined whether the charging signal is at the second level (step S812). In this embodiment, the charging signal is provided to a charge pump. When the charging signal is at the second level, the charge pump charges a capacitor C. When the charging signal is at the first level, the charge pump stops charging the capacitor C.

When the charging signal is at the second level, the count value is increased (step S813), and step S812 is returned. When the charging signal is not at the second level, the count value is latched (step S814). It is determined whether the latched count value in step S814 is greater than a charging standard value (step S815). When the count value is less than the charging standard value, return to step S811 to reset the count value to return the count value to an initial value. However, when the count value is greater than the charging standard value, it means that the display panel may be abnormal. Therefore, an interrupt request is generated (step S816). In a possible embodiment, when the microcontroller circuit receives an interrupt request, the microcontroller circuit executes a detection procedure to find out the abnormal phenomenon.

In other embodiments, before step S811, a central processing unit in the microcontroller circuit executes a program code to generate an image driving signal. In this example, the charge pump in the microcontroller circuit charges a capacitor according to a charging signal. The voltage of the capacitor serves as an operating voltage. Then, an image driver in the microcontroller circuit drives the display panel according to the image driving signal. When the capacitor is charged, the charging time of the capacitor is recorded (that is, steps S811 to S813). When the charging time of the capacitor is greater than the charging standard value, a detection procedure of the program code is executed.

In some embodiments, step S812 further determines whether the count value is less than a maximum value. In this example, as long as the charging signal is not at the second level or the count value is not less than the maximum value, step S814 is executed. However, if the charging signal is at the second level and the count value is less than the maximum value, step S813 is executed.

Because the microcontroller circuit has a charge detection function, when the charging time of the capacitor C is too long, the microcontroller circuit executes a specific program to find out the cause of the abnormality, such as excessive load or short circuit on the pins of the display panel . Therefore, the tester can quickly learn the abnormality according to the report result of the microcontroller circuit.

The method of the present invention, or a specific type or part thereof, can exist in the form of code. The code can be stored in physical media, such as floppy disks, CDs, hard disks, or any other machine-readable (such as computer-readable) storage media, or not limited to external forms of computer program products. Among them, When the program code is loaded and executed by a machine, such as a computer, the machine becomes the microcontroller circuit used to participate in the present invention. The code can also be transmitted through some transmission media, such as wire or cable, optical fiber, or any transmission type. When the code is received, loaded and executed by a machine, such as a computer, the machine becomes used to participate in this Invention of the microcontroller circuit. When implemented in a general-purpose processing unit, the program code combined with the processing unit provides a unique device that operates similar to the application of a specific logic circuit.

Unless otherwise defined, all vocabulary (including technical and scientific vocabulary) herein belong to the general understanding of persons with ordinary knowledge in the technical field of the present invention. In addition, unless clearly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in the relevant technical field, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method of the embodiment of the present invention can be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100: display device

110: display panel

120: Microcontroller circuit

121: memory

122: Central Processing Unit

123, 500: image drive

124: Charge Pump

125, 200, 300: control circuit

210, 260, 310, 360: comparator

220, 320: counter

230, 330: edge detector

240, 340: storage circuit

250, 350: switch

305: Voltage divider circuit

411, 413: rising edge

412, 414: Falling Edge

50, 56: Numerical value

520: voltage generating circuit

510: COM/SEG digital signal generator

530: drive

S _I : image signal

PRC: Code

S _D : image drive signal

D ₀ ~D ₇ , INT ₀ : input and output pins

S _DT : Information

LCDPO_INT: interrupt signal

VLCD: Operating voltage

CMP_OUT: Charging signal

LCDCLK: clock signal

Vref ₁ , Vref ₂ : Reference voltage

CNT _T , CNT _N : count value

S _EN : enable signal

ST _C : Charging standard value

V _P , V1~V3: processing voltage

R ₁ ~R ₄ : resistance

COM ₀ ~ COM _M : Common signal

SEG ₀ ~SEG _N : Segment signal

S611~S613, S711~S714, S811~S813: steps

VSS: Ground voltage

Figure 1 is a schematic diagram of the display device of the present invention. Figure 2 is a possible embodiment of the control circuit of the present invention. Figure 3 is another possible embodiment of the control circuit of the present invention. Figure 4A is a schematic diagram of the charging signal and the interrupt signal of the present invention in the normal mode. Figure 4B is a schematic diagram of the charging signal and the interrupt signal of the present invention in the test mode. Figure 5 is a possible schematic diagram of the image driver of the present invention. Figure 6 is a schematic diagram of a possible flow of the control method of the present invention. FIG. 7 is a schematic diagram of a possible flow of the microcontroller circuit of the present invention operating in the test mode. FIG. 8 is a schematic diagram of a possible flow of the microcontroller circuit of the present invention operating in the normal mode.

100: display device

110: display panel

120: Microcontroller circuit

121: memory

122: Central Processing Unit

123: Image Drive

124: Charge Pump

125: control circuit

S _I : image signal

PRC: Code

S _D : image drive signal

D ₀ ~D ₇ , INT ₀ : input and output pins

S _DT : Information

LCDPO_INT: interrupt signal

VLCD: Operating voltage

CMP_OUT: Charging signal

LCDCLK: clock signal

Claims (10)

A microcontroller circuit is used to control a display panel and includes: A memory for storing a program code; A central processing unit that executes the program code to generate an image driving signal; An image driver, receiving an operating voltage, and driving the display panel according to the image driving signal; A charge pump charges a capacitor according to a charging signal, wherein the voltage of the capacitor is used as the operating voltage; and A control circuit generates the charging signal according to the operating voltage; Wherein, in a normal mode, the control circuit determines whether the charging time of the capacitor is greater than a charging standard value, and when the charging time of the capacitor is greater than the charging standard value, the CPU executes a detection procedure of the program code. For the microcontroller circuit described in item 1 of the scope of patent application, in a test mode, the control circuit records the charging time of the capacitor according to the charging signal to generate the charging standard value. The microcontroller circuit described in item 2 of the scope of patent application, wherein the control circuit includes: A first comparator compares a processing voltage and a reference voltage to generate the charging signal, wherein the processing voltage is related to the operating voltage. The microcontroller circuit described in item 3 of the scope of patent application, wherein the control circuit further includes: A voltage divider circuit processes the operating voltage to generate the processed voltage. The microcontroller circuit described in item 3 of the scope of patent application, wherein the control circuit includes: A counter, triggered by a first edge of the charging signal, to start adjusting a count value, and stop adjusting the count value according to a second edge of the charging signal; and An edge detector generates a consistent energy signal according to the second edge of the charging signal, Wherein, in the test mode, the central processing unit reads the count value according to the enable signal, and generates the charging standard value according to the count value. In the microcontroller circuit described in claim 5, the first edge is a rising edge, and the second edge is a falling edge. The microcontroller circuit described in item 5 of the scope of patent application, wherein the control circuit further includes: A storage circuit to store the charging standard value; A second comparator compares the count value with the charging standard value according to the enable signal, wherein in the normal mode, when the count value is greater than the charging standard value, the second comparator sends an interrupt signal to The central processing unit. Such as the microcontroller circuit described in item 7 of the scope of patent application, wherein the second comparator compares the count value with a preset value, and when the count value is greater than the preset value, the second comparator sends out the The interrupt signal, when the count value is greater than the charging standard value or the preset value, the second comparator sets the value of a flag to a specific value. For example, the microcontroller circuit described in item 8 of the scope of patent application, wherein when the central processing unit receives the interrupt signal, the central processing unit reads the value of the flag, and when the value of the flag is equal to a set value, The central processing unit executes the detection program. A control method is suitable for a microcontroller circuit, the microcontroller circuit is coupled to a display panel, and the control method includes: Execute a program code to generate an image drive signal; Charge a capacitor, where the voltage of the capacitor is used as an operating voltage; Providing the operating voltage to an image driver, wherein the image driver drives the display panel according to the image driving signal; and Determine whether the charging time of the capacitor is greater than a charging standard value; When the charging time of the capacitor is greater than the charging standard value, a detection procedure of the program code is executed.

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