200914857 九、發明說明： 【發明所屬之技術領域】 &本發明係關於一種應用於平面顯示裝置的測試系統， 尤私種應用於薄膜電晶體液晶顯示裝置（TFT-LCD )的後 段製程測試系統。 【先前技術】 TFT-LCD模組的製程一般分為3階段：前段陣列 (Array)製程、中段Cen製程以及後段模組（M〇duie)200914857 IX. Description of the invention: [Technical field to which the invention pertains] & The present invention relates to a test system applied to a flat display device, particularly for a back-end process test system for a thin film transistor liquid crystal display device (TFT-LCD) . [Prior Art] The process of the TFT-LCD module is generally divided into three stages: the front-end array (Array) process, the middle-stage Cen process, and the rear-end module (M〇duie).
〇 製程。請參考第1 ® ’為一後段模組製程之流程示意圖， 中後^又模組製程為將中段處理後之面板與例如背光模 組（Back light unit)、驅動電路（Driving Circuit)、 外框等多種零組件組裝的製帛’包含了不同的測試工序， 例如外引腳（〇uter Lead B〇nding，〇LB)測試、焊接 (S〇ldering)測試、組裝測試、點亮（Lighting)測試、 像素/(Pixel)測試以及老化（Aging)測試等。 »立後段模組製程令之老化測試，係將面板模組置入高溫 ^扰中（例如一高溫腔體），並輸入測試圖像（p^ter =Π 源至面板模組，以進行老化測試，使液晶面板在 间/皿環i兄下工作，以檢測液晶面板之顯示情況以及面 :陷U期發現其不良點，使液晶面板之穩定性以及可 罪度得以提升。此外液晶面板經老化測試後’將使 晶體安定化，在製程上，亦可將點亮測試的部分測試項目， 直接於老化測試中進行。 模二ΐ =，為習知老化測試系統21°與其待測液晶 :，、， 之連接不意圓。該待測液晶模組220包含—低雷 壓差動信號（L0W V〇itage Differential以即心）連乂面 230 (annector)以及一老化測試電源連接介面Μ。。丨該 老化測試系統21 0包含一電源供應器250以及一電腦26〇^ 200914857 該電源供應器250與誃去作 接’提供該待測液晶模:老測試電源連接介® 240電連 一信號輸出端270,該;試電源，·該電腦260包含 接介面230電連接ζ ^唬輪出端與該低電壓差動信號連 輸出一低電壓差動低電壓差動信號連接介面230 差動信號流驅動= =:11液晶模組22。，該低電壓 成老化測試。 、]液日日板，且220產生不同圖像，以完〇 Process. Please refer to the 1 ® 'flow diagram for the process of a back-end module. The middle and rear module processes are the panels processed by the middle section and, for example, the backlight unit (Backlight unit), the driving circuit (Driving Circuit), and the outer frame. The process of assembling a variety of components includes different test procedures, such as external lead (Berding Lead B〇nding, 〇 LB) test, welding (S〇ldering) test, assembly test, lighting test. , Pixel (Pixel) test and Aging test. »In the aging test of the rear module process, the panel module is placed in the high temperature disturbance (such as a high temperature cavity), and the test image is input (p^ter = Π source to the panel module for aging) Test, so that the liquid crystal panel works under the sibling of the liquid crystal panel to detect the display condition of the liquid crystal panel and the surface: the defect is found in the U phase, and the stability and the sin of the liquid crystal panel are improved. After the aging test, the crystal will be stabilized. In the process, part of the test items of the lighting test can also be directly performed in the aging test. The modulo ΐ = is the conventional aging test system 21 ° and its liquid crystal to be tested: The connection to the LCD module 220 includes a low-voltage differential signal (L0W V〇itage Differential), an interface 230 and an aging test power connection interface. The aging test system 207 includes a power supply 250 and a computer 26 〇 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 提供 提供 提供 提供 提供 提供 提供 提供 提供 老 老 老 老 老 老 老 老 老 老 老 老 老 老 老End 27 0, the test power supply, the computer 260 includes the interface 230 electrical connection ζ ^ 唬 wheel output and the low voltage differential signal output a low voltage differential low voltage differential signal connection interface 230 differential signal flow drive = =: 11 liquid crystal module 22, the low voltage is aging test.,] liquid day, and 220 produces different images to complete
便、的進步，製造商需要更加快速、方 、㈣性的測試方法，習知的老化測試方 需要：〉、具有下列缺點以及限制，而無法配合這樣的 疒节H &知的老化測試系統需產生-特定規格的顯示 #唬（例如LVI)S信號標準或m信號標準），因此，當進 灯測4之液晶模組需要使用特定的顯示信號規格時，該老 化測试系統需能依該液晶模組顯示規格的不同，提供不同 的顯不L ’上述情形大大增加了習知老化測試系統 雜度以及成本。 再者，每一該等特定規格的顯示信號（例如LVDS信號 標準或TTL信號標準），均需以不同規格的連接介面進行 連接，使得習知老化測試系統需具有每一配合該等特定規 格顯示信號的連接介面以及連接線，再次增加了系統的複 雜度以及成本》 ' ' 其次’基於每一組裝於液晶模組中之晶片（Ch i ρ )以 及積體電路（1C)均具有不同的異常耐受度（IC Margin)， 為了增加測試的信賴性，老化測試系統應針對液晶模組中 之晶片以及積體電路進行獨立的電源供應控制（power level control )，以測試每一晶片以及積體電路的可靠 度’以完成元件壓力（Component stress )測試。習知老 化測試系統，因其所供應電源須經穩壓穩流處理，即使習 200914857 知老化測試系統的輸入電源大於工 〇 之電源仍將被控制於工作電# ^ ^，輪出至各單70 無法於老化測試中完成作缺壓力測試 大限制了習知老化測試系統於 因此，一種無須輸入特定 壓力測試的老化測試機制及針;= = 的液晶顯示裝置，是十分有其需要的。4仃取佳化权计 【發明内容】 本發明的一目的係提供一 Γ"系統，該測試系統提供一===面：示裝置的測 唬，該測試信號可啟動該平面 以7/置一測試# 本發明的另-目的係提佴一上置以顯不測試用圖像。 測試系統，包含-測試電Ϊ;二用t平面顯示裝置的 :模組複數電源值，以板==測： 進仃元件壓力測試。 之不冋7C件 本發明的另一目的係提供一 測試系統，該測試系統提供一測試= 貝示褒置的 W同時完成老化測試以及元件壓力測^及複數電源值， U *裝置，該平面顯示】：：：：：；”試機制的平面顯 時脈控制器，該時脈控制哭連接介面以及- 測試信號連接介面接收啟動有7建測試模式，透過該 式。 &動唬以啟動該内建測試模 為實現上述目的，本發明趄 置的測試系統，包含： 八—種應用於平面顯示裝 連接，：收面顯示裝置之源極驅動單元電 動單元接收輸入電源並輸出一第—輪出電源至該源極驅 7 200914857 之閘極 二輸出 電連接 閘極驅 有一相 接，接 〇0 一 早7C、 動信號 本 了解。 Ο 壓與第-昇壓電路以及平面顯示裝置 :::疋電連接，接收該第一輪出電源並輸出一第 電源至該閘極驅動單元； m與該第一昇壓電路以及該第二昇壓電路 =收该第二輸出電源並輸出一第三輸出電源至該 以r第三輸出電源與該第二輪出電源相較具 υ $平面顯示裝置之之顯示控制單元電連 入電源，輸出一第四輸出電源至該源極驅動 閘極驅動單Α以及該顯示控制單it,並輸出—啟 至，顯示控制單元以啟動該内建測試模式。 案得藉由以下列圖示與詳細說明，俾得一更深入之 【實施方式】 請見第3圖所示’為本發明—較佳實施例所揭露之— 年應用於平面顯示裝置的測試系統3〇〇，包含一 電路31G (例如脈波調節器，pwM)、 Ο (^^^t„，charge purap curcuitf^；€32t〇 =單兀330、-整流n 34〇 ( Regulat〇r )單元以及一 二：350。該第一昇壓電路31"妾收一輸入電源， !出-第-輸出電源並用以驅動後續顯示面板之源極驅動 :二ΐ可以由該第一輸出電源輸出一比正常工作規格較 间的電壓至後續面板的源極驅動單元，以針對源極驅動單 :ί t:化或壓力測試。本實施例中’該第-輸出電源為 w.i μ原，該第一昇壓電路310係利用脈寬調變（Pulse :ldthsModulation)方式實現該第-輸出電源之調節，該 ::壓電路310產生一脈波寬度調變信號，並利用該脈 ;又調變^號以及另一其内部的特定波型輸出，產生複 數控制信號，以對該第_昇壓電$ 31G的工作週期進行回 200914857 授，制而實現該第一輪出電源之調節，以系統而論，該第 一昇壓電路31 0使得該測試系統3〇〇具有依據負載狀態對 輸出電源進行動態控制的能力。值得注意的是，該第一昇 壓電路31 0進行電源控制的方法不應以本實施例所揭露者 為限丄任何使該第一昇壓電路31 0得以進行該第一輸出電 源調節的方法，均可替代於該苐一昇壓電路31 〇中實施。 該第二昇壓電路320與該第一昇麼電路31〇電連接，接收 該，一輸出電源’可依據需要利用變壓器或電容以及電感 等幵壓與濾波裝置，將輸入之該第一輸出電源轉換為一第 ，輸出電源並用以驅動後續平面顯示裝置之閘極驅動單 =，並也可以由該第二輸出電源輸出一比正常工作規格較 焉的電壓至後續面㈣閘極驅動單元，以㈣問極驅動單 疋進行老化或壓力測試。本實施射，該第二輸出電源為 一類比電源’該第二昇壓f路32〇包含複數二極體（圖式 未繪出）’該第二昇壓電路32〇接收該第一輸出電源，並 利用該些二極體間之切換（s w i t c h丨n g )動作’以產生該第 二輸出電源，但亦不應以此為限，任何足以對該第一輸出 電源進行昇壓錢波以輸出電壓值較高之該第二輸出電源 ^方法，均可替代於該第二昇壓電路320中實施。該延遲 :路330與該第二昇壓電路32〇電連接，#收該第二昇壓 電，320的輪出產生_第三輸出電源，經由該延遲電路咖 亥第三輸出電源之信號時脈與該第二輸出電源相 “ η’本實施例中’該第三輸出電源為-類比 1三輸出電源之信號時脈與該第二輸出電源相較 ^有一延遲相位差。第二、第三輸出電源分別為Vgi、vgh， 極，單元輸出至晝素TFT(圖示未缘出)的控制 ;TFT i舍：的開'"FT的閘極收到Vg卜則該開 二：則該畫素的就不會接收由源極驅動器傳 术的〜像。fL说，反之，甚 圭去沾Μ ΤΡτ 右一畫素的開關TFT的閘極收到 200914857 J值炎:亥開關TFT開啟，則該畫素的就會接收由源極驅動 影像訊號。若後續的顯示面板所需的Vgl和Vgh 二m立差，則延遲電路33G不—定要存在於此測試 有延俨沐f者說’測試系統輪出的Vgb Vgh間並不-定要 有延遲相位的存在。 電源^ 34G 輪入電源並提供一第四輸出 由一、電示裝置之時脈控制器’該第四輸出電源並經 測試模式，太眘以產生一測試啟動信號以啟動該顯示裝置之 而以第：輸出電m ’該第四輸出電源係為-數位電源’ -丄=電阻36°以產生啟動信號之原因在於 續時又控制器的控制信號所需電壓較低。如果後 ===:格容許，亦可不設置電阻，而直接 分別與該第一昇堡雷拉Ή n 5 _ H測試介面350 電路單元33() 電路310、該第二昇壓電路320、該延遲 =流器340電連接，接收該第-輸 Ο 電源以及該測試啟動疒梦亥第二輪出電源、該第四輸出 測試系請之輸由；面350係用以整合本 該等輸出電源以及料測“ ® 35G的使用，使得 測裝置。測試介面35() ^ 方便並且可#地供給予待 連接之裝置。 可以疋探針、插座等利於電性連性 統的Si:與：：：：顯示模組的連接，說明該測試系 顯示模組的連接測圖，為該測試系統30〇與一平面 平面顯示模組400 圖，包含該測試系統300以及一 41〇、-顯示控制單面顯示模組400包含一顯示面板 驅動單元440,顯〇、一閘極驅動單元"Ο、一源極 及-正常制單元420還包含一第二測試介面 450輸入的電源不:=="φ 47〇。由第二測試介面 、、-二過穩壓器，因此可由外界輸入不同 10 200914857 的驅動電壓，以驅動閘極驅動單元430、源極驅動器單元 4W、時序控制單元42〇等電路。其中該顯示面板41〇分別 與遠閘極驅動單元430以及該源極驅動單元440電連接。 該顯示控制單元420分別與該閘極驅動單元43〇以及該源 極驅動單元440之輸入端電連接。該閘極驅動單元43〇之 複數輸出端與該顯示面板41〇中複數子像素（subpixei) , 的閘極端分別電連接。該源極驅動單元440之複數輸出端 與=顯示面板41〇中複數子像素（subPixel)中TFT的源 極如刀別電連接。該第二測試介面4 5 〇與該顯示控制單元 f ) 420相連接，該顯示控制單元420再與該閘極驅動單元43〇 以及該源極驅動單元440電連接，以提供該平面顯示模組 400所需測試信號以及電源。 該平面顯示模組的操作原理如下：該顯示控制單元42〇 接收輸入的彳5號，轉換為驅動該顯示面板41 〇所需之閘極 控制信號，以做為該閘極驅動單元43〇之輸入，以及源極 ，制仏號，以為該源極驅動單元44〇之輸入。該閘極驅動 單π 430利用閘極控制信號產生子像素控制信號，用以分 =控制該顯示面板410中複數子像素（subpixel)的閘極 端。該源極驅動單元440利用源極控制信號產生子像素源 ί'/ 極控制信號，用以分別控制該顯示面板41 〇中複數子像素 (subpixel)的源極端。需注意的是，任何可利用主動驅 動方式進行驅動的平面顯示模組均可利用本發明所揭露之 裝置以及方法進行測試，例如薄膜電晶體液晶顯示裝置 (TFT-LCD)、低溫多晶矽液晶顯示裝置（LTps_LCD)、超 扭矩液晶顯示裝置（SUper Twisted Nematic-LCD) '有機 發光二極體顯示裝置（〇LED )均應視為已為本發明所揭露， 但亦不以此為限。 本實施例中’該顯示控制單元42〇包含一時脈控制器 421 (Timing controller，Tc on)及一記憶裝置 422，該 11 200914857 ，制器421具有一内建測 儲存測試用圖像，藉由—輪入信=、式，記憶元件422 該顯示控制單元輪出存於記憔晋"蜊試圖像模式後， 該顯示面板410上，該内建測試圖像模圖像至 先權（priority )，亦即咳平 、式具有最尚執行優 信號後將立即執行測試圖^式二，400於接收啟動 體電路均需以客製方式訂製，'故=二=應用積 設計’應注意的是，只要今雜_ ^不同區求進行變更 測試圖像模式，且該測試°圖像：：具有-内建 〇 動，即可利用該測試系統號啟 記憶裝置422獨立於時脈控制器421之 ；二：， 時脈控制器中。 -亦了内建於 欲使用該測試系 '統300進行測試時 測試介面35G與該第-測#介而φ ± 糟亥第— 黛-松中雷货電連接’分別傳送該 第輸出電源至该源極驅動單元44〇 ;該第二輸出電源以 及第三輸出電源至該閘極驅動單& 43();該第四輸' 至該顯示控制單元420;該測試啟動信號啟動時脈控制= 421之測試圖像模式。利用上述電源供應方法，該測試系 Ο 統300可直接供應電源予該顯示面板4〇〇，使得該測試系 統300可分別針對該顯示控制單元42〇、該閘極驅動單元 430以及該源極驅動單元440不同的元件壓力標準進行測 試，換言之，該測試系統300可分別調整該等輸出電源， 以測試該等元件對異常電源狀況的耐受度。 值得一提的是，本發明中，該延遲電路3 3 〇係針對特 定系統的規格而使用，該測試系統300在應用於不需要延 遲信號進行工作位準設定的系統時，可移除該延遲電路 330。該第二昇壓電路320與該第一昇壓電路310亦可整合 為一具有動態電源調節能力之昇壓裝置。前述之數位電源 僅具有諸如高（Hi gh )、低（Low )位準之電位，類比電源 12 200914857 則具由時軸上連續性信號變化的能力，且類比電源通常比 數位電源具有較高之輸出電壓。 本發明藉由一測試啟動信號進行一具有内建測試模式 之平面顯示裝置之測試，輸入該平面顯示裳置之測試電源 可依需要動態縣’以#對該平面顯示裝置之不同元件進 行元件壓力測試，並可依需要提供一延遲電源以匹配該平 面顯不裝置中特定兀件的靈要益* M n 忏旳耑要前述測試電源以及信號的 過一連接介面完成，該連接介面可增加電源以及 #號傳遞過程的便利以及可靠度。本發明亦揭露一種平面 顯不裝置，其顯示控制單元中具有一内建測試圖像模式， 以於接收一測試啟動信號後啟動測試模式。 本：：二佳具體實施例的前述說明係用於示範及說明 之I二生：二：徹底或使本發明限於該精確形式或已揭示 之靶例性具體實施例，因此，先前說明 限制性。顯然許多修正及變化對於熟習此項技術^士將是 很明顯的。具體實施例之選擇及描述 明的原理及其實際應用之最佳模式，從而允Advances in advancement, manufacturers need more rapid, square, (four) test methods, the conventional aging testers need to: 〉, have the following shortcomings and limitations, and can not match such 疒 H & aging test system It is necessary to generate a specific specification display #唬 (for example, LVI) S signal standard or m signal standard). Therefore, when the liquid crystal module of the light measurement 4 needs to use a specific display signal specification, the aging test system needs to be able to The LCD module displays different specifications and provides different display. The above situation greatly increases the complexity and cost of the conventional aging test system. Furthermore, each of the display signals of the specific specifications (for example, the LVDS signal standard or the TTL signal standard) are connected by different connection interfaces, so that the conventional aging test system needs to have each of the specific specifications displayed. The connection interface of the signal and the connection line again increase the complexity and cost of the system. Secondly, each wafer (Ch i ρ ) and integrated circuit (1C) assembled in the liquid crystal module have different anomalies. Tolerance (IC Margin), in order to increase the reliability of the test, the burn-in test system should perform independent power level control for the wafers and integrated circuits in the liquid crystal module to test each wafer and integrated body. The reliability of the circuit 'to complete the component stress test. The conventional aging test system, because the power supply it supplies must be stabilized and regulated, even if the input power of the 200914857 aging test system is greater than the power of the work, it will be controlled to the working power # ^ ^, turn to each order 70 It is impossible to complete the stress test in the aging test. The conventional aging test system is limited. Therefore, an aging test mechanism and a needle without a specific pressure test are required; the liquid crystal display device of == is very desirable. 4 佳 佳 佳 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 A test # Another object of the present invention is to provide an image for display without being tested. Test system, including - test power; two with t-plane display device: module complex power supply value, with board == measurement: inlet and component pressure test. A further object of the present invention is to provide a test system that provides a test = a display of the aging test and a component pressure test and a complex power supply value, U * device, the plane Display]:::::;" The test mechanism's flat display clock controller, the clock control crying connection interface and - test signal connection interface receive start has 7 built test mode, through this type. & The built-in test module is used for the above purposes, and the test system of the present invention comprises: eight types of flat display connection, the source drive unit of the receiving display device receives the input power and outputs a first- Turn the power supply to the source drive 7 200914857 gate 2 output electrical connection gate drive has a connection, connect 0 early 7C, the dynamic signal is understood. Ο Pressure and the first boost circuit and the flat display device::疋 electrically connecting, receiving the first round of power and outputting a first power to the gate driving unit; m and the first boosting circuit and the second boosting circuit=receiving the second output power And outputting a third output power to the second output power source and the second wheel output power source, wherein the display control unit of the flat display device is electrically connected to the power source, and outputting a fourth output power source to the source drive The gate drive unit and the display control unit it, and output-start, display the control unit to start the built-in test mode. The case is further explained by the following illustration and detailed description. Please refer to FIG. 3, which is a test system for a flat display device, which is disclosed in the preferred embodiment of the present invention, and includes a circuit 31G (eg, pulse wave regulator, pwM), Ο ( ^^^t„,charge purap curcuitf^; €32t〇=single 330, rectification n 34〇 (Regulat〇r) unit and one two: 350. The first boost circuit 31" , the output-output power source is used to drive the source driving of the subsequent display panel: the second output power source can output a voltage higher than the normal working specification to the source driving unit of the subsequent panel to target the source Extreme drive single: ί t: chemical or stress test. In the embodiment, the first output circuit is a Wi μ original, and the first boost circuit 310 adjusts the first output power by using a Pulse Width Modulation (Pulse: ldths Modulation) method. Generating a pulse width modulation signal and using the pulse; and adjusting the ^ and another internal specific waveform output to generate a complex control signal to return the duty cycle of the first boost current $31G In 200914857, the adjustment of the first round of power supply is implemented, and in the system, the first boosting circuit 31 0 enables the test system 3 to have the ability to dynamically control the output power according to the load state. It should be noted that the method for performing power control by the first boosting circuit 31 0 should not be limited to any of the first boosting circuit 31 0 to perform the first output power adjustment. The method can be implemented instead of the first boost circuit 31. The second boosting circuit 320 is electrically connected to the first boosting circuit 31, and receives an output power supply. The first output can be input by using a transformer or a capacitor and an inductor, etc., as needed. The power source is converted into a first, output power source for driving the gate driving device of the subsequent planar display device, and the second output power source can also output a voltage that is higher than the normal working specification to the subsequent surface (four) gate driving unit. Aging or stress testing is performed by (4) asking the pole drive unit. In the present embodiment, the second output power source is an analog power supply. The second boosting path 32 〇 includes a plurality of diodes (not shown). The second boosting circuit 32 receives the first Outputting a power supply and utilizing the switching between the two diodes to generate the second output power, but not limited thereto, any sufficient to boost the first output power The second output power source method having a higher output voltage value can be implemented instead of the second booster circuit 320. The delay: the path 330 is electrically connected to the second boosting circuit 32, the second boosting power is generated, and the rounding of 320 generates a third output power, and the third output power signal is passed through the delay circuit. The clock and the second output power phase "n" in the present embodiment, the third output power is - analog 1 three output power signal clock and the second output power has a delay phase difference. The third output power supply is Vgi, vgh, and pole, and the unit outputs to the control of the pixel TFT (the picture is not shown); the gate of the TFT's open "FT receives the Vg. Then the pixel will not receive the ~ image transmitted by the source driver. fL said, on the contrary, more than the Μ ΤΡ τ The right pixel of the switching TFT's gate received 200914857 J value inflammation: Hai switch TFT When it is turned on, the pixel will receive the image signal driven by the source. If the Vgl and Vgh required by the subsequent display panel are two millimeters apart, the delay circuit 33G does not have to exist in this test. It is said that 'the Vgb Vgh that is out of the test system does not have a delay phase. Power ^ 34G turns into the power supply and Providing a fourth output by the clock controller of the electric display device, the fourth output power source and passing the test mode, being too cautious to generate a test start signal to activate the display device to: output the power m ' The fourth output power supply is a digital power supply '-丄=resistance 36° to generate the start signal. The reason is that the voltage required by the controller's control signal is low at the same time. If the post ===: cell allows, the resistor is not set. And directly connected to the first riser Raleigh n 5 _ H test interface 350 circuit unit 33 () circuit 310, the second boost circuit 320, the delay = stream 340, respectively, to receive the first - The power supply and the test start the second round of power supply of the 疒梦海, the fourth output test system is requested to be exported; the surface 350 is used to integrate the output power supply and the material measurement "® 35G use, make the measuring device . The test interface 35() ^ is convenient and can be used to give the device to be connected. It can be used to connect the probes, sockets, etc. to the connection of the Si::::: display module, indicating the connection diagram of the test system display module, for the test system 30〇 and a plane plane display The module 400 includes the test system 300 and a 41 〇, - display control single-sided display module 400 includes a display panel driving unit 440, a display, a gate drive unit " Ο, a source and - normal The unit 420 further includes a power supply input by the second test interface 450: =="φ 47〇. The second test interface, the -2 over-voltage regulator, can therefore input different driving voltages of 200914857 from the outside to drive the gate driving unit 430, the source driver unit 4W, the timing control unit 42 and the like. The display panel 41 is electrically connected to the remote gate driving unit 430 and the source driving unit 440, respectively. The display control unit 420 is electrically connected to the gate drive unit 43A and the input terminal of the source drive unit 440, respectively. The plurality of output terminals of the gate driving unit 43 are electrically connected to the gate terminals of the plurality of sub-pixels (subpixei) of the display panel 41. The complex output of the source driving unit 440 is electrically connected to the source of the TFT in the plurality of sub-pixels (subPixel) in the display panel 41. The second test interface is connected to the display control unit f 420. The display control unit 420 is further electrically connected to the gate driving unit 43 and the source driving unit 440 to provide the planar display module. 400 required test signals and power. The operating principle of the flat display module is as follows: the display control unit 42 receives the input 彳5 number and converts it into a gate control signal required to drive the display panel 41 to serve as the gate driving unit 43. The input, as well as the source, and the nickname, are the inputs of the source drive unit 44〇. The gate driver single π 430 generates a sub-pixel control signal by using a gate control signal for controlling the gate terminal of the plurality of subpixels in the display panel 410. The source driving unit 440 generates a sub-pixel source ''/pole control signal by using the source control signal for respectively controlling the source terminals of the plurality of subpixels in the display panel 41. It should be noted that any flat display module that can be driven by the active driving method can be tested by using the device and method disclosed in the present invention, such as a thin film transistor liquid crystal display device (TFT-LCD), a low temperature polycrystalline germanium liquid crystal display device. (LTps_LCD), Super Torque Liquid Crystal Display (SUper Twisted Nematic-LCD) 'Organic LED display device (〇LED) should be considered as disclosed in the present invention, but not limited thereto. In the present embodiment, the display control unit 42 includes a clock controller 421 (Timing controller, Tc on) and a memory device 422. The device 1121. The controller 421 has a built-in test storage test image. - the round-up letter =, the type, the memory element 422, after the display control unit is rotated in the record mode, the display panel 410, the built-in test image mode image to the priority (priority ), that is, the cough level, the type with the best execution of the excellent signal will immediately execute the test chart ^2, 400 in the receiving starter circuit must be customized in a custom way, 'so = two = application product design' should pay attention In the present, as long as the different areas are required to change the test image mode, and the test image:: has - built-in shaking, the test system number can be used to open the memory device 422 independently of the clock controller. 421; 2:, in the clock controller. - Also built in the test system 'System 300 to test the test interface 35G and the first - test #介 and φ ± 亥海第-黛-松中雷货电连接' respectively transmit the output power to the a source driving unit 44〇; the second output power source and the third output power source to the gate driving unit & 43 (); the fourth output 'to the display control unit 420; the test start signal starts clock control = 421 test image mode. With the power supply method described above, the test system 300 can directly supply power to the display panel 4, such that the test system 300 can be respectively directed to the display control unit 42, the gate drive unit 430, and the source drive. Unit 440 tests different component pressure standards, in other words, test system 300 can separately adjust the output power sources to test the tolerance of such components to abnormal power conditions. It is worth mentioning that, in the present invention, the delay circuit 3 3 is used for the specification of a specific system, and the test system 300 can remove the delay when applied to a system that does not require a delay signal for work level setting. Circuit 330. The second boosting circuit 320 and the first boosting circuit 310 can also be integrated into a boosting device having dynamic power regulating capability. The aforementioned digital power supply only has potentials such as high (Hi gh ) and low (Low) levels, and the analog power supply 12 200914857 has the ability to change the continuity signal on the time axis, and the analog power supply is usually higher than the digital power supply. The output voltage. The invention performs a test of a flat display device with a built-in test mode by using a test start signal, and inputting the test power source of the flat display display can dynamically perform component pressure on different components of the flat display device according to the need Testing, and providing a delay power supply as needed to match the specific components of the flat display device. * n The test power supply and the signal are connected through a connection interface, the connection interface can increase the power supply. And the convenience and reliability of the ## delivery process. The invention also discloses a flat display device having a built-in test image mode in the display control unit for starting the test mode after receiving a test enable signal. The foregoing description of the two preferred embodiments is for the purposes of illustration and description. FIG. 2: The invention is limited or limited to the precise form or the disclosed specific embodiments. . Obviously many corrections and changes will be apparent to those skilled in the art. The selection and description of the specific embodiments and the best mode of the practical application, thereby allowing
術人士理解用於各種具體實施例之本發明，且I ίThe skilled person understands the invention for use in various embodiments and I ί
J 特定使用或所涵蓋實作之各種修 八有、D於 由在此所附之申锖專利顧二〗*發明意於使其範疇 了〈甲响專利靶圍及其等同者定義，其中哈此s «兒明’否則所有請求項均包含其最廣泛之入理圍 瞭解到’ V由熟習此項技術者對於具 = / 而不脫離由以下申請專利範圍所太，改變’ 管-件或用於公眾，* 此外，本揭露書的摘要係提：用地提及。 圍的範疇或意涵。 、解釋或限制申請專利範 13 200914857 【圖式簡單說明】 第1圖為一後段模I且製程之流程示意圖。 第2圖為習知老化測試系統與其待測液晶模組之連接示意 第3圖為本發明一較佳實施例所揭露之一種應用於平面顯 示裝置的測試系統。 第4圖為測試系統與平面顯示模組的連接測試示意圖。J. The specific use or cover of the various implementations of the repairs, D from the application of the patents attached hereby, the invention of the invention is intended to make it a category of "A ring of patent target and its equivalent definition," This s «Ke Ming' otherwise all claims are included in their most extensive knowledge of the understanding of 'V by familiarity with this technology for the person with = / without leaving the scope of the following patent application too, change 'tube-piece or For the public, * In addition, the abstract of this disclosure is mentioned: land use mentioned. The scope or meaning of the surrounding. Interpret or limit the application for patents. 13 200914857 [Simple description of the diagram] Figure 1 is a schematic diagram of the process of a post-module I and the process. FIG. 2 is a schematic diagram showing the connection between a conventional aging test system and a liquid crystal module to be tested. FIG. 3 is a test system applied to a flat display device according to a preferred embodiment of the present invention. Figure 4 is a schematic diagram of the connection test between the test system and the flat display module.
【主要元件符號說明】 21 〇老化測試系統 230低電壓差動信號連接介面 240老化測試電源連接介面 2 5 0電源供應器[Main component symbol description] 21 〇 aging test system 230 low voltage differential signal connection interface 240 aging test power connection interface 2 5 0 power supply
220待測液晶模組 2 6 0電腦 300測試系統 320第二昇壓裝置 340整流器單元 4〇〇平面顯示模組 420顯示控制單元 422記憶裝置 440 源極驅動單元 2 7 0 號輸出端 310第一昇壓裝置 330延遲電路單元 3 5 0測試介面 41 0顯示面板 4 21時脈控制器 4 3 0閘極，驅動單元 450第二測試介面 470正常工作模式介面 14220 LCD module to be tested 260 computer 300 test system 320 second boosting device 340 rectifier unit 4 〇〇 flat display module 420 display control unit 422 memory device 440 source drive unit 2 7 0 output terminal 310 first Boost device 330 delay circuit unit 305 test interface 41 0 display panel 4 21 clock controller 4 3 0 gate, drive unit 450 second test interface 470 normal working mode interface 14