TWI798035B - Trimming circuit, LED display driver chip and LED display device - Google Patents

Abstract

The invention mainly discloses a trimming circuit, which is applied in an LED display driving chip, and includes a bias circuit, a trimming unit and a readout circuit. According to the design of the present invention, an enable signal is used to control the bias circuit to provide at least one start-up voltage to the readout circuit, thereby driving the readout circuit to read N trimming bits from the trimming unit, thereby transmitting a The trimming code is used to trim the output current of the LED display driver chip. In particular, under the control of the enabling signal, the trimming circuit of the present invention only works for a very short time after the chip is powered on, and then enters the off state, thus not increasing the power consumption of the LED display driver chip.

Description

Trimming circuit, LED display driver chip and LED display device

The invention relates to the field of LED display technology, especially a trimming circuit applied to LED display driving chips.

Light-emitting diodes (Light-emitting diodes, LEDs) have many advantages such as small size, light weight, long service life, and high luminous efficiency, and have been widely used in lighting devices and display devices. The LED display device is a self-illuminating flat-panel display device, which has the advantages of bright colors, wide dynamic range, high brightness, long life, and high reliability. The LED display device with a large screen has been widely used in large squares, commercial advertisements, Sports venues, information dissemination, news releases, stock exchange venues, as a public display medium.

FIG. 1 shows a structure diagram of a conventional LED display device. As shown in FIG. 1 , a conventional LED display device 1a includes: an LED display panel 11a, a display control unit 14a and at least one LED display driver chip 13a. Electronic engineers who are familiar with the design and manufacture of LED displays must know that the display control unit 14a controls each of the LED display driver chips 13a to simultaneously light up the entire display area of the LED display panel 11a according to different image display requirements, or only light up the LEDs. at least one display area of the display panel 11 .

The LED display driver chip 13a shown in FIG. 1 is usually a constant current driver chip and therefore includes a constant current generating circuit. It is worth noting that, with the improvement of display effect requirements, the size of the LED sub-pixels of the LED display panel 11a is continuously reduced, so that the accuracy requirements of the output current IOUT are also continuously improved. However, the process deviation of the semiconductor chip manufacturing and packaging of the LED display driver chip 13a will cause the parameter deviation of the semiconductor elements that constitute the LED display driver chip 13a, causing the test value of the output current of the adjacent LED display driver chip 13a to be different from that of The design value is too different. Therefore, engineers usually add a trimming circuit 131a inside the LED display driver chip 13a, so that the output current can be trimmed in the final test (Final test, FT) stage.

FIG. 2 is a block diagram of the trimming circuit 131a shown in FIG. 1 . As shown in FIG. 2 and FIG. 1, the conventional trimming circuit 131a included in the LED display driver chip 13a mainly includes: a trimming unit 1311a and a readout circuit 1312a, wherein the trimming unit 1311a includes N Trim bit cell 131Ta, and the readout circuit 1312a includes N readout units 131Ra.

It should be understood that as the number of channels of the LED display driver chip 13a increases, the numbers of the trimming bit cells 131Ta and the numbers of the readout units 131Ra must also correspondingly increase. However, the increase in the number of the trimming bit cells 131Ta and the readout units 131Ra also increases the power consumption of the LED display driver chip 13a.

From the above description, it can be known that a novel low power consumption trimming circuit is urgently needed in this field.

The main purpose of the present invention is to provide a trimming circuit, which is applied in an LED display driver chip, and includes a bias circuit, a trimming unit and a readout circuit. According to the design of the present invention, an enable signal is used to control the bias circuit to provide at least one start-up voltage to the readout circuit, thereby driving the readout circuit to read N trimming bits from the trimming unit, thereby transmitting a The trimming code is used to trim the output current of the LED display driver chip. In particular, under the control of the enabling signal, the trimming circuit of the present invention only works for a very short time after the chip is powered on, and then enters the off state, thus not increasing the power consumption of the LED display driver chip.

To achieve the above object, the present invention proposes an embodiment of the trimming circuit, which includes: a trimming unit coupled to an input trimming code, and includes N trimming bit cells, where N is a positive integer; The readout circuit has N readout units respectively coupled to the N trimming bit cells; and a bias circuit coupled to the N readout units and an enable signal; wherein, in a trimming stage, the bias circuit generates at least one startup voltage according to the control of the enable signal and sends it to the N readout units, so that the readout circuit reads out N trimming bits, thereby generating an output trimming code ; Wherein, in a non-trimming phase, the bias circuit stops generating the start-up voltage according to the control of the enable signal, so that the readout circuit stops operating.

In one embodiment, the bias circuit includes: A first MOSFET element has a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to a current source, the source terminal is coupled to a first fuse element, and the gate terminal is coupled to the drain terminal to form A first common contact point; a second MOSFET element having a gate terminal, a drain terminal and a source terminal, the gate terminal is coupled to the first common contact point, and the source terminal is coupled to a second fuse element; a third MOSFET element having a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to the first common point, the source terminal is coupled to a ground terminal, and the gate terminal is connected through a The first inverter is coupled to the enable signal; a fourth MOSFET element has a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to an operating voltage, and the gate terminal is coupled to the drain terminal forming a second common point; wherein the drain end of the second MOSFET element is coupled to the second common point; and a fifth MOSFET element having a gate end, a drain end and a source terminal, the source terminal is coupled to the operating voltage, the drain terminal is coupled to the second common point, and the gate terminal is coupled to the enable signal; wherein, the readout unit is coupled to the fourth The gate terminal of the MOSFET element receives one startup voltage; wherein, the readout unit is coupled to the first common point so as to receive another startup voltage.

In one embodiment, the trimming bit cell includes: a sixth MOSFET element having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the drain terminal is coupled to a a third fuse element, and the gate terminal is coupled to the input trimming code.

In one embodiment, the readout unit includes: a seventh MOSFET element having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the the gate terminal of the fourth MOSFET element; and an eighth MOSFET element having a gate terminal, a drain terminal and a source terminal coupled to the drain terminal of the seventh MOSFET element to form a third A common point, the source end is coupled to the third fuse element, and the gate end is coupled to the first common point.

In one embodiment, the trimming circuit of the present invention further includes a latch unit, which includes N latches respectively coupled to the N readout units included in the readout circuit for respectively A one-bit latch operation is performed on the N trimming bits read out by the readout circuit.

Moreover, the present invention also proposes an LED display driver chip, which is characterized in that the LED display driver chip includes a trimming circuit, and the trimming circuit includes: a trimming unit coupled to an input trimming code, and includes N trimming bit cells, N is a positive integer; a readout circuit, with N readout units respectively coupled to the N trimming bit cells; and a bias circuit, coupled to the N readout cells output unit and an enable signal; wherein, in a trimming stage, the bias circuit generates at least one start-up voltage according to the control of the enable signal and sends it to the N readout units, so that the readout circuit can read N trimming bits, so as to generate an output trimming code; wherein, in a non-trimming stage, the bias circuit stops generating the start-up voltage according to the control of the enable signal, so that the readout circuit stops operating .

In one embodiment, the bias circuit includes: a first MOSFET element having a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to a current source, and the source terminal is coupled to a first fuse element , and the gate terminal is coupled to the drain terminal to form a first common contact point; a second MOSFET element has a gate terminal, a drain terminal and a source terminal, and the gate terminal is coupled to the first common contact point , and the source terminal is coupled to a second fuse element; a third MOSFET element has a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to the first common point, and the source terminal is coupled to connected to a ground terminal, and the gate terminal is coupled to the enable signal through a first inverter; a fourth MOSFET element has a gate terminal, a drain terminal and a source terminal, and the source terminal is coupled to a Working voltage, and the gate end is coupled to the drain end to form a second common point; wherein, the drain end of the second MOSFET element is coupled to the second common point; and A fifth MOSFET element has a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, the drain terminal is coupled to the second common point, and the gate terminal is coupled to the enabling signal; wherein, the readout unit is coupled to the gate terminal of the fourth MOSFET element, thereby receiving a start voltage; wherein, the readout unit is coupled to the first common point, A further said starting voltage is thus received.

In one embodiment, the trimming bit cell includes: a sixth MOSFET element having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the drain terminal is coupled to a a third fuse element, and the gate terminal is coupled to the input trimming code.

In one embodiment, the readout unit includes: a seventh MOSFET element having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the the gate terminal of the fourth MOSFET element; and an eighth MOSFET element having a gate terminal, a drain terminal and a source terminal coupled to the drain terminal of the seventh MOSFET element to form a third A common point, the source end is coupled to the third fuse element, and the gate end is coupled to the first common point.

In one embodiment, the LED display driver chip of the present invention further includes a latch unit, which includes N latches respectively coupled to the N readout units included in the readout circuit for A one-bit latch operation is performed on the N trimming bits read out by the readout circuit respectively.

Moreover, the present invention also proposes an LED display device, which includes: an LED display panel, a display control unit, and at least one LED display driver chip of the present invention as described above.

In a feasible embodiment, the LED display panel includes X×Y LED elements, where X and Y are both positive integers, and the LED elements are selected from conventional LED elements, quantum dot LED elements, and perovskite LED elements. Any one of the group consisting of components, Mirco-LED components and Mini-LED components.

1a: LED display device

11a: LED display panel

13a: LED display driver chip

14a: Display control unit

131a: trimming circuit

1311a: trimming unit

131Ta: trim bit cell

1312a: readout circuit

131Ra: readout unit

1: LED display device

11: LED display panel

13: LED display driver chip

14: Display control unit

131: Trimming circuit

1311: Trimming unit

131T: Trim bit cell

1312: readout circuit

131R: readout unit

1313: bias circuit

1314: Latch unit

131L: latch

131I: current source

13N1: the first inverter

13N2: Second inverter

M1: the first MOSFET element

M2: Second MOSFET element

M3: Third MOSFET element

M4: Fourth MOSFET element

M5: Fifth MOSFET element

M6: Sixth MOSFET element

M7: Seventh MOSFET element

M8: Eighth MOSFET element

F1: The first fuse element

F2: Second fuse element

F3: The third fuse element

Fig. 1 is a structural diagram of a known LED display device; Fig. 2 is a block diagram of the trimming circuit shown in Fig. 1; Fig. 3 is a structural diagram of an LED display device of the present invention; Fig. 4 is a schematic diagram of the LED display device shown in Fig. 3 The block diagram of the trimming circuit; Figure 5 is a block diagram of a trimming bit cell shown in Figure 4, a readout unit and the bias circuit; and Figure 6 is a trimming bit shown in Figure 4 Cell, a readout unit, and the circuit topology of the bias circuit.

In order to enable your examiners to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are hereby attached.

FIG. 3 shows a structure diagram of an LED display device of the present invention. As shown in FIG. 3 , the LED display device 1 of the present invention includes: an LED display panel 11 , a display control unit 14 and at least one LED display driver chip 13 . In particular, the present invention adds a trimming circuit 131 to the LED display driver chip 13, and the trimming circuit 131 is used to trim the reference current generating unit included in the LED display driver chip 13 according to a trimming code. The generated reference current I0 realizes the trimming of the output current of a driving channel of the LED display driving chip 13 .

FIG. 4 is a block diagram of the trimming circuit 131 shown in FIG. 3 . As shown in Figure 4 and Figure 3, the trimming circuit 131 of the present invention included in the LED display driver chip 13 mainly includes: a trimming unit 1311, a readout circuit 1312, a bias circuit 1313, and a lock storage unit 1314. Wherein, the trimming unit 1311 is coupled to an input trimming code, and includes N trimming bit cells 131T, where N is a positive integer. Moreover, the readout circuit 1312 has N readout units 131R respectively coupled to the N trimming bit cells 131T. Further, according to the design of the present invention, the bias circuit 1313 is coupled to N readout units 131R and an enable signal EN. According to this design, in a trimming phase, the bias circuit 1313 generates a first start-up voltage VBP and a second start-up voltage VBN according to the control of the enable signal En and transmits them to the N readout units 131R, so that The readout circuit 1312 operates to read out N trimming bits, and then generates an output trimming code that is sent to a reference current generating unit of the LED display driver chip 13, from which Therefore, the purpose of adjusting the output current of the LED display driver chip 13 is realized. Moreover, in a non-trimming phase, the bias circuit 1313 stops generating the start-up voltage according to the control of the enable signal En, so that the readout circuit 1312 stops operating.

FIG. 5 is a block diagram of a trim bit cell 131T, a readout unit 131R and the bias circuit 1313 shown in FIG. 4 . Moreover, FIG. 6 is a circuit topology diagram of a trim bit cell 131T, a readout unit 131R and the bias circuit 1313 shown in FIG. 4 . In one embodiment, as shown in FIG. 5 and FIG. 6, the bias circuit 1313 mainly includes: a first MOSFET element M1, a second MOSFET element M2, a third MOSFET element M3, and a fourth MOSFET element M4 , and a fifth MOSFET element M5. Wherein, the first MOSFET element M1 has a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to a current source 131I, the source terminal is coupled to a first fuse element F1, and the gate terminal is coupled to The drain end forms a first common contact. On the other hand, the second MOSFET element M2 has a gate terminal, a drain terminal and a source terminal, the gate terminal is coupled to the first common point, and the source terminal is coupled to a second fuse element F2.

In more detail, the third MOSFET element M3 has a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to the first common point, the source terminal is coupled to a ground terminal, and the gate The terminal is coupled to the enable signal En through a first inverter 13N1. Moreover, the fourth MOSFET element M4 has a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to an operating voltage VDD, and the gate terminal is coupled to the drain terminal to form a second common point; wherein , the drain end of the second MOSFET element M2 is coupled to the second common point. As shown in FIG. 5 and FIG. 6, the fifth MOSFET element M5 has a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage VDD, and the drain terminal is coupled to the second common connection. point, and the gate terminal is coupled to the enable signal En. According to this circuit plan, the readout unit 131R is coupled to the gate terminal of the fourth MOSFET element M4 to receive a start-up voltage VBP. On the other hand, the readout unit 131 is coupled to the first common point, so as to receive another startup voltage VBN.

As shown in FIG. 5 and FIG. 6 , the trimming bit cell 131T includes a sixth MOSFET element M6 having a gate terminal, a drain terminal and a source terminal, wherein the source terminal is coupled to the operating voltage VDD, The drain terminal is coupled to a third fuse element F3, and the gate terminal is coupled to the input trimming code. In more detail, the readout unit 131R mainly includes: a seventh MOSFET element M7 and an eighth MOSFET element M8. As shown in FIG. 6, the seventh MOSFET element M7 has a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage VDD, and the gate terminal is coupled to the fourth MOSFET element M4. the gate terminal. Moreover, the eighth MOSFET element M8 has a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to the drain terminal of the seventh MOSFET element M7 to form a third common point, and the source terminal is coupled to connected to the third fuse element F3, and the gate terminal is coupled to the first common point.

Further, the latch unit 1314 includes N latches 131L respectively coupled to the N readout units 131R included in the readout circuit 1312 for reading out the N latches 131R included in the readout circuit 1312. The trim bit performs a bit latch operation. As shown in FIG. 6 , the latch 131L is coupled to the output end of the readout unit 131R through a second inverter 13N2 .

Therefore, in the case of having the trimming circuit 131 of the present invention, when the LED display driver chip 13 undergoes the final test (Final test, FT) before leaving the factory, if it is necessary to trim the LED display driver chip 13 processing, the level of the enable signal EN can be pulled high, so that the bias circuit 1313 generates the first start-up voltage VBP and the second start-up voltage VBN and transmits them to the readout circuit 1312, thereby starting the readout circuit 1312 run. At the same time, an input trim code is sent to the trim unit 1311, so that the trim unit 1311 writes a trim bit (that is, bit 1, bit 2) in the N trim bit cells 131T respectively. ,..., bit N). Next, the readout circuit reads 1312 the N trimming bits from the trimming unit 1311, and the N latches 131R of the latching unit 1314 perform one-bit locking according to a clock signal CLK respectively. Save operation. After the above operations are completed, the level of the enable signal EN is pulled down, so that the bias circuit 1313 stops generating the startup voltage, thereby stopping the operation of the readout circuit 1312 and ending the operation of the LED display driver chip 13. trim stage.

During normal use of the LED display driver chip 13 , after the chip is powered on, the N trimming bits (ie, a set of trimming codes) programmed into the trimming unit 1311 need to be read out. At this time, the enable signal EN is first pulled high, so that the bias circuit 1313 generates the first start-up voltage VBP and the second start-up voltage VBN and transmits them to the readout circuit 1312 to start the readout circuit 1312. run. The readout circuit reads out N described trimming bits from the trimming unit 1311 in 1312, and the latching unit The N latches 131L of the unit 1314 perform a one-bit latch operation according to a clock signal CLK. After the above operations are completed, the level of the enable signal EN is pulled down, so that the bias circuit 1313 stops generating the startup voltage, thereby stopping the operation of the readout circuit 1312 and ending the operation of the LED display driver chip 13. Modified code loading operation. In particular, under the control of the enable signal EN, the trimming circuit of the present invention only works for a very short time after the chip is powered on, and then enters the off state, so the power consumption of the LED display driver chip 13 will not be increased.

In this way, the above has completely and clearly described a trimming circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a trimming circuit, which is applied in an LED display driver chip, and includes a bias circuit, a trimming unit and a readout circuit. According to the design of the present invention, an enable signal is used to control the bias circuit to provide at least one start-up voltage to the readout circuit, thereby driving the readout circuit to read N trimming bits from the trimming unit, thereby transmitting a The trimming code is used to trim the output current of the LED display driver chip. In particular, under the control of the enabling signal, the trimming circuit of the present invention only works for a very short time after the chip is powered on, and then enters the off state, thus not increasing the power consumption of the LED display driver chip.

(2) The present invention also discloses an LED display device, which includes: an LED display panel, a display control unit, and at least one LED display driver chip of the present invention as described above. In a feasible embodiment, the LED display panel includes X×Y LED elements, where X and Y are both positive integers, and the LED elements are selected from conventional LED elements, quantum dot LED elements, and perovskite LED elements. Any one of the group consisting of components, Mirco-LED components and Mini-LED components.

It must be emphasized that what is disclosed in the above-mentioned case is a preferred embodiment, and all partial changes or modifications derived from the technical ideas of this case and easily deduced by those familiar with the technology are all inseparable from the patent of this case. category of rights.

To sum up, regardless of the purpose, means and efficacy of this case, it shows that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I implore your review committee to understand it clearly and grant a patent as soon as possible. Society is for the Most Prayer.

131: Trimming circuit

1311: Trimming unit

131T: Trim bit cell

1312: readout circuit

131R: readout unit

1313: bias circuit

1314: Latch unit

131L: latch

Claims (10)

A trimming circuit, comprising: a trimming unit, coupled to an input trimming code, and includes N trimming bit cells, where N is a positive integer; a readout circuit, with N readout units respectively coupled to N the trimming bit cells; and a bias circuit coupled to the N readout units and an enabling signal; wherein, in a trimming phase, the biasing circuit operates according to the control of the enabling signal Generate at least one startup voltage and send it to N readout units, so that the readout circuit reads out N trimming bits, thereby generating an output trimming code; wherein, in a non-modifying phase, the bias circuit According to the control of the enabling signal, the starting voltage is stopped to be generated, so that the readout circuit stops working. The trimming circuit as described in Claim 1, wherein the bias circuit includes: a first MOSFET element having a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to a current source, and the source terminal It is coupled to a first fuse element, and the gate terminal is coupled to the drain terminal to form a first common point; a second MOSFET element has a gate terminal, a drain terminal and a source terminal, and the gate terminal is coupled to connected to the first common point, and the source terminal is coupled to a second fuse element; a third MOSFET element has a gate terminal, a drain terminal and a source terminal, and the drain terminal is coupled to the first A common point, the source terminal is coupled to a ground terminal, and the gate terminal is coupled to the enable signal through a first inverter; a fourth MOSFET element has a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to an operating voltage, and the gate terminal is coupled to the drain terminal to form a second common point; wherein, the drain terminal of the second MOSFET element is coupled to the second common and a fifth MOSFET element having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, the drain terminal is coupled to the second common point, and the gate terminal is coupled to connected to the enable signal; wherein, the readout unit is coupled to the gate terminal of the fourth MOSFET element, thereby receiving a start-up voltage; Wherein, the readout unit is coupled to the first common point so as to receive another startup voltage. The trimming circuit according to claim 2, wherein the trimming bit cell includes: a sixth MOSFET element having a gate terminal, a drain terminal and a source terminal, and the source terminal is coupled to the operating voltage , the drain terminal is coupled to a third fuse element, and the gate terminal is coupled to the input trimming code. The trimming circuit according to claim 3, wherein the readout unit includes: a seventh MOSFET element having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and The gate terminal is coupled to the gate terminal of the fourth MOSFET element; and an eighth MOSFET element has a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to the seventh MOSFET element. The drain end thus forms a third common point, the source end is coupled to the third fuse element, and the gate end is coupled to the first common point. The trimming circuit as described in claim 4 further includes a latch unit, which includes N latches respectively coupled to the N readout units included in the readout circuit, for respectively reading the The N trimming bits read out by the output circuit perform a one-bit latch operation. An LED display driver chip is characterized in that it includes a trimming circuit, and the trimming circuit includes: a trimming unit coupled to an input trimming code, and includes N trimming bit cells, where N is a positive integer; A readout circuit, with N readout units respectively coupled to N said trimming bit cells; and a bias circuit, coupled to N said readout units and an enabling signal; wherein, in a trimming In the adjustment stage, the bias circuit generates at least one startup voltage according to the control of the enable signal and sends it to the N readout units, so that the readout circuit reads out N trimming bits, thereby generating an output trimming code; wherein, in a non-trimming phase, the bias circuit stops generating the start-up voltage according to the control of the enable signal, so that the readout circuit stops operating. The LED display driver chip as described in Claim 6, wherein the bias circuit includes: a first MOSFET element having a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to a current source, and the source The terminal is coupled to a first fuse element, and the gate terminal is coupled to the drain terminal to form a first common point; a second MOSFET component has a gate terminal, a drain terminal and a source terminal, and the gate terminal coupled to the first common point, and the source terminal is coupled to a second fuse element; a third MOSFET element has a gate terminal, a drain terminal and a source terminal, and the drain terminal is coupled to the first A common contact, the source terminal is coupled to a ground terminal, and the gate terminal is coupled to the enabling signal through a first inverter; a fourth MOSFET element has a gate terminal, a drain terminal and a A source terminal, the source terminal is coupled to an operating voltage, and the gate terminal is coupled to the drain terminal to form a second common point; wherein, the drain terminal of the second MOSFET element is coupled to the second common and a fifth MOSFET element having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, the drain terminal is coupled to the second common point, and the gate terminal coupled to the enabling signal; wherein the readout unit is coupled to the gate terminal of the fourth MOSFET element to receive a start voltage; wherein the readout unit is coupled to the first Common contact, thereby receiving another said start-up voltage. The LED display driver chip as described in Claim 7, wherein the trimming bit cell includes: a sixth MOSFET element having a gate terminal, a drain terminal and a source terminal, and the source terminal is coupled to the working voltage, the drain terminal is coupled to a third fuse element, and the gate terminal is coupled to the input trimming code. The LED display driver chip according to claim 8, wherein the readout unit includes: a seventh MOSFET element having a gate terminal, a drain terminal and a source terminal, the source terminal is coupled to the operating voltage, and the gate terminal is coupled to the gate terminal of the fourth MOSFET element; and a The eighth MOSFET element has a gate terminal, a drain terminal and a source terminal, the drain terminal is coupled to the drain terminal of the seventh MOSFET element to form a third common point, and the source terminal is coupled to the first A three-fuse element, and the gate end is coupled to the first common point. An LED display device, comprising: an LED display panel, a display control unit and at least one LED display driver chip as described in Claim 9.

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