TWI716525B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TWI716525B
TWI716525B TW106100429A TW106100429A TWI716525B TW I716525 B TWI716525 B TW I716525B TW 106100429 A TW106100429 A TW 106100429A TW 106100429 A TW106100429 A TW 106100429A TW I716525 B TWI716525 B TW I716525B
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conductive
substrate
top surface
conductive pattern
dielectric layer
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TW106100429A
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TW201737439A (zh
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李瓊延
李泰勇
新閔哲
歐瑟門
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美商艾馬克科技公司
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Abstract

本發明提供一種半導體封裝及其製造方法以用於確保安裝半導體裝置的空間，方法是蝕刻臨時金屬板以形成多個導電柱。

Description

半導體封裝及其製造方法
本發明的某些實施例涉及一種半導體封裝及其製造方法。
相關申請的交叉參考
本申請引用2016年4月7日遞交的第10-2016-0042986號韓國專利申請、主張所述韓國專利申請的優先權並主張所述韓國專利申請的權益，所述韓國專利申請的內容在此以全文引入的方式併入本文中。
隨著對當今半導體行業中的電子產品的小型化和高性能的增加的需求，正在研究且已經研發出用於提供大容量半導體封裝的各種技術。為了提供大容量半導體封裝，許多被動和/或主動元件被整合或堆疊在有限的基板上，由此獲得高度整合的半導體封裝。
經由比較此類系統與如在本申請的其餘部分中參看圖式闡述的本發明的一些態樣，習知和傳統方法的進一步限制和缺點將對所屬領域的技術人員變得顯而易見。
本發明提供一種半導體封裝及其製造方法，該方法可以藉由在臨時(或虛設)金屬板上藉由蝕刻形成多個導電柱來確保用於安裝半導 體裝置的空間。
本發明還提供一種半導體封裝及其製造方法，該方法可以減少用於製造導電柱的成本和處理時間。
2‧‧‧填充物
2a‧‧‧表面
2b‧‧‧頂部表面
100‧‧‧半導體封裝
110‧‧‧基板
110a‧‧‧頂部表面
110b‧‧‧底部表面
111‧‧‧介電層
111a‧‧‧頂部表面
111b‧‧‧底部表面
111h‧‧‧通孔
112‧‧‧第一導電圖案
112a‧‧‧頂部表面
112c‧‧‧側表面
112s‧‧‧第一晶種層
113‧‧‧導電通孔
113a‧‧‧頂部表面
113s‧‧‧通孔晶種層
114‧‧‧第二導電圖案
114s‧‧‧第二晶種層
115‧‧‧導電柱
115a‧‧‧表面
115b‧‧‧頂部表面
115x‧‧‧臨時金屬板
115x’‧‧‧剩餘部分
115xa‧‧‧頂部表面
115xb‧‧‧頂部表面
116‧‧‧鈍化層
120‧‧‧半導體裝置
121‧‧‧第一半導體裝置
121a‧‧‧微型凸塊
122‧‧‧第二半導體裝置
122a‧‧‧微型凸塊
130‧‧‧囊封物
131‧‧‧第一囊封部分
132‧‧‧第二囊封部分
140‧‧‧導電凸塊
S1-S4‧‧‧步驟
圖1是說明根據本發明的實施例的半導體封裝的截面圖；圖2是說明製造圖1中說明的半導體封裝的實例方法的流程圖；並且圖3A到3L是說明在圖2中說明的實例半導體封裝製造方法中形成基板的實例方法的截面圖。
本發明的各種態樣可以許多不同形式實施且不應理解為受限於在本文中所闡述的實例實施例。實際上，提供本發明的這些實例實施例是為了使本發明將為透徹且完整的，並且將向所屬領域的技術人員傳達本發明的各個態樣。
在圖式中，為了清楚起見而放大了層和區域的厚度。此處，類似參考標號通篇所指為類似元件。如本文中所使用，術語“和/或”包括相關聯的所列項目中的一個或多個的任何和所有組合。另外，本文中所使用的術語僅僅是出於描述特定實施例的目的而並不意圖限制本發明。如本文中所使用，除非上下文另外明確指示，否則單數形式也意圖包括複數形式。將進一步理解，術語“包括”、“包含”在用於本說明書時指定所陳述的特徵、數目、步驟、操作、元件和/或元件的存在，但是並不排除一個或多個其它特徵、數目、步驟、操作、元件、元件和/或其群組的存在或添 加。
應理解，雖然術語第一、第二等可以在本文中用於描述各種部件、元件、區域、層和/或區段，但是這些部件、元件、區域、層和/或區段不應受這些術語的限制。這些術語僅用於區分一個部件、元件、區域、層和/或區段與另一部件、元件、區域、層和/或區段。因此，舉例來說，下文論述的第一部件、第一元件、第一區域、第一層和/或第一區段可被稱為第二部件、第二元件、第二區域、第二層和/或第二區段而不脫離本發明的教示。現將詳細參考本發明的當前實施例，在附圖中說明所述實施例的實例。
根據本發明的一態樣，提供一種製造半導體封裝的方法。所述方法包括藉由蝕刻金屬板形成導電柱，其中在蝕刻之後，導電柱可以連接到金屬板的剩餘的平面部分。填充物可隨後用於填充在導電柱之間，並且在填充之後，可以移除金屬板的剩餘的平面部分，並且半導體晶粒可以電連接到導電柱。
根據本發明的另一態樣，提供一種製造半導體封裝的方法，其中所述方法包括藉由蝕刻金屬板來形成導電柱。在蝕刻之後，導電柱可以連接到金屬板的剩餘的平面部分，並且填充物可用於填充在導電柱之間。在填充之後，可以移除金屬板的剩餘的平面部分。隨後第一導電圖案可以形成於填充物的頂部表面上並且位於導電柱的頂部表面上，其中第一導電圖案中的一個或多個可以電連接到導電柱中的對應的一個或多個。
介電層可以形成為覆蓋填充物、導電柱和第一導電圖案。導電通孔可以形成為延伸穿過介電層並且連接到第一導電圖案，第二導電圖 案可以形成於介電層的頂部表面上，其中第二導電圖案可以電連接到導電通孔。第一半導體晶粒可以安裝在介電層的頂部表面上，其中第一半導體晶粒電連接到第二導電圖案的至少一部分。第二半導體晶粒可以安裝在介電層的底部表面上，其中第二半導體晶粒電連接到第一導電圖案的至少一部分。
本發明的另一態樣提供一種半導體封裝，其包括基板，該基板包括：介電層；第一導電圖案，其在介電層的底部表面處至少部分嵌入介電層中；第二導電圖案，其形成於介電層的頂部表面上；導電通孔，其形成為電連接第一導電圖案和第二導電圖案；以及導電柱，其從第一導電圖案的底部表面向下突出。至少一個半導體裝置可以安裝在基板的頂部表面和/或底部表面中的一個或多個上，並且囊封物可以形成於基板上以完全覆蓋半導體裝置。
如上文所述，在根據本發明的半導體封裝及其製造方法中，由於多個導電柱可以藉由蝕刻形成於臨時(或虛設)金屬板上，可以易於確保用於安裝半導體裝置的空間。
另外，在根據本發明的半導體封裝及其製造方法中，可以減小用於製造導電柱的成本和處理時間。
參考圖1，示出了說明根據本發明的實施例的實例半導體封裝的截面圖。
如圖1中所說明，半導體封裝100包括：基板110；一個或多個半導體裝置120(例如，第一半導體裝置121、第二半導體裝置122等)，其電連接到基板110；一個或多個囊封物130(例如，第一囊封部分131、 第二囊封部分132等)，其覆蓋半導體裝置120；以及導電凸塊140，其電連接到基板110。
基板110可以包括介電層111和多個導電通孔113，這些導電通孔通過或到達介電層111的頂部表面111a和/或底部表面111b。另外，基板110可進一步包括多個第一導電圖案112，這些第一導電圖案安置在介電層111的底部表面111b上(例如，嵌入在介電層111中)並且電連接到多個導電通孔113。另外，基板110可以進一步包括安置在介電層111的頂部表面111a上並且電連接到多個導電通孔113的多個第二導電圖案114。基板110可以進一步包括安置在介電層111的底部表面111b上並且電連接到第一導電圖案112的導電柱115。導電柱115也可以電連接到導電通孔113。因而，第一半導體晶粒121和第二半導體晶粒122可以電連接到導電柱115。
基板110的頂部表面110a可以例如與介電層111的頂部表面111a相同，並且基板110的底部表面110b可以例如與介電層111的底部表面111b相同。
參考圖2和圖3A到3L，提供說明製造圖1的半導體封裝(100)的實例方法的流程圖以及說明在圖2的製造半導體封裝的實例方法中形成基板(110)的實例方法的截面圖。在下文中，將參考圖2和圖3A到3L描述製造半導體封裝100的基板110的實例配置和實例方法。
如圖2中所說明，製造半導體封裝100的實例方法包括形成基板(S1)、附接(或安裝)半導體裝置(S2)、囊封(S3)和形成導電凸塊(S4)。另外，如圖2和3A到3L中所說明，基板的形成(S1)包括形成 導電柱(S11)、研磨(S12)、形成第一導電圖案(S13)、形成導電通孔(S14)、形成第二導電圖案(S15)、形成鈍化層(S16)和移除填充物(S17)。
如在圖3A到3C中所說明，在形成導電柱(S11)中，準備平面臨時(或虛設)金屬板115x並且多個遮罩圖案1隨後形成於臨時金屬板115x的頂部表面115xa上。未被所述多個遮罩圖案1覆蓋的臨時金屬板115x被移除到預定深度。由遮罩圖案1覆蓋的臨時金屬板115x的區域由此形成導電柱115。當遮罩圖案1被移除時可隨後接入導電柱115。
因而，可以看出導電柱115可以藉由向下移除未被多個遮罩圖案1覆蓋的臨時金屬板115x的暴露部分形成。臨時金屬板115x的頂部表面115xa的暴露部分的移除可以舉例來說經由蝕刻到預定深度。此處，導電柱115的底部部分可以藉由臨時金屬板115x的剩餘部分115x'彼此連接。舉例來說，彼此間隔開的導電柱115在剩餘部分115x'的頂部表面115xb上，該頂部表面可以舉例來說是原始的臨時金屬板115x的平面或板形部分。然而導電柱115和剩餘部分115x'都是原始臨時金屬板115x的剩餘的部分，它們在本文中被論述為單獨的實體。
導電柱115中的每一個的寬度A可以例如基本上在200μm和450μm之間的範圍內，並且鄰近導電柱115之間的橫向距離B可以基本上在90μm和500μm之間的範圍內，但本發明的各態樣並不限於此。另外，導電柱115中的每一個的高度C可以基本上在60μm和100μm之間的範圍內，但本發明的各態樣並不限於此。當增大導電柱115中的每一個的寬度A和高度C中的至少一者時，橫向距離B也可以增大。根據半導體封裝100的配置和功能，導電柱115中的每一個的寬度A和高度C可以是不同的以 便具有寬度A、橫向距離B和高度C中的一個。應注意由於導電柱115被蝕刻(例如，從一側等)，導電柱115中的每一個可具有指示此類蝕刻的形狀特性。舉例來說，由於蝕刻，導電柱115的側表面可以包括粗糙度(或粗略紋理)。並且，舉例來說，由於在導電柱115的第一端(或中心部分)處的金屬與在導電柱115的第二端處的金屬相比暴露於蝕刻劑較長時間週期，所以導電柱115的側表面可以發生傾斜。舉例來說，導電柱115可具有砂漏(或雪人)形狀、截錐形(或錐台)的形狀、圍繞中心凸出的截短球體的形狀等。
由於導電柱115是藉由蝕刻臨時金屬板115x而形成的，所以在與藉由電鍍或無電極鍍覆形成導電柱115相比時可以減少處理成本和時間。應注意，雖然在本文中僅呈現了一個蝕刻後步驟，但是遮蔽和/或蝕刻步驟可以多次執行，例如，形成階梯式或多層級結構。
在形成導電柱115之後，可以移除(例如，化學剝離等)在導電柱115上剩餘的遮罩圖案1。臨時金屬板115x可以由銅(Cu)製成，但本發明的各態樣並不限於此。另外，遮罩圖案1可以由光阻劑製成，但本發明的各態樣並不限於此。
如在圖3D到3F中所說明，在研磨(S12)中，填充物2形成為覆蓋具有導電柱115的剩餘部分115x'的蝕刻過的頂部表面115xb，並且剩餘部分115x'被移除。
首先，如圖3D中所說明，填充物2可以形成為覆蓋剩餘的臨時金屬板115x的蝕刻過的頂部表面115xb，並且填充導電柱115之間的空間以允許填充物2的頂部表面2b被放置成與導電柱115的頂部表面115b一 樣高或者高於導電柱115的頂部表面115b。舉例來說，填充物2可以填充導電柱115中的每一個之間的空間，使得填充物2的頂部表面2b與導電柱115的頂部表面115b一樣高或者高於導電柱115的頂部表面115b。填充物2可以由絕緣材料製成，例如，舉例來說，光阻劑或環氧樹脂，但本發明的各態樣並不限於此。填充物2可以多種方式中的任何一種形成(例如，旋轉塗布、噴射、浸漬、沉積、印刷、模制等)。
如圖3E中所說明，在填充物2形成之後，剩餘的臨時金屬板115'x和導電柱115翻轉以允許剩餘的臨時金屬板115x'安置在導電柱115和填充物2上。
在被翻轉之後，如圖3F中所說明，臨時金屬板115x的剩餘部分115x'被移除(例如，藉由機械研磨和/或化學方法、使用雷射進行移除、使用流體和/或氣體的噴射進行移除等)。另外，當剩餘部分115x'被移除時，導電柱115和填充物2的相應的表面115a和2a暴露於外部。另外，藉由移除臨時金屬板115x暴露於外部的導電柱115的表面115a和填充物2的表面2a可以是共面的。藉由剩餘部分115x'的研磨的移除舉例來說可以使用例如金剛石研磨機或其等效物執行，但本發明的各態樣並不限於此。
如圖3G和3H中所說明，在第一導電圖案的形成(S13)中，由導電材料製成的第一晶種層112s覆蓋導電柱115的表面115a和填充物2的表面2a，並且第一導電圖案112藉由電鍍形成於第一晶種層112s上。
首先，如圖3G中所說明，第一晶種層112s可以形成為具有均勻的厚度以便覆蓋導電柱115的表面115a和填充物2的表面2a。第一晶種層112s可以包括銅、鈦或鈦鎢，但本發明的各態樣並不限於此。第一晶 種層112s可以多種方式(例如，氣相沉積、無電極鍍覆等)中的任何一種形成。
如圖3H中所說明，為了形成第一導電圖案112，多個遮罩圖案(未示出)可以形成於第一晶種層112s的區域上覆蓋除了將形成第一導電圖案112的區域之外的那些區域。此類遮罩圖案可以舉例來說利用光阻劑形成，但本發明的各態樣並不限於此。具有預定厚度的第一導電圖案112可隨後形成，舉例來說，藉由電鍍未被遮罩圖案覆蓋的第一晶種層112s的區域。應注意第一導電圖案112(或導電層)可以包括多種材料中的任何一種(例如，銅、鋁、鎳、鐵、銀、金、鈦、鉻、鎢、鈀、其組合、其合金、其等效物等)，但是本發明的範圍不限於此。另外，應注意第一導電圖案112(或導電層)可以利用多種處理中的任何一個或多個形成或沉積(例如，電解電鍍、無電極鍍覆、化學氣相沉積(CVD)、濺鍍或物理氣相沉積(PVD)、原子層沉積(ALD)、等離子體氣相沉積、印刷、絲網印刷、光刻等)，但是本發明的範圍不限於此。
在形成第一導電圖案112之後，移除第一晶種層112s上的剩餘的遮罩圖案(例如，化學剝離等)。另外，在移除遮罩圖案之後，也可以移除在未形成第一導電圖案112的區域中的第一晶種層112s(例如，藉由化學蝕刻等)以將填充物2的表面2a暴露於外部。舉例來說，第一晶種層112s和第一導電圖案112可以覆蓋與圖3H中所示的相同的區域。第一導電圖案112可以藉由第一晶種層112s電連接到導電柱115。另外，第一晶種層112s是用於藉由電鍍形成第一導電圖案112的參考層，並且為了易於描述，以下描述將是考慮到第一導電圖案112為包括第一晶種層112s和第一 導電圖案112的單層作出的。第一導電圖案112可以由銅(Cu)製成，但本發明的各態樣並不限於此。
圖3I說明形成導電通孔(S14)。介電層111可以形成為完全覆蓋第一導電圖案112和填充物2的表面2a，可以形成使多個第一導電圖案112暴露於外部的多個通孔111h，並且多個導電通孔113可以形成為填充通孔111h。
介電層111形成為具有預定厚度以完全覆蓋填充物2和第一導電圖案112。介電層111可以與第一導電圖案112和第一晶種層112s電絕緣。第一導電圖案112可以經配置使得它們的頂部表面112a和側表面112c由介電層111覆蓋。介電層111可以由舉例來說預浸體(pre-preg)、累積膜(build-up film)、氧化矽膜、氮化矽膜、模制化合物及其等效物中的一個或多個製成，但本發明的各態樣並不限於此。介電層可以包括多種介電材料中的任何一種的一個或多個層，這些介電材料例如，無機介電材料(例如，Si3N4、SiO2、SiON、SiN、氧化物、氮化物、其組合、其等效物等)和/或有機介電材料(例如，聚合物、聚醯亞胺(PI)、苯環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、模制材料、酚醛樹脂、環氧樹脂、矽酮、丙烯酸酯聚合物、其組合、其等效物等)，但是本發明的範圍並不限於此。介電層111可以使用多種處理中的任何一個或多個形成(例如，旋轉塗布、噴霧塗布、印刷、燒結、熱氧化、物理氣相沉積(PVD)、化學氣相沉積(CVD)、金屬有機化學氣相沉積(MOCVD)、原子層沉積(ALD)、低壓化學氣相沉積(LPCVD)、等離子體增強式化學氣相沉積(PECVD)、等離子體氣相沉積(PVD)、薄片層合、蒸發等)，但是本發明的範圍並不限 於此。
多個通孔111h從介電層111的頂部表面111a向下形成，由此藉由多個通孔111h使多個第一導電圖案112暴露於外部。多個導電通孔113藉由填充多個通孔111h而被形成以電連接到第一導電圖案112。通孔111h可以多種方式中的任何一種形成(例如，雷射燒蝕、機械燒蝕或鑽孔、化學蝕刻等)。
多個導電通孔113可以填充通孔111h而被形成，方法是藉由電鍍暴露於外部的多個第一導電圖案112到多個通孔111h之中。舉例來說，導電通孔113可以藉由使用第一導電圖案112作為晶種層進行電鍍來填充通孔111h而被形成。另外，導電通孔113可以藉由在通孔111h和第一導電圖案112的內壁上形成通孔晶種層113s並且在通孔晶種層113s上進行電鍍而被形成。如上文所述，導電通孔113可以使用第一導電圖案112作為晶種層或者具有單獨的通孔晶種層113s作為參考層以用於電鍍，但本發明的各態樣並不限於此。通孔晶種層113s可包括例如銅、鈦、或鈦鎢，但本發明的各態樣並不限於此。應注意，通孔111h可以多種方式中的任何一種形成(例如，電鍍、無電極鍍覆、印刷、膠合等)。
圖3J說明第二導電圖案的形成(S15)。多個第二導電圖案114形成於介電層111和導電通孔113的頂部表面上以電連接到導電通孔113。
第二導電圖案114可以與第一導電圖案112相同的方式形成。舉例來說，第二導電圖案114可以藉由形成第二晶種層114s以完全覆蓋介電層111的頂部表面111a和導電通孔113的頂部表面113a而被形成。 遮罩圖案可隨後形成於第二晶種層114s的區域上，使待形成第二導電圖案114的區域暴露，並且在第二晶種層114s上進行電鍍。第二晶種層114s可以舉例來說是銅層、鈦層或鈦鎢層，並且第二導電圖案114可以包括銅，但本發明的各態樣並不限於此。另外，第二晶種層114s可以是參考層，所述參考層是用於藉由電鍍而形成第二導電圖案114，並且為了易於描述，以下描述將是考慮到第二導電圖案114為包括第二晶種層114s和第二導電圖案114的單層作出的。
形成於介電層111的頂部表面111a和導電通孔113的頂部表面113a上的第二導電圖案114可以通過導電通孔113電連接到第一導電圖案112。
如圖3K中所說明，在鈍化層的形成(S16)中，鈍化層116(或介電層)形成為覆蓋介電層111的頂部表面111a和第二導電圖案114。舉例來說，第二導電圖案114中的至少一者可以暴露於鈍化層116的外部。舉例來說，第二導電圖案114可以各自通過鈍化層116中的相應的開口暴露和/或多個第二導電圖案114可以通過鈍化層中的單個開口暴露。暴露於外部的第二導電圖案114可以電連接到半導體裝置121，如圖1中所示。應注意，鈍化層116可以由本文中關於介電層111描述的任何材料形成和/或可以利用本文中關於介電層111所論述的任何方法形成。
在一個實施例中，在多個第二導電圖案114之中，基板110的頂部表面110a的中心區域中的第二導電圖案114可以暴露於外部(例如，通過鈍化層116中的一個或多個開口)，並且基板110的頂部表面110a的週邊區域中的第二導電圖案114可以由鈍化層116覆蓋。
如圖3L中所說明，在填充物的移除(S17)中，移除填充物2以將介電層111的底部表面111b和第一導電圖案112(例如，未被導電柱115覆蓋的導電圖案112的那些部分)暴露於外部。此處，當填充物2被移除時，導電柱115的側表面115c可以暴露於外部。因而，如圖3L中所示，基板110(或其一部分)可以通過移除填充物2形成。舉例來說，可以提供基板110，使得彼此間隔開的導電柱115接觸第一導電圖案112的底部表面112b且電連接到第一導電圖案112的底部表面112b並且向下突出。
另外，當填充物2被移除時，暴露於外部的第一導電圖案112變為待電連接到半導體裝置122的模式。在第一導電圖案112中，基板110的底部表面110b的中心區域中的第一導電圖案112可以暴露於外部，並且基板110的底部表面110b的週邊區域中的第一導電圖案112可以電連接到導電柱115。
參考圖1和3L，在半導體裝置的安裝(S2)中，至少一個半導體裝置120安裝為電連接到第二導電圖案114和/或第一導電圖案112，這些導電圖案相應地在基板110的頂部表面110a或底部表面110b處暴露。舉例來說，一個或多個半導體裝置120可以安裝在基板110的頂部表面110a上(例如，至少第一半導體裝置121)以電連接到基板110的第二導電圖案114，安裝在基板110的底部表面110b上(例如，至少第二半導體裝置122)以電連接到基板110的第一導電圖案112，或者安裝在基板110的頂部表面110a和底部表面110b這兩者上。
舉例來說，在半導體裝置的安裝(S2)中，至少一個第一半導體裝置121可以安裝在基板110的頂部表面110a上以電連接到暴露於基 板110的頂部表面110a的第二導電圖案114，並且至少一個第二半導體裝置122可以安裝在基板110的底部表面110b上以電連接到暴露於基板110的底部表面110b的第一導電圖案112。第二半導體裝置122可以安裝在基板110的底部表面110b的中心區域上並且導電柱115可以在基板110的底部表面110b的週邊區域中向下突出。舉例來說，可以通過導電柱115中的每一個的高度C確保足以將第二半導體裝置122安裝在基板110的底部表面110b上的垂直空間。
第一半導體裝置121可以是倒裝晶片型半導體晶粒並且可以舉例來說藉由微型凸塊121a電連接到基板110的第二導電圖案114。另外，第二半導體裝置122可以是倒裝晶片型半導體晶粒並且可以藉由例如微型凸塊122a電連接到基板110的第一導電圖案112。微型凸塊121a和122a可包括例如導電球，例如，焊料球、例如銅柱的導電柱和/或具有形成於銅柱上的焊料帽的導電柱。另外，包括接合墊的半導體裝置120可以藉由線接合電連接到基板110的第一導電圖案112或第二導電圖案114。然而，本發明並不限制半導體裝置120和導電圖案112和114中的每一個之間連接關係於本文中所公開的內容。半導體裝置120可以例如藉由大規模回焊處理、熱壓縮處理和/或雷射接合處理電連接到基板110。另外，半導體裝置120可以進一步包括提供於垂直方向上的半導體裝置。
此處，半導體裝置120可包括與半導體晶片分開的積體電路晶片。半導體裝置120可包括例如電路，例如，中央處理單元(CPU)、數位訊號處理器(DSP)、網路處理器、功率管理單元、音訊處理器、射頻(RF)電路、無線基帶晶片上系統(SoC)處理器、感測器、專用積體電路(ASIC)。 另外，半導體裝置120可以是例如電阻器、電容器、電感器、連接器的裝置，但本發明的各態樣並不限於此。此外，半導體裝置120可以包括具有晶片的其它封裝，例如，BGA封裝、引線框封裝等。
在囊封(S3)中，如圖1中所示，囊封物130形成為覆蓋(例如，部分地覆蓋、完全覆蓋等)基板110的頂部表面110a和底部表面110b。在囊封(S3)中，第一囊封物131可以形成為覆蓋基板110的頂部表面110a和第一半導體裝置121，並且第二囊封物132可以形成為完全覆蓋基板110的底部表面110b和第二半導體裝置122。當第二囊封物132形成時，導電柱115的底部表面115b可以暴露於外部。
囊封物130可以形成為囊封半導體裝置120和基板110上的除了導電柱115的底部表面115b之外的全部表面，由此保護半導體裝置120免受外部機械/電子/化學污染或影響。應注意囊封物130也可以形成為暴露半導體裝置120中的任何一個或多個的至少頂部表面。
第一囊封物131和第二囊封物132可以是使用模具和模制框同時形成的，但本發明的各態樣並不限於此。第一囊封物131和/或第二囊封物132可以包括例如預浸體(pre-preg)、堆積膜(build-up film)、氧化矽膜、氮化矽膜、模制化合物及其等效物中的一個或多個，但本發明的各態樣並不限於此。
另外，在第一半導體裝置121安裝在基板110的頂部表面110a上之後囊封物130的第一囊封物131可以形成為完全覆蓋第一半導體裝置121和基板110的頂部表面110a，並且在第二半導體裝置122安裝在基板110的底部表面110b上之後第二囊封物132可以形成為完全覆蓋第二半 導體裝置122和基板110的底部表面110b。半導體裝置120的安裝和囊封物130的形成也可以相反順序執行。
囊封物130(或囊封材料)可包括例如聚醯亞胺(PI)、苯並環丁烷(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、酚醛樹脂和環氧樹脂，但本發明的各態樣並不限於此。舉例來說，囊封材料可以包括多種囊封或模制材料中的任何一種(例如，樹脂、聚合物、聚合物複合材料、具有填充物的聚合物、環氧樹脂、具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、矽酮樹脂、其組合、其等效物等)。囊封物130(或囊封材料)可以多種方式中的任何一種形成(例如，壓縮模制、轉移模制、液體封裝劑模制、真空層合、糊料印刷、膜輔助模制等)。
在導電凸塊的形成(S4)中，導電凸塊140形成於導電柱115的底部表面115b上以允許導電柱115電連接到囊封物130的外部。導電凸塊140可以充當輸入和/或輸出連接以用於將半導體封裝100安裝在電子裝置的外部板上。導電凸塊140可以舉例來說，是導電柱、銅柱、導電球、焊料球或銅球，但本發明的各態樣並不限於此。
由於經由上述實例製造方法製造的半導體封裝100的各個態樣是藉由蝕刻臨時金屬板115x以形成導電柱115而形成的，所以高效的確保了安裝半導體裝置120的空間，並且與導電柱115藉由鍍覆堆疊的情況相比可以減少處理成本和時間。
另外，雖然可以描述囊封物130，但是本發明的各種實施例可以舉例來說任選地不具有囊封物或者可以也使用填充物材料。舉例來說，可以移除全部的填充物2或僅填充物2的一部分，並且在第二半導體 裝置122附接到第一導電圖案112之後，第二半導體裝置122可能無法被覆蓋。或者，它可以使用填充物材料或囊封材料覆蓋。因而，可以看出本發明的囊封物132可以被整體移除或部分移除，並且如果移除的話，那麼可以使用相同類型的囊封材料或者另一類型的材料可用於覆蓋第二半導體裝置122或者以不同的程度被移除直到在填充物2被移除之前佔據的體積為止。因此，覆蓋第二半導體裝置122的實施例可以看起來如圖1中所示，佔據由囊封物132佔據的體積的某一部分，或者示出為被囊封物132佔據的體積並不填充有任何東西。
雖然已經參考某些支援的實施例描述了根據本發明的各種態樣的半導體封裝及其製造方法，但是所屬領域的技術人員應理解，本發明不限於所公開的具體實施例，而是，本發明將包含落入所附申請專利範圍內的所有實施例。
S1-S4‧‧‧步驟

Claims (28)

  1. 一種製造半導體封裝的方法，所述方法包括：提供柱狀結構，其包含從金屬板的一部分突出的導電柱；將基板的底部表面耦接到所述導電柱的頂部表面使得沿著所述基板的所述底部表面的第一導電圖案被耦接到所述導電柱；移除所述金屬板的所述剩餘的平面部分；並且將第一半導體晶粒的頂部表面附接到所述基板的所述底部表面，使得所述第一半導體晶粒的所述頂部表面是經由沿著所述基板的底部表面的所述第一導電圖案而被電耦接到所述導電柱。
  2. 根據申請專利範圍第1項所述的方法，其中前述耦接所述基板的底部表面到所述導電柱的所述頂部表面包括：在所述導電柱的頂部表面上形成所述第一導電圖案；形成覆蓋所述導電柱和所述第一導電圖案的第一介電層；並且形成延伸穿過所述第一介電層的導電通孔以連接到所述第一導電圖案。
  3. 根據申請專利範圍第2項所述的方法，其中前述耦接所述基板的底部表面到所述導電柱的所述頂部表面還包括：在所述第一介電層的頂部表面上並且在所述導電通孔的頂部表面上形成第二導電圖案以將所述第二導電圖案電連接到所述導電通孔；並且形成第二介電層，所述第二介電層覆蓋所述第二導電圖案的第一部分並且不覆蓋所述第二導電圖案的第二部分。
  4. 根據申請專利範圍第3項所述的方法，其進一步包括將第二半導體 晶粒附接到所述第二導電圖案的所述第二部分。
  5. 根據申請專利範圍第4項所述的方法，其包括用囊封材料覆蓋所述第二半導體晶粒的至少一部分和所述第二介電層的至少一部分。
  6. 根據申請專利範圍第2項所述的方法，其包括：移除所述填充物以暴露所述第一導電圖案的一部分、所述導電柱的側表面和所述第一介電層的一部分；並且用囊封材料覆蓋所述第一導電圖案的所述暴露部分、所述導電柱的所述暴露側表面和所述第一介電層的所述暴露部分。
  7. 根據申請專利範圍第6項所述的方法，其中附接該第一半導體晶粒的該頂部表面包括，在移除所述填充物之後，將所述第一半導體晶粒附接到所述第一導電圖案。
  8. 根據申請專利範圍第7項所述的方法，其中用囊封材料覆蓋所述第一導電圖案的所述暴露部分、所述導電柱的所述暴露側表面、所述第一介電層的所述暴露部分進一步包括用囊封材料覆蓋所述第一半導體晶粒的一部分。
  9. 根據申請專利範圍第1項所述的方法，其包括在所述導電柱的底部表面上形成導電凸塊。
  10. 根據申請專利範圍第1項所述的方法，其中鄰近導電柱之間的距離的範圍介於大體上90μm到大體上500μm。
  11. 根據申請專利範圍第1項所述的方法，其中所述導電柱中的每一個的頂部表面和底部表面之間的高度的範圍介於大體上60μm到大體上100μm。
  12. 根據申請專利範圍第1項所述的方法，其中所述導電柱中的每一個的寬度的範圍介於大體上200μm到大體上450μm。
  13. 一種製造半導體封裝的方法，所述方法包括：提供柱狀結構，其包含無鍍覆銅的導電柱；提供基板到所述導電柱的頂部表面上，其中所述基板的底部表面被附接到所述導電柱的頂部表面；在所述基板的頂部表面上安裝第一半導體晶粒以將所述第一半導體晶粒電連接到所述基板的一個或多個導電圖案；以及在所述基板的所述底部表面上安裝第二半導體晶粒以將所述第二半導體晶粒的頂部表面電連接到所述一個或多個導電圖案中的一導電圖案，其中所述導電圖案是沿著所述基板的所述底部表面。
  14. 根據申請專利範圍第13項所述的方法，其包括以囊封材料覆蓋所述第二半導體晶粒的至少一部分、所述基板的所述底部表面以及所述導電柱的側表面；其中所述導電柱的所述側表面包括被蝕刻的銅。
  15. 根據申請專利範圍第14項所述的方法，其包括以另外的囊封材料覆蓋所述第一半導體晶粒一部分以及所述基板的頂部表面。
  16. 根據申請專利範圍第13項所述的方法，其中提供所述基板到所述導電柱的所述頂部表面上包括耦接基板，其包括：第一導電圖案，其在所述導電柱的頂部表面上；介電層，其覆蓋所述導電柱和所述第一導電圖案；導電通孔，其延伸穿透所述介電層並且連接到所述第一導電圖案；以 及第二導電圖案，其在所述介電層的頂部表面上，其中所述第二導電圖案電連接到所述導電通孔。
  17. 一種半導體封裝，其包括：基板，其包括介電層和一個或多個導電圖案；導電柱，其從所述基板的底部表面向上突出，所述導電柱包含無鍍覆銅；第一半導體裝置，其安裝在所述基板的頂部表面上；第二半導體裝置，其安裝在所述基板的底部表面上；以及囊封物，其在所述基板上並且覆蓋所述第二半導體裝置和所述導電柱的側表面。
  18. 根據申請專利範圍第17項所述的半導體封裝，其中：所述第一半導體裝置，其被安裝在所述基板的所述頂部表面上，是被連接到所述一個或多個導電圖案；所述第二半導體裝置，其被安裝在所述基板的所述底部表面上，是被連接到所述一個或多個導電圖案；並且所述導電柱的所述側表面包括被蝕刻的銅。
  19. 根據申請專利範圍第18項所述的半導體封裝，其中：所述第二半導體裝置在所述基板的所述底部表面的底部區域中電連接到所述一個或多個導電圖案；並且所述導電柱在所述基板的所述底部表面的週邊區域中電連接到所述一個或多個導電圖案，所述週邊區域界定所述底部區域的相對側。
  20. 根據申請專利範圍第19項所述的半導體封裝，其中所述囊封物包括：第一囊封物，其覆蓋所述第一半導體裝置和所述基板的所述頂部表面；以及第二囊封物，其覆蓋所述第二半導體裝置、所述基板的所述底部表面以及所述導電柱的所述側表面。
  21. 根據申請專利範圍第20項所述的半導體封裝，其包括連接到所述導電柱的底部表面的多個導電凸塊。
  22. 根據申請專利範圍第21項所述的半導體封裝，其中所述多個導電凸塊延伸超過所述第二囊封物的底部表面。
  23. 根據申請專利範圍第17項所述的半導體封裝，其中：所述一個或多個導電圖案包括：第一導電圖案，其在所述介電層的底部表面處至少部分地被埋藏在所述介電層中；以及第二導電圖案，其在所術介電層的頂部表面上；所述基板還包括導電通孔以電連接所述第一導電圖案和所述第二導電圖案；以及所述導電柱從所述第一導電圖案的底部表面下向突出。
  24. 一種半導體封裝，其包括：基板，其包含介電層和一個或多個導電圖案；導電柱，耦接到所述基板的底部表面的頂部表面，所述導電柱從所述基板的所述底部表面下向突出；第一半導體裝置，其安裝在所述基板的所述頂部表面；第二半導體裝置，其安裝在所述基板的所述底部表面；以及 金屬板，其跨度所述導電柱並且被耦接到每個所述導電柱的底部表面。
  25. 根據申請專利範圍第24項所述的半導體封裝，其中：被安裝在所述基板的所述頂部表面上的所述第一半導體裝置連接到所述一個或多個導電圖案；以及被安裝在所述基板的所述底部表面上的所述第二半導體裝置連接到所述一個或多個導電圖案。
  26. 根據申請專利範圍第25項所述的半導體封裝，其中：在所述基板的所述底部表面的底部區域中，所述第二半導體裝置電連接到所述一個或多個導電圖案；以及在所述基板的所述底部表面的週邊區域中，所述導電柱電連接到所述一個或多個導電圖案，所述週邊區域界定所述底部區域的相對側。
  27. 根據申請專利範圍第24項所述的半導體封裝，其進一步包括囊封物，所述囊封物覆蓋所述第二半導體裝置、所述基板的所述底部表面以及所述導電柱的側表面。
  28. 根據申請專利範圍第24項所述的半導體封裝，其中：所述一個或多個導電圖案包括：第一導電圖案，其在所述介電層的底部表面處被至少部份地埋藏在所述介電層中；以及第二導電圖案，其在所述介電層的頂部表面上；所述基板進一步包括導電通孔以電連接所述第一導電圖案和所述第二導電圖案；以及所述導電柱從所述第一導電圖案的底部表面向下突出。
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CN116779592A (zh) 2023-09-19
US10020263B2 (en) 2018-07-10
KR20170115378A (ko) 2017-10-17
CN107275229A (zh) 2017-10-20
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