TWI713168B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A chip package structure includes a circuit substrate, a plurality of conductive connectors, a first chip, and a two-stage thermosetting adhesive layer. The circuit substrate has a first surface and, a second surface opposite to the first surface. The conductive connectors are located on the first surface. The conductive connectors are electrically connected to the circuit substrate. The first chip has an active surface and, a rear surface opposite to the active surface, and a plurality of conductive portions are located on the active surface. The first chip is located on the first surface with the rear surface. The two-stage thermosetting adhesive layer encapsulates the conductive connectors and the first chip and part of the conductive connectors and part of the conductive portions of the first chip are exposed on the same plane. A manufacturing method of a chip package structure is also provided.

Description

Chip packaging structure and manufacturing method thereof

The present invention relates to a package structure and a manufacturing method thereof, and particularly relates to a chip package structure and a manufacturing method thereof.

In the Multi-Chip Package (MCP), stacking multiple chips vertically to save package size is already a mature technology. However, in the multi-chip package structure, the components on the bottom layer on the substrate are likely to be displaced or even separated from the substrate during the subsequent stacking process, thereby affecting the package yield. Therefore, how to effectively reduce the displacement or even separation of the components on the bottom layer of the substrate during the subsequent stacking of other electronic components to improve the packaging yield has become one of the problems to be solved urgently.

The chip packaging structure and the manufacturing method thereof of the present invention can effectively reduce the displacement or even the separation of the multiple conductive connectors on the circuit substrate and the first chip during the subsequent stacking of other electronic components, and can reduce multiple The probability that the conductive connectors will contact each other and be electrically short-circuited due to displacement, so as to improve the yield of the chip package structure.

The invention provides a chip packaging structure, which includes a circuit substrate, a plurality of conductive connectors, a first chip and a two-stage thermosetting adhesive layer. The circuit substrate has a first surface and a second surface opposite to the first surface. A plurality of conductive connections are located on the first surface. A plurality of conductive connectors are electrically connected to the circuit substrate. The first chip has an active surface, a back surface opposite to the active surface, and a plurality of conductive parts on the active surface. The first wafer is configured on the first surface with a back surface. The two-stage thermosetting adhesive layer encapsulates the plurality of conductive connectors and the first chip, and jointly exposes part of the plurality of conductive connectors and the plurality of conductive parts of the first chip on the same plane.

The present invention provides a method for manufacturing a chip package structure, including providing a circuit substrate, wherein the circuit substrate has a first surface and a second surface opposite to the first surface. A plurality of conductive connecting members are formed on the first surface, wherein the plurality of conductive connecting members are electrically connected to the circuit substrate. A two-stage thermosetting adhesive layer is formed to encapsulate multiple conductive connections. A first chip is arranged on the first surface and embedded with a two-stage thermosetting adhesive layer, wherein the first chip has an active surface, a back surface opposite to the active surface, and a plurality of conductive parts on the active surface. A heating process is performed to completely cure the two-stage thermosetting adhesive layer.

Based on the above, the chip package structure of the present invention first uses a two-stage thermosetting adhesive layer to encapsulate a plurality of conductive connectors and the first chip, and then performs a heating process to completely cure the two-stage thermosetting adhesive layer, so as to protect and fix the multiple layers. There are two conductive connectors and the first chip, so it effectively reduces the displacement of the multiple conductive connectors and the first chip on the circuit substrate during the subsequent stacking of other electronic components (such as the second chip and the third chip) and even the circuit substrate The separation condition can reduce the probability that a plurality of conductive connectors will contact each other due to displacement and be electrically short-circuited, so as to improve the yield of the chip package structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Hereinafter, the present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1D are partial cross-sectional schematic diagrams of a part of a manufacturing method of a chip package structure according to an embodiment of the present invention. 1A, first, a circuit substrate 110 is provided, wherein the circuit substrate 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a. The circuit substrate 110 may be a printed circuit board, but the present invention is not limited to this. As long as the circuit substrate 110 has suitable conductive circuits for subsequent electrical connections, it belongs to the protection scope of the present invention.

Please continue to refer to FIG. 1A, a plurality of conductive connectors 120 are formed on the first surface 110 a of the circuit substrate 110, and the plurality of conductive connectors 120 are electrically connected to the circuit substrate 110. The conductive connectors 120 may be solder balls, electroplated bumps, electroless plating bumps, junction bumps, conductive polymer bumps or metal composite bumps. The solder balls may be tin balls, and the bump materials may be selected from the following Groups: tin, copper, gold, silver, indium, nickel/gold, nickel/palladium/gold, copper/nickel/gold, copper/gold, aluminum and combinations thereof, but the present invention is not limited thereto. The formation method of the conductive connecting member 120 may be by pre-coating tin paste or pick and place on the first surface 110a, and then performing a reflow process to form the conductive connecting member 120, wherein tin is pre-coated The paste can be prepared by printing or plating, but the present invention is not limited to this.

Please refer to FIG. 1B, after the conductive connection 120 is formed, a two-stage thermosetting adhesive layer 131 is formed to encapsulate the conductive connection 120. The top surface 131 a of the two-stage thermosetting adhesive layer 131 may be higher than the top surface 120 a of the conductive connector 120. In other words, the two-stage thermosetting adhesive layer 131 can cover the conductive connector 120 so that the conductive connector 120 is not exposed. On the other hand, the two-stage thermosetting adhesive layer 131 may be disposed on the circuit substrate 110 to expose a part of the side area of the circuit substrate 110.

In this embodiment, the two-stage thermosetting adhesive layer 131 is, for example, in a semi-cured state. Here, the two-stage thermosetting adhesive layer 131 is, for example, a liquid (Liquid) at the A stage, a partially cured semi-solid (Jelly) at the B stage, and a fully cured solid (Solid) at the C stage. Epoxy resin. The method of forming the two-stage thermosetting adhesive layer 131 may include a spin coating process or a screen printing process.

Please continue to refer to FIG. 1B, the two-stage thermosetting adhesive layer 131 can be first coated on the circuit substrate 110 in a liquid manner, and then pre-cured through the first stage of heating and heating process. The heating process is, for example, heating and baking. grilled. The pre-cured two-stage thermosetting adhesive layer 131 may further assist the conductive connector 120 to be temporarily fixed on the first surface 110a of the circuit substrate 110 before the first chip 140 is arranged, but the invention is not limited thereto. On the other hand, the two-stage thermosetting adhesive layer 131 may be located between two adjacent conductive connectors 120 to electrically isolate the two adjacent conductive connectors 120.

1C, a first chip 140 is disposed on the first surface 110a. The first chip 140 has an active surface 140a, a back surface 140b opposite to the active surface 140a, and a plurality of conductive portions 142 on the active surface 140a. In this embodiment, the first wafer 140 is disposed on the first surface 110a with the back surface 140b. In other words, the active surface 140 a of the first chip 140 and the plurality of conductive portions 142 are far away from the circuit substrate 110. The first chip 140 can be fixed on the circuit substrate 110 through a die attach process. During the die attach process, an adhesive layer (not shown) must be formed on the back surface 140b of the first chip 140 and then attached to the circuit substrate. On the substrate 110, since the two-stage thermosetting adhesive layer 131 is still semi-cured in this state, when the first chip 140 is fixed to the circuit substrate 110 through a die attach process, the first chip 140 can penetrate The two-stage thermosetting adhesive layer 131 is fixed on the circuit substrate 110. The adhesive layer can be a die-bonding film (DAF) or other suitable materials, but the invention is not limited thereto.

In this embodiment, the first wafer 140 is embedded in the two-stage thermosetting adhesive layer 131. In other words, the two-stage thermosetting adhesive layer 131 encapsulates the first wafer 140. The top surface 142a of the plurality of conductive parts 142 and the top surface 120a of the conductive connector 120 may be located on the same plane. On the other hand, a plurality of conductive connections 120 may surround the first chip 140. In other words, the plurality of conductive connections 120 may be located on both sides of the first chip 140, and the orthographic projection of the plurality of conductive connections 120 on the circuit substrate 110 and the orthographic projection of the first chip 140 on the circuit substrate 110 do not overlap .

In this embodiment, when the two-stage thermosetting adhesive layer 131 is pre-cured through the first stage of heating and heating process, the second stage of heating and heating process can be performed, so that in the process of arranging the first wafer 140 on the first surface 110a The two-stage thermosetting adhesive layer 131 is paste-like, and the plurality of conductive portions 142 can be completely embedded in the two-stage thermosetting adhesive layer 131. Therefore, the top surface 131 a of the two-stage thermosetting adhesive layer 131 may be higher than the top surface 142 a of the conductive portion 142. In other words, the two-stage thermosetting adhesive layer 131 can cover the conductive portion 142 so that the top surface 142a of the conductive portion 142 is not exposed.

Please refer to FIG. 1D. After the first wafer 140 is configured, a heating process is performed to completely cure the two-stage thermosetting adhesive layer 131. In other words, after the first wafer 140 is configured, the semi-cured two-stage thermosetting adhesive layer 131 can be heated to make the semi-cured two-stage thermosetting adhesive layer 131 become a fully cured two-stage thermosetting adhesive layer 130. Next, a planarization process is performed on the top surface 130a of the two-stage thermosetting adhesive layer 130 to expose a plurality of conductive portions 142 and a plurality of conductive connectors 120. In other words, after the planarization process is performed, the top surface 130a is on the same plane (two-stage A portion of the conductive connectors 120 and the conductive portions 142 of the first chip 140 are jointly exposed on the top surface 130a) of the thermosetting adhesive layer 130, so that the conductive portions 142 and the conductive connectors 120 can be electrically connected to other electronic components. The planarization process is, for example, a mechanical grinding process (mechanical grinding process), a chemical-mechanical polishing process (chemical-mechanical polishing, CMP), or other suitable processes or a combination thereof. After the above process, the fabrication of the chip package structure 100 of this embodiment can be substantially completed.

In this embodiment, the two-stage thermosetting adhesive layer 131 is first used to encapsulate the conductive connectors 120 and the first chip 140, and then the heating process is performed to completely cure the two-stage thermosetting adhesive layer 131 for good protection and fixation. The plurality of conductive connectors 120 and the first chip 140 effectively reduce the displacement or even separation of the plurality of conductive connectors 120 and the first chip 140 on the circuit substrate 110 during the subsequent stacking of other electronic components. It is possible to reduce the probability that the plurality of conductive connectors 120 will contact each other and be electrically shorted due to displacement, so as to improve the yield of the chip package structure 100.

It must be noted here that the following embodiments use the component numbers and part of the content of the above embodiments, wherein the same or similar reference numbers are used to represent the same or similar components, and the description of the same technical content is omitted, and the description of the omitted parts is omitted. Reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2 is a schematic partial cross-sectional view of a chip package structure according to another embodiment of the invention. Please refer to FIG. 2. The difference between the chip package structure 100a in FIG. 2 and the chip package structure 100 in FIG. 1D is that after the planarization process of FIG. 1D is performed, the second chip 150 can be flip-chip bonded to the two-stage thermosetting adhesive layer 130. And it is electrically connected to the first chip 140 and the circuit substrate 110. For example, the active surface 150a of the second chip 150 faces the first chip 140, the second chip 150 is electrically connected to the first chip 140 through a plurality of conductive portions 142, and is connected to the circuit substrate through a plurality of conductive connections 120 110 electrical connection. In one embodiment, the second chip 150 has a plurality of solder balls 152, some of the solder balls 152 correspond to the plurality of conductive portions 142, and the other part of the solder balls 152 correspond to the plurality of conductive connectors 120.

Since the two-stage thermosetting adhesive layer 130 well protects and fixes the plurality of conductive connectors 120 and the first chip 140, it can effectively reduce the number of conductive connectors 120 and the first chip 140 on the circuit substrate 110 during the process of bonding the second chip 150. The first chip 140 is displaced or even separated from the circuit substrate, and the probability that the plurality of conductive connectors 120 are contacted and electrically short-circuited due to displacement can be reduced, so as to improve the yield of the chip package structure 100a.

3 is a schematic partial cross-sectional view of a chip package structure according to another embodiment of the invention. Please refer to FIG. 3, the difference between the chip package structure 100b in FIG. 3 and the chip package structure 100a in FIG. 2 is that after the second chip 150 is configured, a package compound 160 can be formed to encapsulate the two-stage thermosetting glue layer 130 and the second chip 150. In addition, a plurality of solder balls 170 may be formed on the second surface 110b and electrically connected to the circuit substrate 110. In this embodiment, the size of the packaging glue 160 can be larger than the size of the two-stage thermosetting glue layer 130. In other words, a part of the packaging glue 160 can be located on the circuit substrate 110 on both sides of the two-stage thermosetting glue layer 130. However, the present invention is not limited to this. In other unillustrated embodiments, the size of the encapsulant 160 may be substantially equal to the size of the two-stage thermosetting adhesive layer 130, exposing the side area of the circuit substrate 110. Since the packaging compound 160 encapsulates the two-stage thermosetting adhesive layer 130 and the second chip 150, it can prevent moisture or foreign matter from intruding, which may affect the chip package structure 100b, such as rust, short circuit or malfunction, to further improve the chip package structure 100b yield.

On the other hand, as shown in FIG. 3, a plurality of solder balls 170 may be fully implanted on the second surface 110b of the circuit substrate 110. In other words, a plurality of solder balls 170 may be implanted on the center and the center of the circuit substrate 110. On both sides, to increase the external electrical contacts of the chip package structure 100b, and the chip package structure 100b can be electrically connected to other packages (not shown) through a plurality of solder balls 170 to further increase the chip package structure 100b Feature.

4 is a schematic partial cross-sectional view of a chip package structure according to another embodiment of the invention. Please refer to FIG. 4, the difference between the chip package structure 100c in FIG. 4 and the chip package structure 100b in FIG. 3 is that the third chip 180 can be stacked and bonded on the second chip 150 before the packaging compound 160 is formed, and then bonded to the path by wire bonding On the substrate 110. In other words, the third chip 180 is stacked and bonded on the second chip 150 in a face-up manner, and the active surface 180 a of the third chip 180 is away from the second chip 150. For example, as shown in FIG. 4, the wires may connect the pads (not shown) on the active surface 180a of the third chip 180 and the pads on the first surface 110a of the circuit board 110, wherein the wires are connected The method can be adjusted according to actual process requirements. On the other hand, the encapsulant 160 can encapsulate the two-stage thermosetting adhesive layer 130, the second chip 150 and the third chip 180.

Since the two-stage thermosetting adhesive layer 130 well protects and fixes the plurality of conductive connectors 120 and the first chip 140, during the process of bonding the second chip 150 and the third chip 180, it can effectively reduce the number of The conductive connecting member 120 and the first chip 140 are displaced or even separated from the circuit substrate, and the probability that the plurality of conductive connecting members 120 are contacted and electrically shorted due to the displacement can be reduced, so as to improve the yield of the chip package structure 100c. It should be noted that the invention does not limit the types of the first chip 140, the second chip 150, and the third chip 180, which may be determined according to actual design requirements.

To sum up, the chip package structure of the present invention first uses a two-stage thermosetting adhesive layer to encapsulate a plurality of conductive connectors and the first chip, and then performs a heating process to completely cure the two-stage thermosetting adhesive layer to provide good protection and Fixing the plurality of conductive connectors and the first chip, thus effectively reducing the displacement or even the difference between the plurality of conductive connectors and the first chip on the circuit substrate during the subsequent stacking of other electronic components (such as the second chip and the third chip) The separation of the circuit substrate can reduce the probability of a plurality of conductive connectors contacting each other due to displacement and electrical short circuit, so as to improve the yield of the chip package structure. In addition, a plurality of solder balls may be fully planted on the second surface of the circuit substrate to increase the external electrical contacts of the chip package structure and further increase the functionality of the chip package structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 100a, 100b, 100c: chip package structure 110: circuit board 110a: first surface 110b: second surface 120: Conductive connector 120a, 130a, 131a, 142a: top surface 130, 131: Two-stage thermosetting adhesive layer 140: The first chip 140a, 150a, 180a: active surface 140b: back 142: Conductive part 150: second chip 152: Solder Ball 160: Encapsulation colloid 170: tin ball 180: third chip

1A to 1D are partial cross-sectional schematic diagrams of a part of a manufacturing method of a chip package structure according to an embodiment of the present invention. 2 is a schematic partial cross-sectional view of a chip package structure according to another embodiment of the invention. 3 is a schematic partial cross-sectional view of a chip package structure according to another embodiment of the invention. 4 is a schematic partial cross-sectional view of a chip package structure according to another embodiment of the invention.

100: Chip package structure

110: circuit board

110a: first surface

110b: second surface

120: Conductive connector

130: Two-stage thermosetting adhesive layer

130a: top surface

140: The first chip

140a: active side

142: Conductive part

Claims (13)

A chip packaging structure, including: A circuit substrate having a first surface and a second surface opposite to the first surface; A plurality of conductive connectors located on the first surface, wherein the plurality of conductive connectors are electrically connected to the circuit substrate; A first chip having an active surface, a back surface opposite to the active surface, and a plurality of conductive portions on the active surface, wherein the first chip is disposed on the first surface with the back surface; and A two-stage thermosetting adhesive layer encapsulates the plurality of conductive connectors and the first chip, and jointly exposes part of the plurality of conductive connectors and the plurality of conductive connectors of the first chip on the same plane unit. According to the chip package structure described in claim 1, wherein the plurality of conductive connecting members surround the first chip. The chip package structure described in the first item of the scope of the patent application further includes a plurality of solder balls located on the second surface and electrically connected to the circuit substrate. The chip package structure described in the first item of the patent application further includes a second chip flip chip on the two-stage thermosetting adhesive layer, and the second chip is connected to the first The chip is electrically connected. The chip package structure according to the fourth item of the scope of patent application further includes a third chip stacked on the second chip, and the third chip is wire-bonded to the circuit substrate. The chip packaging structure described in item 5 of the scope of the patent application further includes a packaging glue that encapsulates the two-stage thermosetting glue layer, the second chip and the third chip. A method for manufacturing a chip packaging structure includes: Providing a circuit substrate, wherein the circuit substrate has a first surface and a second surface opposite to the first surface; Forming a plurality of conductive connecting members on the first surface, wherein the plurality of conductive connecting members are electrically connected to the circuit substrate; Forming a two-stage thermosetting adhesive layer to encapsulate the plurality of conductive connectors; Disposing a first chip on the first surface and embedding the two-stage thermosetting adhesive layer, wherein the first chip has an active surface, a back surface opposite to the active surface, and a plurality of conductive parts on the active surface ;as well as A heating process is performed to completely cure the two-stage thermosetting adhesive layer. According to the manufacturing method of the chip package structure described in item 7 of the scope of patent application, it further includes performing a planarization process on the top surface of the two-stage thermosetting adhesive layer after the heating process, so as to expose the plurality of conductive materials. Section and the plurality of conductive connections. According to the manufacturing method of the chip package structure described in item 7 of the scope of patent application, the two-stage thermosetting adhesive layer is a paste in the process of arranging the first chip on the first surface, so that the A plurality of conductive parts are completely embedded in the two-stage thermosetting adhesive layer. The manufacturing method of the chip package structure as described in item 7 of the scope of the patent application further includes performing a reflow process on the plurality of conductive connections before forming the two-stage thermosetting adhesive layer. According to the manufacturing method of the chip package structure described in item 8 of the scope of patent application, it further includes flip-chip bonding a second chip on the two-stage thermosetting adhesive layer after the planarization process, and the second chip is passed through The plurality of conductive parts are electrically connected to the first chip. The manufacturing method of the chip package structure as described in item 11 of the scope of the patent application further includes stacking and bonding a third chip on the second chip, and wire bonding to the circuit substrate. The manufacturing method of the chip package structure as described in item 12 of the scope of patent application further includes forming a package glue to encapsulate the two-stage thermosetting glue layer, the second chip and the third chip.

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