CN113380721A - Chip packaging structure and manufacturing method thereof - Google Patents

Chip packaging structure and manufacturing method thereof Download PDF

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Publication number
CN113380721A
CN113380721A CN202010625416.8A CN202010625416A CN113380721A CN 113380721 A CN113380721 A CN 113380721A CN 202010625416 A CN202010625416 A CN 202010625416A CN 113380721 A CN113380721 A CN 113380721A
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China
Prior art keywords
chip
adhesive layer
thermosetting adhesive
conductive
circuit substrate
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CN202010625416.8A
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Chinese (zh)
Inventor
周世文
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Publication of CN113380721A publication Critical patent/CN113380721A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a chip packaging structure which comprises a circuit substrate, a plurality of conductive connecting pieces, a first chip and a two-stage thermosetting adhesive layer. The circuit substrate is provided with a first surface and a second surface opposite to the first surface. A plurality of conductive connectors are located on the first surface. The conductive connecting pieces are electrically connected with the circuit substrate. The first chip has an active surface, a back surface opposite to the active surface, and a plurality of conductive portions on the active surface. The first chip is configured on the first surface with a back surface. The two-stage thermosetting adhesive layer encapsulates the plurality of conductive connecting pieces and the first chip, and the plurality of conductive connecting pieces and the plurality of conductive parts of the first chip are exposed on the same plane. A method for manufacturing the chip package structure is also provided.

Description

Chip packaging structure and manufacturing method thereof
Technical Field
The present disclosure relates to chip packages, and particularly to a chip package and a method for manufacturing the same.
Background
In a Multi-Chip Package (MCP), stacking a plurality of chips vertically to save a Package size has been a well-established technology. However, in the multi-chip package structure, the components on the bottom layer of the substrate are easily displaced and even separated from the substrate in the subsequent stacking process, thereby affecting the yield of the package. Therefore, how to effectively reduce the displacement and even the separation of the components at the upper and lower layers of the substrate from the substrate in the subsequent process of stacking other electronic components to improve the packaging yield is one of the problems to be solved at present.
Disclosure of Invention
The invention relates to a chip packaging structure and a manufacturing method thereof, which can effectively reduce the situation that a plurality of conductive connecting pieces on a circuit substrate and a first chip generate displacement or even are separated from the circuit substrate in the subsequent process of stacking other electronic components, and can reduce the probability of mutual contact and electrical short circuit of the plurality of conductive connecting pieces due to the displacement so as to improve the yield of the chip packaging structure.
According to an embodiment of the invention, a chip packaging structure comprises a circuit substrate, a plurality of conductive connecting pieces, a first chip and a two-stage thermosetting adhesive layer. The circuit substrate is provided with a first surface and a second surface opposite to the first surface. A plurality of conductive connectors are located on the first surface. The conductive connecting pieces are electrically connected with the circuit substrate. The first chip has an active surface, a back surface opposite to the active surface, and a plurality of conductive portions on the active surface. The first chip is configured on the first surface with a back surface. The two-stage thermosetting adhesive layer encapsulates the plurality of conductive connecting pieces and the first chip, and the plurality of conductive connecting pieces and the plurality of conductive parts of the first chip are exposed on the same plane.
According to an embodiment of the invention, a method for manufacturing a chip package structure includes providing a circuit substrate, wherein the circuit substrate has a first surface and a second surface opposite to the first surface. A plurality of conductive connecting pieces are formed on the first surface, wherein the plurality of conductive connecting pieces are electrically connected with the circuit substrate. And forming a two-stage thermosetting adhesive layer to encapsulate the plurality of conductive connecting pieces. A first chip is arranged on the first surface and embedded into the two-stage thermosetting adhesive layer, wherein the first chip is provided with an active surface, a back surface opposite to the active surface and a plurality of conductive parts on the active surface. And carrying out a heating process to completely cure the two-stage thermosetting adhesive layer.
Based on the above, in the chip package structure of the invention, the two-stage thermosetting adhesive layer is used to encapsulate the plurality of conductive connecting members and the first chip, and then the heating process is performed to completely cure the two-stage thermosetting adhesive layer, so as to well protect and fix the plurality of conductive connecting members and the first chip, thereby effectively reducing the situation that the plurality of conductive connecting members and the first chip on the circuit substrate displace or even are separated from the circuit substrate in the subsequent process of stacking other electronic components (such as the second chip and the third chip), and reducing the probability of mutual contact and electrical short circuit of the plurality of conductive connecting members due to displacement, so as to improve the yield of the chip package structure.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1D are schematic partial cross-sectional views illustrating a part of a method for manufacturing a chip package structure according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of a portion of a chip package structure according to another embodiment of the invention;
FIG. 3 is a schematic cross-sectional view of a portion of a chip package structure according to another embodiment of the invention;
fig. 4 is a partial cross-sectional view of a chip package structure according to still another embodiment of the invention.
Description of the reference numerals
100. 100a, 100b, 100 c: chip packaging structure
110: circuit substrate
110 a: first surface
110 b: second surface
120: conductive connecting piece
120a, 130a, 131a, 142 a: the top surface
130. 131: two-stage thermosetting adhesive layer
140: first chip
140a, 150a, 180 a: active surface
140 b: back side of the panel
142: conductive part
150: second chip
152: solder ball
160: packaging colloid
170: tin ball
180: third chip
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The same or similar reference numerals denote the same or similar components, and the following paragraphs will not be repeated.
Fig. 1A to fig. 1D are schematic partial cross-sectional views illustrating a part of a method for manufacturing a chip package structure according to an embodiment of the invention. Referring to fig. 1A, first, a circuit substrate 110 is provided, wherein the circuit substrate 110 has a first surface 110a and a second surface 110b opposite to the first surface 110 a. The circuit substrate 110 may be a printed circuit board, but the invention is not limited thereto, and it is within the scope of the invention that the circuit substrate 110 has suitable conductive traces for performing the subsequent required electrical connection.
Referring to fig. 1A, a plurality of conductive connecting members 120 are formed on the first surface 110a of the circuit substrate 110, wherein the plurality of conductive connecting members 120 are electrically connected to the circuit substrate 110. The conductive connection element 120 may be a solder ball, an electroplated bump, an electroless plated bump, a tie-line bump, a conductive polymer bump or a metal composite bump, wherein the solder ball may be a solder ball, and the material of the bump may be selected from the following group: tin, copper, gold, silver, indium, nickel/gold, nickel/palladium/gold, copper/nickel/gold, copper/gold, aluminum, and combinations thereof, but the present invention is not limited thereto. The conductive connection member 120 may be formed by pre-coating solder paste or ball drop (Pick and Place) on the first surface 110a, and performing a reflow (reflow) process to form the conductive connection member 120, wherein the pre-coating solder paste may be prepared by a printing (printing) or electroplating (plating) process, but the invention is not limited thereto.
Referring to fig. 1B, after the conductive connecting members 120 are formed, a two-stage thermosetting adhesive layer 131 is formed to encapsulate the plurality of conductive connecting members 120. The top surface 131a of the two-stage thermosetting adhesive layer 131 may be higher than the top surface 120a of the conductive connecting member 120. In other words, the two-stage thermosetting adhesive layer 131 may cover the conductive connecting element 120, so that the conductive connecting element 120 is not exposed. On the other hand, the two-stage thermosetting adhesive layer 131 may be disposed on the circuit substrate 110 to expose a portion of the side area of the circuit substrate 110.
In the present embodiment, the two-stage thermosetting adhesive layer 131 is, for example, in a semi-cured state. Here, the two-stage thermosetting adhesive layer 131 is, for example, a Liquid (Liquid) at a-stage, a partially cured semi-Solid (Jelly) at B-stage, and a fully cured Solid (Solid) epoxy at C-stage. The method of forming the two-stage thermosetting adhesive layer 131 may include a spin coating process or a screen printing process.
Referring to fig. 1B, the two-stage thermosetting adhesive layer 131 may be coated on the circuit substrate 110 in a liquid state, and then the two-stage thermosetting adhesive layer 131 is pre-cured by a first heating process, such as heating and baking. The pre-cured two-stage thermosetting adhesive layer 131 may further assist the temporary fixation of the conductive connecting member 120 on the first surface 110a of the circuit substrate 110 before the first chip 140 is disposed, but the invention is not limited thereto. On the other hand, the two-stage thermosetting adhesive layer 131 may be located between two adjacent conductive connecting members 120 to electrically isolate the two adjacent conductive connecting members 120.
Referring to fig. 1C, a first chip 140 is disposed on the first surface 110a, wherein the first chip 140 has an active surface 140a, a back surface 140b opposite to the active surface 140a, and a plurality of conductive portions 142 on the active surface 140 a. In the present embodiment, the first chip 140 is disposed on the first surface 110a with the back surface 140 b. In other words, the active surface 140a of the first chip 140 and the plurality of conductive portions 142 are away from the circuit substrate 110. The first chip 140 can be fixed on the circuit substrate 110 through a die attach (die attach) process, and when the die attach process is performed, a glue layer (not shown) needs to be formed on the back surface 140b of the first chip 140 first, and then the first chip 140 is adhered to the circuit substrate 110, because the two-stage thermosetting glue layer 131 is still semi-cured in a glue state in this state, when the die attach (die attach) process is performed on the first chip 140 and fixed on the circuit substrate 110, the first chip 140 can be fixed on the circuit substrate 110 through the two-stage thermosetting glue layer 131. The adhesive layer may be a Die Attach Film (DAF) or other suitable material, but the invention is not limited thereto.
In the present embodiment, the first chip 140 is embedded in the two-stage thermosetting adhesive layer 131. In other words, the two-stage thermosetting adhesive layer 131 encapsulates the first chip 140. The top surfaces 142a of the plurality of conductive parts 142 and the top surfaces 120a of the conductive connectors 120 may be located on the same plane. On the other hand, a plurality of conductive connectors 120 may surround the first chip 140. In other words, the conductive connectors 120 may be located on two sides of the first chip 140, and an orthographic projection of the conductive connectors 120 on the circuit substrate 110 and an orthographic projection of the first chip 140 on the circuit substrate 110 do not overlap.
In the embodiment, when the two-stage thermosetting adhesive layer 131 is pre-cured by the first stage heating process, the second stage heating process may be performed, so that the two-stage thermosetting adhesive layer 131 is pasty in the process of disposing the first chip 140 on the first surface 110a, and the plurality of conductive portions 142 may be completely embedded in the two-stage thermosetting adhesive layer 131. Therefore, the top surface 131a of the two-stage thermosetting adhesive layer 131 may be higher than the top surface 142a of the conductive portion 142. In other words, the two-stage thermosetting adhesive layer 131 may cover the conductive portion 142 such that the top surface 142a of the conductive portion 142 is not exposed.
Referring to fig. 1D, after the first chip 140 is disposed, a heating process is performed to completely cure the two-stage thermosetting adhesive layer 131. That is, after the first chip 140 is disposed, the semi-cured two-stage thermosetting adhesive layer 131 may be heated, so that the semi-cured two-stage thermosetting adhesive layer 131 becomes the fully cured two-stage thermosetting adhesive layer 130. Next, a planarization process is performed on the top surface 130a of the two-stage thermosetting adhesive layer 130 to expose the conductive portions 142 and the conductive connecting members 120, in other words, after the planarization process is performed, a portion of the conductive connecting members 120 and the conductive portions 142 of the first chip 140 are exposed on the same plane (the top surface 130a of the two-stage thermosetting adhesive layer 130) so that the conductive portions 142 and the conductive connecting members 120 can be electrically connected to other electronic components. The planarization process is, for example, a mechanical grinding process (CMP), a chemical-mechanical polishing process (CMP), or other suitable processes or combinations thereof. The fabrication of the chip package structure 100 of the present embodiment can be substantially completed through the above processes.
In the embodiment, the two-stage thermosetting adhesive layer 131 is used to encapsulate the plurality of conductive connecting members 120 and the first chip 140, and then the heating process is performed to completely cure the two-stage thermosetting adhesive layer 131 so as to well protect and fix the plurality of conductive connecting members 120 and the first chip 140, so that the situation that the plurality of conductive connecting members 120 and the first chip 140 on the circuit substrate 110 are displaced or even separated from the circuit substrate in the subsequent process of stacking other electronic components is effectively reduced, and the probability that the plurality of conductive connecting members 120 are in mutual contact and electrically shorted due to the displacement can be reduced, so as to improve the yield of the chip package structure 100.
It should be noted that, in the following embodiments, the component numbers and part of the contents of the above embodiments are used, wherein the same or similar component numbers are used to indicate the same or similar components, and the descriptions of the same technical contents are omitted, and the description of the omitted parts can refer to the foregoing embodiments, and the descriptions of the following embodiments are not repeated.
Fig. 2 is a partial cross-sectional view of a chip package structure according to another embodiment of the invention. Referring to fig. 2, the chip package structure 100a in fig. 2 is different from the chip package structure 100 in fig. 1D in that: after the planarization process shown in fig. 1D, the second chip 150 may be flip-chip bonded on the two-stage thermosetting adhesive layer 130 and electrically connected to the first chip 140 and the circuit substrate 110. For example, the active surface 150a of the second chip 150 faces the first chip 140, and the second chip 150 is electrically connected to the first chip 140 through the plurality of conductive portions 142 and electrically connected to the circuit substrate 110 through the plurality of conductive connectors 120. In an embodiment, the second chip 150 has a plurality of solder balls 152 thereon, wherein a portion of the solder balls 152 corresponds to the plurality of conductive portions 142, and another portion of the solder balls 152 corresponds to the plurality of conductive connectors 120.
Since the two-stage thermosetting adhesive layer 130 well protects and fixes the plurality of conductive connecting members 120 and the first chip 140, in the process of bonding the second chip 150, the situation that the plurality of conductive connecting members 120 on the circuit substrate 110 and the first chip 140 are displaced or even separated from the circuit substrate can be effectively reduced, and the probability that the plurality of conductive connecting members 120 are in mutual contact and electrically shorted due to displacement can be reduced, so as to improve the yield of the chip package structure 100 a.
Fig. 3 is a partial cross-sectional view of a chip package structure according to another embodiment of the invention. Referring to fig. 3, the chip package structure 100b in fig. 3 is different from the chip package structure 100a in fig. 2 in that: after the second chip 150 is disposed, the encapsulant 160 can be formed to encapsulate the two-stage thermosetting adhesive layer 130 and the second chip 150, and a plurality of solder balls 170 can be formed on the second surface 110b and electrically connected to the circuit substrate 110. In this embodiment, the size of the encapsulant 160 may be larger than that of the two-stage thermosetting adhesive layer 130, in other words, a portion of the encapsulant 160 may be located on the circuit substrate 110 on both sides of the two-stage thermosetting adhesive layer 130. However, the invention is not limited thereto, and in other embodiments not shown, the size of the encapsulant 160 may be substantially equal to the size of the two-stage thermosetting adhesive layer 130, so as to expose the side area of the circuit substrate 110. The two-stage thermosetting adhesive layer 130 and the second chip 150 encapsulated by the encapsulant 160 can prevent moisture or external foreign matters from entering, so as to further affect the chip package structure 100b, such as corrosion, short circuit or malfunction, and further improve the yield of the chip package structure 100 b.
On the other hand, as shown in fig. 3, the solder balls 170 may be fully implanted on the second surface 110b of the circuit substrate 110, in other words, the solder balls 170 may be implanted in the center and both sides of the circuit substrate 110 to increase the external electrical contact of the chip package structure 100b, and the chip package structure 100b may be electrically connected to other packages (not shown) through the solder balls 170 to further increase the functionality of the chip package structure 100 b.
Fig. 4 is a partial cross-sectional view of a chip package structure according to still another embodiment of the invention. Referring to fig. 4, the chip package structure 100c in fig. 4 is different from the chip package structure 100b in fig. 3 in that: before forming the encapsulant 160, a third chip 180 may be stacked and bonded on the second chip 150, and wire-bonded on the circuit substrate 110. In other words, the third chip 180 is stacked and bonded on the second chip 150 in a face-up manner, and the active surface 180a of the third chip 180 is away from the second chip 150. For example, as shown in fig. 4, wires may connect pads (not shown) on the active surface 180a of the third chip 180 and pads on the first surface 110a of the circuit substrate 110, wherein the connection manner of the wires may be adjusted according to actual process requirements. On the other hand, the encapsulant 160 may encapsulate the two-stage thermosetting adhesive layer 130, the second chip 150 and the third chip 180.
Since the two-stage thermosetting adhesive layer 130 well protects and fixes the plurality of conductive connecting members 120 and the first chip 140, in the process of bonding the second chip 150 and the third chip 180, the displacement of the plurality of conductive connecting members 120 on the circuit substrate 110 and the separation of the first chip 140 from the circuit substrate can be effectively reduced, and the probability of mutual contact and electrical short circuit of the plurality of conductive connecting members 120 due to the displacement can be reduced, so as to improve the yield of the chip package structure 100 c. It should be noted that the present invention is not limited to the types of the first chip 140, the second chip 150, and the third chip 180, and may depend on the actual design requirement.
In summary, in the chip package structure of the present invention, the two-stage thermosetting adhesive layer is used to encapsulate the plurality of conductive connecting members and the first chip, and then the heating process is performed to completely cure the two-stage thermosetting adhesive layer, so as to protect and fix the plurality of conductive connecting members and the first chip well, thereby effectively reducing the situation that the plurality of conductive connecting members and the first chip on the circuit substrate are displaced or even separated from the circuit substrate in the subsequent process of stacking other electronic components (such as the second chip and the third chip), and reducing the probability of mutual contact and electrical short circuit of the plurality of conductive connecting members due to displacement, so as to improve the yield of the chip package structure. In addition, the solder balls can be fully implanted on the second surface of the circuit substrate to increase the external electrical contact of the chip packaging structure and further increase the functionality of the chip packaging structure.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (13)

1. A chip package structure, comprising:
the circuit substrate is provided with a first surface and a second surface opposite to the first surface;
a plurality of conductive connectors on the first surface, wherein the plurality of conductive connectors are electrically connected to the circuit substrate;
a first chip having an active surface, a back surface opposite to the active surface, and a plurality of conductive portions on the active surface, wherein the first chip is disposed on the first surface with the back surface; and
and the two-stage thermosetting adhesive layer encapsulates the plurality of conductive connecting pieces and the first chip and jointly exposes a part of the plurality of conductive connecting pieces and the plurality of conductive parts of the first chip on the same plane.
2. The chip package structure according to claim 1, wherein the plurality of conductive connectors surround the first chip.
3. The chip package structure according to claim 1, further comprising a plurality of solder balls on the second surface and electrically connected to the circuit substrate.
4. The chip package structure according to claim 1, further comprising a second chip flip-chip on the two-stage thermosetting adhesive layer, wherein the second chip is electrically connected to the first chip through the plurality of conductive portions.
5. The chip package structure according to claim 4, further comprising a third chip stacked on the second chip, wherein the third chip is wire bonded to the circuit substrate.
6. The chip package structure according to claim 5, further comprising an encapsulant encapsulating the two-stage thermosetting adhesive layer, the second chip, and the third chip.
7. A method for manufacturing a chip package structure includes:
providing a circuit substrate, wherein the circuit substrate is provided with a first surface and a second surface opposite to the first surface;
forming a plurality of conductive connecting pieces on the first surface, wherein the plurality of conductive connecting pieces are electrically connected with the circuit substrate;
forming a two-stage thermosetting adhesive layer to encapsulate the plurality of conductive connectors;
disposing a first chip on the first surface and embedded in the two-stage thermosetting adhesive layer, wherein the first chip has an active surface, a backside opposite to the active surface, and a plurality of conductive portions on the active surface; and
and carrying out a heating process to completely cure the two-stage thermosetting adhesive layer.
8. The method for manufacturing a chip package structure according to claim 7, further comprising performing a planarization process on a top surface of the two-stage thermosetting adhesive layer after the heating process is performed to expose the plurality of conductive portions and the plurality of conductive connectors.
9. The method of claim 7, wherein the two-stage thermosetting adhesive layer is in a paste state during the disposing of the first chip on the first surface, such that the plurality of conductive portions are completely embedded in the two-stage thermosetting adhesive layer.
10. The method of manufacturing a chip package structure according to claim 7, further comprising performing a reflow process on the plurality of conductive connectors before forming the two-stage thermosetting adhesive layer.
11. The method of claim 8, further comprising flip-chip bonding a second chip on the two-stage thermosetting adhesive layer after the planarization process, wherein the second chip is electrically connected to the first chip through the plurality of conductive portions.
12. The method of claim 11, further comprising stacking a third chip on the second chip and wire bonding the third chip to the circuit substrate.
13. The method of claim 12, further comprising forming an encapsulant to encapsulate the two-stage thermosetting adhesive layer, the second chip and the third chip.
CN202010625416.8A 2020-03-09 2020-07-01 Chip packaging structure and manufacturing method thereof Pending CN113380721A (en)

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TW109107584A TWI713168B (en) 2020-03-09 2020-03-09 Chip package structure and manufacturing method thereof

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569275A (en) * 2011-12-28 2012-07-11 三星半导体(中国)研究开发有限公司 Stacking type semiconductor packaging structure and manufacturing method thereof
CN104769713A (en) * 2013-01-09 2015-07-08 晟碟半导体（上海）有限公司 Semiconductor device including independent film layer for embedding and/or spacing semiconductor die

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200723495A (en) * 2005-12-07 2007-06-16 Chipmos Technologies Inc Chip package structure
WO2010061552A1 (en) * 2008-11-25 2010-06-03 住友ベークライト株式会社 Electronic component package and electronic component package manufacturing method
US8426255B2 (en) * 2011-09-14 2013-04-23 Chipmos Technologies, Inc. Chip package structure and method for manufacturing the same
JP5680210B2 (en) * 2012-07-17 2015-03-04 日東電工株式会社 Sealing layer-covered semiconductor element and semiconductor device manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569275A (en) * 2011-12-28 2012-07-11 三星半导体(中国)研究开发有限公司 Stacking type semiconductor packaging structure and manufacturing method thereof
CN104769713A (en) * 2013-01-09 2015-07-08 晟碟半导体（上海）有限公司 Semiconductor device including independent film layer for embedding and/or spacing semiconductor die

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