TWI710037B - Stt-mram覆晶磁屏蔽及其製造方法 - Google Patents
Stt-mram覆晶磁屏蔽及其製造方法 Download PDFInfo
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- TWI710037B TWI710037B TW107105267A TW107105267A TWI710037B TW I710037 B TWI710037 B TW I710037B TW 107105267 A TW107105267 A TW 107105267A TW 107105267 A TW107105267 A TW 107105267A TW I710037 B TWI710037 B TW I710037B
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- H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
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Abstract
提供數種在覆晶封裝件內磁屏蔽垂直STT-MRAM結構的所有六面之方法及所產生之裝置。數個具體實施例包括:在晶圓的上表面及鋁焊墊的外部上方形成鈍化堆疊;在該鈍化堆疊上方形成聚合物層;在該鋁焊墊、該聚合物層之數個部分上方且沿著該聚合物層的側壁形成UBM層;在該UBM層上方形成T形銅柱;在該T形銅柱上方形成μ-凸塊;將該晶圓切成複數個晶粒;在各晶粒之底面上方形成環氧樹脂層;在該環氧樹脂層上方且沿著各晶粒、該環氧樹脂層、該鈍化堆疊及該聚合物層的側壁形成磁屏蔽層;以及使該μ-凸塊連接至具有數個BGA球的封裝基板。
Description
本揭示內容係有關於半導體封裝件的設計及製造方法。本揭示內容特別可應用於積體電路(IC)中的自旋轉移力矩(STT)-磁性隨機存取記憶體(MRAM)結構。
例如STT-MRAM晶片的IC晶片通常囊封在保護封裝件中以防止磁性通道接面(MTJ)受到雜散(stray)或外加電磁場的干擾或自旋變化以及防止在後續加工期間受損。為了更好地保護,STT-MRAM結構需要利用屏蔽結構從所有側面予以屏蔽,不過,例如,打線接合封裝(wire-bond packaging)的已知屏蔽方法會因為屏蔽結構未形成閉路而導致有較低的磁性抗擾力,這對垂直STT-MRAM結構而言更是如此。此外,屏蔽結構的較寬開口會導致較低的磁屏蔽效能,例如,磁屏蔽的閾值較差。
參考第1圖的橫截面圖,其圖示打線接合MRAM封裝件中的磁屏蔽,磁性環氧樹脂層101及103各自形成於MRAM結構105之一部分的上方及下方,而保護屏蔽層107係各自形成於環氧樹脂層101及103上方及下
面。不過,如上所述,此設計有問題,因為保護屏蔽層107有寬開口109,會使得MRAM晶粒105暴露而受到外加電磁場的干擾。此外,該打線接合封裝件不能做到系統晶片(SOC)所要求的高密度輸入/輸出(I/O)。
因此,亟須一種方法能夠以覆晶封裝件從六個側面磁性屏蔽垂直STT-MRAM結構。
本揭示內容的一態樣為一種在覆晶封裝件內磁屏蔽垂直STT-MRAM結構的所有六面之方法。
本揭示內容之另一方態樣為一種具有於覆晶封裝件內對於所有六面予以磁屏蔽之垂直STT-MRAM結構的裝置。
本揭示內容的附加態樣及其他特徵會在以下說明中提出以及部份在本技藝一般技術人員審查以下內容或學習本揭示內容的實施後會明白。按照隨附申請專利範圍的特別提示,可實現及得到本揭示內容的優點。
根據本揭示內容,某些技術效果部分可用一種方法達成,包括:在晶圓之上表面及鋁(Al)焊墊之數個外部上方形成鈍化堆疊;在該鈍化堆疊上方形成聚合物層;在該鋁焊墊、該聚合物層之數個部分上方且沿著該聚合物層的側壁形成凸塊下金屬(UBM)層;在該UBM層上方形成T形銅(Cu)柱;在該T形銅柱上方形成μ-凸塊;將該晶圓切成複數個晶粒;在各晶粒之底面上方形成環氧樹脂層;在該環氧樹脂層上方且沿著各晶粒、該環氧樹脂層、
該鈍化堆疊及該聚合物層的側壁形成磁屏蔽層;以及使該μ-凸塊連接至具有數個球格陣列(BGA)球的封裝基板。
本揭示內容之數個態樣包括:用以下步驟形成該鈍化堆疊:在該晶圓及該鋁焊墊上方形成氧化物層;在該氧化物層上方形成氮化物層;以及形成通孔,其係通過圖案化該氮化物層及該氧化物層向下到該鋁焊墊。更有數個態樣包括:在形成該聚合物層之前,在該鈍化堆疊上方形成第二磁屏蔽層;以及在該第二磁屏蔽層、該鋁焊墊之數個部分上方且沿著該第二磁屏蔽層及該鈍化堆疊的側壁形成該聚合物層。另一態樣包括用以下步驟形成該UBM層及該T形銅柱:在該聚合物層及該鋁焊墊上方且沿著該聚合物層的側壁形成UBM層;在位於該鋁焊墊之相對兩側的該UBM層上方形成光阻層;在該UBM層上方且沿著該光阻層的側壁形成銅層;剝除該光阻層;以及移除該UBM層的暴露部分向下到該聚合物層。附加數個態樣包括用以下步驟使該μ-凸塊連接至封裝基板:在該聚合物層與該封裝基板之間形成底膠層。更有數個態樣包括:沿著該鈍化堆疊的側壁形成該UBM層。附加數個態樣包括用以下步驟形成該μ-凸塊:在該T形銅柱上方形成金屬層;以及以200℃至260℃的溫度回焊該金屬層。更有數個態樣包括:在形成磁屏蔽層之前,沿著該UBM層及該T形銅柱的各個側壁形成氮化矽(SiN)間隔件於該聚合物層的數個部分上方;形成第二環氧樹脂層於該聚合物層上方且鄰近各個SiN間隔件;以及在該第二環氧樹脂層上方且沿著該
第二環氧樹脂層的側壁形成第二磁屏蔽層。另一態樣包括用以下步驟使該μ-凸塊連接至封裝基板:在該第二磁屏蔽層與該封裝基板之間形成底膠層。更有數個態樣包括:圖案化在該晶圓之正面上方位於數個μ-凸塊之禁入區(KOZ)四周的該磁屏蔽層。
本揭示內容之數個態樣包括:一種裝置,其包括:有數個BGA球的封裝基板;連接至該封裝基板之上表面的μ-凸塊;在該μ-凸塊上方的銅柱;在該銅柱上的UBM層;在該UBM層之數個部分上方且在該UBM層之側壁上的聚合物層;在該聚合物層上方的鈍化堆疊;在該鈍化堆疊之數個部分及該UBM層上方的鋁焊墊;在該鈍化堆疊及該鋁焊墊上方的晶圓;在該晶圓上方的環氧樹脂層;以及在該環氧樹脂層上方且沿著該環氧樹脂層、該晶圓、該鈍化堆疊及該聚合物層之側壁的磁屏蔽層。
該裝置之數個態樣包括:該鈍化堆疊,其包括:在該聚合物層上方的氮化物層;以及在該氮化物層上方的氧化物層。另一態樣包括:在該聚合物層上方且沿著該聚合物層之側壁的第二磁屏蔽層;在該第二磁屏蔽層上方且沿著該聚合物層之該等側壁的該氮化物層;以及在該氮化物層上方且沿著該聚合物層之該等側壁的該氧化物層。其他數個態樣包括:在該聚合物層與該封裝基板之間的底膠層。更一態樣包括:沿著該UBM層及該銅柱之各個側壁的SiN間隔件;鄰近各個SiN間隔件的第二環氧樹脂層;以及在該第二環氧樹脂層下方且沿著該第二環氧樹
脂層之側壁的第二磁屏蔽層。附加數個態樣包括:在該第二磁屏蔽層與該封裝基板之間的底膠層。另一態樣包括:在該第二環氧樹脂層、該氮化物層及該UBM層之數個部分上方且在該UBM層之側壁上的該聚合物層。其他數個態樣包括:該磁屏蔽層經形成為有0.1毫米(mm)至0.5毫米的厚度。附加數個態樣包括:該磁屏蔽層包括鎳(Ni)-鐵(Fe)合金。
本揭示內容的更一態樣為一種裝置,其包括:有數個BGA球的封裝基板;連接至該封裝基板之上表面的μ-凸塊;在該μ-凸塊上方的銅柱;在該銅柱上的UBM層;沿著該UBM層及該銅柱之各個側壁的SiN間隔件;鄰近各個SiN間隔件的環氧樹脂層;在該第二環氧樹脂層下方且沿著該第二環氧樹脂層之側壁的磁屏蔽層;在該第二磁屏蔽層與該封裝基板之間的底膠層;在該環氧樹脂層、該氮化物層及該UBM層之數個部分上方且在該UBM層之側壁上的聚合物層;在該聚合物層上方的鈍化堆疊;在該鈍化堆疊之數個部分及該UBM層上方的鋁焊墊;在該鈍化堆疊及該鋁焊墊上方的一晶圓;在該晶圓上方的第二環氧樹脂層;以及在該環氧樹脂層上方且沿著該環氧樹脂層、該晶圓、該鈍化堆疊及該聚合物層之側壁的第二磁屏蔽層。
熟諳此藝者由以下詳細說明可明白本揭示內容的其他方面及技術效果,其中係僅以預期可實現本揭示內容的最佳模式舉例描述本揭示內容的具體實施例。應
瞭解,本揭示內容能夠做出其他及不同的具體實施例,以及在各種明顯的方面,能夠修改數個細節而不脫離本揭示內容。因此,附圖及說明內容本質上應被視為圖解說明用而不是用來限定。
101、103‧‧‧磁性環氧樹脂層、環氧樹脂層
105‧‧‧MRAM結構、MRAM晶粒
107‧‧‧保護屏蔽層
109‧‧‧寬開口
201‧‧‧晶圓
201’‧‧‧晶粒
203‧‧‧鋁焊墊
205’‧‧‧氧化物層
207’‧‧‧氮化物層
209‧‧‧鈍化堆疊
211‧‧‧通孔
301’‧‧‧聚合物層
303‧‧‧通孔
305’‧‧‧UBM層
307‧‧‧銅層、T形銅柱
401‧‧‧SiN間隔件
403‧‧‧μ-凸塊
501‧‧‧環氧樹脂層
503‧‧‧磁屏蔽層
601‧‧‧封裝基板
603‧‧‧BGA球
605‧‧‧底膠層
701‧‧‧晶圓
701’‧‧‧晶粒
703‧‧‧鋁焊墊
705、705’‧‧‧氧化物層
707、707’‧‧‧氮化物層
709‧‧‧鈍化堆疊
801、801’‧‧‧磁屏蔽層
901‧‧‧通孔
1001’‧‧‧聚合物層
1003‧‧‧通孔
1005’‧‧‧UBM層
1007‧‧‧銅層、T形銅柱
1009‧‧‧μ-凸塊
1101‧‧‧環氧樹脂層
1103‧‧‧磁屏蔽層
1201‧‧‧封裝基板
1203‧‧‧BGA球
1205‧‧‧底膠層
1301‧‧‧上部
1303‧‧‧側壁
1305‧‧‧磁屏蔽層
1401‧‧‧底部
1403‧‧‧開口
1405‧‧‧KOZ
1501‧‧‧底部
1503‧‧‧開口
1505‧‧‧KOZ
1601‧‧‧底部
1603‧‧‧開口
1605‧‧‧KOZ
1607‧‧‧MRAM區塊
在此用附圖舉例說明而不是限定本揭示內容,圖中類似的元件用相同的元件符號表示。
第1圖的橫截面圖示意圖示打線接合型態MRAM封裝件中的磁屏蔽;第2圖至第6圖的橫截面圖根據一示範具體實施例示意圖示磁屏蔽層之封裝層級加工的製程流程;第7圖至第12圖的橫截面圖根據一示範具體實施例示意圖示磁屏蔽層之晶圓層級加工的製程流程;第13圖的上視圖根據一示範具體實施例圖示覆晶封裝之三維磁屏蔽層的上部及側壁;第14圖的上視圖根據一示範具體實施例圖示有在μ-凸塊之KOZ四周之開口的三維磁屏蔽層之底部;以及第15圖及第16圖的上視圖根據一示範具體實施例圖示覆晶封裝之三維磁屏蔽層的底部。
為了解釋,在以下的說明中,提出許多特定細節供徹底瞭解示範具體實施例。不過,顯然在沒有該等特定細節下或用等價配置仍可實施示範具體實施例。在
其他情況下,眾所周知的結構及裝置用方塊圖圖示以免不必要地混淆示範具體實施例。此外,除非另有說明,在本專利說明書及申請專利範圍中表示成分、反應條件等等之數量、比例及數值性質的所有數字應被理解為在所有情況下可用措辭“約”來修飾。
本揭示內容針對且解決在形成磁屏蔽結構於垂直STT-MRAM裝置後伴隨而來MTJ中受到雜散或外加磁場之干擾或自旋變化的當前問題。尤其是,這個問題的解決係藉由形成只具有在垂直STT-MRAM結構上方之μ-凸塊開口的三維磁屏蔽層。
根據本揭示內容具體實施例的方法包括:在一晶圓的上表面及鋁焊墊的外部上方形成鈍化堆疊。在該鈍化堆疊上方形成聚合物層。形成UBM層於該鋁焊墊、該聚合物層之數個部份且沿著該聚合物層的側壁上方。在該UBM層上方形成一T形銅柱。在該T形銅柱上方形成一μ-凸塊。將該晶圓切成複數個晶粒且在各晶粒之底面上方形成環氧樹脂層。在該環氧樹脂層上方且沿著各晶粒、該環氧樹脂層、該鈍化堆疊及該聚合物層的側壁形成磁屏蔽層,然後將該μ-凸塊連接至具有BGA球的封裝基板。
此外,熟諳此藝者由以下實施方式可明白本揭示內容的其他態樣、特徵及技術效果,其中係僅以預期可實現本揭示內容的最佳模式舉例描述本揭示內容的具體實施例。本揭示內容能夠做出其他及不同的具體實施例,而且能夠修改其在各種不同方面的數個細節。因此,附圖
及說明內容本質上應被視為圖解說明用而不是用來限定。
第2圖至第6圖的橫截面圖根據一示範具體實施例示意圖示磁屏蔽層之封裝層級加工的製程流程。請參考第2圖,例如半導體晶圓或STT-MRAM晶圓的晶圓201設有鋁焊墊203。然後,形成氧化物層205於晶圓201及鋁焊墊203上方。接下來,形成氮化物層207於氧化物層205上方。隨後,圖案化氮化物層207及氧化物層205的數個部分向下到鋁焊墊203,而形成氮化物層207’與氧化物層205’(在此是在鈍化堆疊209之後),以及通孔211。
請參考第3圖,於鈍化堆疊209及通孔211上方形成聚合物層301(為了便於說明而未圖示)。接下來,用微影製程蝕刻數個部分的聚合物層301,而形成聚合物層301’及通孔303。隨後,形成UBM層305於聚合物層301’及通孔303上方,以及形成光阻層(為了便於說明而未圖示)於在鋁焊墊203之相對兩側上的UBM層305上方。接下來,例如用鍍覆法於UBM層305上方並沿著光阻層的側壁形成銅層307。隨後,剝除光阻層,而形成T形銅柱307,以及例如,用濕蝕刻移除數個部分的UBM層305向下到聚合物層301’,而形成UBM層305’。
接下來,例如,於聚合物層301’的部分上方沿著UBM層305’及T形銅柱307之各個側壁用化學氣相沉積(CVD)及蝕刻形成SiN間隔件401,如第4圖所示。然後,例如,藉由以200℃至260℃的溫度回焊錫(Sn)-銀(Ag)合金,形成μ-凸塊403於每個T形銅柱307上方。
然後,將晶圓201切成複數個晶粒201’。
請參考第5圖,形成環氧樹脂層501於各晶粒的頂面及底面上方。隨後,於環氧樹脂層501上方且沿著各晶粒201’、環氧樹脂層501、鈍化堆疊209及聚合物層301’的側壁,用機械方式形成例如由Ni-Fe合金製成、厚度有0.1毫米至0.5毫米的磁屏蔽層503。在這種情況下,於聚合物層301’、氮化物層207’、氧化物層205、晶粒201’及磁屏蔽層503的側壁之間會形成小間隙;不過,也可預期到該等側壁也可鄰近不同的層。
接下來,翻轉單一晶粒201’,然後藉由形成在磁屏蔽層503與封裝基板601之間的底膠層605將μ-凸塊403連接至具有BGA球603的封裝基板601,如第6圖所示。結果,形成具有三維磁屏蔽層503的覆晶封裝件,藉此在各個方向保護在KOZ四周的單一晶粒201’。
第7圖至第12圖的橫截面圖根據一示範具體實施例示意圖示磁屏蔽層之晶圓層級加工的製程流程。請參考第7圖,例如半導體晶圓或STT-MRAM晶圓的晶圓701設有鋁焊墊703。然後,於晶圓701及鋁焊墊703上方依序形成氧化物層705與氮化物層707(以下稱作鈍化堆疊709)。隨後,用物理氣相沉積(PVD)或電化學沉積(ECD)形成例如由Fe-Ni合金製成的磁屏蔽層801於鈍化堆疊709上方,如第8圖所示。然後,磁屏蔽層801與鈍化堆疊709被向下圖案化到鋁焊墊703,而形成磁屏蔽層801’、氮化物層707’、氧化物層705’及通孔901,如第9圖所示。
請參考第10圖,於磁屏蔽層801’及通孔901上方形成聚合物層1001(為了便於說明而未圖示)。然後,用微影製程蝕刻聚合物層1001的數個部分,而形成聚合物層1001’及通孔1003。接下來,形成UBM層1005於聚合物層1001’及通孔1003上方。然後,於在鋁焊墊703之相對兩側上的UBM層1005上方形成光阻層(為了便於說明而未圖示)。接下來,例如,於UBM層1005上方且沿著光阻層的側壁用鍍覆法形成銅層1007。隨後,剝除光阻層,而形成T形銅柱1007且用例如濕蝕刻移除數個部分的UBM層1005,而形成UBM層1005’。之後,例如藉由以200℃至260℃的溫度回焊Sn-Ag合金,形成μ-凸塊1009於每個T形銅柱1007上方。
接下來,晶圓701切成複數個晶粒701’且在各晶粒701’的底面上方形成環氧樹脂層1101,如第11圖所示。隨後,於環氧樹脂層1101上方且沿著各晶粒701’、環氧樹脂層1101、鈍化堆疊709及聚合物層1001’的側壁形成例如由Ni-Fe合金製成、厚度有0.1毫米到0.5毫米的磁屏蔽層1103。如第12圖所示,翻轉複數個晶粒701’,然後藉由形成於聚合物層1001’、封裝基板1201之間的底膠層1205將μ-凸塊1009連接至具有BGA球1203的封裝基板1201。再度形成具有三維磁屏蔽層801’及1103的覆晶封裝件,藉此在各個方向保護在KOZ四周的複數個晶粒701’。
第13圖及第14圖的上視圖根據一示範具
體實施例圖示覆晶封裝之三維磁屏蔽層的上部及底部。請參考第13圖及第14圖,三維磁屏蔽層1305的上部1301及側壁1303囊封複數個晶粒的六個側面中之5個且在μ-凸塊之KOZ 1405四周之開口1403的底部1401囊封該等複數個晶粒的第六面,藉此減少暴露面積且改善所得裝置的磁屏蔽效率。
第15圖及第16圖的上視圖根據一示範具體實施例圖示覆晶封裝之三維磁屏蔽層的底部。請參考第15圖,磁屏蔽層1305的底部1501在μ-凸塊之KOZ 1505內有開口1503,藉此減少暴露面積且改善磁屏蔽效率。第16圖為用於密集I/O SOC之底部屏蔽的另一組態。磁屏蔽層1305的底部1601具有在KOZ 1605四周的開口1603以確保MRAM區塊1607中沒有開口,藉此保護MRAM區塊免受害於任何外加電磁場。
本揭示內容的具體實施例可實現數種技術效果,例如較高的屏蔽效率,以及在保護金屬層中導致磁性抗擾力水平改善的較小開口。此外,本方法具有成本效益,因為保護金屬層在封裝層級形成。此外,由於保護金屬層是預製的而容易製造。根據本揭示內容具體實施例所形成的裝置可用於各種工業應用,例如,微處理器、智慧型手機、行動電話、手機、機上盒、DVD燒錄機及播放機、汽車導航、印表機及周邊設備,網路及電信設備,遊戲系統及數位相機。本揭示內容在產業上可用於包括STT-MRAM的各種半導體裝置。
在以上說明中,特別用數個示範具體實施例描述本揭示內容。不過,顯然仍可做出各種修改及改變而不脫離本揭示內容更寬廣的精神及範疇,如申請專利範圍所述。因此,本專利說明書及附圖應被視為圖解說明用而非限定。應瞭解,本揭示內容能夠使用各種其他組合及具體實施例且在如本文所述的本發明概念範疇內能夠做出任何改變或修改。
201’‧‧‧晶粒
203‧‧‧鋁焊墊
205’‧‧‧氧化物層
207’‧‧‧氮化物層
301’‧‧‧聚合物層
305’‧‧‧UBM層
307‧‧‧銅層、T形銅柱
401‧‧‧SiN間隔件
403‧‧‧μ-凸塊
501‧‧‧環氧樹脂層
503‧‧‧磁屏蔽層
601‧‧‧封裝基板
603‧‧‧BGA球
605‧‧‧底膠層
Claims (20)
- 一種用於製造半導體裝置之方法,該方法包含:在晶圓之上表面及鋁(Al)焊墊之數個外部上方形成鈍化堆疊;在該鈍化堆疊上方形成聚合物層;在該鈍化堆疊上方形成第二磁屏蔽層;在該鋁焊墊、該聚合物層之數個部分上方且沿著該聚合物層的側壁形成凸塊下金屬(UBM)層;在該UBM層上方形成T形銅(Cu)柱;在該T形銅柱上方形成微凸塊(μ-凸塊);將該晶圓切成複數個晶粒;在各晶粒之底面上方形成環氧樹脂層;在該環氧樹脂層上方且沿著各晶粒、該環氧樹脂層、該鈍化堆疊及該聚合物層的側壁形成磁屏蔽層;以及使該μ-凸塊連接至具有數個球格陣列(BGA)球的封裝基板。
- 如申請專利範圍第1項所述之方法,包含藉由以下步驟形成該鈍化堆疊:在該晶圓及該鋁焊墊上方形成氧化物層;在該氧化物層上方形成氮化物層;以及形成通孔,係通過圖案化該氮化物層及該氧化物層向下到該鋁焊墊而形成該通孔。
- 如申請專利範圍第1項所述之方法,更包含: 在形成該聚合物層之前,在該鈍化堆疊上方形成該第二磁屏蔽層;以及在該第二磁屏蔽層、該鋁焊墊之數個部分上方且沿著該第二磁屏蔽層及該鈍化堆疊的側壁形成該聚合物層。
- 如申請專利範圍第3項所述之方法,包含藉由以下步驟形成該UBM層及該T形銅柱:在該聚合物層及該鋁焊墊上方且沿著該聚合物層的側壁形成UBM層;在位於該鋁焊墊之相對兩側上的該UBM層上方形成光阻層;在該UBM層上方且沿著該光阻層的側壁形成銅層;剝除該光阻層;以及移除該UBM層的暴露部分向下到該聚合物層。
- 如申請專利範圍第3項所述之方法,包含藉由以下步驟使該μ-凸塊連接至封裝基板:在該聚合物層與該封裝基板之間形成底膠層。
- 如申請專利範圍第1項所述之方法,更包含:沿著該鈍化堆疊的側壁形成該UBM層。
- 如申請專利範圍第1項所述之方法,包含藉由以下步驟形成該μ-凸塊:在該T形銅柱上方形成金屬層;以及以200℃至260℃的溫度回焊該金屬層。
- 如申請專利範圍第1項所述之方法,更包含: 在形成磁屏蔽層之前,沿著該UBM層及該T形銅柱的各個側壁形成氮化矽(SiN)間隔件於該聚合物層的數個部分上方;形成第二環氧樹脂層於該聚合物層上方且鄰近各個SiN間隔件;以及在該第二環氧樹脂層上方且沿著該第二環氧樹脂層的側壁形成該第二磁屏蔽層。
- 如申請專利範圍第8項所述之方法,包含藉由以下步驟使該μ-凸塊連接至封裝基板:在該第二磁屏蔽層與該封裝基板之間形成底膠層。
- 如申請專利範圍第1項所述之方法,更包含:圖案化在該晶圓之正面上方位於數個μ-凸塊之禁入區(KOZ)四周的該磁屏蔽層。
- 一種半導體裝置,包含:封裝基板,具有數個球格陣列(BGA)球;微凸塊(μ-凸塊),連接至該封裝基板之上表面;銅(Cu)柱,在該μ-凸塊上方;凸塊下金屬(UBM)層,在該銅柱上;聚合物層,在該UBM層之數個部分上方且在該UBM層之側壁上;鈍化堆疊,在該聚合物層上方;鋁(Al)焊墊,在該鈍化堆疊之數個部份及該UBM層上方;晶圓,在該鈍化堆疊及該鋁焊墊上方; 環氧樹脂層,在該晶圓上方;磁屏蔽層,在該環氧樹脂層上方且沿著該環氧樹脂層、該晶圓、該鈍化堆疊及該聚合物層之側壁;以及第二磁屏蔽層,在該鈍化堆疊下方。
- 如申請專利範圍第11項所述之半導體裝置,其中,該鈍化堆疊包含:氮化物層,在該聚合物層上方;以及氧化物層,在該氮化物層上方。
- 如申請專利範圍第11項所述之半導體裝置,其中,該第二磁屏蔽層,在該聚合物層上方且沿著該聚合物層之側壁;該氮化物層,在該第二磁屏蔽層上方且沿著該聚合物層之該等側壁;以及該氧化物層,在該氮化物層上方且沿著該聚合物層之該等側壁。
- 如申請專利範圍第13項所述之半導體裝置,更包含:底膠層,在該聚合物層與該封裝基板之間。
- 如申請專利範圍第11項所述之半導體裝置,更包含:氮化矽(SiN)間隔件,沿著該UBM層及該銅柱之各個側壁;第二環氧樹脂層,鄰近各個SiN間隔件;以及該第二磁屏蔽層,在該第二環氧樹脂層下方且沿著該第二環氧樹脂層之側壁。
- 如申請專利範圍第15項所述之半導體裝置,包含: 底膠層,在該第二磁屏蔽層與該封裝基板之間。
- 如申請專利範圍第15項所述之半導體裝置,包含:該聚合物層,在該第二環氧樹脂層、該氮化物層及該UBM層之數個部分上方且在該UBM層之側壁上。
- 如申請專利範圍第11項所述之半導體裝置,其中,該磁屏蔽層經形成為有0.1毫米(mm)至0.5毫米的厚度。
- 如申請專利範圍第11項所述之半導體裝置,其中,該磁屏蔽層包含鎳(Ni)-鐵(Fe)合金。
- 一種半導體裝置,包含:封裝基板,具有數個球格陣列(BGA)球;微凸塊(μ-凸塊),連接至該封裝基板之上表面;銅(Cu)柱,在該μ-凸塊上方;凸塊下金屬(UBM)層,在該銅柱上;氮化矽(SiN)間隔件,沿著該UBM層及該銅柱之各個側壁;環氧樹脂層,鄰近各個SiN間隔件;磁屏蔽層,在該第二環氧樹脂層下方且沿著該第二環氧樹脂層之側壁;底膠層,在該第二磁屏蔽層與該封裝基板之間;聚合物層,在該環氧樹脂層、該氮化物層及該UBM層之數個部分上方且在該UBM層之側壁上;鈍化堆疊,在該聚合物層上方;鋁(Al)焊墊,在該鈍化堆疊之數個部分及該UBM層上方; 晶圓,在該鈍化堆疊及該鋁焊墊上方;第二環氧樹脂層,在該晶圓上方;以及第二磁屏蔽層,在該環氧樹脂層上方且沿著該環氧樹脂層、該晶圓、該鈍化堆疊及該聚合物層之側壁。
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US10361162B1 (en) * | 2018-01-23 | 2019-07-23 | Globalfoundries Singapore Pte. Ltd. | Magnetic shielding of STT-MRAM in multichip packaging and method of manufacturing the same |
US20200098698A1 (en) * | 2018-09-26 | 2020-03-26 | Intel Corporation | Novel wafer level chip scale package (wlcsp), flip-chip chip scale package (fccsp), and fan out shielding concepts |
US10998489B2 (en) * | 2019-01-14 | 2021-05-04 | Nxp B.V. | Magnetic shielding structure for MRAM array |
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US20220246446A1 (en) * | 2019-07-26 | 2022-08-04 | Nantong Tongfu Microelectronics Co., Ltd | Packaging structure and fabrication method thereof |
KR102208360B1 (ko) * | 2020-04-21 | 2021-01-28 | 엔트리움 주식회사 | 반도체 패키지 및 그 제조 방법 |
US11610848B2 (en) * | 2021-06-07 | 2023-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package, semiconductor device and shielding housing of semiconductor package |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140319522A1 (en) * | 2013-04-25 | 2014-10-30 | International Business Machines Corporation | Far back end of the line metallization method and structures |
US20160359100A1 (en) * | 2015-03-26 | 2016-12-08 | Globalfoundries Singapore Pte. Ltd. | Mram magnetic shielding with fan-out wafer level packaging |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6717241B1 (en) | 2000-08-31 | 2004-04-06 | Micron Technology, Inc. | Magnetic shielding for integrated circuits |
US6936763B2 (en) | 2002-06-28 | 2005-08-30 | Freescale Semiconductor, Inc. | Magnetic shielding for electronic circuits which include magnetic materials |
US6885074B2 (en) | 2002-11-27 | 2005-04-26 | Freescale Semiconductor, Inc. | Cladded conductor for use in a magnetoelectronics device and method for fabricating the same |
DE102004040503A1 (de) | 2004-08-20 | 2006-02-23 | Infineon Technologies Ag | Halbleiterbauelement, Verfahren zur Bearbeitung eines Wafers und Verfahren zur Abschirmung eines Halbleiterbauelements |
US7183617B2 (en) | 2005-02-17 | 2007-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic shielding for magnetically sensitive semiconductor devices |
KR20070077686A (ko) | 2006-01-24 | 2007-07-27 | 삼성전자주식회사 | 비한정형 범프 패드를 갖는 웨이퍼 레벨 칩 스케일 패키지및 그의 제조 방법 |
US7598596B2 (en) | 2006-11-21 | 2009-10-06 | Freescale Semiconductor, Inc. | Methods and apparatus for a dual-metal magnetic shield structure |
US20090184414A1 (en) | 2008-01-22 | 2009-07-23 | Chang Jun Park | Wafer level chip scale package having an enhanced heat exchange efficiency with an emf shield and a method for fabricating the same |
KR101711045B1 (ko) * | 2010-12-02 | 2017-03-02 | 삼성전자 주식회사 | 적층 패키지 구조물 |
CN102623482A (zh) | 2011-02-01 | 2012-08-01 | 飞思卡尔半导体公司 | Mram器件及其装配方法 |
US9799592B2 (en) | 2013-11-19 | 2017-10-24 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
US9070692B2 (en) | 2013-01-12 | 2015-06-30 | Avalanche Technology, Inc. | Shields for magnetic memory chip packages |
JP6401036B2 (ja) * | 2014-12-10 | 2018-10-03 | 株式会社ジェイデバイス | 磁気不揮発性メモリ素子の磁気シールドパッケージ |
US9875971B2 (en) | 2015-03-26 | 2018-01-23 | Globalfoundries Singapore Pte. Ltd. | Magnetic shielding of MRAM package |
TWI565025B (zh) | 2015-10-22 | 2017-01-01 | 力成科技股份有限公司 | 半導體封裝體及其製作方法 |
-
2018
- 2018-01-08 US US15/864,741 patent/US10347826B1/en active Active
- 2018-02-13 TW TW107105267A patent/TWI710037B/zh active
- 2018-03-07 DE DE102018203380.3A patent/DE102018203380B4/de active Active
- 2018-12-05 CN CN201811479247.0A patent/CN110021701B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140319522A1 (en) * | 2013-04-25 | 2014-10-30 | International Business Machines Corporation | Far back end of the line metallization method and structures |
US20160359100A1 (en) * | 2015-03-26 | 2016-12-08 | Globalfoundries Singapore Pte. Ltd. | Mram magnetic shielding with fan-out wafer level packaging |
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US20190214550A1 (en) | 2019-07-11 |
DE102018203380A1 (de) | 2019-07-11 |
CN110021701B (zh) | 2023-08-11 |
US10347826B1 (en) | 2019-07-09 |
TW201931480A (zh) | 2019-08-01 |
CN110021701A (zh) | 2019-07-16 |
DE102018203380B4 (de) | 2024-03-28 |
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