TWI708366B - Electrostatic discharge protection circuit for starting circuit - Google Patents

Abstract

An electrostatic discharge protection circuit for a startup circuit, which is coupled between a source of a junction field effect transistor and an internal analog circuit, is provided. The electrostatic discharge protection circuit includes a resistor, a capacitor, and a blocking transistor. The resistor and the capacitor are connected in series between the source of the junction field effect transistor and a reference voltage. The blocking transistor has a first terminal coupled to the source of the junction field effect transistor, a control terminal receiving a detection voltage, and a second terminal coupled to the internal analog circuit. The detection voltage is response to a node voltage of an intermediate nodes between the resistor and the capacitor.

Description

Electrostatic discharge protection circuit for starting circuit

The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge protection circuit for starting a circuit.

In a high-voltage start-up circuit, the drain terminal of the junction field effect transistor (JFET) is usually directly connected to the power terminal of the integrated circuit (IC), and from the source terminal to the internal circuit. When the power terminal of the integrated circuit is subjected to an electrostatic discharge (ESD) event, the rapid electrostatic discharge may directly pass through the source terminal from the drain terminal of the junction field effect transistor and cause damage to the internal circuit of the source terminal. Therefore, in order to avoid this electrostatic discharge damage, a protection circuit is needed to protect the internal circuits in the integrated circuit.

The invention provides an electrostatic discharge protection circuit for starting a circuit, which can prevent electrostatic discharge current from entering the internal circuit in an integrated circuit to avoid damage to the internal circuit.

The electrostatic discharge protection circuit of the present invention is used for a startup circuit and is coupled between the source of the junction field effect transistor of the startup circuit and the internal analog circuit. The electrostatic discharge protection circuit includes resistors, capacitors, and blocking transistors. The resistor and the capacitor are connected in series between the source of the junction field effect transistor and the reference voltage. The blocking transistor has a first terminal coupled to the source of the surface field effect transistor, a control terminal receiving a detection voltage, and a second terminal coupled to the internal analog circuit, wherein the detection voltage is reflected by the resistance and the capacitor The node voltage between the intermediate nodes.

Based on the foregoing, the electrostatic discharge protection circuit of the embodiment of the present invention, when an electrostatic discharge occurs and is used to receive the power supply terminal of the input voltage, the blocking transistor is cut off to protect the internal analog circuit from electrostatic damage; The power-off crystal is turned on and does not affect the operation of the internal analog circuit.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Fig. 1 is an electrical schematic diagram of a starting circuit according to a first embodiment of the present invention. 1, in this embodiment, the startup circuit 10 at least includes a junction field effect transistor JFET1 and an electrostatic discharge protection circuit 100 for the startup circuit 10, wherein the drain and power terminal of the junction field effect transistor JFET1 Directly coupled to receive the input voltage VIN, the gate and body of the junction field effect transistor JFET1 are coupled to the ground voltage, and the electrostatic discharge protection circuit 100 is coupled to the source of the junction field effect transistor JFET1 and the internal analog circuit Between 11.

The electrostatic discharge protection circuit 100 includes a resistor R1, a capacitor, a blocking transistor TB, and an inverter circuit CTN. The capacitor here is composed of a metal oxide semi-transistor TC1, and the blocking transistor TB is an example of a P-type transistor , But the embodiment of the present invention is not limited thereto.

The capacitor formed by the resistor R1 and the metal oxide semi-transistor TC1 is connected in series between the source of the junction field effect transistor JFET1 and the reference voltage (here, the ground voltage is taken as an example), that is, the resistor R1 is coupled to the junction field Between the source of the effect transistor JFET1 and the intermediate node NC1, the control terminal of the metal oxide semi-transistor TC1 is coupled to the intermediate node NC1, the first and second ends of the metal oxide semi-transistor TC1 are coupled to the reference voltage, and The body terminal of the oxygen semi-transistor TC1 is coupled to the reference voltage.

The inverter circuit CTN is coupled between the intermediate node NC1 and the control terminal of the blocking transistor TB to provide a detection voltage VDT with an inverted voltage in response to the node voltage VC1 of the intermediate node NC1. The blocking transistor TB has a first terminal coupled to the source of the surface field effect transistor JFET1, a control terminal receiving the detection voltage VDT, and a second terminal coupled to the internal analog circuit 11.

When electrostatic discharge occurs at the power supply terminal receiving the input voltage VIN, the transient voltage is conducted to the source of the junction field effect transistor JFET1, and the node voltage VC1 of the intermediate node NC1 is at a low potential due to the capacitive coupling effect, causing the inverter circuit CTN The output detection voltage VDT is equal to the voltage of the source of the junction field effect transistor JFET1, so that the blocking transistor TB is in the off state, blocking the electrostatic discharge voltage of the source of the junction field effect transistor JFET1 from being conducted to the internal analog Circuit 11.

When in normal operation, the node voltage VC1 of the intermediate node NC1 is the same as the source voltage of the junction field effect transistor JFET1, and the detection voltage VDT output by the inverter circuit CTN is at a low level, so that the blocking transistor TB is turned on State, the internal analog circuit 11 can normally accept the input voltage VIN and operate.

In other words, when an electrostatic discharge occurs and is used to receive the power terminal of the input voltage VIN, the blocking transistor TB is cut off to protect the internal analog circuit 11 from static electricity; during normal operation, the blocking transistor TB is turned on without affecting The internal analog circuit 11 operates.

In the embodiment of the present invention, the inverter circuit CTN includes a P-type transistor TP and an N-type transistor TN. The P-type transistor TP has a first terminal coupled to the source of the surface field effect transistor JFET1, a control terminal coupled to the intermediate node NC1, and a second terminal coupled to the control terminal of the blocking transistor TB. The N-type transistor TN has a first terminal coupled to the control terminal of the blocking transistor TB, a control terminal coupled to the intermediate node NC1, and a second terminal coupled to the reference voltage.

Fig. 2 is an electrical schematic diagram of a starting circuit according to a second embodiment of the present invention. 1 and 2, the starting circuit 20 is substantially the same as the starting circuit 10, and the difference lies in the electrostatic discharge protection circuit 200, in which similar or identical components use similar or identical reference numerals. In the electrostatic discharge protection circuit 200, the control terminal of the MOSFET TC2 is coupled to the source of the surface field effect transistor JFET1, and the first terminal and the second terminal of the MOSFET TC2 are coupled to the intermediate node NC2, In addition, the integral terminal of the MOS transistor TC2 is coupled to the reference voltage. The resistor R2 is coupled between the intermediate node NC2 and the reference voltage, and blocks the control terminal of the transistor TB from being coupled to the intermediate node NC2.

When electrostatic discharge occurs at the power terminal receiving the input voltage VIN, the transient voltage is conducted to the source of the junction field effect transistor JFET1, and the node voltage VC2 of the intermediate node NC2 is caused by the capacitive coupling effect and the junction field effect transistor JFET1 The source voltage is the same, so that the blocking transistor TB is in the off state, and the electrostatic discharge voltage of the source of the junction field effect transistor JFET1 is blocked from being conducted to the internal analog circuit 11.

When in normal operation, the node voltage VC2 of the intermediate node NC2 is at a low potential, so that the blocking transistor TB is in a conducting state, and the internal analog circuit 11 can normally accept the input voltage VIN and operate.

Fig. 3 is an electrical schematic diagram of a startup circuit according to a third embodiment of the present invention. 1 and 3, the starting circuit 30 is substantially the same as the starting circuit 10, and the difference lies in the electrostatic discharge protection circuit 300, in which similar or identical components use similar or identical reference numerals. In this embodiment, the electrostatic discharge protection circuit 300 further includes a leakage transistor TK. The leakage transistor TK has a first terminal coupled to the source of the surface field effect transistor JFET1, a control terminal receiving the detection voltage VDT, and The second terminal is coupled to the reference voltage.

In this embodiment, the blocking transistor TB is an example of a P-type transistor, and the leakage transistor TK is an example of an N-type transistor. Here, when electrostatic discharge occurs at the power terminal receiving the input voltage VIN, the detection voltage VDT is equivalent to the voltage of the source of the junction field effect transistor JFET1. At this time, the blocking transistor TB is in the off state to prevent the electrostatic discharge voltage of the source of the junction field effect transistor JFET1 from being conducted to the internal analog circuit 11, and the leakage transistor TK is in the on state to block the junction field effect. The electrostatic discharge voltage of the source of the transistor JFET1 is conducted to the reference voltage.

When in normal operation, the detection voltage VDT is low. At this time, the blocking transistor TB is in the on state, so that the internal analog circuit 11 can normally accept the input voltage VIN for operation, and the leakage transistor TK is in the off state to avoid affecting the operation of the internal analog circuit 11.

In the embodiment of the present invention, the blocking transistor TB takes an N-type transistor as an example, and the leakage transistor TK takes a P-type transistor as an example. At this time, the ESD protection circuit 300 can omit the inverter circuit CTN, that is, the control terminal of the blocking transistor TB can be directly coupled to the intermediate node NC1.

In summary, the electrostatic discharge protection circuit of the embodiment of the present invention, when an electrostatic discharge occurs and is used to receive the power supply terminal of the input voltage, the transistor is blocked to protect the internal analog circuit from electrostatic damage; during normal operation , Blocking the conduction of the transistor does not affect the operation of the internal analog circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 20, 30: start circuit 11: Internal analog circuit 100, 200, 300: Electrostatic discharge protection circuit CTN: Inverting circuit JFET1: Junction field effect transistor NC1, NC2: intermediate nodes R1, R2: resistance TC1, TC2: metal oxide semi-transistor TK: Leakage Transistor TN: N-type transistor TP: P type transistor VC1, VC2: node voltage VDT: Detection voltage VIN: input voltage

Fig. 1 is an electrical schematic diagram of a starting circuit according to a first embodiment of the present invention. Fig. 2 is an electrical schematic diagram of a starting circuit according to a second embodiment of the present invention. Fig. 3 is an electrical schematic diagram of a startup circuit according to a third embodiment of the present invention.

10: Starting circuit

11: Internal analog circuit

100: Electrostatic discharge protection circuit

CTN: Inverting circuit

JFET1: Junction field effect transistor

NC1: intermediate node

R1: resistance

TC1: Metal Oxide Semi-transistor

TN: N-type transistor

TP: P type transistor

VC1: Node voltage

VDT: Detection voltage

VIN: input voltage

Claims (10)

An electrostatic discharge protection circuit for a startup circuit, coupled between a source of a junction field effect transistor of the startup circuit and an internal analog circuit, includes: A resistor and a capacitor in series between the source of the junction field effect transistor and a reference voltage; and A blocking transistor has a first end coupled to the source of the junction field effect transistor, a control end receiving a detection voltage, and a second end coupled to the internal analog circuit, wherein The detection voltage reflects a node voltage of an intermediate node between the resistor and the capacitor. The electrostatic discharge protection circuit according to claim 1, wherein the capacitor is composed of a metal oxide semi-transistor. The electrostatic discharge protection circuit according to claim 2, wherein the resistor is coupled between the source and the intermediate node of the junction field effect transistor, and a control terminal of the metal oxide semi-transistor is coupled to the At the intermediate node, a first terminal and a second terminal of the MOS transistor are coupled to the reference voltage, The electrostatic discharge protection circuit also includes an inverter circuit, which is coupled between the intermediate node and the control terminal of the blocking transistor. The electrostatic discharge protection circuit according to claim 3, wherein the inverter circuit includes: A P-type transistor having a first terminal coupled to the source of the junction field effect transistor, a control terminal coupled to the intermediate node, and a first terminal coupled to the control terminal of the blocking transistor Two ends; and An N-type transistor has a first terminal coupled to the control terminal of the blocking transistor, a control terminal coupled to the intermediate node, and a second terminal coupled to the reference voltage. The electrostatic discharge protection circuit according to claim 3, wherein the integral terminal of the metal oxide semi-transistor is coupled to the reference voltage. The electrostatic discharge protection circuit according to claim 2, wherein a control terminal of the metal oxide semi-transistor is coupled to the source of the junction field effect transistor, a first end of the metal oxide semi-transistor and a The second terminal is coupled to the intermediate node, the resistor is coupled between the intermediate node and the reference voltage, and the control terminal of the blocking transistor is coupled to the intermediate node. The electrostatic discharge protection circuit according to claim 6, wherein the integral terminal of the metal oxide semi-transistor is coupled to the reference voltage. The electrostatic discharge protection circuit according to claim 1, further comprising a leakage transistor having a first terminal coupled to the source electrode of the junction field effect transistor, a control terminal receiving the detection voltage, and A second terminal of the reference voltage is coupled. The electrostatic discharge protection circuit according to claim 8, wherein the blocking transistor is one of a P-type transistor and an N-type transistor, and the leakage transistor is the P-type transistor and the N-type transistor The other of the crystals. The electrostatic discharge protection circuit according to claim 8, wherein the reference voltage is a ground voltage.

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