TWI708279B - Method for manufacturing semiconductor epitaxial wafer - Google Patents

Method for manufacturing semiconductor epitaxial wafer Download PDF

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TWI708279B
TWI708279B TW107138317A TW107138317A TWI708279B TW I708279 B TWI708279 B TW I708279B TW 107138317 A TW107138317 A TW 107138317A TW 107138317 A TW107138317 A TW 107138317A TW I708279 B TWI708279 B TW I708279B
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wafer
semiconductor
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heat treatment
manufacturing
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TW201937558A (en
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廣瀬諒
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日商Sumco股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26566Bombardment with radiation with high-energy radiation producing ion implantation of a cluster, e.g. using a gas cluster ion beam
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures

Abstract

本發明提供一種即便簇離子注入條件相同亦可具有更高的吸除能力的半導體磊晶晶圓的製造方法。本發明的半導體磊晶晶圓的製造方法包括:第1步驟,對半導體晶圓的表面注入包含碳、氫及氧此三種元素作為構成元素的多元素簇離子,於該半導體晶圓的表層部形成所述多元素簇離子的構成元素固溶而成的改質層;第2步驟,於該第1步驟之後,進行用以增大所述改質層內所形成的黑點狀缺陷的缺陷密度的缺陷形成熱處理;以及第3步驟,緊接該第2步驟,於所述半導體晶圓的改質層上形成磊晶層。The invention provides a method for manufacturing a semiconductor epitaxial wafer with higher gettering ability even if the cluster ion implantation conditions are the same. The method for manufacturing a semiconductor epitaxial wafer of the present invention includes: a first step of implanting multi-element cluster ions containing three elements of carbon, hydrogen and oxygen as constituent elements on the surface of the semiconductor wafer A modified layer formed by solid solution of the constituent elements of the multi-element cluster ions is formed; the second step, after the first step, is performed to enlarge the defects of black dot-like defects formed in the modified layer Density defect formation heat treatment; and a third step, following the second step, forming an epitaxial layer on the modified layer of the semiconductor wafer.

Description

半導體磊晶晶圓的製造方法Method for manufacturing semiconductor epitaxial wafer

本發明是有關於一種半導體磊晶晶圓的製造方法。本發明特別是有關於一種發揮更高的吸除(gettering)能力的半導體磊晶晶圓的製造方法。 The invention relates to a method for manufacturing a semiconductor epitaxial wafer. The present invention particularly relates to a method for manufacturing a semiconductor epitaxial wafer that exerts a higher gettering ability.

使半導體器件(device)的特性劣化的主要原因可列舉金屬污染。例如於背面照射型固體攝像元件中,混入至成為該元件的基板的半導體磊晶晶圓中的金屬成為使固體攝像元件的暗電流增加的主要原因,產生被稱為白痕缺陷的缺陷。背面照射型固體攝像元件藉由將配線層等配置於較感測器部更靠下層的位置,而將來自外部的光直接取入至感測器中,於暗處等亦可拍攝更清晰的圖像或動態影像,因此近年來被廣泛地用於數位視訊攝影機(digital video camera)或智慧型電話(smartphone)等行動電話中。因此,期望極力減少白痕缺陷。 The main cause of deterioration of the characteristics of semiconductor devices can be metal contamination. For example, in a back-illuminated solid-state imaging device, metal mixed in a semiconductor epitaxial wafer serving as a substrate of the device becomes a main cause of an increase in dark current of the solid-state imaging device, and a defect called a white mark defect occurs. The backside-illuminated solid-state imaging device arranges the wiring layer and the like on the lower layer than the sensor part, and directly captures the light from the outside into the sensor, so that it can take clearer pictures in dark places. Images or moving images have been widely used in mobile phones such as digital video cameras and smart phones in recent years. Therefore, it is desired to minimize white mark defects.

半導體元件基板中的金屬混入主要是於半導體磊晶晶圓的製造步驟及固體攝像元件的製造步驟(器件製造步驟)中產生。認為前者的半導體磊晶晶圓的製造步驟中的金屬污染是由源自磊晶成長爐的構成材料的重金屬顆粒所致,或者由於使用氯系氣體作為磊晶成長時的爐內氣體,因此是由其配管材料發生金屬 腐蝕而產生的重金屬顆粒所致等。近年來,藉由將磊晶成長爐的構成材料更換成耐腐蝕性優異的材料等而於某種程度上改善了該些金屬污染,但並不充分。另一方面,於後者的固體攝像元件的製造步驟中,於離子注入、擴散及氧化熱處理等各處理中,半導體磊晶晶圓的重金屬污染令人擔憂。 The metal incorporation in the semiconductor device substrate is mainly generated in the manufacturing steps of semiconductor epitaxial wafers and the manufacturing steps of solid-state imaging devices (device manufacturing steps). It is believed that the metal contamination in the manufacturing process of the former semiconductor epitaxial wafer is caused by heavy metal particles originating from the constituent materials of the epitaxial growth furnace, or because chlorine-based gas is used as the furnace gas during epitaxial growth. Generate metal from its piping material Corrosion caused by heavy metal particles, etc. In recent years, the metal contamination has been improved to some extent by replacing the constituent material of the epitaxial growth furnace with a material excellent in corrosion resistance, but this is not sufficient. On the other hand, in the manufacturing steps of the latter solid-state imaging device, heavy metal contamination of the semiconductor epitaxial wafer is worrying during each process such as ion implantation, diffusion, and oxidation heat treatment.

因此,通常藉由在半導體磊晶晶圓上形成用以捕獲金屬的吸除層,來避免對半導體磊晶晶圓的金屬污染。 Therefore, a gettering layer for capturing metal is usually formed on the semiconductor epitaxial wafer to avoid metal contamination of the semiconductor epitaxial wafer.

此處,作為形成吸除層的技術,存在於形成磊晶層之前照射簇離子(cluster ion)的技術。專利文獻1中揭示有於半導體磊晶晶圓的製造方法中,注入包含碳、氫及氧作為構成元素的簇離子的技術。而且,專利文獻1中亦揭示有:藉由注入包含碳、氫及氧此三種元素的簇離子,而形成推斷為由晶格隙矽引起的比較大的尺寸的黑點狀缺陷(專利文獻1中的第2黑點狀缺陷)。根據專利文獻1的實驗結果而暗示出該黑點狀缺陷作為強力的吸除點(gettering site)發揮功能。 Here, as a technique for forming the gettering layer, there is a technique for irradiating cluster ions before forming the epitaxial layer. Patent Document 1 discloses a technique of implanting cluster ions containing carbon, hydrogen, and oxygen as constituent elements in a method of manufacturing a semiconductor epitaxial wafer. Moreover, Patent Document 1 also discloses that by implanting cluster ions containing three elements of carbon, hydrogen, and oxygen, black dot-like defects with a relatively large size presumably caused by lattice silicon are formed (Patent Document 1 The 2nd black dot defect in). According to the experimental results of Patent Document 1, it is suggested that the black dot-shaped defect functions as a strong gettering site.

[現有技術文獻] [Prior Art Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本專利特開2017-157613號公報 [Patent Document 1] Japanese Patent Laid-Open No. 2017-157613

藉由使用專利文獻1中所揭示的簇離子注入技術,可獲得具有極其優異的吸除能力的半導體磊晶晶圓。但是,利用簇離子注 入的吸除點的形成機制及其特性雖於某程度上逐步明瞭,但仍處於研究過程中。特別是關於除了碳及氫以外亦進而包含另外一種以上的元素作為簇離子的構成元素的多元素簇離子,未解明的方面多。以下,於本說明書中,在簇離子的構成元素包含三種以上的元素的情況下,稱為「多元素簇離子」。 By using the cluster ion implantation technique disclosed in Patent Document 1, a semiconductor epitaxial wafer with extremely excellent gettering ability can be obtained. However, using cluster ion implantation Although the formation mechanism and characteristics of the absorption point of entry are gradually understood to a certain extent, it is still in the research process. In particular, there are many unexplained aspects regarding multi-element cluster ions that include one or more other elements as constituent elements of cluster ions in addition to carbon and hydrogen. Hereinafter, in this specification, when the constituent element of the cluster ion contains three or more elements, it is referred to as "multi-element cluster ion".

此處,為了進一步提高專利文獻1中的利用改質層的吸除能力,例如有效的是增多簇離子的劑量。但是,若過於增多劑量,則存在於改質層上所形成的磊晶層中產生大量的磊晶缺陷的情況。如此,於藉由增加劑量來改善吸除能力的方面存在極限。 Here, in order to further improve the gettering ability by the modified layer in Patent Document 1, for example, it is effective to increase the dose of cluster ions. However, if the dose is increased too much, a large number of epitaxial defects may be generated in the epitaxial layer formed on the modified layer. As such, there is a limit in improving the absorption ability by increasing the dose.

因此,就簇離子注入條件以外的觀點而言,期待確立用以進一步提高吸除能力的新的方法。 Therefore, from a viewpoint other than the cluster ion implantation conditions, it is expected to establish a new method to further improve the gettering ability.

因此,本發明的目的在於提供一種即便簇離子注入條件相同亦可具有更高的吸除能力的半導體磊晶晶圓的製造方法。 Therefore, the object of the present invention is to provide a method for manufacturing a semiconductor epitaxial wafer that has higher gettering ability even if the cluster ion implantation conditions are the same.

為了解決所述課題,本發明者進行了努力研究。而且,本發明者對如下情況進行了研究:代替簇離子注入條件而調整磊晶成長條件,藉此能否提高吸除能力。此處,使用圖1說明伴隨磊晶成長處理的熱處理順序(sequence)的通常的概念圖。該熱處理順序可大致區分為如下三個過程:(i)將半導體晶圓投入至磊晶成長爐內後,直至到達磊晶成長溫度為止的升溫過程;(ii)於半導體晶圓表面上使磊晶層成長的磊晶成長過程;(iii)形成磊晶層後,直至自磊晶成長爐取出所獲得的半導體磊晶晶圓為止的降溫 過程。 In order to solve the above-mentioned problems, the inventors conducted diligent studies. In addition, the inventors of the present invention conducted studies on whether the conditions for the growth of epitaxial crystals can be adjusted instead of the cluster ion implantation conditions to improve the gettering ability. Here, a general conceptual diagram of the heat treatment sequence (sequence) accompanying the epitaxial growth process will be explained using FIG. 1. The heat treatment sequence can be roughly divided into the following three processes: (i) After the semiconductor wafer is put into the epitaxial growth furnace, the temperature rise process until the epitaxial growth temperature is reached; (ii) the epitaxy is applied on the surface of the semiconductor wafer The epitaxial growth process of the growth of the epitaxial layer; (iii) After the epitaxial layer is formed, the temperature drop until the obtained semiconductor epitaxial wafer is taken out from the epitaxial growth furnace process.

本發明者進行了努力研究,結果得知成為吸除點的黑點狀缺陷的生成數量大幅依存於所述(i)升溫過程。而且,本發明者得知:藉由進行兼作為用以增大黑點狀缺陷的缺陷密度的缺陷形成熱處理的升溫過程,即便簇離子注入條件相同,亦可進一步提高吸除能力。本發明是基於所述見解而完成,其主旨構成如下所述。 The inventors conducted diligent studies, and as a result, it was found that the number of generation of black dot-like defects that serve as suction points greatly depends on the (i) heating process. Furthermore, the inventors learned that by performing a heating process that also serves as a defect formation heat treatment for increasing the defect density of black spot defects, even if the cluster ion implantation conditions are the same, the gettering ability can be further improved. The present invention was completed based on the above knowledge, and its gist structure is as follows.

(1)一種半導體磊晶晶圓的製造方法,其特徵在於包括:第1步驟,對半導體晶圓的表面注入包含碳、氫及氧此三種元素作為構成元素的多元素簇離子,於該半導體晶圓的表層部形成所述多元素簇離子的構成元素固溶而成的改質層;第2步驟,於該第1步驟之後,進行用以增大所述改質層內所形成的黑點狀缺陷的缺陷密度的缺陷形成熱處理;以及第3步驟,緊接該第2步驟,於所述半導體晶圓的改質層上形成磊晶層。 (1) A method for manufacturing a semiconductor epitaxial wafer, which is characterized in that it comprises: a first step of implanting multi-element cluster ions containing three elements of carbon, hydrogen and oxygen as constituent elements into the surface of the semiconductor wafer. A modified layer formed by solid solution of the constituent elements of the multi-element cluster ions is formed on the surface layer of the wafer; the second step, after the first step, is performed to increase the blackness formed in the modified layer The defect formation heat treatment of the defect density of point defects; and the third step, following the second step, forming an epitaxial layer on the modified layer of the semiconductor wafer.

(2)如所述(1)所記載的半導體磊晶晶圓的製造方法,其中所述第2步驟中的所述缺陷形成熱處理的熱處理條件中,於小於800℃的第1溫度區域保持所述半導體晶圓的第1保持時間為0秒以上且45秒以下,且自第1溫度區域升溫後的、於800℃以上且小於1000℃的第2溫度區域保持所述半導體晶圓的第2保持時間為30秒以上。 (2) The method for manufacturing a semiconductor epitaxial wafer as described in (1), wherein in the heat treatment conditions of the defect formation heat treatment in the second step, the heat treatment conditions are maintained in a first temperature region less than 800°C. The first holding time of the semiconductor wafer is 0 second or more and 45 seconds or less, and the second temperature region of the semiconductor wafer is maintained in the second temperature region of 800°C or more and less than 1000°C after the temperature rise from the first temperature region The holding time is more than 30 seconds.

(3)如所述(1)或(2)所記載的半導體磊晶晶圓的製造方法,其中所述多元素簇離子的構成元素由碳、氫及氧此三種元素所組成。 (3) The method for manufacturing a semiconductor epitaxial wafer as described in (1) or (2), wherein the constituent elements of the multi-element cluster ion are composed of three elements: carbon, hydrogen, and oxygen.

(4)如所述(1)至(3)中任一項所記載的半導體磊晶晶圓的製造方法,其中所述半導體晶圓為矽晶圓。 (4) The method for manufacturing a semiconductor epitaxial wafer according to any one of (1) to (3), wherein the semiconductor wafer is a silicon wafer.

根據本發明,可提供一種即便簇離子注入條件相同亦可具有更高的吸除能力的半導體磊晶晶圓的製造方法。 According to the present invention, it is possible to provide a method for manufacturing a semiconductor epitaxial wafer that has a higher gettering ability even if the cluster ion implantation conditions are the same.

10:半導體晶圓 10: Semiconductor wafer

10A:半導體晶圓的表面 10A: Surface of semiconductor wafer

16:簇離子 16: cluster ion

18:改質層 18: modified layer

20:磊晶層 20: epitaxial layer

100:半導體磊晶晶圓 100: Semiconductor epitaxial wafer

D:黑點狀缺陷 D: Black spot defects

圖1是表示伴隨磊晶成長的通常的熱處理順序的概念圖。 Fig. 1 is a conceptual diagram showing a general heat treatment sequence accompanying epitaxial growth.

圖2是表示參考實驗例1中的磊晶矽晶圓的基板界面附近的穿透式電子顯微鏡(Transmission Electron Microscope,TEM)剖面圖的圖。 2 is a diagram showing a cross-sectional view of a transmission electron microscope (Transmission Electron Microscope, TEM) in the vicinity of the substrate interface of the epitaxial silicon wafer in Reference Experimental Example 1. FIG.

圖3是表示參考實驗例2中的磊晶矽晶圓的基板界面附近的TEM剖面圖的圖。 3 is a diagram showing a TEM cross-sectional view near the substrate interface of the epitaxial silicon wafer in Reference Experimental Example 2. FIG.

圖4是說明本發明的一實施形態的伴隨磊晶成長的熱處理順序的一態樣的示意剖面圖。 4 is a schematic cross-sectional view illustrating an aspect of a heat treatment sequence accompanying epitaxial growth in an embodiment of the present invention.

圖5中的(A)至(C)是說明本發明的一實施形態的半導體磊晶晶圓100的製造方法的示意剖面圖。 (A) to (C) in FIG. 5 are schematic cross-sectional views illustrating a method of manufacturing a semiconductor epitaxial wafer 100 according to an embodiment of the present invention.

於實施形態的詳細說明之前,首先對完成本發明的實驗 (參考實驗例1、參考實驗例2)進行說明。 Before the detailed description of the embodiment, the experiment of the present invention (Refer to Experimental Example 1, Reference Experimental Example 2) for description.

[參考實驗例1] [Reference experiment example 1]

準備由CZ單晶矽錠獲得的矽晶圓(直徑:300mm,厚度:725μm,摻雜劑種類:磷,電阻率:10Ω.cm)。繼而,使用簇離子產生裝置(日新離子機器公司製造,型號:克拉麗絲(CLARIS)(註冊商標)),將包含使二乙基醚(C4H10O)簇離子化而成的CH3O的多元素簇離子以加速電壓80keV/Cluster的注入條件注入至矽晶圓的表面。另外,將該簇離子的劑量設為1.0×1015cluster/cm2Prepare a silicon wafer (diameter: 300mm, thickness: 725μm, dopant type: phosphorus, resistivity: 10Ω·cm) obtained from CZ single crystal silicon ingots. Then, using a cluster ion generator (manufactured by Nisshin Ion Instruments Co., Ltd., model: CLARIS (registered trademark)), the CH containing the cluster ionized diethyl ether (C 4 H 10 O) Multi-element cluster ions of 3 O are injected into the surface of the silicon wafer under the conditions of an acceleration voltage of 80 keV/Cluster. In addition, the dose of the cluster ion is 1.0×10 15 cluster/cm 2 .

其次,將所述矽晶圓搬送至高速熱處理裝置(海索爾(hisol)公司製造,型號艾庫薩摩(AccuThermo)Aw610)內。而且,為了進行模擬1100℃、300秒的磊晶成長的熱處理(以下,模擬成長熱處理),而於氮氣氣體環境下,以如下條件進行熱處理。 Secondly, the silicon wafer is transported to a high-speed thermal processing device (made by Hisol, model AccuThermo Aw610). Furthermore, in order to perform a heat treatment that simulates epitaxial growth at 1100° C. for 300 seconds (hereinafter, simulated growth heat treatment), the heat treatment is performed under the following conditions in a nitrogen atmosphere.

爐內投入溫度:500℃ Input temperature in the furnace: 500℃

直至模擬成長溫度為止的升溫速率:60℃/s Heating rate until the simulated growth temperature: 60℃/s

(樣品2~樣品4) (Sample 2~Sample 4)

除了將樣品1中的升溫速率60℃/s變更為15℃/s、8℃/s、4℃/s以外,與樣品1同樣地分別製作樣品2~樣品4。 Samples 2 to 4 were produced in the same manner as in sample 1, except that the heating rate of 60°C/s in sample 1 was changed to 15°C/s, 8°C/s, and 4°C/s.

對於樣品1~樣品4各樣品,取得進行模擬成長熱處理前後的TEM剖面。將結果示於圖2中。 For each sample of sample 1 to sample 4, TEM cross-sections before and after the simulated growth heat treatment were obtained. The results are shown in Figure 2.

[參考實驗例2] [Reference experiment example 2]

(樣品5) (Sample 5)

以與樣品1相同的條件,將包含CH3O的多元素簇離子注入 至矽晶圓的表面。繼而,為了進行800℃、300秒的模擬成長熱處理,而與參考實驗例1同樣地將簇離子注入後的矽晶圓搬送至高速熱處理裝置(海索爾(hisol)公司製造)內,並且以如下條件進行熱處理。 Under the same conditions as the sample 1, a multi-element cluster containing CH 3 O was ion implanted onto the surface of the silicon wafer. Then, in order to perform a simulated growth heat treatment at 800°C for 300 seconds, the silicon wafer after the cluster ion implantation was transferred to a high-speed heat treatment device (manufactured by Hisol) in the same manner as in Reference Experimental Example 1. The heat treatment is performed under the following conditions.

爐內投入溫度:500℃ Input temperature in the furnace: 500℃

直至模擬成長溫度為止的升溫速率:8℃/s The heating rate until the simulated growth temperature: 8℃/s

(樣品6~樣品8) (Sample 6~Sample 8)

除了將樣品5中的模擬成長熱處理的熱處理溫度800℃變更為900℃、1000℃、1100℃以外,與樣品5同樣地分別製作樣品6~樣品8。 Except that the heat treatment temperature of the simulated growth heat treatment in the sample 5 was changed from 800°C to 900°C, 1000°C, and 1100°C, samples 6 to 8 were produced in the same manner as in sample 5.

對於樣品5~樣品8各樣品,取得進行模擬磊晶成長的熱處理後的TEM剖面。將結果示於圖3中。 For each sample of Sample 5 to Sample 8, a TEM section after the heat treatment to simulate epitaxial growth was obtained. The results are shown in Figure 3.

<參考實驗例1、參考實驗例2的考察> <Review of Reference Experiment Example 1, Reference Experiment Example 2>

首先,基於根據參考實驗例1的圖2,可確認到:於1100℃、300秒的模擬成長熱處理前,所形成的黑點狀缺陷的缺陷密度並不大幅依存於升溫速率。另一方面,於模擬成長熱處理後,黑點狀缺陷的缺陷密度雖均減少,但其減少量大幅依存於升溫速率。 First, based on Fig. 2 according to Reference Experimental Example 1, it can be confirmed that the defect density of black dot-like defects formed before the simulated growth heat treatment at 1100°C for 300 seconds does not greatly depend on the heating rate. On the other hand, after the simulated growth heat treatment, although the defect density of black dot-like defects is reduced, the amount of reduction greatly depends on the heating rate.

而且,基於根據參考實驗例2的圖3,可確認到:藉由800℃、900℃及1000℃的模擬成長熱處理而黑點狀缺陷的生成量比較大。 Furthermore, based on Fig. 3 according to Reference Experimental Example 2, it can be confirmed that the amount of generation of black spot defects is relatively large by the simulated growth heat treatment at 800°C, 900°C, and 1000°C.

若綜合考慮以上結果,則認為是如下假設:經簇離子注入的矽晶圓若受到800℃以上且小於1000℃的熱處理,則黑點狀 缺陷成長,另一方面,若小於800℃,則黑點狀缺陷種其自身消失,若受到1000℃以上的熱處理,則黑點狀缺陷分解。將基於該假設的熱處理順序示於圖4中。樣品1~樣品3中,小於800℃的黑點狀缺陷種消失的溫度帶的通過時間雖然比較短,但黑點狀缺陷成長的溫度帶的通過時間亦比較短。樣品4中,小於800℃的黑點狀缺陷種消失的溫度帶的通過時間雖然比較長,但若受到800℃以上且小於1000℃的熱處理,則黑點狀缺陷成長的時間亦長。因此推測,如圖2上段的TEM剖面照片般,於模擬成長熱處理前的狀態下,黑點狀缺陷的缺陷密度是以相同程度被觀察到。而且,如圖2下段的TEM剖面照片般,於模擬成長熱處理後,黑點狀缺陷的缺陷密度產生非偶然的差異。 If the above results are considered comprehensively, it is considered as the following assumption: if a silicon wafer implanted with cluster ions is subjected to a heat treatment at 800°C or more and less than 1000°C, it will be black dots. Defects grow. On the other hand, if it is less than 800°C, the black spot-like defect species itself disappears, and if it is subjected to heat treatment at 1000°C or higher, the black spot-like defect is decomposed. The heat treatment sequence based on this assumption is shown in FIG. 4. In samples 1 to 3, although the passage time of the temperature zone where the black dot-shaped defect species disappeared less than 800°C was relatively short, the passage time of the temperature zone where the black dot-shaped defect grew was also relatively short. In Sample 4, although the passage time of the temperature zone where the black spot-shaped defect species of less than 800°C disappeared was relatively long, if it was subjected to a heat treatment of 800°C or higher and less than 1000°C, the black spot-shaped defect grew for a long time. Therefore, it is inferred that, as in the TEM cross-sectional photograph in the upper part of FIG. 2, in the state before the simulated growth heat treatment, the defect density of black dot-like defects is observed to the same degree. Moreover, as shown in the TEM cross-sectional photograph in the lower part of FIG. 2, after the simulated growth heat treatment, the defect density of the black dot-like defects has a non-incidental difference.

因此,本發明者得知:藉由在形成磊晶層之前進行用以增大改質層內所形成的黑點狀缺陷的缺陷密度的缺陷形成熱處理,可提高吸除能力。 Therefore, the inventors learned that by performing defect formation heat treatment for increasing the defect density of black dot-shaped defects formed in the modified layer before forming the epitaxial layer, the gettering ability can be improved.

基於以上實驗結果,一邊參照所述圖4的熱處理順序及圖5中的(A)至(C)的表示製造流程的示意剖面圖,一邊對本發明的一實施形態的磊晶矽晶圓的雜質擴散舉動預測方法進行說明。再者,圖5中的(A)至(C)中,為了便於說明而與實際的厚度的比例不同,相對於半導體晶圓10而誇張地示出改質層18及磊晶層20的厚度。 Based on the above experimental results, while referring to the heat treatment sequence in FIG. 4 and the schematic cross-sectional views of (A) to (C) in FIG. 5 showing the manufacturing process, the impurity of the epitaxial silicon wafer according to an embodiment of the present invention The spreading behavior prediction method is explained. In addition, in (A) to (C) in FIG. 5, for convenience of explanation, the ratio of the actual thickness is different, and the thickness of the modified layer 18 and the epitaxial layer 20 is exaggeratedly shown with respect to the semiconductor wafer 10 .

(半導體磊晶晶圓的製造方法) (Method of manufacturing semiconductor epitaxial wafer)

依照本發明的一實施形態的半導體磊晶晶圓100的製造方法 包括:第1步驟,對半導體晶圓10的表面10A注入包含三種元素以上的元素作為構成元素的多元素簇離子16,於該半導體晶圓10的表層部形成多元素簇離子16的構成元素固溶而成的改質層18(圖5中的(A)至(C)的步驟A、步驟B);第2步驟,於該第1步驟之後,進行用以增大改質層18內所形成的黑點狀缺陷D的缺陷密度的缺陷形成熱處理;以及第3步驟,緊接該第2步驟,於半導體晶圓的改質層18上形成磊晶層(圖5中的(A)至(C)的步驟C)。此處,多元素簇離子16的構成元素包含碳、氫及氧。以下,為了簡略化,存在將包含碳、氫及氧作為構成元素的多元素簇離子簡稱為「CHO簇」的情況。CHO簇可包含碳、氫及氧以外的元素作為構成元素,亦可設為僅碳、氫及氧此三種元素。再者,圖5中的(A)至(C)的步驟C是由該製造方法的結果所得的半導體磊晶晶圓100的示意剖面圖。磊晶層20成為用以製造背面照射型固體攝像元件等半導體元件的器件層。半導體晶圓10為矽晶圓,磊晶層20為矽磊晶層的磊晶矽晶圓為半導體磊晶晶圓100的較佳態樣之一。以下,依次對各步驟的詳細情況進行說明。 Method for manufacturing semiconductor epitaxial wafer 100 according to an embodiment of the present invention Including: the first step is to implant multi-element cluster ions 16 containing three or more elements as constituent elements into the surface 10A of the semiconductor wafer 10, and form the constituent element solids of the multi-element cluster ions 16 on the surface of the semiconductor wafer 10 The melted modified layer 18 (step A and step B of (A) to (C) in FIG. 5); the second step, after the first step, is performed to increase the inside of the modified layer 18 The formed black dot-shaped defects D are formed by the defect density of the defect formation heat treatment; and the third step, following the second step, is to form an epitaxial layer on the modified layer 18 of the semiconductor wafer ((A) to (A) to (C) Step C). Here, the constituent elements of the multi-element cluster ion 16 include carbon, hydrogen, and oxygen. Hereinafter, for simplification, the multi-element cluster ion containing carbon, hydrogen, and oxygen as constituent elements may be simply referred to as "CHO cluster". The CHO cluster may include elements other than carbon, hydrogen, and oxygen as constituent elements, or may be set to only three elements of carbon, hydrogen, and oxygen. Furthermore, step C from (A) to (C) in FIG. 5 is a schematic cross-sectional view of the semiconductor epitaxial wafer 100 obtained as a result of the manufacturing method. The epitaxial layer 20 serves as a device layer for manufacturing semiconductor elements such as back-illuminated solid-state imaging elements. The semiconductor wafer 10 is a silicon wafer, and the epitaxial silicon wafer with the epitaxial layer 20 being a silicon epitaxial layer is one of the preferred aspects of the semiconductor epitaxial wafer 100. Hereinafter, the details of each step will be described in order.

<第1步驟> <Step 1>

本發明中的第1步驟(圖5中的(A)至(C)的步驟A、步驟B)中,如所述般,對半導體晶圓10的表面10A注入包含三種元素以上的元素作為構成元素的多元素簇離子16,於該半導體晶圓10的表層部形成多元素簇離子16的構成元素固溶而成的改質層18。第1步驟中所使用的多元素簇離子16如所述般包含碳、氫 及氧作為構成元素。 In the first step of the present invention (step A and step B of (A) to (C) in FIG. 5), as described above, the surface 10A of the semiconductor wafer 10 is implanted with an element containing three or more elements as a constituent The multi-element cluster ions 16 of the element form a modified layer 18 in which constituent elements of the multi-element cluster ions 16 are solid-dissolved on the surface portion of the semiconductor wafer 10. The multi-element cluster ion 16 used in the first step contains carbon and hydrogen as described above. And oxygen as a constituent element.

<<半導體晶圓>> <<Semiconductor Wafer>>

作為半導體晶圓10,例如可列舉:包含矽、化合物半導體(GaAs、GaN、SiC)且於表面不具有磊晶層的塊狀的單晶晶圓。於製造背面照射型固體攝像元件的情況下,通常使用塊狀的單晶矽晶圓。另外,半導體晶圓10可使用利用線鋸(wire saw)等將藉由柴可斯基法(Czochralski,CZ法)或浮融區法(Floating Zone,FZ法)所育成的單晶矽錠切片(slice)所得的晶圓。另外,為了獲得更高的吸除能力,亦可於半導體晶圓10中添加碳及/或氮。進而,亦可於半導體晶圓10中添加規定濃度的任意的摻雜劑,製成所謂n+型或者p+型、或n-型或者p-型的基板。 As the semiconductor wafer 10, for example, a bulk single crystal wafer containing silicon and compound semiconductors (GaAs, GaN, SiC) and having no epitaxial layer on the surface is mentioned. In the case of manufacturing a back-illuminated solid-state imaging device, a bulk single crystal silicon wafer is generally used. In addition, the semiconductor wafer 10 can be sliced by using a wire saw (Czochralski, CZ method) or a floating zone method (Floating Zone, FZ method) to slice a single crystal silicon ingot. (Slice) the resulting wafer. In addition, in order to obtain higher gettering ability, carbon and/or nitrogen may also be added to the semiconductor wafer 10. Furthermore, an arbitrary dopant at a predetermined concentration may be added to the semiconductor wafer 10 to form a so-called n+ type or p+ type, or n- type or p- type substrate.

另外,作為半導體晶圓10,亦可使用於塊狀半導體晶圓表面上形成有半導體磊晶層的磊晶晶圓。例如為於塊狀單晶矽晶圓的表面上形成有矽磊晶層的磊晶矽晶圓。該矽磊晶層可藉由化學氣相沈積(Chemical Vapor Deposition,CVD)法於通常的條件下形成。磊晶層較佳為將厚度設為0.1μm~20μm的範圍內,更佳為設為0.2μm~10μm的範圍內。 In addition, as the semiconductor wafer 10, an epitaxial wafer having a semiconductor epitaxial layer formed on the surface of a bulk semiconductor wafer can also be used. For example, it is an epitaxial silicon wafer with a silicon epitaxial layer formed on the surface of a bulk single crystal silicon wafer. The silicon epitaxial layer can be formed by chemical vapor deposition (CVD) method under normal conditions. The thickness of the epitaxial layer is preferably in the range of 0.1 μm to 20 μm, and more preferably in the range of 0.2 μm to 10 μm.

<<簇離子照射>> <<Cluster ion irradiation>>

此處,所謂本說明書中的「簇離子」,是藉由如下方式而獲得:利用電子碰撞法使電子與氣體狀分子相撞而使氣體狀分子的鍵結解離,藉此製成多種原子數的原子集合體,並產生碎片(fragment)而使該原子集合體離子化,並且進行經離子化的多種原子數的原 子集合體的質量分離,進而抽出特定質量數的經離子化的原子集合體。即,簇離子為對多個原子集合成塊而成的簇賦予正電荷或負電荷並加以離子化而成者,可明確區別為碳離子等單原子離子、或一氧化碳離子等單分子離子。 Here, the so-called "cluster ion" in this specification is obtained by using the electron collision method to collide electrons with gaseous molecules to dissociate the bonds of the gaseous molecules, thereby making various atomic numbers Atom aggregates, and generate fragments (fragment) to ionize the atom aggregates, and perform ionized atoms of various atomic numbers The masses of the sub-aggregates are separated, and then the ionized atom aggregates of a specific mass number are extracted. That is, cluster ions are those obtained by imparting positive or negative charges to clusters formed by agglomerating a plurality of atoms and ionizing them, and can be clearly distinguished as monoatomic ions such as carbon ions or monomolecular ions such as carbon monoxide ions.

於對作為半導體晶圓10的矽晶圓照射簇離子的情況下,若將簇離子照射至矽晶圓,則因其能量而瞬間成為1350℃~1400℃左右的高溫狀態,矽熔解。其後,矽經急速冷卻,簇離子的構成元素於矽晶圓中的表面附近固溶。即,所謂本說明書中的「改質層」,是指所照射的離子的構成元素固溶於矽晶圓表層部的結晶的晶格隙位置或置換位置而成的層。作為構成元素的一例,例如若著眼於碳,則由二次離子質譜分析法(Secondary Ion Mass Spectrometry,SIMS)所得的矽晶圓的深度方向上的碳的濃度分佈(profile)雖依存於簇離子的加速電壓及簇尺寸,但與單體離子的情況相比變尖銳(sharp),所照射的碳局部地存在的區域(即改質層)的厚度大致成為500nm以下(例如50nm~400nm左右)。因此,於多元素簇離子16的構成元素包含碳等有助於吸除的元素的情況下,改質層18作為強力的吸除點發揮功能。 In the case of irradiating cluster ions to the silicon wafer as the semiconductor wafer 10, if the cluster ions are irradiated to the silicon wafer, the energy instantly becomes a high temperature state of about 1350°C to 1400°C, and the silicon melts. Thereafter, the silicon is rapidly cooled, and the constituent elements of cluster ions are dissolved in the vicinity of the surface of the silicon wafer. That is, the "modified layer" in this specification refers to a layer in which constituent elements of the irradiated ions are solid-dissolved in the crystal lattice positions or replacement positions of the crystals on the surface of the silicon wafer. As an example of a constituent element, for example, if the focus is on carbon, the concentration profile of carbon in the depth direction of a silicon wafer obtained by Secondary Ion Mass Spectrometry (SIMS) depends on cluster ions. The accelerating voltage and cluster size are sharper than in the case of single ions, and the thickness of the region where the irradiated carbon is locally present (that is, the modified layer) is approximately 500 nm or less (for example, about 50 nm to 400 nm) . Therefore, when the constituent element of the multi-element cluster ion 16 contains an element that contributes to absorption, such as carbon, the modified layer 18 functions as a strong absorption point.

於本實施形態中,所注入的多元素簇離子16為CHO簇,包含碳、氫及氧作為構成元素。晶格位置的碳原子的共價鍵半徑較矽單晶小而形成矽結晶晶格的收縮場(contraction field),因此吸引晶格隙的雜質的吸除能力變高。而且,認為藉由以CHO簇的形態注入碳及氧,並經過其後的伴隨磊晶成長的熱處理,而 形成黑點狀缺陷D。再者,氫使矽磊晶層(磊晶層20)的點缺陷鈍化,且就有助於改善使用由本實施形態所得的半導體磊晶晶圓100來製成半導體器件時的器件特性的方面而言亦有利。 In this embodiment, the implanted multi-element cluster ions 16 are CHO clusters, containing carbon, hydrogen, and oxygen as constituent elements. The covalent bond radius of the carbon atoms at the crystal lattice position is smaller than that of the silicon single crystal, and the contraction field of the silicon crystal lattice is formed. Therefore, the ability to attract impurities in the lattice gap becomes higher. Moreover, it is believed that by implanting carbon and oxygen in the form of CHO clusters, and then undergoing a heat treatment accompanying epitaxial growth, A black dot-shaped defect D is formed. Furthermore, hydrogen passivates the point defects of the silicon epitaxial layer (epitaxial layer 20), and contributes to improving the device characteristics when the semiconductor epitaxial wafer 100 obtained in this embodiment is used to manufacture a semiconductor device. Words are also favorable.

<第2步驟> <Step 2>

於所述第1步驟之後,第2步驟中進行用以增大改質層18內所形成的黑點狀缺陷D的缺陷密度的缺陷形成熱處理。如使用參考實驗例1、參考實驗例2進行說明般,黑點狀缺陷D的缺陷密度大幅依存於直至到達磊晶成長溫度為止的升溫過程中的溫度。因此,藉由在形成磊晶層之前進行用以形成缺陷的熱處理,可增大最終所獲得的半導體磊晶晶圓100中的黑點狀缺陷D的缺陷密度,且可提高吸除能力。 After the first step, in the second step, a defect formation heat treatment for increasing the defect density of the black dot-shaped defects D formed in the modified layer 18 is performed. As described using Reference Experimental Example 1 and Reference Experimental Example 2, the defect density of the black dot-shaped defects D greatly depends on the temperature during the temperature rise process until reaching the epitaxial growth temperature. Therefore, by performing the heat treatment for forming defects before forming the epitaxial layer, the defect density of the black spot defects D in the semiconductor epitaxial wafer 100 finally obtained can be increased, and the gettering ability can be improved.

該第2步驟中的缺陷形成熱處理的熱處理條件若可增大黑點狀缺陷D的缺陷密度,則並無限制,較佳為於小於800℃的第1溫度區域保持半導體晶圓的第1保持時間為0秒以上且45秒以下,且自第1溫度區域升溫後的、於800℃以上且小於1000℃的第2溫度區域保持所述半導體晶圓的第2保持時間為30秒以上。 The heat treatment conditions of the defect formation heat treatment in the second step are not limited as long as the defect density of the black dot-shaped defects D can be increased, and it is preferable to maintain the first holding of the semiconductor wafer in the first temperature range less than 800°C. The time is 0 second or more and 45 seconds or less, and the second holding time for holding the semiconductor wafer in the second temperature region of 800° C. or more and less than 1000° C. after raising the temperature from the first temperature region is 30 seconds or more.

參照圖4,如所述般,第1溫度區域相當於缺陷種消失的溫度帶,因此通過該溫度帶的時間較佳為儘可能短。因此,較佳為將第1保持時間設為45秒以下,更佳為設為30秒以下,進而佳為設為10秒以下,特佳為設為5秒以下。另外,只要將向磊晶成長爐內投入半導體晶圓10的爐內投入溫度設為800℃以上,則亦可將第1保持時間設為0秒。 Referring to FIG. 4, as described above, the first temperature zone corresponds to the temperature zone where the defect species disappear, so the time to pass through this temperature zone is preferably as short as possible. Therefore, the first holding time is preferably 45 seconds or less, more preferably 30 seconds or less, still more preferably 10 seconds or less, and particularly preferably 5 seconds or less. In addition, as long as the furnace input temperature of the semiconductor wafer 10 into the epitaxial growth furnace is 800° C. or higher, the first holding time may be set to 0 seconds.

另外,第2溫度區域相當於缺陷成長的溫度帶,因此通過該溫度帶的時間較佳為比較長。因此,較佳為將第2保持時間設為30秒以上,更佳為設為60秒以上。雖認為第2保持時間越長越佳,但若考慮到製造效率,則可將第2保持時間的上限設為300秒。 In addition, the second temperature zone corresponds to a temperature zone where defects grow, and therefore the time to pass through this temperature zone is preferably relatively long. Therefore, the second holding time is preferably 30 seconds or more, and more preferably 60 seconds or more. Although it is considered that the longer the second holding time is, the better, but in consideration of manufacturing efficiency, the upper limit of the second holding time can be set to 300 seconds.

再者,圖4中,圖示出於第2溫度區域中以固定溫度進行保持的態樣,但本發明並不受該態樣的任何限定。例如,於第2溫度區域中,可將升溫速率設為數℃/秒(例如1℃/秒~3℃/秒)左右、或以進而慢的升溫速率進行升溫來實現所述第2保持時間,亦可重覆進行升溫及固定溫度的保持等。 In addition, in FIG. 4, the figure is shown in the aspect of maintaining at a fixed temperature in the second temperature range, but the present invention is not limited to this aspect at all. For example, in the second temperature zone, the heating rate can be set to a few degrees Celsius/second (for example, 1°C/sec to 3°C/second), or the temperature can be increased at a slower heating rate to achieve the second holding time. It is also possible to repeatedly increase the temperature and maintain the fixed temperature.

另外,利用本步驟的缺陷形成熱處理與用以恢復結晶性的恢復熱處理不同。用以恢復結晶性的恢復熱處理是用以對藉由簇離子注入而形成的非晶狀態進行恢復,較缺陷形成熱處理而言,需要比較長時間地進行比較高的溫度的熱處理。 In addition, the defect formation heat treatment using this step is different from the recovery heat treatment for restoring crystallinity. The recovery heat treatment for restoring crystallinity is used to recover the amorphous state formed by cluster ion implantation. Compared with the defect formation heat treatment, a relatively high temperature heat treatment is required for a relatively long time.

<第3步驟> <Step 3>

緊接所述第2步驟,進行於半導體晶圓10的改質層18上形成磊晶層20的第3步驟(圖5中的(A)至(C)的步驟C)。作為所形成的磊晶層20,例如可列舉矽磊晶層,可藉由通常的條件而形成。於該情況下,例如將氫作為載氣,將二氯矽烷、三氯矽烷等源氣體導入至腔室內,成長溫度亦視所使用的源氣體而不同,可於1000℃~1200℃的範圍的溫度下藉由CVD法於半導體晶圓10上進行磊晶成長。磊晶層20較佳為將厚度設為1μm~15μm 的範圍內。其原因在於:於小於1μm的情況下,可能因摻雜劑自半導體晶圓10向外擴散而導致磊晶層20的電阻率變化,另外,於超過15μm的情況下,有對固體攝像元件的分光感度特性產生影響之虞。 Immediately after the second step, the third step of forming the epitaxial layer 20 on the modified layer 18 of the semiconductor wafer 10 (step C of (A) to (C) in FIG. 5) is performed. The epitaxial layer 20 to be formed includes, for example, a silicon epitaxial layer, and it can be formed under normal conditions. In this case, for example, hydrogen is used as a carrier gas, and source gases such as dichlorosilane and trichlorosilane are introduced into the chamber. The growth temperature also varies depending on the source gas used, and can be in the range of 1000°C to 1200°C. The epitaxial growth is performed on the semiconductor wafer 10 by the CVD method at a temperature. The epitaxial layer 20 preferably has a thickness of 1 μm to 15 μm In the range. The reason is that in the case of less than 1 μm, the resistivity of the epitaxial layer 20 may change due to the outdiffusion of the dopant from the semiconductor wafer 10, and in the case of more than 15 μm, the solid-state imaging device may be affected. The spectral sensitivity characteristics may have an impact.

第3步驟後的黑點狀缺陷D的缺陷密度雖較剛進行第2步驟後的黑點狀缺陷D的缺陷密度減小,但因經過利用第2步驟的缺陷形成熱處理,而較先前所形成的缺陷密度而言,最終生成的缺陷密度變大。因此,即便將簇離子注入條件設為相同,亦可較先前而言非偶然地提高所獲得的半導體磊晶晶圓100的吸除能力。 Although the defect density of the black dot-shaped defects D after the third step is lower than that of the black dot-shaped defects D immediately after the second step, the defect formation heat treatment using the second step is more than that of the previous ones. In terms of defect density, the resulting defect density becomes larger. Therefore, even if the cluster ion implantation conditions are set to be the same, the gettering ability of the obtained semiconductor epitaxial wafer 100 can be improved non-incidentally than before.

再者,所謂本說明書中的黑點狀缺陷D,是指於利用TEM以亮模式觀察半導體磊晶晶圓100的劈開剖面的情況下,於改質層18內以黑點的形式觀察到的缺陷,直徑為數奈米(nm)左右的微小尺寸的缺陷除外。黑點狀缺陷D的尺寸為15nm以上且100nm以下,所謂「黑點狀缺陷的尺寸」,是設為TEM圖像中的缺陷的直徑。再者,於黑點狀缺陷D為並非圓形或不可視作圓形的形狀的情況下,使用內包黑點狀缺陷D的最小直徑的外接圓,近似於圓形而設定直徑。另外,關於黑點狀缺陷的「缺陷密度」,是對TEM圖像中存在黑點狀缺陷D的區域中的單位規定面積的缺陷的個數根據此時的TEM觀察中所使用的樣品的最終厚度而定義。 In addition, the so-called black dot-like defects D in this specification refers to the black dots observed in the modified layer 18 when the cleavage section of the semiconductor epitaxial wafer 100 is observed in bright mode by TEM Defects except for those with a small size of a few nanometers (nm) in diameter. The size of the black dot-shaped defect D is 15 nm or more and 100 nm or less, and the "size of the black dot-shaped defect" is the diameter of the defect in the TEM image. Furthermore, when the black point defect D is a shape that is not circular or can not be regarded as a circle, the circumscribed circle of the smallest diameter that contains the black point defect D is used, and the diameter is set to approximate a circle. In addition, the "defect density" of black dot-shaped defects refers to the number of defects per unit of a predetermined area in the area where black dot-shaped defects D exist in the TEM image based on the final result of the sample used in the TEM observation at this time. The thickness is defined.

以下,對本實施形態的多元素簇離子的照射態樣進行說 明。 Hereinafter, the irradiation state of the multi-element cluster ions of this embodiment will be explained Bright.

所照射的多元素簇離子16的構成元素若含包含碳、氫及氧,則其他構成元素並無特別限定。多元素簇離子16的構成元素進而可包含的元素可列舉硼、磷、砷、銻等。 As long as the constituent elements of the irradiated multi-element cluster ion 16 contain carbon, hydrogen, and oxygen, other constituent elements are not particularly limited. The constituent elements of the multi-element cluster ion 16 may further include boron, phosphorus, arsenic, and antimony.

再者,離子化的化合物並無特別限定,作為可離子化的化合物,例如可使用二乙基醚(C4H10O)、乙醇(C2H6O)、二乙基酮(C5H10O)等。特佳為使用藉由二乙基醚、乙醇等所生成的簇CnHmOl(l、m、n彼此獨立,1≦n≦16,1≦m≦16,1≦l≦16)。特佳為簇離子的碳原子數為16個以下,且簇離子的氧原子數為16個以下。其原因在於容易控制小尺寸的簇離子射束。另外,例如若使用三甲基亞磷酸酯(C3H9O3P)等,則除了碳、氫及氧以外,多元素簇離子16的構成元素中亦可包含磷。 In addition, the ionized compound is not particularly limited. As the ionizable compound, for example, diethyl ether (C 4 H 10 O), ethanol (C 2 H 6 O), diethyl ketone (C 5 H 10 O) and so on. It is particularly preferable to use clusters C n H m O l generated by diethyl ether, ethanol, etc. (l, m, and n are independent of each other, 1≦n≦16, 1≦m≦16, 1≦l≦16) . It is particularly preferable that the number of carbon atoms of the cluster ion is 16 or less, and the number of oxygen atoms of the cluster ion is 16 or less. The reason is that it is easy to control a cluster ion beam of a small size. In addition, for example, if trimethyl phosphite (C 3 H 9 O 3 P) or the like is used, in addition to carbon, hydrogen, and oxygen, the constituent elements of the multi-element cluster ion 16 may include phosphorus.

簇尺寸可於2個~100個、較佳為60個以下、更佳為50個以下的範圍內適宜設定。簇尺寸的調整可藉由調整自噴嘴噴出的氣體的氣體壓力及真空容器的壓力、離子化時對燈絲(filament)施加的電壓等而進行。再者,簇尺寸可藉由以下方式求出:藉由利用四極高頻電場的質譜分析或飛行時間(time-of-flight)質譜分析而求出簇個數分佈,取簇個數的平均值。 The cluster size can be appropriately set in the range of 2 to 100, preferably 60 or less, and more preferably 50 or less. The cluster size can be adjusted by adjusting the gas pressure of the gas ejected from the nozzle, the pressure of the vacuum container, the voltage applied to the filament during ionization, and the like. Furthermore, the cluster size can be obtained by the following methods: obtain the distribution of the number of clusters by mass spectrometry using a quadrupole high frequency electric field or time-of-flight mass spectrometry, and take the average of the number of clusters .

簇離子的加速電壓與簇尺寸一起對簇離子的構成元素的深度方向的濃度分佈的峰值位置造成影響。於本實施形態中,可將多元素簇離子16的加速電壓設為超過0keV/Cluster且小於200keV/Cluster,較佳為設為100keV/Cluster以下,進而佳為設 為80keV/Cluster以下。再者,關於加速電壓的調整,通常使用(1)靜電加速、(2)高頻加速此兩種方法。前者的方法有等間隔地排列多個電極,於該些電極間施加相等的電壓,於軸方向上製作等加速電場的方法。後者的方法有一邊使離子以直線狀行進一邊使用高頻進行加速的線性直線加速器(linac)法。 The acceleration voltage of the cluster ion and the cluster size affect the peak position of the concentration distribution of the constituent elements of the cluster ion in the depth direction. In this embodiment, the acceleration voltage of the multi-element cluster ion 16 can be set to exceed 0 keV/Cluster and less than 200 keV/Cluster, preferably set to 100 keV/Cluster or less, and more preferably set Below 80keV/Cluster. Furthermore, regarding the adjustment of the acceleration voltage, two methods (1) electrostatic acceleration and (2) high frequency acceleration are usually used. In the former method, a plurality of electrodes are arranged at equal intervals, an equal voltage is applied between the electrodes, and an equal acceleration electric field is created in the axial direction. In the latter method, there is a linear linear accelerator (linac) method in which ions are accelerated by high frequency while traveling in a straight line.

另外,簇離子的劑量可藉由控制離子照射時間而調整。碳、氫及氧各元素的劑量是由簇離子種類及簇離子的劑量(Cluster/cm2)來決定。本實施形態中,可以碳的劑量為1×1013原子/cm2~1×1017原子/cm2的方式調整多元素簇離子16的劑量,較佳為將碳的劑量設為5×1013原子/cm2以上且5×1016原子/cm2以下。其原因在於:於碳的劑量小於1×1013原子/cm2的情況下,存在無法獲得充分的吸除能力的情況,於碳的劑量超過1×1016原子/cm2的情況下,有對磊晶層20的表面造成大的損傷之虞。 In addition, the dose of cluster ions can be adjusted by controlling the ion irradiation time. The dose of each element of carbon, hydrogen, and oxygen is determined by the cluster ion species and the cluster ion dose (Cluster/cm 2 ). In this embodiment, the dose of the multi-element cluster ion 16 can be adjusted such that the dose of carbon is 1×10 13 atoms/cm 2 to 1×10 17 atoms/cm 2 , and it is preferable to set the dose of carbon to 5×10 13 atoms/cm 2 or more and 5×10 16 atoms/cm 2 or less. The reason is that when the dose of carbon is less than 1×10 13 atoms/cm 2 , there is a case where sufficient absorption capacity cannot be obtained, and when the dose of carbon exceeds 1×10 16 atoms/cm 2 , there is The surface of the epitaxial layer 20 may be severely damaged.

另外,多元素簇離子16的射束電流值只要設為50μA以上且5000μA以下即可。再者,簇離子的射束電流值例如可藉由變更離子源中的原料氣體的分解條件等而調整。 In addition, the beam current value of the multi-element cluster ion 16 may be 50 μA or more and 5000 μA or less. Furthermore, the beam current value of the cluster ions can be adjusted by changing the decomposition conditions of the source gas in the ion source, for example.

以上,對本發明的代表性實施形態進行了說明,但本發明並不限定於該些實施形態。 The representative embodiments of the present invention have been described above, but the present invention is not limited to these embodiments.

[實施例] [Example]

(試行例1) (Trial Example 1)

準備由CZ單晶矽錠獲得的矽晶圓(直徑:300mm,厚度:725μm,摻雜劑種類:磷,電阻率:10Ω.cm)。繼而,使用簇離 子產生裝置(日新離子機器公司製造,型號:克拉麗絲(CLARIS)(註冊商標)),將包含使二乙基醚(C4H10O)簇離子化而成的CH3O的多元素簇離子以加速電壓80keV/Cluster的注入條件注入至矽晶圓的表面。另外,將該簇離子的劑量設為1.0×1015cluster/cm2(碳的劑量亦為1.0×1015原子/cm2)。 Prepare a silicon wafer (diameter: 300mm, thickness: 725μm, dopant type: phosphorus, resistivity: 10Ω·cm) obtained from CZ single crystal silicon ingots. Then, using a cluster ion generator (manufactured by Nisshin Ion Instruments Co., Ltd., model: CLARIS (registered trademark)), the CH containing the cluster ionized diethyl ether (C 4 H 10 O) Multi-element cluster ions of 3 O are injected into the surface of the silicon wafer under the conditions of an acceleration voltage of 80 keV/Cluster. In addition, the dose of the cluster ions is 1.0×10 15 cluster/cm 2 (the dose of carbon is also 1.0×10 15 atoms/cm 2 ).

其次,將所述矽晶圓搬送至爐內溫度600℃的逐片式磊晶成長裝置(應用材料(Applied Materials)公司製造)內。繼而,將直至800℃為止的升溫時間設為5秒(升溫速率40℃/s),將800℃~1000℃為止的升溫時間設為5秒(升溫速率40℃/s)並上升至1000℃。緊接著,於裝置內升溫至1120℃,在該溫度下實施30秒的氫烘烤處理後,以氫作為載氣,以三氯矽烷作為源氣體,於1120℃下藉由CVD法於矽晶圓的形成有改質層的一側的表面上使矽的磊晶層(厚度:5μm,摻雜劑種類:磷,電阻率:50Ω.cm)進行磊晶成長,製作試行例1的磊晶矽晶圓。 Next, the silicon wafer is transferred to a wafer-by-wafer epitaxial growth device (manufactured by Applied Materials) with a furnace temperature of 600°C. Next, set the temperature rise time to 800°C to 5 seconds (heating rate 40°C/s), and set the temperature rise time from 800°C to 1000°C to 5 seconds (heating rate 40°C/s) and increase to 1000°C . Immediately afterwards, the temperature in the device was raised to 1120°C. After the hydrogen baking treatment was carried out at this temperature for 30 seconds, hydrogen was used as the carrier gas, and trichlorosilane was used as the source gas. The silicon crystal was deposited at 1120°C by the CVD method. A silicon epitaxial layer (thickness: 5μm, dopant type: phosphorus, resistivity: 50Ω·cm) was grown epitaxially on the round surface on the side where the modified layer was formed to produce the epitaxial crystal of Trial Example 1. Silicon wafer.

(試行例2~試行例25) (Trial Example 2~Trial Example 25)

如下述表1所示般將直至800℃為止的升溫時間設為5秒(升溫速率40℃/s)、10秒(升溫速率20℃/s)、30秒(升溫速率6.7℃/s)、45秒(升溫速率4.4℃/s)、60秒(升溫速率3.3℃/s),將800℃~1000℃為止的升溫時間設為5秒(升溫速率40℃/s)、10秒(升溫速率20℃/s)、30秒(升溫速率6.7℃/s)、60秒(升溫速率3.3℃/s)、300秒(升溫速率0.67℃/s),除此以外,與試行例1同樣地製作試行例2~試行例25的磊晶矽晶圓。 As shown in Table 1 below, set the heating time up to 800°C to 5 seconds (heating rate 40°C/s), 10 seconds (heating rate 20°C/s), 30 seconds (heating rate 6.7°C/s), 45 seconds (heating rate 4.4°C/s), 60 seconds (heating rate 3.3°C/s), set the heating time from 800°C to 1000°C to 5 seconds (heating rate 40°C/s), 10 seconds (heating rate) 20°C/s), 30 seconds (heating rate of 6.7°C/s), 60 seconds (heating rate of 3.3°C/s), 300 seconds (heating rate of 0.67°C/s), except for this, it was produced in the same way as Trial Example 1 The epitaxial silicon wafers of Trial Example 2 to Trial Example 25.

Figure 107138317-A0305-02-0019-1
Figure 107138317-A0305-02-0019-1

<評價1:利用TEM剖面照片的觀察> <Evaluation 1: Observation using TEM section photographs>

關於試行例1~試行例25的磊晶矽晶圓的各晶圓,利用TEM(Transmission Electron Microscope:穿透式電子顯微鏡)觀察基板界面附近的剖面,求出黑點狀缺陷的缺陷密度。再者,將於自基板界面起深度為300nm以內的範圍內觀察到的缺陷尺寸為15 nm~100nm以下的缺陷設為黑點狀缺陷。將所觀察到的缺陷密度一併示於表1中。 Regarding each of the epitaxial silicon wafers of Trial Example 1 to Trial Example 25, a cross-section near the substrate interface was observed with a TEM (Transmission Electron Microscope), and the defect density of black spot defects was determined. Furthermore, the size of the defect observed within the depth of 300nm from the substrate interface is 15 Defects below nm to 100 nm are regarded as black dot-shaped defects. The observed defect density is shown in Table 1 together.

<評價2:吸除能力評價> <Evaluation 2: Evaluation of Absorption Ability>

對試行例1~試行例25的磊晶矽晶圓的各晶圓,評價吸除能力。首先,使用Ni污染液(1.0×1013原子/cm2)並藉由旋塗污染法將各磊晶矽晶圓的磊晶層的表面強制污染,繼而於氮氣環境中於900℃下實施30分鐘的擴散熱處理。其後,對於各磊晶矽晶圓,進行SIMS測定,分別測定簇離子注入區域(本評價中,為了簡便而設為自基板界面起300nm)中的Ni濃度的分佈。而且,求出離子注入區域中的Ni的捕獲量(相當於SIMS分佈中的Ni濃度的積分值)。Ni的捕獲量是如下述般進行分類並設為評價基準。將評價結果一併示於表1。 For each of the epitaxial silicon wafers of Trial Example 1 to Trial Example 25, the gettering ability was evaluated. First, use Ni contamination solution (1.0×10 13 atoms/cm 2 ) and use spin-coating contamination method to contaminate the surface of the epitaxial layer of each epitaxial silicon wafer forcibly, and then implement it at 900°C in a nitrogen atmosphere. Minutes of diffusion heat treatment. Thereafter, for each epitaxial silicon wafer, SIMS measurement was performed, and the distribution of the Ni concentration in the cluster ion implantation region (in this evaluation, 300 nm from the substrate interface for simplicity) was measured. Then, the trapped amount of Ni in the ion implantation region (corresponding to the integrated value of the Ni concentration in the SIMS distribution) is obtained. The captured amount of Ni is classified as follows and used as an evaluation criterion. The evaluation results are shown in Table 1 together.

◎:9.7×1012原子/cm2以上 ◎: 9.7×10 12 atoms/cm 2 or more

○:9.5×1012原子/cm2以上且小於9.7×1012原子/cm2 ○: 9.5×10 12 atoms/cm 2 or more and less than 9.7×10 12 atoms/cm 2

△:9.0×1012原子/cm2以上且小於9.5×1012原子/cm2 △: 9.0×10 12 atoms/cm 2 or more and less than 9.5×10 12 atoms/cm 2

×:小於9.0×1012原子/cm2 ×: less than 9.0×10 12 atoms/cm 2

<評價結果的考察> <Examination of Evaluation Results>

首先,根據表1而可確認到吸除能力的高低、與黑點狀缺陷的缺陷密度存在明確的相關關係,可確認到黑點狀缺陷的缺陷密度越大,吸除能力亦越高。而且,亦可確認到推斷為缺陷種消失的溫度帶的通過時間越短、且推斷為缺陷成長的溫度帶的通過時間越長,黑點狀缺陷的缺陷密度越變大。因此,即便簇離子注入 條件相同,藉由進行用以增大黑點狀缺陷的缺陷密度的缺陷形成熱處理,亦可提高吸除能力。 First, according to Table 1, it can be confirmed that the level of the sucking ability has a clear correlation with the defect density of black dot-shaped defects, and it can be confirmed that the higher the defect density of black dot-shaped defects, the higher the sucking ability. It was also confirmed that the shorter the passage time of the temperature zone estimated to be the disappearance of the defect species, and the longer the passage time of the temperature zone estimated to be the growth of the defect, the higher the defect density of black dot-shaped defects. Therefore, even if cluster ion implantation Under the same conditions, by performing defect formation heat treatment to increase the defect density of black dot-shaped defects, the absorption ability can also be improved.

[產業上的可利用性] [Industrial availability]

根據本發明,可提供一種即便簇離子注入條件相同亦可具有更高的吸除能力的半導體磊晶晶圓的製造方法。 According to the present invention, it is possible to provide a method for manufacturing a semiconductor epitaxial wafer that has a higher gettering ability even if the cluster ion implantation conditions are the same.

10‧‧‧半導體晶圓 10‧‧‧Semiconductor Wafer

10A‧‧‧半導體晶圓的表面 10A‧‧‧Semiconductor wafer surface

16‧‧‧簇離子 16‧‧‧Cluster ion

18‧‧‧改質層 18‧‧‧Modified layer

20‧‧‧磊晶層 20‧‧‧Epitaxial layer

100‧‧‧半導體磊晶晶圓 100‧‧‧Semiconductor epitaxial wafer

D‧‧‧黑點狀缺陷 D‧‧‧Black dot defect

Claims (4)

一種半導體磊晶晶圓的製造方法,其特徵在於包括: 第1步驟,對半導體晶圓的表面注入包含碳、氫及氧此三種元素作為構成元素的多元素簇離子,於所述半導體晶圓的表層部形成所述多元素簇離子的構成元素固溶而成的改質層; 第2步驟,於所述第1步驟之後,進行用以增大所述改質層內所形成的黑點狀缺陷的缺陷密度的缺陷形成熱處理;以及 第3步驟,緊接所述第2步驟,於所述半導體晶圓的改質層上形成磊晶層。A method for manufacturing a semiconductor epitaxial wafer, which is characterized by comprising: The first step is to implant multi-element cluster ions containing three elements of carbon, hydrogen and oxygen as constituent elements into the surface of the semiconductor wafer, and form solid solution of the constituent elements of the multi-element cluster ions on the surface of the semiconductor wafer The modified layer; In the second step, after the first step, a defect formation heat treatment is performed to increase the defect density of the black dot-shaped defects formed in the modified layer; and In the third step, following the second step, an epitaxial layer is formed on the modified layer of the semiconductor wafer. 如申請專利範圍第1項所述的半導體磊晶晶圓的製造方法,其中所述第2步驟中的所述缺陷形成熱處理的熱處理條件中,於小於800℃的第1溫度區域保持所述半導體晶圓的第1保持時間為0秒以上且45秒以下,且自第1溫度區域升溫後的、於800℃以上且小於1000℃的第2溫度區域保持所述半導體晶圓的第2保持時間為30秒以上。The method for manufacturing a semiconductor epitaxial wafer according to the first item of the patent application, wherein in the heat treatment conditions of the defect formation heat treatment in the second step, the semiconductor is maintained in a first temperature region less than 800°C The first holding time of the wafer is 0 second or more and 45 seconds or less, and the second holding time for holding the semiconductor wafer in the second temperature region of 800°C or more and less than 1000°C after the temperature rise from the first temperature region For more than 30 seconds. 如申請專利範圍第1項所述的半導體磊晶晶圓的製造方法,其中所述多元素簇離子的構成元素由碳、氫及氧此三種元素所組成。According to the method for manufacturing a semiconductor epitaxial wafer described in the first item of the patent application, the constituent elements of the multi-element cluster ion are composed of three elements: carbon, hydrogen and oxygen. 如申請專利範圍第1項至第3項中任一項所述的半導體磊晶晶圓的製造方法,其中所述半導體晶圓為矽晶圓。According to the method for manufacturing a semiconductor epitaxial wafer according to any one of items 1 to 3 of the scope of patent application, the semiconductor wafer is a silicon wafer.
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