JPS60198832A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60198832A
JPS60198832A JP5560784A JP5560784A JPS60198832A JP S60198832 A JPS60198832 A JP S60198832A JP 5560784 A JP5560784 A JP 5560784A JP 5560784 A JP5560784 A JP 5560784A JP S60198832 A JPS60198832 A JP S60198832A
Authority
JP
Japan
Prior art keywords
oxygen
transistor
region
concentration
silicon wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5560784A
Other languages
Japanese (ja)
Inventor
Michiaki Kojima
小島 道章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5560784A priority Critical patent/JPS60198832A/en
Publication of JPS60198832A publication Critical patent/JPS60198832A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Abstract

PURPOSE:To obtain a substrate for IC having high reliability by a method wherein an Si wafer having an intrinsic gettering effect, and moreover made concentration of O2 within depth of 10mum from the surface of the Si substrate to 5X10<17>/cm<3> or less, and the surface region thereof is made to no defect layer substantially is used. CONSTITUTION:Heat treatments of a high temperature and a low temperature are performed to an Si wafer having concentration of O2 of 12-18X10<17>/cm<3> normally, and concentration of O2 of the layer within depth of 10mum from the surface 1, which is the active region of a transistor, is made to 5X10<17>/cm<3> or less. An actually no defect layer is formed in such a way, the defect of the element activating region 2 thereof is reduced to 10<3>-10<6>/cm<3>, and an intrinsic gettering effect is generated. Moreover lattice defects 4 of a large number are left as they are like the beginning in a region under the region 2. When a substrate obtained in such a way is used, a transistor having no characteristic inferiority and no characteristic variation can be obtained.

Description

【発明の詳細な説明】 本発明は半導体装置にかがシ、とくにトランジスタ等の
活性化領域内の微細欠陥や酸素ドナーの発生を防止する
事により特性不良及び特性変動を極力無くした信頼性の
高い高歩留シの半導体集積回路装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention improves reliability by minimizing defects in characteristics and fluctuations in characteristics by preventing the generation of microscopic defects and oxygen donors in active regions of semiconductor devices, especially transistors, etc. The present invention relates to a high yield semiconductor integrated circuit device.

近年の半導体集積回路装置は、増々太答融化超微細配線
化して来ており、高精度の半導体集積回路装置を実現す
るには、安定した回路及び製進プロセスが絶縁必要条件
である。そこでトランジスタの活性化領域にある過飽和
酸素による、転位や析出物等の格子欠陥による特性不良
の発生を防止し、更に入力リーク不良や動作マージンや
劣化を引き起す酸素ドナーの発生を防止したシリコンウ
ェハーを使用する事が不可欠になって来たのである。
In recent years, semiconductor integrated circuit devices have become increasingly interconnected and ultra-fine, and stable circuits and manufacturing processes are required for insulation in order to realize high-precision semiconductor integrated circuit devices. Therefore, silicon wafers are designed to prevent characteristic defects caused by lattice defects such as dislocations and precipitates due to supersaturated oxygen in the active region of transistors, and also to prevent the generation of oxygen donors that cause input leakage defects and deterioration of the operating margin. It has become essential to use.

これまでの半導体集積回路装置の歩留υ向上及び信頼性
対策は、主にシリコンウェハー表面のキズやゴミに主眼
が於かれ、種々の解決を見て来たが、シリコンウェハー
そのものが起す格子欠陥や酸素ドナーによる特性不良に
ついては、充分な評価が行なわれていなかった。
Until now, measures to improve the yield υ and reliability of semiconductor integrated circuit devices have mainly focused on scratches and dust on the surface of silicon wafers, and various solutions have been found, but lattice defects caused by the silicon wafer itself Characteristic defects caused by oxygen donors and oxygen donors have not been sufficiently evaluated.

この鳥類LSIに於いては、製造中のトラブルの為に発
生する特性不良よシもトランジスタの活性化領域内に含
まれる酸素及び炭素等の原子或いはイオンによる格子欠
陥及び酸素ドナーが与える特性不良の方が大きな問題と
なっている。
In this avian LSI, there are not only characteristic defects that occur due to troubles during manufacturing, but also characteristic defects caused by lattice defects and oxygen donors caused by atoms or ions such as oxygen and carbon contained in the active region of the transistor. is a bigger problem.

例えば、トランジスタの活性化領域内である壁乏層内に
、シリコン内に含まれる炭素や過飽和酸素によ多発生す
る析出物や転位等による格子欠陥や酸素ドナーが発生す
れば、それがリーク源となって回路機能が誤動作する場
合がある。
For example, if lattice defects or oxygen donors occur in the wall-poor layer, which is the active region of a transistor, due to precipitates or dislocations that occur frequently due to carbon or supersaturated oxygen contained in silicon, these may be the source of leakage. This may cause the circuit function to malfunction.

シリコン基板の場合空乏層幅Xdは次式のように表わさ
れることが知られ又いる。
It is also known that in the case of a silicon substrate, the depletion layer width Xd is expressed by the following equation.

CT=底面容椅 εr=比誘電1率(11,7) ε〇−誘電E$<8.854X10” (Fsm−”)
’)φB−ビルトイン電圧<0.7V> q =電子電荷(1,6X 10” (C1>凧=アク
セプタ原子の濃度 〈13Ω−儂基板= 10.2刈o”(m−”) >〈
50Ω−園基板”、 2.5 X 10” (m)〉前
記の問題は、トランジスタの活性化領域の酸素を消滅さ
せる処置がなされていない為に起っていた。
CT = bottom surface εr = relative dielectric constant (11,7) ε〇−dielectric E$<8.854X10” (Fsm−”)
') φB - built-in voltage <0.7V> q = electron charge (1,6X 10"(C1> kite = concentration of acceptor atoms <13Ω - my substrate = 10.2 o"(m-")>
50 ohm substrate, 2.5 x 10''(m)> The above problem occurred because no measures were taken to eliminate oxygen in the active region of the transistor.

第1図は拡散工程を縦てない従来の基板酸素濃度が12
〜18X10”α−のシリコンウェハーの断面図で、第
2図は第1図のシリコンウェハーを用いて半導体集積回
路装置を製造する時と同じ熱処理を加えた後の断面図で
ある。
Figure 1 shows that the oxygen concentration of a conventional substrate without a diffusion process is 12
2 is a cross-sectional view of a silicon wafer of ~18×10" α-. FIG. 2 is a cross-sectional view after being subjected to the same heat treatment as when manufacturing a semiconductor integrated circuit device using the silicon wafer of FIG. 1.

第1図に於いて、1はシリコンウェハーの表面、2はト
ランジスタの活性化領域、0で示すところは3はシリコ
ンウェハー内に含まれる酸素である。
In FIG. 1, 1 is the surface of the silicon wafer, 2 is the active region of the transistor, and 3 is oxygen contained within the silicon wafer.

この様なシリコンウェハーを用いて800℃〜1000
℃の熱処理工程経て製造された、半導体集積回路装置の
断面図は、第2図の様になりトランジスタの活性化領域
内に、炭素や酸素の原因によ多発生した析出物や転位の
格子欠陥4(Xで示す)や酸素ドナー5(△で示す)が
発生する為、特性不良及び特性変動を引き起す欠点があ
った。
Using a silicon wafer like this,
The cross-sectional view of a semiconductor integrated circuit device manufactured through a heat treatment process at ℃ is as shown in Figure 2. In the active region of a transistor, lattice defects such as precipitates and dislocations frequently occur due to carbon and oxygen. Since oxygen donors 4 (indicated by

本発明の目的は、以上の問題点に対処してなされたもの
でその目的は、トランジスタの活性化領域の酸素を、極
力取如除く事によシ過飽和酸素の析出物や転位による格
子欠陥の発生を防止し、この原因による特性不良をなく
すと共に、特性変動を起す酸素ドナーの発生を防止して
信頼性の高い高歩留シの半導体集積回路装置を提供する
事にある。
The purpose of the present invention has been made to address the above problems, and the purpose is to eliminate lattice defects caused by supersaturated oxygen precipitates and dislocations by removing as much oxygen as possible from the active region of a transistor. It is an object of the present invention to provide a highly reliable, high-yield semiconductor integrated circuit device by preventing the occurrence of oxygen donors and eliminating characteristic defects due to this cause, as well as preventing the generation of oxygen donors that cause characteristic fluctuations.

本発明の要旨は、I−G効果(イン) IJシック・ゲ
ッタリング=シリコンウェハーの内部の欠陥が持つ有害
不純物のゲッタリンク作用)が々υトランジスタの活性
化領域である表面よυ10μm以内の酸素a度を5 X
 10”cm 以下Vこし、この傾城を、s史上の無欠
陥層にしたシリコンウェハーを用いた半導体装置にある
The gist of the present invention is that the I-G effect (IJ thick gettering = getter linking effect of harmful impurities possessed by defects inside a silicon wafer) is caused by oxygen within υ10 μm from the surface, which is the active region of the transistor. a degree 5
A semiconductor device using a silicon wafer having a V of 10" cm or less and making this slope a defect-free layer in history.

上記のトランジスタの活性化領域である表面から10μ
m以内の酸素、濃度を5 X 10”cm 以下にし、
この領域を無欠陥層にするシリコンウェハーを作成する
には、基板酸素濃度を12〜18X1017cTrL炭
素濃度をQ、4ppm 以下に規格化し、表面近傍に必
る酸素を消滅させる為不活性ガスで1000℃の高温で
16時間程度熱処理を行ない(温度が10008Cを越
えると処理時間は少なくて良い。)、次に■・G効果を
持たせる為、シリコンウェハー内部の潜在重接欠陥を成
長させる必要から800℃8度の熱処理を10時間程度
施こす方法がとられる。
10μ from the surface which is the active region of the above transistor.
oxygen within 5 x 10"cm, the concentration is below 5 x 10"cm,
To create a silicon wafer in which this region is a defect-free layer, the substrate oxygen concentration is 12~18X1017cTrL, the carbon concentration is Q, and the carbon concentration is normalized to 4 ppm or less, and the temperature is heated to 1000°C with an inert gas to eliminate the oxygen near the surface. Heat treatment is performed at a high temperature of 16 hours (if the temperature exceeds 10008C, the treatment time may be shortened), and then, in order to create the A method is used in which heat treatment is performed at 8 degrees Celsius for about 10 hours.

以下本発明の実施例につき第3図と第4図それに第5図
を参照して詳細に説明する。
Embodiments of the present invention will be described in detail below with reference to FIGS. 3, 4, and 5.

第3図は本発明の一実施例によるシリコンウェハーの断
面図を示し、第4図は、第3図のシリコンウェハーを用
いて半導体!#4積回路装置を製造する時と同じ熱処理
を加えた後の断面図を示している。
FIG. 3 shows a cross-sectional view of a silicon wafer according to an embodiment of the present invention, and FIG. 4 shows a semiconductor device using the silicon wafer of FIG. A cross-sectional view after the same heat treatment as when manufacturing the #4 integrated circuit device is shown.

第3図及び第4図に於いて、第1図及び第2図と同じ部
分は、同一番号を付しているので省略する。第5図は表
面酸素濃度と表面欠陥密度の相関図を示している。
In FIGS. 3 and 4, the same parts as in FIGS. 1 and 2 are designated by the same numbers and will therefore be omitted. FIG. 5 shows a correlation diagram between surface oxygen concentration and surface defect density.

本発明が従来の半導体集積回路装置と異なるのは、従来
の基板酸素濃度が12〜18 X 10I?ctri−
”のシリコンウェハーに高温と底温の熱処理を施しエト
ランジスタの活性化@域である表面から10μm以内の
酸素濃度を5 X 10’堀1゛以下にし、そこに事実
上の無欠陥層を作υウェハー内部は、欠陥’k 10’
 〜10”am 発生させI−G効果を持たせたものを
半導体集積回路装置の製造に用いている事である。
The present invention differs from conventional semiconductor integrated circuit devices in that the conventional substrate oxygen concentration is 12 to 18 x 10I? ctri-
``A silicon wafer is subjected to high-temperature and bottom-temperature heat treatment to reduce the oxygen concentration within 10 μm from the surface, which is the activation region of the transistor, to less than 1゛ in a 5 x 10' hole, creating a virtually defect-free layer there. Inside the υ wafer, there are defects 'k10'
~10" am and has an I-G effect is used in the manufacture of semiconductor integrated circuit devices.

それは、第3図の六子たとえばトランジスタの活性化領
域2内を無欠陥r@にしている為、第4図の俤に、半導
体集M[i、!lW&装伽゛を製造した後でもトランジ
スタの活件化fr¥v、2内は、酸素系の格子欠陥が発
生せず又P素ドナーも発生しない。
This is because the active region 2 of the transistor in FIG. 3, for example, is made defect-free r@, so that the semiconductor assembly M[i, ! Even after manufacturing IW&S, no oxygen-based lattice defects or P element donors are generated in the active region fr\v,2 of the transistor.

これは、第5図から表面の〜素濃度が少ない程表面欠陥
が減少し、表面の酸素#度が5 X 1 (1”cML
では欠陥がO〜1ケ/20りi Kなる事からも解る。
This is because, as shown in Fig. 5, the surface defects decrease as the ~element concentration on the surface decreases, and the surface oxygen level decreases to 5 x 1 (1"cML).
This can be understood from the fact that the number of defects is O~1/20 iK.

更に、シリコンウェハー内部は、欠陥が103〜10’
c+n 作られているのでこの欠陥が、有害不純物のゲ
ッタリング作用を杓なう為、トランジスタは極めて安定
した特性が得られる。
Furthermore, inside the silicon wafer, there are 103 to 10' defects.
Since the transistor is made of c+n, this defect counteracts the gettering effect of harmful impurities, so that the transistor has extremely stable characteristics.

以上説明した逆υ本発明によれば、トランジスタの活性
化領域であるシリコンウ、・・−の表面よ910μm以
内を、事実上の無欠陥層としている為、この領域に酸素
系の格子欠陥や酸素ドナーが発生しない事と内部欠陥を
作り1.G効果を持たせている事から有害不純物を、ゲ
ッタリングして特性不良や特性変動をなくしているので
高歩留りで高4i!頓性の半導体集積回路装置を容易に
得る事ができる。
According to the inverse υ invention described above, since the area within 910 μm from the surface of silicon, which is the active region of the transistor, is virtually defect-free, this area has oxygen-based lattice defects and oxygen 1. No donor is generated and internal defects are created. Since it has a G effect, harmful impurities are gettered and characteristic defects and characteristic fluctuations are eliminated, resulting in high yield and high 4i! A ready-to-use semiconductor integrated circuit device can be easily obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は拡散工程を経てない従来の基板酸素濃が1−2
〜18X10に?αのシリコンウェハーの断面図、第2
図は第1図のシリコンウェハーを用いて半導体集積回路
装置を製造する時と同じ熱処理を加えた後の断面図、第
3図は本発明の一実施例によるシリコンウェハーの断面
図、第4図は第3図のシリコンウェハーを用いて半導体
集積回路装置を製造する時と同じ熱処理を加えた後の断
面図、第5図は表面酸素濃度と表面欠陥密度の相関図で
ある。 1・・・・・・シリコンウェハー表面、2・・・・・・
素子の活性化領域、3・・・・・・酸素、4・・・・・
・格子欠陥、5・・・・・・酸素ドナー。 第3図 別4図 第5闇 渋面五傍0蔽1濃罠
Figure 1 shows that the oxygen concentration of a conventional substrate that has not undergone a diffusion process is 1-2.
~18X10? Cross-sectional view of α silicon wafer, 2nd
The figure is a cross-sectional view after applying the same heat treatment as when manufacturing a semiconductor integrated circuit device using the silicon wafer shown in FIG. 1, FIG. 3 is a cross-sectional view of a silicon wafer according to an embodiment of the present invention, and FIG. is a cross-sectional view after the silicon wafer shown in FIG. 3 has been subjected to the same heat treatment as when manufacturing a semiconductor integrated circuit device, and FIG. 5 is a correlation diagram between surface oxygen concentration and surface defect density. 1...Silicon wafer surface, 2...
Activation region of element, 3...Oxygen, 4...
- Lattice defect, 5...Oxygen donor. Figure 3 Separate figure 4 Figure 5 Dark frowning five side 0 cover 1 dark trap

Claims (1)

【特許請求の範囲】[Claims] I−G効果を有し、かつシリコン表面よ910μm以内
の酸素濃度を5 X 10”crrL−” 以下にし、
この表面領域を実質的に無欠陥層にしたシリコンウェハ
ーを用いたことを特徴とする半導体装置。
It has an I-G effect and the oxygen concentration within 910 μm from the silicon surface is 5 x 10"crrL-" or less,
A semiconductor device characterized by using a silicon wafer whose surface region is substantially defect-free.
JP5560784A 1984-03-23 1984-03-23 Semiconductor device Pending JPS60198832A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5560784A JPS60198832A (en) 1984-03-23 1984-03-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5560784A JPS60198832A (en) 1984-03-23 1984-03-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60198832A true JPS60198832A (en) 1985-10-08

Family

ID=13003451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5560784A Pending JPS60198832A (en) 1984-03-23 1984-03-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60198832A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0496382A2 (en) * 1991-01-22 1992-07-29 Nec Corporation Intrinsic gettering for a semiconducteur epitaxial wafer
EP1195804A1 (en) * 2000-01-26 2002-04-10 Shin-Etsu Handotai Co., Ltd Method for producing silicon epitaxial wafer
TWI708279B (en) * 2018-03-01 2020-10-21 日商Sumco股份有限公司 Method for manufacturing semiconductor epitaxial wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0496382A2 (en) * 1991-01-22 1992-07-29 Nec Corporation Intrinsic gettering for a semiconducteur epitaxial wafer
EP1195804A1 (en) * 2000-01-26 2002-04-10 Shin-Etsu Handotai Co., Ltd Method for producing silicon epitaxial wafer
EP1195804A4 (en) * 2000-01-26 2005-06-15 Shinetsu Handotai Kk Method for producing silicon epitaxial wafer
TWI708279B (en) * 2018-03-01 2020-10-21 日商Sumco股份有限公司 Method for manufacturing semiconductor epitaxial wafer

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