JP2669722B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a defect-free junction layer by low temperature annealing for forming a source / drain junction layer of a MOS transistor. .

[0002]

2. Description of the Related Art As devices are highly integrated, it is necessary to form a high-quality junction layer having a shallow junction layer and no defects such as crystal defects. High-temperature and short-time heat treatment techniques such as lamp annealing have been regarded as promising for forming a shallow junction layer having a high activation rate. However, there has been a problem in that slip lines are introduced at the time of cooling with the dislocation loops generated during the heat treatment as nuclei and the characteristics of the bonding layer are deteriorated. Especially in the case of short-time annealing (RTA), the probability of introducing a slip line was high because of the rapid cooling process. Therefore, it is necessary to completely restore the crystallinity before annealing for a short time. Moreover, in order to recover the crystallinity without extending the bonding layer in the depth direction and the horizontal direction (lateral direction), it is necessary to perform annealing in a low temperature region of 800 ° C. or lower.

[0003]

However, usually, for example,
Implantation conditions used in the LSI for forming an As ⁺ ion-implanted layer on the Si substrate 3 (As ⁺ acceleration energy:
40-80 KeV, injection amount: 3-5 × 10 ¹⁵ c
m ⁻² ), in the As ⁺ implantation region on the Si substrate,
Defects are generated in the upper and lower two stages of the interface 1 between the original amorphous Si and the Si crystal and the vicinity 2 of Rp with the dislocation loop as a nucleus [see FIG. 6]. Those defective portions are indicated by reference numerals 1a and 2a. In particular, the defect 1a generated at the interface 1 at a deep position easily causes a junction leak.

[0004]

As described above, according to the conventional method, the region where the crystallinity is disturbed at the amorphous / crystalline interface 1 is large at the time of ion implantation, and the region is used as a nucleus at the time of heat treatment to form crystals. Defects occur. Therefore, a damage layer generated at the time of implantation (turbulence at the amorphous / crystalline interface)
Need to be less.

According to the present invention, ions are implanted on a semiconductor substrate at a low acceleration energy to form an ion-implanted region, a low temperature heat treatment is applied to recover the crystallinity of the ion-implanted region, and then a high temperature is applied by a lamp annealing method. A method for manufacturing a semiconductor device, characterized by forming a highly activated bonding layer by performing heat treatment for a short time.

In the present invention, for example, ion implantation using As ⁺ is performed at a low acceleration energy of 10 to 20 KeV,
The crystallinity is recovered by heat treatment at 800 ° C., a defect-free bonding layer is formed, and then lamp annealing is performed to, for example, 1000 ° C.
A shallow defect-free bonding layer having a high activation rate is formed by performing high-temperature heat treatment at a temperature of 10 ° C. for a short time of about 10 seconds. In the present invention, for example, first, the semiconductor substrate is a Si substrate,
As ions or BF ₂
Ions are implanted at an ion implantation dose of 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² . The injection energy is 20 KeV
It has the following low acceleration energy. Next, the Si substrate on which the ion-implanted region is formed is subjected to a low-temperature heat treatment. The heat treatment temperature is preferably from 800 to 850C, more preferably 800C. This low-temperature heat treatment restores the crystallinity of the Si substrate, particularly the ion-implanted region. Finally, a high temperature, short time heat treatment is applied at 950-1100 ° C. The heat treatment temperature is preferably 1000 ° C. when a known lamp annealing method is used, and the heat treatment is preferably performed in a short time of about 10 seconds.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment shown in the drawings. The present invention is not limited by this.

To form a source / drain junction layer 7 having a depth of 0.1 μm by implanting As ions 6 on a Si substrate 5 having a plurality of gate electrodes 4 and 4 having sidewalls 3. First, a Si substrate 5 having gates 4 and 4
(See FIG. 1), ion implantation is performed with a low acceleration energy of 20 KeV and an As ion implantation amount of 5 × 10 ¹⁵ cm ⁻² to form an ion implantation layer 8 (see FIG. 2).

Next, a low-temperature heat treatment at 800 ° C. for one hour is performed in a nitrogen gas atmosphere. At this time, the injection energy is 20K
Since it is eV or less, the region where the crystallinity is disturbed in the Si substrate due to ion implantation can be made small, and it is possible to prevent the occurrence of crystal defects by using it as a nucleus. This can be seen from FIG. 4 which shows a characteristic diagram of the interface 1 and the vicinity 2 of Rp. FIG.
The curve C shown by the solid line in FIG. 2 shows the characteristics at the interface 1, and the curve D shown by the broken line D shows the characteristics at around Rp 2. Thus, the crystallinity is recovered by the low temperature heat treatment at 800 ° C. to form the defect-free bonding layer 7 [see FIG. 3].

Subsequently, the Si substrate having the defect-free bonding layer whose crystallinity has been restored is subjected to lamp annealing at 1000 ° C. for 10 seconds. At this time, it is confirmed by the curve A shown by the broken line in FIG. 5 that the depth d of the shallow junction layer does not change up to 1000 ° C.

That is, in FIG. 5, the curve A shows the dependence of the lamp annealing temperature on the junction depth d.
It can be seen that the junction depth increases at 1000 ° C. or higher, but is maintained at a substantially constant depth (0.1 μm) at 1000 ° C. or lower. The curve B shows the sheet resistance R dependence of the bonding layer, and it can be seen that the sheet resistance R decreases as the lamp annealing temperature rises.
(The same applies to 1000 ° C or less), a low value of 50Ω / □ or less is obtained.

As described above, in the present embodiment, the defect density decreases as the implantation energy decreases, and at the energy of 20 KeV or less, the defects at both Rp and the amorphous / crystalline interface almost disappear. Annealing was performed for 10 seconds by lamp annealing, and the sheet resistance decreased as the lamp annealing temperature increased, and a low value of 50Ω / □ or less was obtained at a temperature of 1000 ° C. or higher. At this time, 1
It was confirmed that the bonding depth did not change up to 000 ° C.

[0013]

As described above, according to the present invention, in forming the source / drain junction layer of the semiconductor device, ion implantation is performed at a low acceleration, the crystallinity is recovered at a low temperature, and then the lamp annealing is performed. Since the high temperature annealing is performed in the above step, there is an effect that a highly activated and defect-free shallow junction layer can be formed.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a manufacturing process showing a first step of a manufacturing process according to an embodiment of the present invention.

FIG. 2 is an explanatory view of a manufacturing process showing a second step of the manufacturing process in the embodiment.

FIG. 3 is an explanatory diagram of a manufacturing process showing a third step of the manufacturing process in the embodiment.

FIG. 4 is a characteristic diagram showing the dependency of defect density on As ion implantation energy.

FIG. 5 is a characteristic diagram showing the lamp annealing temperature dependence of the sheet resistance and the junction depth of the junction layer.

FIG. 6 is a configuration explanatory view showing crystal defects of an As ion implantation layer.

[Explanation of symbols]

 5 Si substrate 6 As ions 7 Bonding layer 8 Ion implantation region

Claims (2)

(57) [Claims] 1. A by implanting ions at a low acceleration energy on a semiconductor substrate to form an ion implanted region, denoted by the low-temperature heat treatment to restore the crystallinity of the ion-implanted region, then Ranpua
A method for manufacturing a semiconductor device, which comprises performing a high-temperature and short-time heat treatment by a Neil method to form a highly activated bonding layer. 2. The method according to claim 1 , wherein the low acceleration energy is 20 keV or less.
2. A method for manufacturing a semiconductor device according to claim 1.