TWI707471B - Ｆｉｎｆｅｔ裝置及製造方法 - Google Patents

Ｆｉｎｆｅｔ裝置及製造方法 Download PDF

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TWI707471B
TWI707471B TW108113057A TW108113057A TWI707471B TW I707471 B TWI707471 B TW I707471B TW 108113057 A TW108113057 A TW 108113057A TW 108113057 A TW108113057 A TW 108113057A TW I707471 B TWI707471 B TW I707471B
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輝 臧
謝瑞龍
史考特 畢索爾
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美商格芯（美國）集成電路科技有限公司
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Abstract

一種製造finFET以防止閘極接觸部與溝槽矽化物(TS)電氣短路之方法。具體實施例包括在基板上方形成finFET，該finFET包含閘極之側邊處所形成之磊晶S/D區；在該磊晶S/D上方凹口中形成α-Si層；在該α-Si層上方形成氧化物層；在該基板上方形成非TS隔離開口；在該非TS隔離開口中形成低介電常數層；移除該氧化物層與α-Si層；形成位在該閘極上方之開口、及位在該磊晶S/D區上方之開口；以及形成位在該閘極上方該開口中之閘極接觸部、及位在該磊晶S/D區上方該開口上方之磊晶S/D接觸部。

Description

FINFET裝置及製造方法
本揭露係關於半導體製作。特別的是，本揭露係關於鰭式場效電晶體(finFET)製作。
FinFET在電子器件中常用於切換、放大、濾波等。FinFET呈現理想之短通道行為，並且包括垂直鰭片中所形成之通道。finFET結構可使用與習知平面型金屬氧化物半導體場效電晶體(MOSFET)所用者類似之布局及處理步驟來製作。
與需要某些設計特徵之積體電路裝置相關聯之更高密度及效能需求不斷增加，諸如更短之閘極長度、高可靠性及提升之製造。關鍵尺寸持續縮減已經為習知製作技術之局限性帶來挑戰。因此，正在探索新裝置結構，以改善finFET效能並允許進一步裝置比例縮放。
習知之溝槽矽化物處理導致閘極接觸凹穴過蝕刻，使其可伸抵磊晶(epi)S/D區並導致電氣短路。第1圖在截面圖中繪示高介電常數金屬閘極(high dielectric constant metal gate；HKMG)103周圍所形成之過蝕刻區101。一旦以金屬填充凹穴而形成閘極接觸部(gate contact)105， 閘極接觸部105便與磊晶S/D區107接觸。這種類型之短路也會發生在使用低介電常數隔離技術之取代接觸期間，該等低介電常數隔離技術導致過蝕刻產生可延展至磊晶S/D區107之凹穴。
因此，需要能夠製作finFET裝置而不使閘極接觸部電氣短路至磊晶S/D之方法。
本揭露之一態樣是一種用於形成中段(middle of line；MOL)FinFET裝置防止閘極接觸部與磊晶S/D短路之方法、以及相關裝置。
本揭露之附加態樣及其它特徵將會在以下說明中提出，並且對於審查以下內容之所屬技術領域中具有通常知識者部分將會顯而易見，或可經由實踐本揭露來學習。可如隨附申請專利範圍中特別指出的內容來實現並且獲得本揭露的優點。
根據本揭露，有一些技術功效可藉由一種方法來部分達成，該方法包括：在基板(substrate)上方形成finFET，該finFET包括閘極之側邊處所形成之磊晶S/D區；在該磊晶S/D上方凹口中形成非晶矽(α-Si)層；在該α-Si層上方形成氧化物層；在該基板上方形成非溝槽矽化物(非TS)隔離開口；在該非TS隔離開口中形成低介電常數層；移除該氧化物層及α-Si層以在磊晶S/D區上方形成開口；以及形成位在該閘極上方開口中之閘極接觸部、及位在該磊晶S/D區上方該開口上方之磊晶S/D接觸部。
本揭露之態樣包括：該finFET具有多晶矽虛設(dummy)閘極之側邊處所形成之該磊晶S/D區。其它態樣包括：該磊晶S/D包括磊晶生長之矽鍺(SiGe)。又進一步態樣包括：在該α-Si層上方形成該氧化物層之後，用金屬閘極或HKMG取代該多晶矽虛設閘極。另一態樣包括：該閘極接觸部包括鉭、鎢、鈦或鋁。其它態樣包括：在該閘極上方形成氮化矽蓋體(cap)。另一態樣包括：形成氧化矽之低介電常數層。又另一態樣包括：該氧化矽包括碳氧化矽(SiOC)或碳化矽(SiC)。其它態樣包括：在該基板上方形成並圖案化光阻層；以及蝕刻穿過該光阻以形成位在該閘極上方之該開口、及位在該磊晶S/D區上方之該開口。
本揭露之另一態樣是一種裝置，其包括：基板上方所形成之finFET，其中該等finFET其中一者包括HKMG之側邊處所形成之磊晶S/D區；該等finFET之間所形成之低介電常數層；以及在截面中檢視時該HKMG之上表面上所形成之閘極接觸部，並且該閘極接觸部未與該磊晶S/D區接觸。
本揭露之態樣包括：該磊晶S/D包括磊晶生長之SiGe。其它態樣包括：該閘極接觸部包括鉭、鎢、鈦或鋁。又進一步態樣包括：該低介電常數層為氧化矽。另一態樣包括：該氧化矽包括SiOC或SiC。
本揭露之又另一態樣是一種方法，其包括：在基板上方形成finFET，該finFET包含閘極、側壁間隔物、及磊晶S/D區；在該磊晶S/D區上方形成第一介電質，該 第一介電質包含底端光阻層及頂端介電質蓋體；將該第一介電質之第一部分從非TS隔離區移除；將該側壁間隔物從該閘極移除，以在該閘極與該磊晶S/D區之間形成開口；用第二介電質填充介於該閘極與該磊晶S/D區之間的該開口；移除該第一介電質之第二部分以曝露該磊晶S/D區上方之該底端光阻層；移除該底端光阻層以曝露該磊晶S/D區；移除閘極蓋體以曝露該閘極；以及形成磊晶S/D接觸部與閘極接觸部。
本揭露之態樣包括：移除該側壁間隔物及高介電常數層。其它態樣包括：形成該finFET，其具有多晶矽虛設閘極之側邊處所形成之該磊晶S/D區。又進一步態樣包括：該磊晶S/D包括磊晶生長之SiGe。另一態樣包括：用金屬閘極或HKMG取代該多晶矽虛設閘極。其它態樣包括：該閘極接觸部包括鉭、鎢、鈦或鋁。
本揭露之附加態樣及技術功效經由以下詳細說明對於所屬技術領域中具有通常知識者將會輕易地變為顯而易見，其中本揭露之具體實施例單純地藉由經深思用以實行本揭露之最佳模式的說明來描述。如將會瞭解的是，本揭露能夠是其它及不同的具體實施例，而且其數項細節能夠在各種明顯方面進行修改，全都不會脫離本揭露。因此，圖式及說明本質上要視為說明性，而不是作為限制。
101:過蝕刻區
103:高介電常數金屬閘極(HKMG)
105,203:閘極接觸部
107,209:磊晶源極/汲極(S/D)區
201:金屬閘極或高介電常數金屬閘極(HKMG)
201a:虛設多晶矽閘極
205,217:源極/汲極(S/D)接觸部
207:氮化物蓋體或SiN蓋體
211:高k介電層或低k介電層
213:淺溝槽隔離(STI)區
215:矽鰭、半導體鰭片或鰭片
219:側壁間隔物
221,231:開口
223:底端光阻層
225:頂端介電質蓋體
227:非溝槽矽化物(TS)隔離區
229:低k介電質
233:光學平坦化層(OPL)
本揭露是在隨附圖式的附圖中舉例來說明，但非作為限制，圖中相似的參考元件符號係指類似的元件， 並且其中：第1圖在截面圖中示意性繪示利用習知處理所產生之finFET裝置，其導致閘極接觸部與磊晶S/D短路；第2A圖在俯視圖中示意性繪示根據一例示性具體實施例產生具有閘極接觸部之finFET裝置；第2B圖至第2D圖根據一例示性具體實施例，沿著第2A圖之多條線在截面圖中示意性繪示finFET裝置；第2E圖根據一例示性具體實施例在俯視圖中示意性繪示finFET裝置；以及第2F圖至第2W圖根據一例示性具體實施例，沿著第2E圖之多條線在截面圖中示意性繪示用於製作finFET裝置之程序步驟。
在底下的說明中，為了解釋，提出許多特定細節以便透徹理解例示性具體實施例。然而，應顯而易知的是，沒有這些特定細節或利用均等配置也可實踐例示性具體實施例。在其它實例中，眾所周知的結構及裝置是以方塊圖形式來展示，為的是要避免不必要地混淆例示性具體實施例。另外，除非另有所指，本說明書及申請專利範圍中用來表達成分、反應條件等等之量、比率、及數值特性的所有數字都要了解為在所有實例中是以「約」一語來修飾。
本揭露因應並解決習知finFET裝置製作時 伴隨而來之閘極接觸部及附近磊晶S/D區之目前問題。根據本揭露之具體實施例之方法包括：在基板上方形成finFET，該finFET包括閘極之側邊處所形成之磊晶S/D區；在該磊晶S/D上方凹口中形成α-Si層；在該α-Si層上方形成氧化物層；在該基板上方形成非TS隔離開口；在該非TS隔離開口中形成低介電常數層；移除該等氧化物層與α-Si層；形成位在該閘極上方之開口、及位在該磊晶S/D區上方之開口；以及形成位在該閘極上方該開口中之閘極接觸部、及位在該磊晶S/D區上方該開口上方之磊晶S/D接觸部。
單純地藉由所思最佳模式的描述，還有其它態樣、特徵、以及技術功效經由下文的詳細說明對於所屬技術領域中具有通常知識者將顯而易知，其中所示及所述為較佳具體實施例。本揭露能夠有其它及不同具體實施例，並且其數項細節能夠用各種明顯觀點來修改。因此，圖式及說明書本質上要視為說明性，而不是作為限制。
第2A圖根據一例示性具體實施例，為finFET裝置之俯視圖，其包括金屬閘極201或HKMG 201、以及閘極接觸部203與S/D接觸部205。第2B圖為沿著第2A圖之線條A-A’的截面圖。在第2B圖中，以截面展示金屬閘極或HKMG 201。在這項實施例中，繪示多個HKMG 201。其中兩個HKMG 201上方形成氮化物蓋體207，而其中一個HKMG 201包括閘極接觸部203，其侷限於這一個HKMG 201之上表面。氮化物蓋體207可由氮化矽 (SiN)所構成。閘極接觸部203係由金屬所構成，並且可選自於鉭、鎢、鈦或鋁。閘極接觸部203侷限於中間HKMG 201之上表面，並且未向下延展至磊晶S/D區209，其繪示於第2B圖中之背景中。在第2B圖中，HKMG 201可包括高k介電層211。高k介電層211可包括HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3等。HKMG可包括金屬或金屬化合物，諸如Mo、Cu、W、Ti、Ta、TiN、TaN、NiSi、CoSi、及/或其它合適之導電材料。低介電常數(低k)介電層211係位於第2B圖中HKMG 201之側邊。諸鰭片之間形成STI區213。第2B圖中之HKMG 201與非TS隔離區中之低k介電層211直接接觸。低k是一種相對於二氧化矽(SiO2)具有小介電常數之材料。SiO2之介電常數為3.9。用於層件211之低k材料實施例包括具有介電常數低於3.9之SiOC或SiC。
第2C圖為沿著第2A圖之線條B-B’的截面圖。此視圖之前景中繪示磊晶S/D區209。進行磊晶生長程序，以將矽鰭215之半導體材料與磊晶生長層或「磊晶(epi)」層合併。S/D接觸部217係由S/D區209上方之金屬所構成。起始finFET結構可在任何合適之基板上形成，諸如絕緣體上矽(silicon-on-insulator；SOI)、矽鍺(SiGe)或塊體(bulk)半導體基板。複數個半導體鰭片215係在基板上使用所屬技術領域中合適之任何技術所形成，包括光阻/硬遮罩圖案化及蝕刻。用於鰭片215及磊晶S/D區209兩者之半導體材料可以相同(例如矽、SiGe)。淺溝槽隔離(shallow trench isolation；STI)區213係置於諸鰭片之間。STI區可包括二氧化矽(SiO2)。然後，可任選地摻雜不在HKMG結構底下之鰭片部分以形成磊晶S/D區209。磊晶S/D區209係形成於HKMG 201之對立面。鰭片215包括finFET之通道，並且將會耦接至finFET之磊晶S/D區209。在第2C圖中，側壁隔離物219係繪示成位在HKMG 201之側邊上。第2D圖為沿著第2A圖之線條C-C’的截面圖。
第2E圖為包括虛設多晶矽閘極201a及磊晶S/D區之finFET裝置的俯視圖。第2F圖為沿著第2E圖之線條A-A’的截面圖。在第2F圖中，多晶矽虛設閘極包括虛設多晶矽閘極201a之對立面處所形成之側壁間隔物219及磊晶S/D區209。虛設多晶矽閘極201a之上表面上方形成SiN蓋體207。第2G圖為沿著第2E圖之線條B-B’的截面圖。鰭片215包括finFET之通道，並且將會耦接至finFET之磊晶S/D區209。磊晶S/D區209上方形成開口221。第2G圖為沿著第2E圖之線條B-B’的截面圖。
第2H圖為沿著第2E圖之線條A-A’的截面圖。第2I圖為沿著第2E圖之線條B-B’的截面圖。開口221(第2F圖及第2G圖)係以雙層層間介電質(inter layer dielectric；ILD)來填充。雙層ILD包括底端光阻層223及頂端介電質蓋體225。底端光阻層223為犧牲層，並且可包括形成為0.01μm至0.7μm厚度之非晶矽(α-Si)。頂端介電質蓋體225係由氧化物所構成，其包括形成為0.01μm至0.7μm厚度之SiO2。
第2J圖及第2K圖在截面圖中繪示用以形成HGMG 201之虛設多晶矽閘極201a移除及取代金屬閘極(replacement metal gate；RMG)沉積。第2J圖為沿著第2E圖之線條A-A’的截面圖。第2K圖為沿著第2E圖之線條B-B’的截面圖。
第2L圖為沿著第2E圖之線條A-A’的截面圖。第2M圖為沿著第2E圖之線條B-B’的截面圖。從第2L圖中STI區213上方非TS隔離區227移除雙層ILD之第一部分，包括底端光阻層223及頂端介電質蓋體225。第2M圖中之雙層ILD留在磊晶S/D區209上方。
第2N圖為沿著第2E圖之線條A-A’的截面圖。第2O圖為沿著第2E圖之線條B-B’的截面圖。將側壁間隔物219從非TS隔離區227移除，如第2N圖所示。
第2P圖為沿著第2E圖之線條A-A’的截面圖。第2Q圖為沿著第2E圖之線條B-B’的截面圖。在非TS隔離區227中沉積並平坦化低k介電質229，如第2P圖所示。
第2R圖為沿著第2E圖之線條A-A’的截面圖。第2S圖為沿著第2E圖之線條B-B’的截面圖。如第2S圖所示，將雙層ILD從磊晶S/D區209上方移除以曝露磊晶S/D區209。開口231係用於要在稍後程序形成之磊晶S/D接觸部。
第2T圖為沿著第2E圖之線條A-A’的截面圖。第2U圖為沿著第2E圖之線條B-B’的截面圖。在第 2T圖中，於HKMG 201其中一者上方沉積並圖案化光學平坦化層(optical planarization layer；OPL)233。反應性離子蝕刻(reactive ion etching；RIE)移除低k介電層229及SiN蓋體207，以曝露將形成閘極接觸部203之HKMG 201之上表面。在第2U圖中，OPL 233填充磊晶S/D區209上方之開口231。
第2V圖為沿著第2E圖之線條A-A’的截面圖。第2W圖為沿著第2E圖之線條B-B’的截面圖。剥除剩餘OPL 233。進行矽化物及金屬化以產生閘極接觸部203及磊晶S/D接觸部205。形成接觸部203及205後可進行附加MOL處理。
本揭露之具體實施例可實現數種技術功效，包括防止閘極接觸部與附近磊晶S/D區之間的電氣短路。本揭露之具體實施例提供了一種用以防止此類電氣短路之新穎處理技術。本揭露在各種工業應用之任一者中享有產業利用性，例如，微處理器、智慧型手機、行動電話、蜂巢式手機、機上盒、DVD錄影機與播放器、車輛導航、印表機與週邊裝置、網路與電信設備、遊戲系統、以及數位照相機。因此，本揭露在包括7奈米及更先進的技術節點中使用半導體鰭片之各類半導體裝置中任一者方面享有產業利用性。
在前述說明中，本揭露係參照其具體例示性具體實施例作說明。然而，將會證實可對其進行各種修改及變更，但不會脫離本揭露的更廣泛精神與範疇，如申請專利範圍中所提。本說明書及圖式從而要視為說明性而非作為限制。據了解，本揭露能夠使用各種其它組合及具體實施例，並且如本文中所表達，能夠在本發明概念的範疇內作任何變更或修改。
201‧‧‧金屬閘極或高介電常數金屬閘極(HKMG)
207‧‧‧氮化物蓋體或SiN蓋體
209‧‧‧磊晶源極/汲極(S/D)區
215‧‧‧矽鰭、半導體鰭片或鰭片
217‧‧‧源極/汲極(S/D)接觸部
219‧‧‧側壁間隔物或SiN蓋體

Claims (20)

  1. 一種半導體裝置，包含：基板上方所形成之多個鰭式場效電晶體(finFET)，其中，第一finFET包含高介電常數金屬閘極(HKMG)之側邊處所形成之磊晶源極/汲極(磊晶S/D)區，其中，在截面中檢視時第二finFET形成於該磊晶S/D區的第一側邊，並且第三finFET形成於該磊晶S/D區的第二側邊，以及其中，在截面中檢視時該第一finFET係置於該第二finFET及該第三finFET之間；該第一finFET、該第二finFET及該第三finFET之間所形成之低介電常數層；以及在截面中檢視時該HKMG之上表面上所形成之閘極接觸部，且該閘極接觸部未與該磊晶S/D區接觸。
  2. 如申請專利範圍第1項所述之半導體裝置，其中，該磊晶S/D區包含磊晶生長之矽鍺(SiGe)。
  3. 如申請專利範圍第1項所述之半導體裝置，其中，該閘極接觸部包含鉭、鎢、鈦或鋁，並且在截面中檢視時該第二finFET及該第三finFET皆具有上表面，氮化物蓋體置於該二finFET及該第三finFET的各該上表面上。
  4. 如申請專利範圍第1項所述之半導體裝置，其中，該低介電常數層是氧化矽。
  5. 如申請專利範圍第4項所述之半導體裝置，其中，該氧化矽包含碳氧化矽(SiOC)或碳化矽(SiC)。
  6. 一種製作半導體裝置之方法，該方法包含： 在基板上方形成鰭式場效電晶體(finFET)，該finFET包含閘極之側邊處所形成之磊晶源極/汲極(磊晶S/D)區；在該磊晶S/D區上方凹口中形成非晶矽(α-Si)層；在該α-Si層上方形成氧化物層；在該基板上方形成非溝槽矽化物(非TS)隔離開口；在該非TS隔離開口中形成低介電常數層；移除該氧化物層及α-Si層，在該磊晶S/D區上方形成開口；以及形成位在該閘極上方開口中之閘極接觸部、及位在該磊晶S/D區上方該開口上方之磊晶S/D接觸部。
  7. 如申請專利範圍第6項所述之方法，其中，該finFET包含多晶矽虛設閘極之側邊處所形成之該磊晶源極/汲極(磊晶S/D)區。
  8. 如申請專利範圍第7項所述之方法，其中，該磊晶S/D區包含磊晶生長之矽鍺(SiGe)。
  9. 如申請專利範圍第8項所述之方法，更包含：在該α-Si層上方形成該氧化物層之後，用金屬閘極或高介電常數金屬閘極(HKMG)取代該多晶矽虛設閘極。
  10. 如申請專利範圍第6項所述之方法，其中，該閘極接觸部包含鉭、鎢、鈦或鋁。
  11. 如申請專利範圍第6項所述之方法，更包含：在該閘極上方形成氮化矽蓋體。
  12. 如申請專利範圍第11項所述之方法，包含： 形成氧化矽之該低介電常數層。
  13. 如申請專利範圍第11項所述之方法，其中，該氧化矽包含碳氧化矽(SiOC)或碳化矽(SiC)。
  14. 如申請專利範圍第6項所述之方法，更包含：在該基板上方形成並圖案化光阻層；以及蝕刻穿過該光阻層以形成位在該閘極上方之該開口、及位在該磊晶S/D區上方之該開口。
  15. 一種製作半導體裝置之方法，該方法包含：在基板上方形成鰭式場效電晶體(finFET)，該finFET包含閘極、側壁間隔物、及磊晶源極/汲極(磊晶S/D)區；在該磊晶S/D區上方形成第一介電質，該第一介電質包含底端光阻層及頂端介電質蓋體；將該第一介電質之第一部分從非溝槽矽化物(非TS)隔離區移除；將該側壁間隔物從該閘極移除，以在該閘極與該磊晶S/D區之間形成開口；用第二介電質填充介於該閘極與該磊晶S/D區之間的該開口；移除該第一介電質之第二部分以曝露該磊晶S/D區上方之該底端光阻層；移除該底端光阻層以曝露該磊晶S/D區；移除閘極蓋體以曝露該閘極；以及形成磊晶S/D接觸部與閘極接觸部。
  16. 如申請專利範圍第15項所述之方法，更包含：移除該側壁間隔物及高介電常數層。
  17. 如申請專利範圍第15項所述之方法，其中，該finFET包含多晶矽虛設閘極之側邊處所形成之該磊晶S/D區。
  18. 如申請專利範圍第17項所述之方法，其中，該磊晶S/D區包含磊晶生長之矽鍺(SiGe)。
  19. 如申請專利範圍第17項所述之方法，更包含：用金屬閘極或高介電常數金屬閘極(HKMG)取代該多晶矽虛設閘極。
  20. 如申請專利範圍第15項所述之方法，其中，該閘極接觸部包含鉭、鎢、鈦或鋁。
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