TWI706467B - 具有磊晶生長之源極／汲極區的電晶體之電阻降低方法 - Google Patents

具有磊晶生長之源極／汲極區的電晶體之電阻降低方法 Download PDF

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TWI706467B
TWI706467B TW105114729A TW105114729A TWI706467B TW I706467 B TWI706467 B TW I706467B TW 105114729 A TW105114729 A TW 105114729A TW 105114729 A TW105114729 A TW 105114729A TW I706467 B TWI706467 B TW I706467B
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里沙 梅安卓
安拿 莫希
塔何 甘尼
葛蘭 葛雷斯
卡希克 強普納森
子烜 馬
科瑞 韋伯
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美商英特爾股份有限公司
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Abstract

本發明揭示用於具有磊晶生長之摻雜硼的矽鍺(SiGe：B)S/D區的p-MOS電晶體之電阻降低的技術。該等技術可包括使一或多個介面層在該電晶體之矽(Si)渠道區與該等SiGe：B置換S/D區之間生長。該一或多個介面層可包括：摻雜硼之Si(Si：B)單層；SiGe：B單層，其中在該介面層中之Ge含量少於在所得之SiGe：B S/D區中者；SiGe：B漸變層(graded layer)，其中在該合金中Ge含量始於低百分比(或0%)且增至較高百分比；或多個SiGe：B階變層(stepped layer)，其中在該合金中Ge含量始於低百分比(或0%)且在各階中增至較高百分比。併入該介面層降低了開通態之電流流動的電阻。

Description

具有磊晶生長之源極/汲極區的電晶體之電阻降低方法
本發明係關於具有磊晶生長之源極/汲極區的電晶體之電阻降低方法。
在基材上之電路裝置(包括在半導體基材上所形成之電晶體、二極體、電阻器、電容器、及其他被動和主動電子裝置)之提高的效能和產率在那些裝置之設計、製造、和操作期間是一般主要考慮因素。例如，在金屬氧化物半導體(MOS)電晶體半導體裝置(諸如在互補型金屬氧化物半導體(CMOS)裝置中使用者)之設計和製造或形成期間，常希望增加電子(載體)在n型MOS裝置(n-MOS)渠道中的移動及增加帶正電荷之電洞(載體)在p型MOS裝置(p-MOS)渠道中的移動。一般之CMOS電晶體裝置利用矽作為用於電洞和電子主體載體MOS渠道二者之渠道材料。實例裝置還利用平面、鰭片-FET和奈 米線幾何形狀之電晶體。
本發明揭示具有磊晶生長之摻雜硼的矽鍺(SiGe：B)S/D區之p-MOS電晶體的電阻降低技術。該技術可包括在電晶體之矽(Si)渠道區與該SiGe：B置換S/D區之間生長一或多個介面層。該一或多個介面層可包括：摻雜硼之Si(Si：B)單層；SiGe：B單層，其中在該介面層中Ge含量低於在所得之SiGe：B S/D區；SiGe：B漸變層，其中在該合金中Ge含量始於低百分比(或0%)且增至更高百分比；或多個SiGe：B階變層，其中在該合金中Ge含量始於低百分比(或0%)且逐階增至更高百分比。在一些情況中(其中該摻雜硼之介面層在一或多個退火程序期間進行熱處理)，硼可擴散到周圍的層。因此，根據用以完成該半導體裝置之形成的熱歷史，該摻雜硼之介面層可占據比原初所沉積者更窄或更寬之區。藉由包括該介面層，該技術改良在該Si渠道與SiGe：B區之間的價能帶偏差，藉此在開通態電流期間提供經改良之用於使載體隧穿過的介面區。例如，該介面層可藉由達成驅動電流增加至少10-50%而改良效能。鑒於本揭示，很多變化型和組態將是明顯的。
一般概述
當形成電晶體時，磊晶生長之摻雜硼的矽鍺 (SiGe：B)的源極/汲極(S/D)區可提供高應力給p-MOS矽(Si)裝置以強化在該渠道區中之移動性。然而，此種該S/D區之置換可形成異介面而導致在該Si渠道與SiGeS/D區之間價能帶的不連續性。該價能帶偏差可以引起開通態電流之大衰退。例如，圖5A闡明常見之p-MOS電晶體裝置之能帶圖解概圖。如可見到的，顯示用於Si渠道區506和SiGe S/D區508之價能帶502。在該Si/SiGe異介面，由於二材料間之帶結構差異，產生價能帶偏差。由於帶正電電洞(載體)509需要穿過所示之熱離子放射阻障體504，導致增加的電阻，而使開通態電流大幅下降。開通態電流之降低是不合宜的，因為彼導致效能降低。應付此問題之一技術係在SiGe：B沉積後，利用由熱循環擴散出硼以提供充份摻雜過該異介面阻障。然而，此一技術導致大的擴散尾進入該渠道而不利地影響短渠道效應，藉此使整體裝置效能變差。
因此，且根據本揭示之一或多個具體例，揭示用於具有磊晶生長SiGe S/D區之p-MOS電晶體的電阻降低的技術。在一些具體例中，該等技術包括在該Si渠道區與該等SiGe：B置換S/D區之間生長一或多個介面層。在一些此等具體例中，該一或多個介面層可包括：摻雜硼之Si(Si：B)單層；SiGe：B單層，其中在該介面層中Ge含量低於在所得之SiGe：B S/D區中者；SiGe：B漸變層，其中在該合金中Ge含量始於低百分比(或0%)且增至更高百分比；及/或多個SiGe：B階變層，其中在該合金中Ge含 量始於低百分比(或0%)且增至更高百分比。為易於描述，SiGe在本文中可被稱為Si1-xGex，其中x表示在該SiGe合金中Ge之百分比(小數型式)且1-x表是在該SiGe合金中Si的百分比(小數型式)。例如，若x是0.3，則該SiGe合金包含30%Ge和70%Si，或若x是0，則該SiGe合金包含0%Ge和100%Si，或若x是0.6，則該SiGe合金包含60%Ge和40%Si，或若x是1，則該SiGe合金包含100%Ge和0%Si。因此，Si在本文中可被稱為SiGe(Si1-xGex，其中x是0)且Ge在本文中可被稱為SiGe(Si1-xGex，其中x是1)。
如先前描述的，在一些具體例中，在該Si渠道區與該等SiGe：B置換S/D區之間的介面層可包含Si：B單層。在一些此等具體例中，該Si：B單介面層可具有1-10nm之厚度，且更特別地2-5nm之厚度，或根據最後用途或標的應用，具有一些其他適合之厚度。在一些具體例中，該介面層可包含摻雜硼之矽鍺(SiGe：B)單層。在一些此等具體例中，該Si：B單介面層可具有1-10nm之厚度，且更特別地2-5nm之厚度，或根據最後用途或標的應用，具有一些其他適合之厚度。另外，在一些此等具體例中，在該單介面層中Ge含量百分比可以低於所得之SiGe：B S/D區中者。例如，若所得之SiGe：B S/D區包含30%Ge，則可沉積具有15%Ge之介面層。因此，在一些具體例中，在SiGe：B S/D區中Ge含量百分比可決定在該介面層中使用之Ge含量百分比，如鑒於本揭示將是明顯 的。例如，在該介面層中Ge含量百分比可被選擇以比在該等SiGe：B S/D區中Ge含量百分比低10-25%。如在本文中使用的，注意："單層"是指相同材料之連續層且可具有在奈米範圍(或更厚，若有此需要)之由單層至相對厚之層的隨意厚度範圍。另外注意：此一單層可以例如在多程(multiple passes)或磊晶生長循環中被沉積，以至於實際上包含多個常見材料的子層而構成該常見材料之整體單層。另外注意：該單層之一或多種組份可在該沉積程序期間由第一濃度漸變成第二濃度。
如本文中使用的，注意："單層"係指相同材料之連續層且可具有在奈米範圍(或更厚，若有此需要)之由單層至相對厚之層的隨意厚度範圍。並且注意：此一單層可以例如被沉積，以至於實際上包含多個常見材料的子層而構成該常見材料之整體單層。另外注意：該單層之一或多種組份可在該沉積程序期間由第一濃度漸變成第二濃度。
在一些具體例中，該介面層可包括多個SiGe：B層，其中在該介面層中Ge含量百分比係以逐階方式增加。例如，在此一具體例中，可能在該Si渠道區與每一SiGe：B S/D區之間有三個介面層，其中最接近該渠道區之層具有Ge含量第一百分比，中間層具有比該第一百分比更大之Ge含量第二百分比，且最接近該對應S/D區之層具有比該第二百分比更大(但比在該等SiGe：B S/D區中Ge含量百分比更少)的Ge含量第三百分比。在此一實例中，該第一百分比可包含0%Ge含量(亦即Si：B)，該第二百分 比可包含10%Ge含量，且該第三百分比可包含20%Ge含量，以上僅列特定實例。在此一特定實例中，在該等SiGe：B S/D區中之Ge含量可包含30%之Ge含量。在一些具體例中，該介面層可包括漸變層，其中在該漸變層中Ge含量百分比在沉積期間增加。換言之，Ge含量百分比會由接近該渠道區之低百分比或0%增至接近對應S/D區之較高百分比。在一些此等具體例中，該漸變層可具有2-10nm之厚度，或根據最後用途或標的應用具有一些其他合適之厚度。
藉由在p-MOS電晶體之該Si渠道區與SiGe：B S/D區之間包括一或多個介面層(如本文中多方面地描述的)而獲得很多利益。例如，經由在圖5A和5B之實例價能帶的差異可以見到一利益。在圖5A中常見裝置的價能帶502顯示價能帶偏差，該價能帶偏差是在該Si渠道區506與該SiGe S/D區508之間的異介面507上，因該二材料之間之帶結構差異所引起。此一異介面507在開通態之電流期間造成經增加之電阻，藉此減低開通態之電流效能，因為需要使帶正電之電洞(載體)509穿過具有高電阻之熱離子發射阻障體504。由於藉由包括介面層517所形成之經改良的價能帶512，使用在本文中多方面地被描述之技術所形成之圖5B的p-MOS電晶體裝置與圖5A的裝置相比，具有較低之熱離子發射阻障體514。此經改良之價能帶512在開通態電流期間，導致降低之電阻，藉此增加開通態電流效能。在一實例具體例(其中該介面層517包 含Si：B單層)中，會有足夠之p-型摻雜劑橫過該異介面以允許載體509隧穿過該介面，而不是依賴穿過圖5A之常見裝置的大異介面507之熱離子發射阻障體504。在一實例具體例(其中該介面層517包含SiGe：B之漸變層或SiGe：B之階變層，其中該Ge含量分別以漸變或階變方式增加)中，該載體509可自由地或以改良方式由該SiGe S/D區508流至該Si渠道區506。此種效能獲得已利用具有0.6V之閘極偏壓和在該汲極上之0.05V之偏壓之線性規畫方式測量，以依照所用之介面層產生10-50%之驅動電流增加；然而，較高之增加可以依照所用之特別組態而達成。
在分析(例如使用掃描/透射電子顯微術(SEM/TEM)、組成測繪、及/或原子探針成像/3D斷層攝影術)時，根據一或多個具體例所配置之結構或裝置將有效地顯示一或多個如本文中多方面地被描述的介面層。例如，在該介面層包含Si：B單層的具體例中，該SiGe S/D區可被蝕刻且可使用分析技術測量在該介面層之矽中的硼摻雜以測定在該SiGe S/D區外部是否有鮮明之類似盒狀(box-like)的硼摻雜輪廓。另外，在該介面層包含具有增加之Ge含量百分比之階變多層或漸變層的具體例中，低Ge濃度或漸變Ge含量可藉由進行TEM之元素測繪或藉由收集原子探針影像(其會顯示鍺原子之3D輪廓)來偵測。該介面層之偵測也可藉由測量在該Si渠道區中是否有擴散尾及測量該尾之尺寸而達成。這是因為常見之包括磊晶生長之 SiGe：B S/D區的p-MOS電晶體裝置可利用在SiGe：B沉積後硼由熱循環擴散出，以提供充份摻雜橫過該異介面阻障體(其存在於該Si渠道區與該等SiGe：B S/D區之間)。然而，此一常見方法使大的擴散尾進入該Si渠道區而引起負面的短渠道效應(如藉由低閾電壓和高的源極對汲極電流洩漏所指明的)，因此使整體裝置效能劣化。使用在本文中多方面地被描述之技術，以一或多個介面層所形成之p-MOS電晶體裝置可被形成，同時在該等SiGe：B S/D區沉積後使熱循環保持最少，因此改良短渠道效應(或至少不傷害該短渠道效應)，同時仍獲得經改良之開通態電流。因此，在本文中描述之技術可以藉由改良開通電流流動瓶頸在極小閘長度下能有持續的電晶體效能。鑒於本揭示，很多組態和變化將是明顯的。
100:形成積體電路之方法
102:進行淺凹槽凹陷以在Si基材中產生鰭片
104:沉積淺凹槽絕緣(STI)材料且平面化
106:[非必需的]凹陷化STI材料以獲得用於鰭片構造之所要的鰭片高度
108:進行井摻雜處理
110:進行閘極處理
112:蝕刻源極/汲極(S/D)區
114:沉積介面層在S/D凹槽中
116:沉積摻雜硼之SiGe於S/D區中
118:完成電晶體之形成
200:基材
210:鰭片
212、214:S/D區
213、215:凹槽
220:STI材料
230:閘極疊合物
232:閘電極
234:間隔件
236:硬罩
240:介面層
252、254:SiGe：B S/D區
256:Si渠道區
260:相關平面A-A的橫截面視圖
340:介面層
402:渠道區
404:奈米線或奈米帶
504:熱離子發射阻障體
506:Si渠道區
507:異介面
508:SiGe S/D區
509:帶正電荷之電洞(載體)
512:價能帶
514:熱離子發射阻障體
517:介面層
1000:計算系統
1002:母板
1004:處理器
1006:通信晶片
圖1闡明根據本發明之不同具體例之積體電路的形成方法。
圖2A-H闡明根據本發明之不同具體例之實例結構，其係在實施圖1的方法時所形成的。
圖2I顯示根據本發明之不同具體例之圖2H中相關平面A-A的橫截面視圖。
圖3顯示根據本發明之一具體例圖2H中相關平面A-A的橫截面視圖以闡明多個介面層及/或漸變介面層。
圖4A闡明根據本發明之一具體例之實例積體電路， 其包括二個具有鰭片狀組態之電晶體結構。
圖4B闡明根據本發明之一具體例之實例積體電路，其包括二個具有奈米線組態之電晶體結構。
圖4C闡明根據本發明之一具體例之實例積體電路，其包括二個電晶體結構，一者具有鰭片狀組態且一者具有奈米線組態。
圖5A闡明常見之p-MOS電晶體裝置之帶型圖解概圖。
圖5B闡明根據本發明之具體例所形成之p-MOS電晶體裝置之帶型圖解概圖。
圖6闡明根據本發明之多種具體例之計算系統，其係以使用本文所揭示之技術所形成之積體電路結構或電晶體裝置來實施。
構造和方法
圖1闡明根據本發明之一或多個具體例之形成積體電路的方法100。圖2A-I闡明根據多種具體例之實例結構，其係當實施圖1之方法100時形成。如鑒於所形成之結構將顯明的，方法100揭示用於形成具有Si渠道區、磊晶生長SiGe：B S/D區、及其間之一或多個介面層的電晶體的技術。圖3闡明根據一具體例之與圖2I之結構類似的實例結構，包括多個介面層及/或漸變介面層。圖2A-I的結構在形成鰭片狀電晶體組態(例如三閘極或鰭片-FET) 的背景中被初步地描繪且描述於本文中以易於闡明。然而，可以使用該等技術以形成平面、雙閘極、鰭片狀、及/或奈米線(或閘極圍繞或奈米帶)電晶體組態、或其他合適之組態，如鑒於本發明將顯明的。例如，圖4A-4C闡明實例獲得之電晶體，彼之一些包括奈米線組態，如以下將更詳細討論的。
如圖1中可見到的，方法100包括進行102淺凹槽凹陷以在Si基材200中產生鰭片210，藉此形成根據具體例之在圖2A中顯示之實例獲得的結構。在一些具體例中，基材200可以是：包含Si之整塊基材；在絕緣體結構上之Si(SOI)，其中該絕緣體材料是氧化物材料或介電材料或一些其他的電絕緣材料；或一些其他合適之多層結構，其中上層包含Si。鰭片210可由基材200被形成102，其使用任何合適蝕刻技術，諸如下列程序之一或多者：溼式蝕刻、乾式蝕刻、微影法、光罩法、圖形化、曝光、顯影、抗蝕層自旋、灰化法、或任何其他的程序。在一些例子中，淺凹槽凹陷102可在原位上/無空斷(air break)下被進行，但在其他例子中，該程序102可在異地被進行。
根據最終用途和標的應用可形成鰭片210(及其間之凹槽)以具有任何想要之尺寸。雖然四個鰭片係在圖2A之實例結構中顯示，可以如想要地形成任何數目之鰭片，諸如一個鰭片、二個鰭片、二十個鰭片、一百個鰭片、一千個鰭片、一百萬個鰭片等。在一些情況中，可以形成所 有的鰭片210(及其間之凹槽)以具有類似或精確尺寸(例如在圖2A中顯示的)，但在其他情況中，根據最後使用或標的應用可以形成一些該等鰭片210(及/或其間之凹槽)以具有不同尺寸。在一些具體例中，可進行淺凹槽凹陷102以產生具有3或更高之高度對寬度比率的鰭片且可以使用此類鰭片於例如非平面之電晶體組態。在一些具體例中，可進行淺凹槽凹陷102以產生具有3或更低之高度對寬度比率的鰭片且可以使用此類鰭片於例如平面之電晶體組態。鑒於本揭示，多種不同的鰭片組態將是明顯的。
根據一具體例，圖1之方法100持續沉積104淺凹槽絕緣(STI)材料220且將該結構平面化以形成在圖2B中顯示之實例所得的結構。STI材料220之沉積104可使用任何合適技術(諸如化學蒸氣沉積(CVD)、電漿強化CVD(PECVD)、原子層沉積(ALD)、旋上(spin-on)處理、及/或任何其他合適程序)完成。在一些例子中，在沉積該STI材料220之前，可以處理基材200和待沉積之鰭片210的表面(例如，化學處理、熱處理等)。STI材料220可包含任何合適之絕緣材料諸如一或多種介電或氧化物材料(例如二氧化矽)。
根據一具體例，圖1之方法100持續非必需地凹陷化106該STI材料220以獲得用於所得之鰭片構造之所要的鰭片高度，藉此形成在圖2C中顯示之實例所得的結構。可以使用任何適合技術(諸如一或多種溼式及/或乾式蝕 刻程序或任何其他適合程序)，可以進行STI材料220之凹陷106。在一些例子中，可以在原位上/無空斷下進行凹陷106，但在其他例子中，可以在異地進行該凹陷106。在一些具體例中，可以省略凹陷106，諸如在所得之想要的電晶體構造是例如平面的情況中。因此，凹陷106是非必需的。在一些具體例中，當所得之想要的電晶體構造是非平面(例如鰭片狀或奈米線/奈米帶構造)時，可以進行凹陷106。根據一具體例，圖1之方法100持續進行108井摻雜處理。根據最後用途或標的應用，可以使用任何標準技術完成井摻雜108。例如，在形成p-MOS電晶體的情況中，可以使用n-型摻雜劑以摻雜至少該Si鰭片210之該部分而待稍後作為p-MOS渠道區。實例n-型摻雜劑可包括磷(P)和砷(As)，這是僅列舉一些實例。注意：根據使用之技術，井摻雜108可在方法100早期進行。
根據一具體例，圖1之方法100持續進行110閘極處理以形成在圖2D中顯示之實例所得之結構。使用任何標準技術，可以形成閘極疊合物230。例如，閘極疊合物230可包括在圖2E中顯示之閘電極232且在閘電極232正下方形成之閘極介電體(未顯示以易於闡明)。使用任何適合技術，可以形成閘極介電體和閘電極232且由任何適合材料可以形成該等層。該閘極介電體可以是例如任何適合氧化物諸如SiO2或高-k閘極介電材料。高-k閘極介電材料之實例包括例如氧化鉿、氧化給矽、氧化鑭、 氧化鑭鋁、氧化鋯、氧化鋯矽、氧化鉭、氧化鈦、氧化鋇鍶鈦、氧化鋇鈦、氧化鍶鈦、氧化釔、氧化鋁、氧化鉛鈧鉭、及鈮酸鉛鋅。在一些具體例中，可以對該閘極介電層進行退火程序以當使用高-k材料時改良其品質。通常，該閘極介電體之厚度應足以使該閘電極與該源極和汲極接點電絕緣。另外，該閘電極232可例如包含寬範圍之材料，諸如多晶矽、氮化矽、碳化矽、或多種適合之金屬或金屬合金，諸如鋁(Al)、鎢(W)、鈦(Ti)、鉭(Ta)、銅(Cu)、氮化鈦(TiN)、或氮化鉭(TaN)。
在一些具體例中，在置換金屬閘極(RMG)程序期間可以形成該閘極疊合物230，且此一程序可包括任何適合之沉積技術(例如CVD、PVD等)。此一程序可包括假閘極氧化物沉積、假閘電極(例如多晶Si)沉積、及圖形化硬罩沉積。另外的處理可包括圖形化該假閘極和沉積/蝕刻間隔件234材料。根據最後用途或標的應用，另外處理也可包括尖端(tip)摻雜。在此等程序之後，該方法可持續絕緣體沉積、平面化、然後假閘電極和閘極氧化物移除以曝露該電晶體之渠道區。在開放該渠道區之後，該假閘極氧化物和電極可分別用例如高k介電體和置換金屬閘極置換。如圖2E之實例結構中可見的，使用標準技術以形成間隔件234。可以形成間隔件234以例如在隨後之處理期間防護該閘極疊合物(諸如閘電極232及/或閘極介電體)。另外注意：圖2E之實例結構包括使用標準技術所形成之硬罩236。可以形成硬罩236以例如在隨後處理 期間防護該閘極疊合物(諸如閘電極232及/或閘極介電體)。
該閘極疊合物界定渠道區以及隨後形成之電晶體的源極和汲極區，其中該渠道區是在該閘極疊合物下方且該源極/汲極(S/D)區位於該渠道區之任一面上。例如，在圖2D中之閘極疊合物230下方的鰭片210的部份可被用於電晶體渠道區且在閘極疊合物230之任一面上的鰭片212和214的部份可被用於電晶體S/D區。注意：基於所得組態，212可被用於該源極區或該汲極區之任一者，且214可被用於另一區。因此，一旦該閘極疊合物被製造，該S/D區212和214可被處理。
根據一具體例，圖1之方法100持續蝕刻112 S/D區212和214以形成圖2F之所得的實例結構。如圖2F的實例結構可見到的，該S/D區212和214被微影圖形化且蝕刻以分別形成凹槽213和215。可以使用任何合適技術(諸如一或多種溼式及/或乾式蝕刻程序、或任何其他合適程序)以進行蝕刻112。在一些例子中，蝕刻112可在原位上/無空斷下進行，但在其他例子中，該蝕刻112可在異地進行。注意：在此實例具體例中，鰭片區212和214被蝕刻以形成凹槽213和215。然而，在用於平面電晶體組態(例如其中之凹陷106不被進行)所形成之結構中，反而是該源極/汲極擴散區被蝕刻112且被移除以形成凹槽。
根據一具體例，圖1之方法100持續沉積114一或多 個介面層240於該S/D凹槽213和215中以形成圖2G之所得的實例結構。根據一具體例，圖1之方法100持續沉積116摻雜硼之矽鍺(SiGe：B)252和254在該S/D區中的介面層240上以形成圖2H之所得的實例結構。根據一具體例，圖2I顯示在圖2H中相關平面A-A的橫截面視圖260以闡明單一介面層240。根據一具體例，圖3顯示在圖2H中相關平面A-A的橫截面視圖360以闡明多個介面層及/或漸變介面層340。如可了解的，層240係稱為介面層，因為該一或多層240位於該Si渠道區256與該置換SiGe：B S/D區252和254的介面上(如在圖2I中可見到的)。依照最後用途或標的應用，沉積114和116可包括本文所述之任何沉積程序(例如CVD、RTCVD、ALD等)、或任何其他合適沉積或生長程序。如在以下更詳細討論的，沉積114可包括沉積單一介面層、多個介面層、及/或漸變介面層(其中在該沉積程序期間正被沉積之一或多種材料係增加或降低)。在一些情況中，漸變層和多個階變層視覺上是類似的。然而，在一些情況中，例如，透過漸變層所進行之調節比在階變層中之調節是更平緩的。
在一些具體例中，介面層可包括摻雜硼之矽(Si：B)單層。例如，在圖2G-I中，介面層240可包含Si：B單層。在一些此等具體例中，該Si：B單介面層可具有1-10nm之厚度，且更特別是2-5nm之厚度，或根據最後用途或標的應用，具有一些其他合適之厚度。視需要，基於最 後結果或標的應用，可以選擇在該Si：B介面層中之硼摻雜量，諸如約1.0E20之摻雜水平或一些其他合適之量。注意：該Si：B介面層可包括與在該SiGe：B S/D區中之摻雜量相比更高、更低或相等之硼摻雜量。用以製造此一Si：B單介面層的條件的特定實例包括選擇性沉積程序，其使用二氯矽烷及/或矽烷、二硼烷、氫氯酸、及氫載體氣體於CVD反應器中，在20Torr壓力及700-750℃之溫度下，以例如導致硼濃度在或接近2E20原子/cm3之層。
在一些具體例中，該等介面層可包括摻雜硼之矽鍺(SiGe：B)單層。例如，在圖2G-I中之介面層240可包含SiGe：B單層。在一些此等具體例中，該SiGe：B單介面層可具有1-10nm之厚度，且更特別地2-5nm之厚度、或依照該最後用途或標的應用具有一些其他合適之厚度。另外，在一些此等具體例中，在該介面層中Ge含量可以是少於在所得之SiGe：B S/D區(例如在圖2H-I中之S/D區252和254)中者。在一實例具體例中，在該介面層中Ge含量可以比在該S/D區中Ge含量低5-30%，諸如低15-20%。例如，若所得之SiGe：B S/D區包含30%Ge(Si1-xGex：B，其中x是0.3)，則該SiGe：B介面層可包含15%Ge(Si1-xGex：B，其中x是0.15)。基於最後用途或標的應用，視需要地可選擇在該SiGe：B介面層中之硼摻雜量。注意：該SiGe：B介面層可包括與在該SiGe：B S/D區中的摻雜量相比更高、更低或相等之摻雜量。用以製造此一SiGe：B單介面層之條件的特定實例包括選擇性 沉積程序，其使用二氯矽烷及/或矽烷、鍺烷(germane)、二硼烷(diborane)、氫氯酸、及氫載劑氣體在CVD反應器中，於20Torr壓力和700-750℃溫度下，例如獲得具有在或接近2E20原子/cm3之硼濃度的層。
在一些具體例中，該介面層240可包括具有增加之Ge百分比的多個層及/或漸變層。例如，圖3中之介面層340可包含SiGe：B單漸變層，其中該Ge百分比由區342至區344至區346增加。在另一實例中，圖3中之介面層340可包含多個SiGe：B層，其中該Ge百分比由層342至層344至層346增加。在另一實例中，在圖3中之介面層340可包含Si：B或SiGe：B單層342及SiGe：B漸變層(其包括區344和346，其中該Ge百分比由區344至區346增加)。注意：可以根據最後用途或標的應用，視需要選擇各層或漸變區之厚度、Ge含量、及硼摻雜。例如，該Ge含量經過2-10nm之距離可由0%增至30%。在此一實例中，該增加可以是在多個層中階變的，以致例如層342包括0%Ge含量(Si：B或Si1-xGex：B，其中x是0)，且層344包括15%Ge含量(Si1-xGex：B，其中x是0.15)，且層346包括30%Ge含量(Si1-xGex：B，其中x是0.3)。在另一實例中，該增加可以是經過不同區漸變的，以致區342包括0-10%Ge含量，且區344包括10-20%Ge含量，且區346包括20-30%Ge含量。在一些具體例中，在一介面層中之Ge含量百分比可以基於在另一介 面層中之Ge含量百分比來決定。例如，在圖3之情況中，該最接近該對應S/D區252或254的介面層346可比在最接近該渠道區256之介面層342中的Ge含量高5、10、15、20、或25%或其他合適百分比。在一些具體例中，該介面層之Ge含量可以基於該等SiGe：B S/D區之Ge含量。例如，該等介面層可包括一Ge含量，其係由低Ge含量(例如0、5、10、或15%)漸變至在該等SiGe：B S/D區中之Ge含量(例如30、35、40、或50%)或至5、10、15、或20%之Ge含量百分比，或比在該等SiGe：B S/D區中之Ge含量百分比低之一些其他適合的百分比。
在一些具體例中，沉積114可包括基本同形之生長圖形，諸如在圖2I和3中可見到的。基本同形包括：在該渠道區256與該等S/D區252/254之間的介面層的一部份(例如在圖2I中之層240的垂直部份、在圖3中之層342、344、346的垂直部份)的厚度基本上與在該等S/D區與該基材200之間的介面層的一部份(例如在圖2I中之層240的水平部份、在圖3中之層342、344、346的水平部份)的厚度相同(例如差別在1或2nm之內)。注意：在包括多個介面層的具體例中，該層可具有基本相同或不同的厚度。另外注意：在一些包括漸變介面層之具體例中，Ge含量漸變的百分比在整個該層中可以一致或可以不一致。並且注意：在一些例子中，多個介面層可包括一些程度之Ge含量漸變且漸變介面層可包括一些程度之 Ge階變含量區而可以展現為不同的層。換言之，在整個介面層中之Ge含量百分比的變換可以是平緩的、階變的或彼之某些組合。另外注意：由該介面層至該S/D區，Ge含量百分比的變換可以是平緩的、階變的或彼之某些組合。在一些具體例(其中在一或多個退火程序期間，將該摻雜硼之介面層曝於熱處理中)，該硼可擴散出至周圍層。因此，根據用以完成該等半導體裝置之形成的熱歷史，該介面區可占據比原初所沉積者更寬或更窄的區。
圖1之方法100持續完成118一或多個電晶體之形成。完成118可包括多種方法，諸如利用絕緣體材料之封裝、置換金屬閘極(RGM)處理、接點形成、及/或後端處理。例如，使用例如矽化程序(通常，接點金屬之沉積及隨後之退火)，接點可以被形成該S/D區。實例之源極汲極接點材料包括例如鎢、鈦、銀、金、鋁、及彼之合金。在一些具體例中，該渠道區可被形成至合適之電晶體組態，諸如形成一或多個奈米線/奈米帶於用於具有奈米線/奈米帶組態之電晶體的渠道區中。回想：雖然在圖2A-I和3中之結構被顯示為具有鰭片狀之非平面組態，可以使用圖1之方法100以形成具有平面組態之電晶體。基於諸如最後用途或標的應用或所要之效能準則的因素，可以選擇特別的渠道組態(例如平面的、鰭片狀、或奈米線/奈米帶)。注意：方法100之程序102-118係以特別順序被顯示在圖1中以易於描述。然而，該程序102-118之一或多者可用不同順序來進行或也可以完全不進行。例如， 方框106是非必需程序，其可不被實施，若所得之所要電晶體構造是平面的。在另一實例變化型中，方框108可依照所用之井摻雜技術，在方法100之早期被進行。在另一實例變化型中，閘極處理110之一部份可在方法100之後期(諸如在置換金屬閘極(RGM)程序期間)被進行。鑒於本揭示，方法100之很多變化將是明顯的。
圖4A闡明根據一具體例之實例積體電路，其包括二個具有鰭片狀組態之電晶體結構。圖4B闡明根據一具體例之實例積體電路，其包括二個具有奈米線組態之電晶體結構。圖4C闡明根據一具體例之實例積體電路，其包括二個電晶體結構，一個具有鰭片狀組態且一個具有奈米線組態。在圖4A-C中的結構係類似於圖2H之結構，除了僅顯示二個鰭片狀區以更好地闡明該渠道區以易於討論。如在圖4A之實例結構中可見到的，在該渠道區402中保持原初之鰭片狀組態。然而，圖4A之結構也可藉由在置換閘極程序(例如RGM程序)期間以鰭片狀結構置換該渠道區而達成。在此類鰭片狀組態(其也被稱為三閘極和鰭片-FET組態)中，有三個有效閘極-二面各有一閘極且頂部有一閘極-如在該領域中已知的。如在圖4A之實例結構中也可見到的，該介面區240位於該渠道區402與該S/D區252之間。注意：在此實例具體例中，該介面區240(包括一或多個介面層，如在本文多方面地描述的)也位於該渠道區402與該S/D 254區之間；然而，為容易闡明，該介面區240不被顯示在該渠道區402之另一面 上。
如在圖4B之實例具體例中可見到的，該渠道區被形成至二奈米線或奈米帶404中。奈米線電晶體(有時被稱為閘極環繞或奈米帶電晶體)係類似地被配置成以鰭片為基礎之電晶體，但並非使用鰭片狀渠道區(其中該閘極是在三面上且因此有三個有效閘極)，而是使用一或多種奈米線且該閘極材料通常在所有面上環繞每一奈米線。依照該特別設計，一些奈米線電晶體具有例如四個有效閘極。如在圖4B之實例結構中可見到的，該等電晶體分別具有二個奈米線404，雖然其他具體例可具有任何個數的奈米線。該奈米線404可能已被形成，但在置換閘極程序(例如RMG程序)期間，例如於該假閘極被移除之後，該渠道區被曝露。如在圖4B之實例結構中也可見到的，該介面區240係位於該渠道區404與該S/D區252之間。注意：在此實例具體例中，該介面區240(包括一或多個介面層，如在本文多方面地描述的)也位於該渠道區404與該S/D區254之間；然而，為容易闡明，該介面區240並未顯示在該渠道區404之另一面上。雖然圖4A和4B之結構闡明該電晶體組態(其每一結構是相同的)，且渠道區可變化。例如，圖4C之結構闡明實例積體電路，其包括二個電晶體結構，其中一者具有鰭片狀組態402且另一者具有奈米線組態404。很多變化和組態鑒於本揭示將是明顯的。
圖5A闡明常見之p-MOS電晶體裝置之能帶概略圖 解。圖5B闡明根據本發明之一具體例所形成之p-MOS電晶體裝置之能帶概略圖解。注意：二裝置包括Si渠道區506(例如n型摻雜之Si渠道區)和SiGe S/D區508(例如摻雜硼之SiGe S/D區)。在圖5A中之常見裝置與使用在本文中多方面描述之技術所形成之圖5B的裝置之間的差異是：圖5B之裝置包括一或多個介面層517(在Si渠道區506與SiGe S/D區508之間)而提供很多益處。例如，透過藉由不同裝置所產生之實例價能帶，可見到一個益處。在圖5A中之常見裝置的價能帶502顯示價能帶偏差，其係在該Si渠道區506與該SiGe S/D區508之間的異介面507上，因在該二材料之間的能帶結構差異所造成。此一異介面507在開通態電流期間使電阻增加，因此降低開通態電流的效能，因為需要帶正電荷之電洞(載體)509穿過具有高電阻之熱離子發射阻障體504。由於經改良的價能帶512(其係藉由包括介面層517所形成)，使用在本文中多方面描述之技術所形成之圖5B的p-MOS電晶體裝置與圖5A之裝置相比，具有較低之熱離子發射阻障體514。此經改良之價能帶512在開通態電流期間導致電阻降低，藉此增加開通態之電流效能。該電阻降低及效能改良係藉由沉積一或多個如本文中所方面描述之介面層517而達成。
在一實例具體例(其中該介面層517包含Si：B單層)中，將會有足夠之p-型摻雜劑橫過該異介面以允許載體509隧穿過該介面，而不是依賴穿過圖5A之常見裝置 的大異介面507之熱離子發射阻障體504。在一實例具體例(其中該介面層517包含SiGe：B之漸變層或SiGe：B之階變層)中，該載體509可自由地或以改良方式由該SiGe：B S/D區508流至該Si渠道區506。此種效能獲得已用具有0.6V之閘極偏壓和在該汲極上之0.05V之偏壓的線性規畫方式測量，以依照所用之介面層產生10-50%之驅動電流增加。利用具有2-3nm寬度之介面層，達成此種效能獲得；然而，較高之增加可以依照所用之特別組態而達成。例如，常見之包括磊晶生長之SiGe：B S/D區的p-MOS電晶體可利用在SiGe：B沉積後硼由熱循環擴散出，以提供充份摻雜過該異介面507阻障體。然而，此一程序使大的擴散尾進入該Si渠道區而引起負面的短渠道效應，因此劣化整體裝置效能。使用在本文中多方面地被描述之技術，以一或多個介面層所形成之p-MOS電晶體裝置可被形成，同時在該等SiGe：B S/D區沉積後使熱循環保持最少，因此改良短渠道效應(或至少不傷害該短渠道效應)，同時仍獲得經改良之開通態電流。因此，在本文中描述之技術可以藉由改良開通電流流動瓶頸在極小閘極長度下能有持續的電晶體效能。鑒於本揭示，很多組態和變化將是明顯的。
實例系統
圖6闡明根據本發明之多種具體例之一種計算系統1000，其係以使用本文所揭示之技術所形成之積體電路結 構或裝置來實施。如可見到的，該計算系統1000容納母板(motherboard)1002。該母板1002可包括很多組件，包括但不限於處理器1004及至少一個通信晶片1006，其分別可物理及電偶合至該母板1002，或否則整合於其中。如將了解的，該母板1002可以是例如任何印刷電路板，不管是主板、安裝在主板上之子板(daughterboard)、或系統1000之唯一板等。
依照彼之應用，計算系統1000可包括一或多個可以或可以不物理地且電性地偶合至該母板1002的其他組件。這些其他組件可包括但不限於依電性記憶體(例如DRAM)、不變性記憶體(例如ROM)、圖形處理器、數位訊號處理器、密碼(crypto)處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池組、聲頻編碼解碼器、視頻編碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、迴轉儀、揚聲器、相機、及大量儲存裝置(諸如硬碟驅動器、光碟(CD)、數位光碟(DVD)等等)。在計算系統1000中所包括之組件的任一者可包括一或多個使用根據一實例具體例所揭示之技術所形成之一或多個積體電路結構或電晶體裝置。在一些具體例中，多種功能可被整合於一或多個晶片中(例如注意：該通信晶片1006可以是該處理器1004之部份，否則被整合於該處理器1004中)。
該通信晶片1006使能有供數據往返傳送於該計算系統1000之無線通信。可以使用"無線"一詞及其衍生詞以 描述電路、裝置、系統、方法、技術、通信頻道等，這些可透過經調控的電磁輻射的使用，經由非固體媒介傳遞數據。該詞並非暗示相關裝置不含有任何線，雖然在一些具體例中彼等可能不含有。該通信晶片1006可實現很多無線標準或計畫之任一者，其包括但不限於Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、長期發展(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、彼之衍生物、以及任何其他定名為3G、4G、5G及以上之無線計畫。該計算系統1000可包括多個通信晶片1006。例如，第一通信晶片1006可專用於較短範圍之無線通信諸如Wi-Fi和藍芽且第二通信晶片1006可專用於較長範圍之無線通信諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他者。
該計算系統1000之處理器1004包括封裝在該處理器1004內之積體電路晶粒。在一些具體例中，該處理器之積體電路晶粒包括利用一或多個積體電路結構或裝置(其利用所揭示之技術所形成的)所實施之機上電路組(onboard ciriuitry)，如本文中多方面地描述。"處理器"一詞可以指稱任何裝置或裝置之一部份，彼等處理例如來自暫存器及/或記憶體之電子數據以將該電子數據轉變成其他可貯存在暫存器及/或記憶體之電子數據。
通信晶片1006也可包括封裝在該通信晶片1006之積體電路晶粒。根據一些此等實例具體例，該通信晶片之積 體電路晶粒包括一或多個使用所揭示之技術(在本文中多方面地描述的)所形成的積體電路結構或裝置。如鑒於本揭示將了解的，注意：多重標準之無線能力可被直接整合於該處理器1004中(例如其中任何晶片1006之功能被整合於處理器1004中，而非具有不同的通信晶片)。另外注意：處理器1004可以是具有此種無線能力的晶片組。總之，可以使用任何數目之處理器1004及/或通信晶片1006。同樣地，任一晶片或晶片組可具有在其中所整合之多重功能。
在多種實施中，該計算系統1000可以是膝上型電腦、小筆記型電腦、筆記型電腦、智慧型手機、數位板、個人數位助理(PDA)、超行動PC、行動電話、桌上型電腦、伺服器、列印機、掃描器、監測器、機上盒、休閒控制單元、數位相機、可攜式音樂播放器、數位錄影機、或任何其他電子裝置，其處理數據或利用一或多個使用所揭示之技術所形成之積體電路結構或電晶體裝置，如本文中多方面地描述的。
另外的實例具體例
下列實例關於另外的具體例，由這些具體例將顯明很多排列和組態。
實例1是一種電晶體，其包含：由矽(Si)基材之部份所形成之矽(Si)渠道區；摻雜硼之矽鍺(SiGe：B)的源極/汲極(S/D)區，其中在該S/D區中Ge含量百分比 是第一值且大於0；及在該渠道區與該等SiGe：B S/D區之間的一或多個介面層，其中該一或多個介面層包含SiGe：B且在該一或多個介面層中Ge含量百分比是比該第一值小之第二值且大於或等於0。
實例2包括實例1之主題，其中該一或多介面層包含摻雜硼之矽(Si：B)單層。
實例3包括實例2之主題，其中Si：B單層在該渠道區與對應之S/D區之間的厚度是2至5nm。
實例4包括實例1之主題，其中該一或多個介面層包含SiGe：B漸變層以致在該漸變層中Ge含量百分比由最接近該渠道區之部份朝最接近該對應S/D區的部份增加。
實例5包括實例4之主題，其中在該漸變層中Ge含量百分比由0%Ge增至Ge含量的第一值。
實例6包括實例4之主題，其中在該漸變層中Ge含量百分比由0%Ge增至比Ge含量的第一值少至少10%的百分比。
實例7包括實例4之主題，其中在該漸變層中Ge含量百分比由大於0之百分比增至Ge含量的第一值。
實例8包括實例4之主題，其中在該漸變層中Ge含量百分比由大於0之百分比增至比Ge含量的第一值少至少10%的百分比。
實例9包括實例4-8之任一主題，其中該漸變層在該渠道區與該對應S/D區之間的厚度是2至10nm。
實例10包括實例1之主題，其中該一或多個介面層 包含多個SiGe：B層，該Ge含量百分比由最接近該渠道區的層朝最接近該對應S/D區之層增加。
實例11包括實例10之主題，其中在最接近該渠道區之層中的Ge含量百分比是在0與15%之間。
實例12包括實例10-11之任一主題，其中在最接近該S/D區之層中的Ge含量百分比係比最接近該渠道區之層中的Ge含量百分比大至少10%。
實例13包括實例1-12之任一主題，其中該一或多個介面層具有基本保形之生長圖形，以致在該渠道區與該對應S/D區之間一或多個介面層的一部份的厚度基本上與在該基材與該對應之S/D區之間該一或多個介面層的一部份的厚度相同。
實例14包括實例13之主題，其中基本上相同係由厚度在1nm內者組成。
實例15包括實例1-14之任一主題，其中該電晶體之幾何形狀包括場效應電晶體(FET)、金屬氧化物半導體FET(MOSFET)、隧式FET(TFET)、平面組態、鰭片狀組態、鰭片FET組態、三閘極組態、奈米線組態、及奈米條組態之至少一者。
實例16是一種互補型金屬氧化物半導體(CMOS)裝置，其包含實例1-15項之任一主題。
實例17是一種計算系統，其包含實例1-16之任一主題。
實例18是一種p型金屬氧化物半導體(p-MOS)電 晶體，其包含：由Si基材之一部份所形成之n型摻雜之矽(Si)渠道區；摻雜硼之矽鍺(SiGe：B)源極/汲極(S/D)區，其中在該S/D區中Ge含量百分比是第一值且大於0；及在該Si渠道區與諸SiGe：B S/D區之間的一或多個介面層，其中該一或多個介面層包含SiGe：B且在該一或多個介面層中Ge含量百分比是比該第一值少之第二值且大於或等於0。
實例19包括實例18之主題，其中該一或多個介面層包含摻雜硼之矽(Si：B)單層。
實例20包括實例19之主題，其中Si：B單層在該渠道區與該對應之S/D區之間的厚度是2至5nm。
實例21包括實例18之主題，其中該一或多個介面層包含SiGe：B漸變層以致在該漸變層中Ge含量百分比由最接近該渠道區之部份朝最接近該對應S/D區的部分增加。
實例22包括實例21之主題，在該漸變層中Ge含量百分比由0%Ge增至Ge含量的第一值。
實例23包括實例21之主題，其中在該漸變層中Ge含量百分比由0%Ge增至比Ge含量的第一值少至少10%的百分比。
實例24包括實例21之任一主題，其中該漸變層中Ge含量百分比由大於0之百分比增至Ge含量之第一值。
實例25包括實例21之主題，其中該漸變層中Ge含量百分比係由大於0之百分比增至比Ge含量之第一值少至少10%的百分比。
實例26包括實例21-25之任一主題，其中在該渠道區與該對應S/D區之間的厚度是2至10nm。
實例27包括實例18之主題，其中該一或多個介面層包含多個SiGe：B層，該Ge含量百分比由最接近該渠道區的層朝最接近該對應S/D區之層增加。
實例28包括實例27之主題，其中在最接近該渠道區之層中的Ge含量百分比是在0與15%之間。
實例29包括實例27-28之任一主題，其中在最接近該對應S/D區之層中的Ge含量百分比係比最接近該渠道區之層中的Ge含量百分比大至少10%。
實例30包括實例18-29之任一主題，其中該一或多個介面層具有基本保形之生長圖形，以致在該渠道區與該對應S/D區之間一或多個介面層的一部份的厚度基本上與在該基材與該對應之S/D區之間該一或多個介面層的一部份的厚度相同。
實例31包括實例30之主題，其中基本上相同係由厚度在1nm內者組成。
實例32包括實例18-31之任一主題，其中該電晶體之幾何形狀包括平面組態、鰭片狀組態、鰭片FET組態、三閘極組態、奈米線組態、及奈米條組態之至少一者。
實例33是一種互補型金屬氧化物半導體(CMOS)裝置，其包含實例18-32項之任一主題。
實例34是一種計算系統，其包含實例18-33之任一 主題。
實例35是一種形成電晶體的方法，該方法包含：在矽(Si)基材中形成鰭片；在該矽鰭片上形成閘極疊合物以限定渠道區及源極/汲極(S/D)區，該渠道位於該閘極疊合物下方且該等S/D區位於該渠道區之任一面上；蝕刻該等S/D區以形成諸S/D凹槽；將一或多個介面層沉積在該等S/D凹槽中；及將摻雜硼之矽鍺(SiGe：B)沉積在該一或多個介面層上以形成置換S/D區，其中在該等置換S/D區中Ge含量百分比是第一值且大於0；其中該一或多個介面層包含SiGe：B且在該一或多個介面層中Ge含量百分比是比該第一值少之第二值且大於或等於0。
實例36包括實例35之主題，其中該一或多個介面層包含摻雜硼之矽(Si：B)單層。
實例37包括實例35之主題，其中該一或多個介面層包含SiGe：B漸變層以致在該漸變層中Ge含量百分比由最接近該渠道區之部份朝最接近該對應S/D區之部份增加。
實例38包括實例35之主題，其中該一或多個介面層包含多個SiGe：B層，Ge含量百分比由最接近該渠道區之層朝最接近該對應S/D區之層增加。
實例39包括實例35-38之任一主題，其另外包含以n型摻雜劑摻雜該Si渠道區。
實例40包括實例35-39之任一主題，其中沉積該SiGe：B置換S/D區包括化學蒸氣沉積(CVD)程序。
實例41包括實例35-40之任一主題，其中該一或多 個介面層具有基本保形之生長圖形，以致在該渠道區與該對應S/D區之間一或多個介面層的一部份的厚度基本上與在該基材與該對應之S/D區之間該一或多個介面層的一部份的厚度相同。
實例42包括實例41之主題，其中基本上相同係由厚度在1nm內者組成。
注意：雖然特定厚度係在以上實例中被提供，根據在此等層之沉積後的熱歷史，該介面層可占據更窄或更寬之區。如基於本發明可被了解的，如本文中多方面地描述之一或多個介面層在電晶體之Si渠道區(例如不管是未摻雜的或n型摻雜的)與置換S/D區之間的存在可提供很多益處，包括例如改良短渠道效應。另外注意：可以使用本文中多方面地描述之技術以根據最後用途或標的應用，形成具有任何幾何形狀或組態之電晶體。例如，一些此等幾何形狀包括場效應電晶體(FET)、金屬氧化物半導體FET(MOSFET)、隧式FET(TFET)、平面組態、鰭片狀組態(例如三閘極、鰭片FET)、及奈米線(或奈米條或閘極環繞)組態，此係僅列舉一些實例幾何形狀。另外，可以使用該等技術以形成CMOS電晶體/裝置/電路，其中使用該等技術以形成該p-MOS電晶體在該CMOS內。
已呈現先前之實例具體例的描述以供闡明及描述之目的。該描述無意鉅細靡遺或限制本發明於所揭示之精確型式。鑒於本發明，很多改良型或變化型是可能的。有意使 本揭示之範圍不受限於此詳細描述，而是受限於所附之申請專利範圍。要求本申請案之優先權之後來提出的申請案可以不同方式要求所揭示之主題，且通常可包括如本文中多方面地揭示或闡明之一或多個限制的任何組合。
100‧‧‧方法

Claims (16)

  1. 一種電晶體，其包含：由矽(Si)基材之一部份所形成之渠道區；摻雜硼之矽鍺(SiGe：B)源極/汲極(S/D)區，其中在該S/D區中Ge含量百分比是第一值且大於0；及在該渠道區與SiGe：B S/D區之間的一或多個介面層，其中該一或多個介面層包含SiGe：B，且在該一或多個介面層中Ge含量百分比是比該第一值少之第二值且大於或等於0，其中該一或多個介面層包含摻雜硼之矽(Si：B)單層，其中該Si：B單層在該渠道區與對應的S/D區之間的厚度是2至5nm，及其中該一或多個介面層包含SiGe：B漸變層以致在該漸變層中Ge含量百分比由最接近該渠道區之部份朝最接近對應的S/D區的部份增加，其中在該漸變層中Ge含量百分比由0% Ge增至Ge含量的第一值，或在該漸變層中Ge含量百分比由0% Ge增至比Ge含量的第一值少至少10%的百分比。
  2. 如請求項1之電晶體，其中在該漸變層中Ge含量百分比由大於0之百分比增至Ge含量的第一值。
  3. 如請求項1之電晶體，其中在該漸變層中Ge含量百分比由大於0之百分比增至比Ge含量的第一值少至少10%的百分比。
  4. 如請求項1之電晶體，其中該漸變層在該渠道區與對應的S/D區之間具有2至10nm之厚度。
  5. 如請求項1之電晶體，其中該一或多個介面層包含多個SiGe：B層，該Ge含量百分比由最接近該渠道區的層朝最接近對應的S/D區之層增加。
  6. 如請求項1之電晶體，其中該一或多個介面層具有基本保形之生長圖形，以致在該渠道區與對應的S/D區之間的一或多個介面層的一部份的厚度與在該基材與對應的S/D區之間的該一或多個介面層的一部份的厚度基本上相同。
  7. 如請求項6之電晶體，其中基本上相同係由厚度在1nm內者組成。
  8. 如請求項1之電晶體，其中該電晶體之幾何形狀包括場效應電晶體(FET)、金屬氧化物半導體FET(MOSFET)、隧式FET(TFET)、平面組態、鰭片狀組態、鰭片FET組態、三閘極組態、奈米線組態、及奈米條組態中之至少一者。
  9. 一種互補型金屬氧化物半導體(CMOS)裝置，其包含請求項1至8中任一項之電晶體。
  10. 一種計算系統，其包含請求項1至8中任一項之電晶體。
  11. 一種p型金屬氧化物半導體(p-MOS)電晶體，其包含：由矽基材之一部份所形成之n型經摻雜之矽(Si)渠 道區；摻雜硼之矽鍺(SiGe：B)源極/汲極(S/D)區，其中在該S/D區中Ge含量百分比是第一值且大於0；及在該Si渠道區與SiGe：B S/D區之間的一或多個介面層，其中該一或多個介面層包含SiGe：B，且在該一或多個介面層中Ge含量百分比是比該第一值少之第二值且大於或等於0，其中該一或多個介面層包含摻雜硼之矽(Si：B)單層，其中該Si：B單層在該渠道區與對應的S/D區之間的厚度是2至5nm，及其中該一或多個介面層包含SiGe：B漸變層以致在該漸變層中Ge含量百分比由最接近該渠道區之部份朝最接近對應的S/D區的部份增加，其中在該漸變層中Ge含量百分比由0% Ge增至Ge含量的第一值，或在該漸變層中Ge含量百分比由0% Ge增至比Ge含量的第一值少至少10%的百分比。
  12. 如請求項11之電晶體，其中該一或多個介面層包含多個SiGe：B層，Ge含量百分比由最接近該渠道區之層朝最接近對應的S/D區之層增加。
  13. 如請求項11至12中任一項之電晶體，其中該電晶體之幾何形狀包括平面組態、鰭片狀組態、鰭片FET組態、三閘極組態、奈米線組態、及奈米條組態中之至少一者。
  14. 一種形成電晶體的方法，該方法包含：在矽(Si)基材中形成鰭片；在該鰭片上形成閘極疊合物以限定渠道區及源極/汲極(S/D)區，該渠道區位於該閘極疊合物下方且該等S/D區位於該渠道區之任一面上；蝕刻該等S/D區以形成S/D凹槽；將一或多個介面層沉積在該等S/D凹槽中；及將摻雜硼之矽鍺(SiGe：B)沉積在該一或多個介面層上以形成置換S/D區，其中在該等置換S/D區中Ge含量百分比是第一值且大於0；其中該一或多個介面層包含SiGe：B，且在該一或多個介面層中Ge含量百分比是比該第一值少之第二值且大於或等於0，其中該一或多個介面層包含摻雜硼之矽(Si：B)單層，其中該Si：B單層在該渠道區與對應的S/D區之間的厚度是2至5nm，及其中該一或多個介面層包含SiGe：B漸變層以致在該漸變層中Ge含量百分比由最接近該渠道區之部份朝最接近對應的S/D區的部份增加，其中在該漸變層中Ge含量百分比由0% Ge增至Ge含量的第一值，或在該漸變層中Ge含量百分比由0% Ge增至比Ge含量的第一值少至少10%的百分比。
  15. 如請求項14之方法，其中該一或多個介面層包含 多個SiGe：B層，Ge含量百分比由最接近該渠道區之層朝最接近對應的S/D區之層增加。
  16. 如請求項14至15中任一項之方法，其另外包含以n型摻雜劑摻雜該Si渠道區。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016200402A1 (en) * 2015-06-12 2016-12-15 Intel Corporation Techniques for forming transistors on the same die with varied channel materials
TWI694604B (zh) * 2015-07-23 2020-05-21 光澄科技股份有限公司 光偵測器
EP3332426B1 (en) 2015-08-04 2019-10-09 Artilux Inc. Germanium-silicon light sensing apparatus
US10861888B2 (en) 2015-08-04 2020-12-08 Artilux, Inc. Silicon germanium imager with photodiode in trench
US10707260B2 (en) 2015-08-04 2020-07-07 Artilux, Inc. Circuit for operating a multi-gate VIS/IR photodiode
US10761599B2 (en) 2015-08-04 2020-09-01 Artilux, Inc. Eye gesture tracking
US10739443B2 (en) 2015-11-06 2020-08-11 Artilux, Inc. High-speed light sensing apparatus II
US10741598B2 (en) 2015-11-06 2020-08-11 Atrilux, Inc. High-speed light sensing apparatus II
US10886309B2 (en) 2015-11-06 2021-01-05 Artilux, Inc. High-speed light sensing apparatus II
US10418407B2 (en) 2015-11-06 2019-09-17 Artilux, Inc. High-speed light sensing apparatus III
US10254389B2 (en) 2015-11-06 2019-04-09 Artilux Corporation High-speed light sensing apparatus
US10930738B2 (en) * 2017-06-29 2021-02-23 Intel Corporation Sub-fin leakage control in semicondcutor devices
US11107811B2 (en) * 2017-07-01 2021-08-31 Intel Corporation Metallization structures under a semiconductor device layer
US10332985B2 (en) * 2017-08-31 2019-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11105928B2 (en) 2018-02-23 2021-08-31 Artilux, Inc. Light-sensing apparatus and light-sensing method thereof
JP6975341B2 (ja) 2018-02-23 2021-12-01 アーティラックス・インコーポレイテッド 光検出装置およびその光検出方法
CN114335030A (zh) 2018-04-08 2022-04-12 奥特逻科公司 光探测装置
US10854770B2 (en) 2018-05-07 2020-12-01 Artilux, Inc. Avalanche photo-transistor
US10969877B2 (en) 2018-05-08 2021-04-06 Artilux, Inc. Display apparatus
US10497796B1 (en) 2018-05-31 2019-12-03 International Business Machines Corporation Vertical transistor with reduced gate length variation
KR20200018863A (ko) * 2018-08-13 2020-02-21 삼성전자주식회사 반도체 장치
US11448830B2 (en) 2018-12-12 2022-09-20 Artilux, Inc. Photo-detecting apparatus with multi-reset mechanism
KR20200136688A (ko) 2019-05-28 2020-12-08 삼성전자주식회사 반도체 소자 및 이의 제조 방법
TW202104927A (zh) 2019-06-19 2021-02-01 美商光程研創股份有限公司 光偵測裝置以及電流再利用方法
US11335552B2 (en) * 2020-04-17 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with oxide semiconductor channel
KR20220020715A (ko) 2020-08-12 2022-02-21 삼성전자주식회사 집적회로 소자

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130240989A1 (en) * 2010-12-21 2013-09-19 Glenn A. Glass Selective germanium p-contact metalization through trench

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7943469B2 (en) * 2006-11-28 2011-05-17 Intel Corporation Multi-component strain-inducing semiconductor regions
US8598003B2 (en) * 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
KR101205136B1 (ko) * 2010-12-17 2012-11-26 에스케이하이닉스 주식회사 반도체 소자 및 그 형성 방법
US8659089B2 (en) * 2011-10-06 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Nitrogen passivation of source and drain recesses
US9142642B2 (en) * 2012-02-10 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for doped SiGe source/drain stressor deposition
US9178045B2 (en) * 2013-09-27 2015-11-03 Samsung Electronics Co., Ltd. Integrated circuit devices including FinFETS and methods of forming the same
US9246003B2 (en) * 2013-11-19 2016-01-26 Globalfoundries Inc. FINFET structures with fins recessed beneath the gate
US9159811B2 (en) * 2013-12-18 2015-10-13 International Business Machines Corporation Growing buffer layers in bulk finFET structures
JP2015206912A (ja) * 2014-04-21 2015-11-19 オリンパス株式会社 光ファイバの接続アダプタおよび内視鏡装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130240989A1 (en) * 2010-12-21 2013-09-19 Glenn A. Glass Selective germanium p-contact metalization through trench
US20130264639A1 (en) * 2010-12-21 2013-10-10 Glenn A. Glass Column iv transistors for pmos integration

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