TWI705571B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI705571B
TWI705571B TW107130120A TW107130120A TWI705571B TW I705571 B TWI705571 B TW I705571B TW 107130120 A TW107130120 A TW 107130120A TW 107130120 A TW107130120 A TW 107130120A TW I705571 B TWI705571 B TW I705571B
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silicon
layer
semiconductor device
band gap
wide band
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TW201914036A (zh
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宮野清孝
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日商紐富來科技股份有限公司
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Abstract

本發明是有關於一種半導體裝置及其製造方法。本發明的半導體裝置包括：矽基板，具有第1面方位的第1面；氧化矽層，設置於矽基板的第1區域上；第1矽層，設置於氧化矽層上，且具有與第1面方位不同的第2面方位的第2面；以及寬能帶隙化合物半導體層，具有六方晶的結晶結構。

Description

半導體裝置及其製造方法
本發明是有關於一種半導體裝置及其製造方法。
使用寬能帶隙（wide band gap）化合物半導體的功率器件（power device）的應用範圍近年來迅速擴大。大多情況下，該些功率器件是藉由與使用矽（Si）的器件加以組合而使用。
至今為止，使用寬能帶隙化合物半導體並與各晶片組合，作為一個模組而進行封裝。
然而，此種形成方法中需要個別地形成各晶片，因此繁雜，另外，模組的小型化存在極限。因此，謀求一種能夠將化合物半導體器件與矽器件混載於一個晶片上的技術。
本發明提供一種能夠將寬能帶隙化合物半導體器件與矽器件混載的半導體裝置及其製造方法。
本發明的一態樣的半導體裝置包括：矽基板，具有第1面方位的第1面；氧化矽層，設置於矽基板的第1區域上；第1矽層，設置於氧化矽層上，且具有與第1面方位不同的第2面方位的第2面；以及寬能帶隙化合物半導體層，具有六方晶的結晶結構。
以下，一面參照圖式，一面對本發明的實施形態進行說明。
本說明書中，所謂「氮化物半導體」，是包括GaN（氮化鎵）、AlN（氮化鋁）、InN（氮化銦）以及該些的中間組成的半導體的總稱。
本說明書中，為了表示零件等的位置關係，將圖式的上方向記述為「上」，將圖式的下方向記述為「下」。本說明書中，「上」、「下」的概念未必為表示與重力方向的關係的用語。
（第1實施形態） 本實施形態的半導體裝置包括：矽基板，具有第1面方位的第1面；氧化矽層，設置於矽基板的第1區域上；第1矽層，設置於氧化矽層上，且具有與第1面方位不同的第2面方位的第2面；以及寬能帶隙化合物半導體層，具有六方晶的結晶結構。
而且，進而包括設置於矽基板的與第1區域不同的第2區域上的第2矽層，且寬能帶隙化合物半導體層設置於第1矽層上，第1面方位為{100}，第2面方位為{111}。
本實施形態的半導體裝置100的製造方法中，於設置於具有面方位為{100}的第1面的矽基板的第1區域上所設置的氧化矽層上並具有面方位為{111}的第2面的第1矽層之上形成具有六方晶的結晶結構的寬能帶隙化合物半導體層，且於矽基板的第2區域上形成第2矽層。
圖1是本實施形態的半導體裝置100的示意剖面圖。
矽基板2上的第1面2a的面方位為{100}面，但亦可自{100}面以10度以下的偏離角發生傾斜。
而且，氧化矽層4設置於矽基板2的第1面2a的第1區域2b上。氧化矽層4是所謂的埋入式氧化物（Buried Oxide，BOX）層。
第1矽層6設置於氧化矽層4上。第1矽層6是所謂的絕緣體上矽（Silicon On Insulator，SOI）層。第1矽層6上的第2面6a的面方位與第1面2a的面方位不同而為{111}面，但亦可自{111}面以10度以下的偏離角發生傾斜。所述矽基板2、氧化矽層4、第1矽層6亦可由SOI基板構成。
而且，寬能帶隙化合物半導體層10設置於第1矽層6的第2面6a上。寬能帶隙化合物半導體層10的寬能帶隙化合物例如使用氮化物半導體。
寬能帶隙化合物半導體層10具有：緩衝層12；第1氮化物半導體層14，設置於緩衝層12上；第2氮化物半導體層16，設置於第1氮化物半導體層14上，且能帶隙大於第1氮化物半導體層14。氮化物半導體的結晶結構為六方晶。
第1氮化物半導體層14例如為未摻雜的AlX Ga1-X N（0≦X＜1）。更具體而言，例如為未摻雜的GaN。第2氮化物半導體層16例如為未摻雜的AlY Ga1-Y N（0＜Y≦1、X＜Y）。更具體而言，例如為未摻雜的Al0.2 Ga0.8 N。
緩衝層12具備使第1矽層6與第1氮化物半導體層14之間的晶格失配加以緩和的功能。緩衝層12例如具有氮化鋁鎵（AlW Ga1-W N（0＜W＜1））的多層結構。
於第2氮化物半導體層16上設置有第1源極電極18、第1閘極電極20及第1汲極電極22。第1閘極電極20設置於第1源極電極18與第1汲極電極22之間。
第1源極電極18、第1閘極電極20及第1汲極電極22例如為金屬電極。較佳為將第1源極電極18及第1汲極電極22與第2氮化物半導體層16歐姆接合。
第1氮化物半導體層14、第2氮化物半導體層16、第1源極電極18、第1閘極電極20、及第1汲極電極22構成常開（normally-on）的高耐壓的高電子遷移率電晶體（High Electron Mobility Transistor，HEMT）30。
再者，於第1矽層6的電阻值低的情況下，若使HEMT 30進行高頻動作，則有時介電性·感應性地與矽基板2進行耦合並產生損失。為了抑制該狀況，理想的是第1矽層6未摻雜並設為高電阻。
p型的第2矽層40是與矽基板2接觸地設置於矽基板2的與第1區域2b不同的第2區域2c上。第2矽層40例如藉由磊晶成長（epitaxial growth）法而形成。作為p型雜質，例如較佳地使用硼（B）。第2矽層40上的第3面40a的面方位例如為{100}面，但亦可以10度以下的偏離角發生傾斜。
而且，於第2矽層40上設置有n型的源極區域44及n型的汲極區域52。作為n型雜質，例如較佳地使用砷（As）、磷（P）。源極區域44及汲極區域52之間的第2矽層40成為通道區域42。
於源極區域44上設置有第2源極電極46。於汲極區域52上設置有第2汲極電極50。於通道區域42上的、第2源極電極46與第2汲極電極50之間設置有閘極絕緣膜54。於閘極絕緣膜54上設置有第2閘極電極48。
第2源極電極46、第2汲極電極50例如為金屬電極。第2閘極電極48例如為多晶矽（polysilicon）電極。閘極絕緣膜54例如是由氧化矽所形成。
源極區域44、通道區域42、汲極區域52、閘極絕緣膜54、第2源極電極46、第2汲極電極50、及第2閘極電極48構成n型的矽-金屬氧化物半導體場效電晶體（silicon-metal oxide semiconductor field effect transistor，Si-MOSFET）60。Si-MOSFET 60例如為低耐壓的Si-MOSFET。
於矽基板2上的、氧化矽層4、第1矽層6及寬能帶隙化合物半導體層10與第2矽層40之間設置有元件分離層70。元件分離層70例如是由氧化矽所形成，並使HEMT 30與Si-MOSFET 60電性絕緣。
圖2是本實施形態的電路500的示意圖。電路500為將HEMT 30與Si-MOSFET 60共源共柵（cascode）連接的電路。具體而言，將HEMT 30的閘極電極與Si-MOSFET 60的源極電極電性連接，另外，將HEMT 30的源極電極與Si-MOSFET 60的汲極電極電性連接
藉由將HEMT 30與Si-MOSFET 60共源共柵連接，可將常開的HEMT 30以常閉的形式使用。
再者，Si-MOSFET亦可為構成HEMT的閘極驅動電路的MOSFET。
繼而，記載本實施形態的半導體裝置100的製造方法。
圖3A～圖3C是本實施形態的半導體裝置的製造方法的示意剖面圖。
首先，準備SOI基板，所述SOI基板包括設置於具有{100}面的第1面2a的矽基板2上的氧化矽層4之上並具有{111}面的第2面6a的第1矽層6。各矽基板的面方位亦可以10度以下的偏離角發生傾斜。
繼而，於第1矽層6上的局部形成遮罩材M1 。繼而，於未形成有遮罩材M1 的第1矽層6上藉由磊晶成長而形成寬能帶隙化合物半導體層10，所述寬能帶隙化合物半導體層10包括：緩衝層12；緩衝層12上的第1氮化物半導體層14；以及第1氮化物半導體層14上的第2氮化物半導體層16（圖3A）。
繼而，於第2氮化物半導體層16上形成遮罩材M2 ，並將形成有遮罩材M1 的部分的氧化矽層4的一部分、第1矽層6的一部分及遮罩材M1 去除（圖3B）。
繼而，於矽基板2的第1面2a上藉由磊晶成長而形成與矽基板2的第1面2a接觸的第2矽層40。
繼而，於氧化矽層4、第1矽層6及寬能帶隙化合物半導體層10與第2矽層40之間形成溝槽（trench），並於所形成的溝槽內形成元件分離層70。
繼而，於第2矽層40上形成源極區域44、汲極區域52、通道區域42、第2源極電極46、第2汲極電極50、閘極絕緣膜54、及第2閘極電極48。繼而，於第2氮化物半導體層16上形成第1源極電極18、第1閘極電極20、第1汲極電極22，從而獲得本實施形態的半導體裝置100（圖3C）。
繼而，記載本實施形態的半導體裝置100的作用效果。
使用寬能帶隙化合物半導體的器件通常與Si-MOSFET等其他器件組合而進行動作。
氮化物半導體的結晶結構為六方晶。因此，通常氮化物半導體形成於容易進行磊晶成長的矽的{111}面上。
另一方面，關於Si-MOSFET，由於P通道金屬氧化物半導體/N通道金屬氧化物半導體(p-channel metal oxide semiconductor/n-channel metal oxide semiconductor，PMOS/NMOS)的遷移率的平衡良好、或者所獲得的閘極絕緣膜的可靠性高，因此較佳為形成於矽的{100}面上。
因此，將使用寬能帶隙化合物半導體的器件與使用矽的器件製作於不同的基板上，並於模組化的階段製成一體的封裝。
本實施形態的半導體裝置100中，於矽基板2的{100}面2a上設置Si-MOSFET 60。而且，於矽基板2上的氧化矽層4上所設置的第1矽層6的{111}面6a上設置HEMT 30。藉此，可將使用寬能帶隙化合物半導體的器件與使用矽的器件混載於一個晶片上。
另外，半導體裝置100所形成的電路500為將HEMT 30與Si-MOSFET 60共源共柵連接的電路。使用氮化物半導體的HEMT於大多情況下為常開，因此，於閘極偏壓為零時亦通電。藉由本實施形態的電路500，可將HEMT以常閉的形式進行動作的電路混載於一個晶片上。
進而，於HEMT 30與矽基板2之間設置有氧化矽層4，因此，可使HEMT 30的耐壓增加。
另外，於矽基板2的電阻值低的情況下，若使HEMT 30進行高頻動作，則有時介電性·感應性地與矽基板2進行耦合並產生損失。然而，如本實施形態的半導體裝置100般，若於HEMT 30與矽基板2之間設置氧化矽層4，則由於氧化矽層4的電阻高，因此能夠抑制由介電性·感應性的耦合引起的損失。
當形成寬能帶隙化合物半導體層10時，要求一種相較於使用矽的器件而更長時間地於高溫下維持基板的製程。例如，於使用氮化物半導體層的製程的情況下，要求一種以1000℃左右維持數小時的製程。然而，使用矽的器件不易耐此種溫度。
本實施形態的半導體裝置100的製造方法中，於形成寬能帶隙化合物半導體層10之後，形成Si-MOSFET 60。藉此，不對使用矽的器件施加高溫便可製作半導體裝置100。
根據本實施形態的半導體裝置，可提供一種能夠將寬能帶隙化合物半導體器件與矽器件混載的半導體裝置。
（第2實施形態） 本實施形態的半導體裝置與第1實施形態的不同點在於：寬能帶隙化合物半導體層設置於矽基板的第2區域上，且第1面方位為{111}面，第2面方位為{100}面。再者，各矽基板的面方位亦可以10度以下的偏離角發生傾斜。此處，關於與第1實施形態重覆的內容，省略敘述。
圖4是本實施形態的半導體裝置200的示意剖面圖。
矽基板2具有{111}面的第1面2a。於矽基板2上設置有氧化矽層4。
於氧化矽層4上設置有第1矽層6。第1矽層6具有{111}面的第2面6a。而且，於第1矽層6上設置有Si-MOSFET 60。
另外，寬能帶隙化合物半導體層10是與矽基板2接觸地設置於矽基板2的第2區域2c上。而且，於寬能帶隙化合物半導體層10上設置有HEMT 30。
圖5A～圖5C是本實施形態的半導體裝置的製造方法的示意剖面圖。
本實施形態的半導體裝置200的製造方法中，將具有{111}面的第1面的矽基板上的氧化矽層之上的具有{100}面的第2面的第1矽層的、氧化矽層的一部分與第1矽層的一部分去除而使矽基板的一部分露出，且於露出的矽基板的一部分上形成具有六方晶的結晶結構的寬能帶隙化合物半導體層。
首先，準備SOI基板，所述SOI基板包括設置於具有{111}面的第1面的矽基板2上的氧化矽層4之上的、具有{100}面的第2面的第1矽層6（圖5A）。
繼而，將氧化矽層4的一部分及第1矽層6的一部分去除（圖5B）。
繼而，於露出的矽基板2的第1面2a上依序形成緩衝層12、第1氮化物半導體層14、及第2氮化物半導體層16。
繼而，於緩衝層12、第1氮化物半導體層14及第2氮化物半導體層16與氧化矽層4及第1矽層6之間形成溝槽，並於所形成的溝槽內形成元件分離層70。
繼而，於第1矽層6上形成源極區域44、汲極區域52、通道區域42、第2源極電極46、第2汲極電極50、閘極絕緣膜54、第2閘極電極48。繼而，於第2氮化物半導體層16上形成第1源極電極18、第1閘極電極20、第1汲極電極22，從而獲得本實施形態的半導體裝置200（圖5C）。
本實施形態的半導體裝置200中，可使第1氮化物半導體層14及第2氮化物半導體層16的膜厚變厚，因此可使HEMT 30的耐壓增加。
另外，與第1實施形態的半導體裝置100相比，不具備第2矽層40，因此，可使磊晶成長的次數減少一次。
根據本實施形態的半導體裝置，可提供一種能夠將寬能帶隙化合物半導體器件與矽器件混載的半導體裝置。
（第3實施形態） 本實施形態的半導體裝置300與第1實施形態及第2實施形態的不同點在於：使用碳化矽（SiC）作為寬能帶隙化合物半導體層10。此處，關於與第1實施形態重覆的內容，省略記載。
圖6是本實施形態的半導體裝置300的示意圖。
半導體裝置300的寬能帶隙化合物半導體層10為p型的4H-SiC或6H-SiC的碳化矽層。4H-SiC及6H-SiC的結晶結構為六方晶。
半導體裝置300具備碳化矽-金屬氧化物半導體場效電晶體（silicon carbide-metal oxide semiconductor field effect transistor，SiC-MOSFET）90。於寬能帶隙化合物半導體層10內設置有n型的源極區域74與n型的汲極區域76。於源極區域74與汲極區域76之間設置有通道區域72。
源極電極78設置於源極區域74上，汲極電極80設置於汲極區域76上。
於通道區域72上設置有閘極絕緣膜84。而且，於閘極絕緣膜84上設置有閘極電極82。
於本實施形態的半導體裝置中，可提供一種能夠將寬能帶隙化合物半導體器件與矽器件混載的半導體裝置。
以上，一面參照具體例一面對本發明的實施形態進行了說明。所述實施形態只不過是作為示例而列舉，並不限定本發明。另外，亦可適當組合各實施形態的構成要素。
實施形態中，關於裝置構成或製造方法等對於本發明的說明而言並非直接需要的部分等，省略了記載，但可適當選擇使用所需要的裝置構成或製造方法等。此外，具備本發明的要素且本領域技術人員可適當進行設計變更的所有檢查方法均包含於本發明的範圍內。本發明的範圍是由申請專利範圍及其均等物的範圍來定義的。
2‧‧‧矽基板2a‧‧‧第1面（{100}面）2b‧‧‧第1區域2c‧‧‧第2區域4‧‧‧氧化矽層6‧‧‧第1矽層6a‧‧‧第2面（{111}面）10‧‧‧寬能帶隙化合物半導體層12‧‧‧緩衝層14‧‧‧第1氮化物半導體層16‧‧‧第2氮化物半導體層18‧‧‧第1源極電極20‧‧‧第1閘極電極22‧‧‧第1汲極電極30‧‧‧HEMT40‧‧‧第2矽層40a‧‧‧第3面42‧‧‧通道區域44‧‧‧源極區域46‧‧‧第2源極電極48‧‧‧第2閘極電極50‧‧‧第2汲極電極52‧‧‧汲極區域54‧‧‧閘極絕緣膜60‧‧‧Si-MOSFET70‧‧‧元件分離層72‧‧‧通道區域74‧‧‧源極區域76‧‧‧汲極區域78‧‧‧源極電極80‧‧‧汲極電極82‧‧‧閘極電極84‧‧‧閘極絕緣膜90‧‧‧SiC-MOSFET100‧‧‧半導體裝置200‧‧‧半導體裝置300‧‧‧半導體裝置500‧‧‧電路M1‧‧‧遮罩材M2‧‧‧遮罩材
圖1是第1實施形態的半導體裝置的示意剖面圖。 圖2是第1實施形態的電路的示意圖。 圖3A～圖3C是第1實施形態的半導體裝置的製造方法的示意剖面圖。 圖4是第2實施形態的半導體裝置的示意剖面圖。 圖5A～圖5C是第2實施形態的半導體裝置的製造方法的示意剖面圖。 圖6是第3實施形態的半導體裝置的示意剖面圖。
2‧‧‧矽基板
2a‧‧‧第1面({100}面)
2b‧‧‧第1區域
2c‧‧‧第2區域
4‧‧‧氧化矽層
6‧‧‧第1矽層
6a‧‧‧第2面({111}面)
10‧‧‧寬能帶隙化合物半導體層
12‧‧‧緩衝層
14‧‧‧第1氮化物半導體層
16‧‧‧第2氮化物半導體層
18‧‧‧第1源極電極
20‧‧‧第1閘極電極
22‧‧‧第1汲極電極
30‧‧‧HEMT
40‧‧‧第2矽層
40a‧‧‧第3面
42‧‧‧通道區域
44‧‧‧源極區域
46‧‧‧第2源極電極
48‧‧‧第2閘極電極
50‧‧‧第2汲極電極
52‧‧‧汲極區域
54‧‧‧閘極絕緣膜
60‧‧‧Si-MOSFET
70‧‧‧元件分離層
100‧‧‧半導體裝置

Claims (8)

  1. 一種半導體裝置，包括：矽基板，具有第1面方位的第1面；氧化矽層，設置於所述矽基板的第1區域上；第1矽層，設置於所述氧化矽層上，且具有與所述第1面方位不同的第2面方位的第2面；寬能帶隙化合物半導體層，具有六方晶的結晶結構；以及第2矽層，設置於所述矽基板的與所述第1區域不同的第2區域上，其中所述寬能帶隙化合物半導體層設置於所述第1矽層上，所述第1面方位為{100}，且所述第2面方位為{111}。
  2. 一種半導體裝置，包括：矽基板，具有第1面方位的第1面；氧化矽層，設置於所述矽基板的第1區域上；第1矽層，設置於所述氧化矽層上，且具有與所述第1面方位不同的第2面方位的第2面；以及寬能帶隙化合物半導體層，具有六方晶的結晶結構，其中所述寬能帶隙化合物半導體層設置於所述矽基板的與所述第1區域不同的第2區域上，所述第1面方位為{111}，且所述第2面方位為{100}。
  3. 如申請專利範圍第1或2項所述的半導體裝置，其中，所述寬能帶隙化合物半導體層具有氮化物半導體層。
  4. 如申請專利範圍第1或2項所述的半導體裝置，其中，所述寬能帶隙化合物半導體層包含碳化矽。
  5. 如申請專利範圍第1項所述的半導體裝置，其進而包括：元件分離層，設置於所述氧化矽層、所述第1矽層及所述寬能帶隙化合物半導體層與所述第2矽層之間。
  6. 如申請專利範圍第2項所述的半導體裝置，其進而包括：元件分離層，設置於所述氧化矽層及所述第1矽層與所述寬能帶隙化合物半導體層之間。
  7. 一種半導體裝置的製造方法，其中，於第1矽層之上形成具有六方晶的結晶結構的寬能帶隙化合物半導體層，所述第1矽層具有設置於氧化矽層上的面方位為{111}的第2面，所述氧化矽層設置於矽基板的第1區域上，所述矽基板具有面方位為{100}的第1面，且於所述矽基板的第2區域上形成第2矽層。
  8. 一種半導體裝置的製造方法，其中，第1矽層具有設置於氧化矽層上的面方位為{100}的第2面，所述氧化矽層設置於具有面方位為{111}的第1面的矽基板上，將所述氧化矽層的一部分與所述第1矽層的一部分去除而使所述矽基板的一部分露出，且於露出的所述矽基板的一部分上形成具有六方晶的結晶結構的寬能帶隙化合物半導體層。
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