TWI695465B - Fan-out semiconductor package - Google Patents

Abstract

A fan-out semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a heat dissipation member attached to the inactive surface of the semiconductor chip, an encapsulant covering at least portions of each of the semiconductor chip and the heat dissipation member, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The heat dissipation member has a thickness greater than that of the semiconductor chip.

Description

Fan-out semiconductor package

The present disclosure relates to a semiconductor package, and more specifically, to a fan-out type semiconductor package in which the electrical connection structure can extend outside the area where the semiconductor chip is provided.

[Cross-reference to related applications]

This application claims the Korean Patent Application No. 10-2017-0148216 filed with the Korean Intellectual Property Office on November 08, 2017 and the Korean Patent Application No. 10 filed with the Korean Intellectual Property Office on May 3, 2018 -The rights and interests of priority No. 2018-0051254, the full disclosure content of the application is incorporated into this case for reference.

The major recent trend in the development of semiconductor wafer-related technologies is to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, as the demand for small-sized semiconductor wafers and the like increases rapidly, it is necessary to implement a semiconductor package having a compact size while including a plurality of pins.

One type of semiconductor packaging technology proposed to meet the above technical requirements is the fan-out semiconductor packaging. Such a fan-out package has a compact size and can allow the electrical connection structure to be re-oriented by going outside the area where the semiconductor chip is provided Implement multiple pins for wiring.

At the same time, fan-out packages have recently been required to have improved heat dissipation characteristics required in advanced application processors (APs).

The aspect of the present disclosure can provide a fan-out type semiconductor package with excellent heat dissipation characteristics and effective warpage control.

According to the aspect of the present disclosure, a fan-out semiconductor package may be provided, in which a heat dissipating member thicker than the semiconductor wafer is attached to the non-active surface of the semiconductor wafer, and then packaged.

100A, 100B, 100C, 100D, 100E, 2100: fan-out semiconductor package

110: core components

110H: through hole

111a: first insulating layer

111b: second insulating layer

111c: third insulating layer

112a: wiring layer/first wiring layer

112b: wiring layer/second wiring layer

112c: wiring layer/third wiring layer

112d: Wiring layer/uppermost wiring layer/fourth wiring layer

113a: connection via layer/first connection via layer

113b: connection via layer/second connection via layer

113c: connection via layer/third connection via layer

115: metal layer

120, 2120, 2220: semiconductor wafer

121, 1101, 2121, 2221: Ontology

122, 2122, 2222: connection pad

122A: Active surface

122P: Non-active surface

123, 150, 2150, 2223, 2250: passivation layer

124: adhesive film

125: heat sink

127: Organic coating

130, 2130: Encapsulated body

132A: Backside wiring layer

132B: Heat dissipation pattern layer

133A: back side through hole

133B: Thermal via

140, 2140, 2240: connecting member

141, 2141, 2241: insulating layer

142: Rerouting layer/lowest rerouting layer

143: Connect through hole

150h, 180h, 2251: opening

160: under bump metal

170: Electrical connection structure

180: Overlay

181: Strengthening layer

190: Surface mount components

210: tape

1000: electronic device

1010, 1110, 2500: motherboard

1020: Chip related components

1030: Network-related components

1040: Other components

1050, 1130: camera module

1060: antenna

1070: display device

1080: battery

1090: Signal cable

1100: Smart phone

1120: Electronic components

1121: Semiconductor packaging

2142: Rerouting layer

2143, 2243: through hole

2160, 2260: metal layer under the bump

2170, 2270: solder balls

2200: Fan-in semiconductor package

2242: Wiring pattern

2243h: through hole

2280: Underfill resin

2290: Molding material

2301, 2302: Intermediate substrate

I-I’: line

P: Surface treatment layer

t1, t2: thickness

By reading the following detailed description in conjunction with the attached drawings, the above and other aspects, features, and advantages of the present disclosure will be more clearly understood.

FIG. 1 is a schematic block diagram showing an example of an electronic device system.

2 is a schematic perspective view showing an example of an electronic device.

3A and 3B are schematic cross-sectional views showing a state of a fan-in semiconductor package before and after packaging.

4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

FIG. 5 is a schematic cross-sectional view illustrating a state where the fan-in type semiconductor package is mounted on the interposer substrate and finally mounted on the main board of the electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a state where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

7 is a schematic cross-sectional view showing a fan-out type semiconductor package.

8 is a schematic cross-sectional view showing a state where a fan-out type semiconductor package is mounted on a main board of an electronic device.

9 is a schematic cross-sectional view showing an example of a fan-out type semiconductor package; FIG. 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package of FIG. 9.

FIG. 11A is a schematic diagram showing a process of forming an organic coating on a heat dissipation member.

11B and 11C are schematic diagrams showing various examples of the process of attaching the heat dissipation member to the inactive surface of the semiconductor wafer.

12A and 12B are schematic diagrams showing an example of a process of manufacturing a fan-out semiconductor package.

13 is a schematic cross-sectional view showing another example of a fan-out type semiconductor package.

14 is a schematic cross-sectional view showing another example of a fan-out type semiconductor package.

15 is a schematic cross-sectional view showing another example of a fan-out type semiconductor package.

16 is a schematic cross-sectional view showing another example of a fan-out type semiconductor package.

FIG. 17 is a graph schematically showing the heat radiation effect of the fan-out type semiconductor package manufactured according to the example.

Hereinafter, exemplary embodiments in the present disclosure will be explained with reference to the attached drawings. In the drawings, the shape and size of components may be exaggerated or reduced for clarity.

However, the present disclosure can be exemplified in many different forms and should not be interpreted as being limited to the specific embodiments described herein. More specifically, the embodiments are provided so that the disclosure will be thorough and complete, and the scope of the disclosure will be fully communicated to those skilled in the art.

In this article, the lower side, the lower part, the lower surface, etc. are used to refer to the direction of the mounting surface of the fan-out semiconductor package relative to the schematic cross section, while the upper side, upper part, upper surface, etc. are used to refer to the The opposite direction. However, these directions are defined for convenience of explanation, and the patent scope of the present application is not particularly limited by the directions defined above.

In the description, the meaning of "connection" between a component and another component includes indirect connection through an adhesive layer and direct connection between the two components. In addition, the concept of "electrical connection" includes physical connection and physical disconnection. It should be understood that when elements such as "first" and "second" are used to refer to elements, the elements are not limited thereby. The use of "first" and "second" may only be used for the purpose of distinguishing the elements from the rest of the elements, and may not limit the order or importance of the elements. In some cases, the first element may be referred to as the second element without departing from the scope of the patent application filed herein. Similarly, the second element may also be referred to as the first element.

The term "exemplary embodiment" as used herein does not refer to the same An exemplary embodiment, but is provided to emphasize specific features or characteristics that are different from those of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by combining with each other in whole or in part. For example, even if an element described in a specific exemplary embodiment is not described in another exemplary embodiment, unless the contrary or contradictory description is provided in another exemplary embodiment, the element It can be understood as a description related to another exemplary embodiment.

The terminology used herein is only for illustrating exemplary embodiments, not for limiting the present disclosure. In this case, unless otherwise explained in the context, the singular form includes the plural form.

Electronic device

FIG. 1 is a schematic block diagram showing an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 may accommodate a motherboard 1010. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. that are physically or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related components 1020 may include: memory chips, such as volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory) memory, ROM)), flash memory, etc.; application processor chips, such as a central processing unit (e.g., central processing unit (CPU)), a graphics processor (e.g., graphics processing unit, GPU)), Digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (applications) -specific integrated circuit, ASIC) etc. However, the wafer-related components 1020 are not limited thereto, but may also include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related components 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), global interoperable microwave access (worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + (high speed packet access +, HSPA+), high speed downlink packet access + (HSDPA+), high speed uplink packet access + (HSUPA+), enhanced data GSM environment (enhanced data GSM environment, EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement, 4G agreement and 5G agreement, and any other wireless agreement and wired agreement specified after the above agreement. However, the network-related component 1030 is not limited to this, but may also include various other wireless standards or protocols or wired standards or protocols. In addition, the network-related components 1030 can be combined with each other together with the chip-related components 1020 described above.

Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics, LTCC), electromagnetic interference (EMI) filter, multilayer ceramic capacitor (MLCC), etc. However, the other components 1040 are not limited to this, but may also include passive components for various other purposes and the like. In addition, other components 1040 may be combined with each other together with the chip-related components 1020 or the network-related components 1030 described above.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected or electrically connected to the motherboard 1010, or may not be physically connected or electrically connected to the motherboard 1010. These other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), and a power amplifier (Figure (Not shown in the figure), compass (not shown in the figure), accelerometer (not shown in the figure), gyroscope (not shown in the figure), speaker (not shown in the figure), mass storage unit (e.g. , Hard disk drive) (not shown), compact disk (CD) drive (not shown), digital versatile disk (digital versatile disk, DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components and the like for various purposes depending on the type of the electronic device 1000.

The electronic device 1000 can be a smart phone, a personal digital assistant (PDA), a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, and a notebook Personal computers, portable netbook PCs, TVs, video game machines, smart watches, automotive components, etc. However, the electronic device 1000 is not limited to this, but can also be Any other electronic device that processes data.

2 is a schematic perspective view showing an example of an electronic device.

Referring to FIG. 2, the semiconductor package may be used for various purposes in the various electronic devices 1000 described above. For example, the motherboard 1110 may be accommodated in the body 1101 of the smartphone 1100, and various electronic components 1120 may be physically connected or electrically connected to the motherboard 1110. In addition, other components (such as the camera module 1130) that may be physically connected or electrically connected to the main board 1110 or may not be physically connected or electrically connected to the main board 1110 may be accommodated in the body 1101. Some of the electronic components 1120 may be chip-related components, such as semiconductor packages 1121, but not limited to this. The electronic device need not be limited to the smartphone 1100, but may be other electronic devices as described above.

Semiconductor packaging

Generally speaking, many precision circuits are integrated in a semiconductor chip. Ran However, the semiconductor wafer itself may not serve as a completed semiconductor product and may be damaged due to external physical or chemical influence. Therefore, the semiconductor wafer may not be used alone, but it can be packaged in an electronic device or the like and used in a packaged state in the electronic device or the like.

Here, since there is a circuit width difference in electrical connection between the semiconductor wafer and the main board of the electronic device, a semiconductor package is required. In detail, the size of the connection pads of the semiconductor chip and the interval between the connection pads of the semiconductor chip are extremely precise, but the size of the component mounting pads of the main board used in the electronic device and the interval between the component mounting pads of the main board are significantly larger The size of the connection pads of the semiconductor wafer and the spacing between the connection pads. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and a packaging technology for buffering the difference in circuit width between the semiconductor chip and the main board is required.

Semiconductor packages manufactured by packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on the structure and purpose of the semiconductor package.

The fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail below with reference to the drawings.

Fan-in semiconductor package

3A and 3B are schematic cross-sectional views showing the state of the fan-in semiconductor package before and after packaging.

4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

3 and 4, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state. The semiconductor wafer 2220 includes a body 2221 including silicon (Si), germanium (Ge), and gallium arsenide (GaAs), etc.; a connection pad 2222, formed on one surface of the body 2221 and containing a conductive material such as aluminum (Al); and a passivation layer 2223, such as an oxide layer, a nitride layer, etc., formed on one surface of the body 2221. Cover and cover at least part of the connection pad 2222. In this case, since the connection pad 2222 can be remarkably small, it may be difficult to mount the integrated circuit (IC) on the intermediate printed circuit board (PCB), the motherboard of the electronic device, or the like.

Therefore, the connection member 2240 may be formed on the semiconductor wafer 2220 depending on the size of the semiconductor wafer 2220 to rewire the connection pad 2222. The connecting member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin, forming a through hole 2243h exposing the connecting pad 2222, and Next, the wiring pattern 2242 and the through hole 2243 are formed. Next, a passivation layer 2250 protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an under bump metal layer 2260 may be formed. That is, the fan-in semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under-bump metal layer 2260 can be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all connection pads (for example, input/output (I/O) terminals) of the semiconductor chip are provided in the semiconductor chip, and may have excellent Electrical characteristics and can be produced at low cost. Therefore, it has been manufactured and installed in the form of a fan-in semiconductor package Many components in a smart phone. In detail, many components installed in a smart phone have been developed to implement fast signal transmission while having a compact size.

However, since all input/output terminals in the fan-in type semiconductor package need to be provided inside the semiconductor chip, the fan-in type semiconductor package has a significant space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input/output terminals or a semiconductor wafer having a compact size. In addition, due to the above disadvantages, the fan-in semiconductor package may not be directly installed and used on the motherboard of the electronic device. The reason is that even in the case where the size of the input/output terminals of the semiconductor chip and the interval between the input/output terminals of the semiconductor chip are increased by the rewiring process, the size of the input/output terminals of the semiconductor chip and the The spacing between the input/output terminals may still be insufficient to directly mount the fan-in semiconductor package on the motherboard of the electronic device.

FIG. 5 is a schematic cross-sectional view illustrating a state where the fan-in type semiconductor package is mounted on the interposer substrate and finally mounted on the main board of the electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a state where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

5 and 6, in the fan-in semiconductor package 2200, the connection pads 2222 (ie, input/output terminals) of the semiconductor chip 2220 can be rewired through the interposer 2301, and the fan-in semiconductor package 2200 can be placed in the fan The embedded semiconductor package 2200 is finally mounted on the motherboard 2500 of the electronic device in a state where it is mounted on the interposer 2301. In this case, the solder balls 2270 etc. can be fixed by underfilling the resin 2280 etc., and the material 2290 etc. can be molded on the outer side of the semiconductor wafer 2220 To cover. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pad 2222 of the semiconductor chip 2220, that is, the input/output terminals may be in a state where the fan-in semiconductor package 2200 is embedded in the interposer substrate 2302 By rewiring through the interposer substrate 2302, the fan-in semiconductor package 2200 can be finally installed on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly install and use a fan-in type semiconductor package on the main board of the electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate interposer substrate, and then mounted on the motherboard of the electronic device by a packaging process, or the fan-in semiconductor package can be embedded in the interposer substrate in the fan-in semiconductor package Installed and used on the motherboard of the electronic device in the state.

Fan-out semiconductor package

7 is a schematic cross-sectional view showing a fan-out type semiconductor package.

Referring to FIG. 7, in the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 may be protected by the encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 may be directed out of the semiconductor chip 2120 through the connection member 2140 Rewire. In this case, a passivation layer 2150 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. Solder balls 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a through hole 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which the input/output terminals of the semiconductor wafer are rewired and arranged outside the semiconductor wafer by the connection member formed on the semiconductor wafer. As described above, in the fan-in semiconductor package, all input/output terminals of the semiconductor chip need to be provided in the semiconductor chip. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls need to be reduced, so that the standardized ball layout may not be used for the fan-in type semiconductor package. On the other hand, as described above, the fan-out type semiconductor package has the form in which the input/output terminals of the semiconductor wafer are rewired and provided outside the semiconductor wafer via the connection member formed on the semiconductor wafer. Therefore, even in the case where the size of the semiconductor wafer is reduced, the standardized ball layout can still be used for the fan-out semiconductor package, so that the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate. As described below.

8 is a schematic cross-sectional view showing a state where a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to FIG. 8, the fan-out semiconductor package 2100 may be mounted on the motherboard 2500 of the electronic device via solder balls 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes the connection member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to a fan-out area outside the size of the semiconductor wafer 2120, making the standardization The ball layout can still be used for the fan-out semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer or the like.

As mentioned above, since the fan-out semiconductor package does not need to use a separate intermediary The substrate can be mounted on the main board of the electronic device, so the fan-out semiconductor package can be implemented with a smaller thickness than the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, the fan-out electronic component package has excellent thermal and electrical characteristics, making the fan-out electronic component package particularly suitable for mobile products. Therefore, the fan-out electronic component package can be implemented in a more compact form than a general package-on-package (POP) type using a printed circuit board (PCB), and can solve the problem caused by the occurrence of warping The problem.

Meanwhile, the fan-out type semiconductor package refers to a packaging technology for mounting a semiconductor chip on a motherboard of an electronic device as described above and protecting the semiconductor chip from external impact, and is in the same concept as a printed circuit board (PCB) such as an interposer substrate The above is different. The printed circuit board has specifications, purposes, etc. different from those of the fan-out semiconductor package, and a fan-in semiconductor package is embedded therein.

Hereinafter, a fan-out semiconductor package in which heat dissipation characteristics can be excellent and warpage can be effectively controlled will be described with reference to the drawings.

9 is a schematic cross-sectional view showing an example of a fan-out type semiconductor package.

10 is a schematic plan view taken along line I-I' of the fan-out semiconductor package of FIG. 9.

9 and 10, the fan-out semiconductor package 100A according to the exemplary embodiment of the present disclosure may include: a semiconductor chip 120 having an active surface 122A and a non-active surface 122P opposite to the active surface 122A, on the active surface 122A The connection pad 122 is provided; the heat dissipation member 125 is attached to the inactive surface 122P of the semiconductor chip 120; the encapsulation body 130 encapsulates each of the semiconductor chip 120 and the heat dissipation member 125 to A small portion; and a connection member 140, which is disposed on the active surface 122A of the semiconductor wafer 120 and includes a redistribution layer 142 electrically connected to the connection pad 122. In the fan-out semiconductor package 100A according to the exemplary embodiment, the heat dissipation member 125 may be attached to the non-active surface of the semiconductor wafer 120 to allow the semiconductor wafer 120 to efficiently dissipate heat.

The heat dissipation member 125 may be formed of a metal having an excellent heat dissipation effect, and may be, for example, copper (Cu) briquettes. In this case, it can be expected to achieve a high heat dissipation effect at low cost. In addition, the effect of suppressing warpage can also be expected by the hard properties of metals, the reduction of mismatches between coefficients of thermal expansion (CTEs), and so on. When a copper briquette or the like is used as a heat dissipation member, a surface treatment may be performed on the surface of the heat dissipation member 125 to improve the tight adhesion between the heat dissipation member 125 and the encapsulant 130. For example, the surface of the heat dissipation member 125 may be surface-treated by organic material coating treatment such as silane treatment as in the exemplary embodiment. In this case, an organic coating layer 127 such as a silane coating layer may be formed on the surface of the heat dissipation member 125.

The heat dissipation member 125 can be attached to the inactive surface 122P of the semiconductor chip 120 through the adhesive film 124. The adhesive film 124 may be a general die attach film (DAF). However, the adhesive film is not limited to this, but may be any adhesive film containing high thermal conductivity. When using a die attach film commercially available in the related art, it is necessary to significantly reduce the thickness of the adhesive film 124 to improve the heat dissipation effect. For example, the thickness of the adhesive film 124 may be 10 μm or less, that is, about 1 μm to 10 μm.

The thickness t2 of the heat dissipation member 125 may be greater than the thickness t1 of the semiconductor wafer 120. In this case, the heat dissipation effect can be improved, and the heat dissipation is encapsulated by the encapsulant 130 In the case of the member 125, the difference between the height of the heat dissipating member 125 and the height of the core member 110 to be explained below can be significantly reduced, and thus the defects caused by the uneven thickness of the encapsulation can be significantly reduced. In detail, when the heat dissipation member 125 is attached to the semiconductor wafer 120 in a state where the semiconductor wafer 120 is not grounded, the total thickness of the semiconductor wafer 120 and the heat dissipation member 125 after the heat dissipation member 125 is attached to the semiconductor wafer 120 may be greater than the core The thickness of the member 110 makes it possible for problems such as uneven thickness of the encapsulation to occur. When the thickness t2 of the heat dissipation member 125 is reduced in order to solve this problem, the heat dissipation effect may be insufficient. Therefore, the thickness t1 of the semiconductor wafer 120 must be smaller than the thickness t2 of the heat dissipation member 125. In this regard, the thickness t1 of the semiconductor wafer 120 may be about 0.4 to 0.6 times the thickness t2 of the heat dissipation member 125.

The encapsulation body 130 may be formed of a material including insulating resin and inorganic filler. In this case, the content of the inorganic filler in the encapsulation body 130 may be higher than the content of the inorganic filler in the general molding material or the encapsulation body to improve thermal conductivity. For example, the content of the inorganic filler in the encapsulant 130 may be 60% to 80% by weight, but it is not limited thereto.

The fan-out semiconductor package 100A may further include a core member 110 having a through hole 110H. When the core member 110 is introduced, the warpage of the fan-out semiconductor package can be controlled more effectively. In particular, when a plurality of wiring layers 112a, 112b, 112c, and 112d formed of metal are formed in the core member 110, the rigidity of the fan-out semiconductor package 100A can be more effectively maintained. Similar to the semiconductor chip 120, the adhesive film 124 and the heat dissipation member 125 may be disposed in the through hole 110H of the core member 110. As described below, the heat dissipation member 125 can be attached to the adhesive film 124 to The non-active surface 122P of the semiconductor chip 120 in the wafer state, the semiconductor chip 120 in the wafer state attached to the heat dissipation member 125 can be singulated by the singulation process, and the heat dissipation member 125 can be as described above It is provided in the through hole 110H in a state of being attached to the semiconductor wafer 120. In this case, the side surface of the semiconductor wafer 120, the side surface of the adhesive film 124, and the side surface of the heat dissipation member 125 may be disposed at substantially the same level. Therefore, when the through hole 110H is filled with the encapsulant 130, negative effects such as void defects can be significantly reduced. When the organic coating layer 127 is formed on the side surface of the heat dissipation member 125, the side surface of the organic coating layer 127 may be disposed at substantially the same level as the side surface of the semiconductor wafer 120 and the side surface of the adhesive film 124 Level.

The fan-out semiconductor package 100A may further include a heat dissipation pattern layer 132B disposed on the encapsulation body 130; and a heat dissipation through hole 133B that penetrates at least part of the encapsulation body 130 and connects the heat dissipation pattern layer 132B and the heat dissipation member 125 to each other. When the heat dissipation pattern layer 132B and the heat dissipation through hole 133B are introduced, the heat dissipated through the heat dissipation member 125 can be more effectively dissipated toward the upper part of the fan-out semiconductor package 100A.

The fan-out semiconductor package 100A may further include a backside wiring layer 132A disposed on the encapsulation body 130; and a backside through hole 133A penetrating at least part of the encapsulation body 130 and connecting the backside wiring layer 132A and the core member 110 The uppermost wiring layers 112d are electrically connected to each other. In addition, the fan-out semiconductor package 100A according to the exemplary embodiment may further include a cover layer 180 disposed on the encapsulation body 130 and having an opening 180h exposing at least a portion of the back-side wiring layer 132A. In this case, the surface of the exposed back-side wiring layer 132A may be provided Surface treatment layer P formed of metal. In addition, the fan-out semiconductor package 100A may further include: a passivation layer 150 disposed under the connection member 140 and having an opening 150h exposing at least a portion of the lowermost heavy wiring layer 142 of the connection member 140; a plurality of under bump metal 160, formed in the opening 150h of the passivation layer 150 and connected to the exposed redistribution layer 142; and a plurality of electrical connection structures 170 disposed under the passivation layer 150 and connected to the plurality of under bump metal 160 . In addition, the fan-out semiconductor package 100A may further include a surface mounting component 190 surface-mounted on the lower surface of the passivation layer 150.

The components included in the fan-out semiconductor package 100A will be explained in more detail below.

The core member 110 may improve the rigidity of the fan-out semiconductor package 100A depending on a specific material, and may be used to ensure the uniformity of the thickness of the encapsulation body 130. When the wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d, the connection via layer 113a, the connection via layer 113b, and the connection via layer 113c are formed in the core member 110, the fan-out semiconductor package 100A can be used as a package-on-package (POP) type package. The core member 110 may have a through hole 110H. The semiconductor chip 120 to which the heat dissipation member 125 is attached through the adhesive film 124 may be disposed in the through hole 110H to be spaced apart from the core member 110 by a predetermined distance. The side surface of the semiconductor wafer 120 and the side surface of the heat dissipation member 125 may be surrounded by the core member 110. However, this form is merely an example, and may be variously modified to have other forms, and the core member 110 may perform another function depending on this form.

The core member 110 may include: a first insulating layer 111a contacting the connecting member 140; a first wiring layer 112a contacting the connecting member 140 and embedded in the first insulating layer 111a; the second wiring layer 112b is provided on the other surface of the first insulating layer 111a opposite to one surface of the first insulating layer 111a embedded with the first wiring layer 112a; the second insulating layer 111b is provided on The first insulating layer 111a covers the second wiring layer 112b; the third wiring layer 112c is disposed on the second insulating layer 111b; the third insulating layer 111c is disposed on the second insulating layer 111b and covers the third wiring layer 112c ; And the fourth wiring layer 112d is provided on the third insulating layer 111c. The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may be electrically connected to the connection pad 122. The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may respectively pass through the first connection via layer 113a, the second connection via layer 113b, and the third connection via The layers 113c are electrically connected to each other.

When the first wiring layer 112a is embedded in the first insulating layer 111a, the stepped portion due to the thickness of the first wiring layer 112a can be significantly reduced, and the insulating distance of the connection member 140 can thus be constant. The lower surface of the first wiring layer 112 a of the core member 110 may be disposed at a level higher than the lower surface of the connection pad 122 of the semiconductor wafer 120. That is, the first wiring layer 112a may be recessed in the first insulating layer 111a, so that there may be a stepped portion between the lower surface of the first insulating layer 111a and the lower surface of the first wiring layer 112a. In this case, the phenomenon that the material of the encapsulant 130 oozes out and contaminates the first wiring layer 112a can be prevented. The second wiring layer 112b and the third wiring layer 112c may be disposed at a level between the active surface 122A and the inactive surface of the semiconductor wafer 120. The core member 110 can be made to a sufficient thickness by a substrate process or the like, and the connection member 140 can be made to a small thickness by a semiconductor process or the like. Therefore, the wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring of the core member 110 The thickness of each of the layers 112d may be greater than the thickness of each of the redistribution layers 142 of the connection member 140.

The material of each of the insulating layer 111a, the insulating layer 111b, and the insulating layer 111c is not particularly limited. For example, an insulating material may be used as the material of each of the insulating layer 111a, the insulating layer 111b, and the insulating layer 111c. In this case, the insulating material may be a thermosetting resin, such as epoxy resin; a thermoplastic resin, such as polyimide resin; a resin that mixes a thermosetting resin or thermoplastic resin with an inorganic filler, or a thermosetting resin or thermoplastic resin Resin impregnated with inorganic filler in core materials such as glass fiber (or glass cloth or glass fiber cloth), such as prepreg, Ajinomoto Build up Film (ABF), FR-4 , Bismaleimide Triazine (Bismaleimide Triazine, BT) and so on. Alternatively, a photosensitive imaging dielectric resin may be used as the insulating material.

The wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d can be used to rewire the connection pad 122 of the semiconductor wafer 120. The material of each of the wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d may perform various functions depending on the design of the corresponding layer. For example, the wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power supply (PWR) pattern, etc., such as a data signal. In addition, with The wire layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d may include via pads, wire bonding pads, electrical connection structure pads, and the like.

The connection via layer 113a, the connection via layer 113b, and the connection via layer 113c can electrically connect the wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d formed on different layers to each other, and then in the core An electrical path is created in the component 110. The material of each of the connection via layer 113a, the connection via layer 113b, and the connection via layer 113c may be a conductive material. Each of the connection via layer 113a, the connection via layer 113b, and the connection via layer 113c may be completely filled with a conductive material, or the conductive material may also be formed along the wall of each of the via holes. At the same time, due to reasons in the manufacturing process, all of the connection via layer 113a, the connection via layer 113b, and the connection via layer 113c may have tapered shapes in the same direction as each other, that is, a tapered shape with an upper diameter greater than a lower diameter.

The semiconductor chip 120 may be an integrated circuit (IC) configured to integrate a number of hundreds to millions or more of elements in a single chip. In this case, the integrated circuit may be, for example, a processor chip (more specifically, an application processor (AP)), such as a central processing unit (eg, CPU), a graphics processor (eg, GPU), Field programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc. However, the integrated circuit is not limited to this, but may be another integrated circuit, such as a memory or a power management element.

The semiconductor wafer 120 may be formed on the basis of an active wafer. In this case, the base material of the body 121 of the semiconductor wafer 120 may be Silicon (Si), Germanium (Ge), Gallium Arsenide (GaAs), etc. Various circuits can be formed on the body 121. The connection pad 122 can electrically connect the semiconductor chip 120 to other components. The material of each of the connection pads 122 may be a conductive material such as aluminum (Al), copper (Cu), or the like. A passivation layer 123 exposing the connection pad 122 may be formed on the active surface 122A of the body 121, and the passivation layer 123 may be an oxide layer, a nitride layer, etc. or a double layer composed of an oxide layer and a nitride layer. With the passivation layer 123, the lower surface of the connection pad 122 may have a stepped portion relative to the lower surface of the encapsulation body 130. Therefore, the encapsulant 130 may fill at least part of the space between the passivation layer 123 and the connection member 140. In this case, the phenomenon that the encapsulating body 130 penetrates into the lower surface of the connection pad 122 can be prevented to some extent. An insulating layer (not shown in the figure) or the like may be further provided in other required positions. The semiconductor wafer 120 may be a bare die. Therefore, the connection pad 122 may physically contact the connection through hole 143 of the connection member 140. However, depending on the type of semiconductor wafer 120, a separate redistribution layer (not shown in the figure) may be further formed on the active surface 122A of the semiconductor wafer 120, and bumps (not shown in the figure), etc. may be connected to the connection垫122。 The pad 122.

The adhesive film 124 may be a general die attach film (DAF). However, the adhesive film is not limited to this, but may be any adhesive film containing a material having high thermal conductivity. When using a die attach film commercially available in the related art, the thickness of the adhesive film 124 is selected to improve the heat dissipation effect. For example, the thickness of the adhesive film 124 may be 10 μm or less, that is, about 1 μm to 10 μm.

The heat dissipation member 125 may be formed of a metal having an excellent heat dissipation effect, and may be, for example, copper (Cu) briquettes. In this case, it can be expected to come at a relatively low cost Achieve high heat dissipation effect. In addition, due to the reduction in the mismatch between the hardness of the metal and the coefficient of thermal expansion, etc., it is also expected to achieve a warpage suppression effect. When a copper briquette or the like is used as a heat dissipation member, a surface treatment may be performed on the surface of the heat dissipation member 125 to improve the tight adhesion between the heat dissipation member 125 and the encapsulant 130. For example, the surface of the heat dissipation member 125 may be surface-treated by organic material coating treatment such as silane treatment as in the exemplary embodiment. In this case, an organic coating layer 127 such as a silane coating layer may be formed on the surface of the heat dissipation member 125.

The thickness t2 of the heat dissipation member 125 may be greater than the thickness t1 of the semiconductor wafer 120. In this case, the heat dissipation effect can be improved, and when the heat dissipation member 125 is enclosed by the encapsulant 130, the difference between the height of the heat dissipation member 125 and the height of the core member 110 to be explained below can be significantly reduced, and Therefore, defects caused by uneven thickness of the encapsulation can be significantly reduced. In detail, when the heat dissipation member 125 is attached to the semiconductor wafer 120 in a state where the semiconductor wafer 120 is not grounded, the total thickness of the semiconductor wafer 120 and the heat dissipation member 125 after the heat dissipation member 125 is attached to the semiconductor wafer 120 may be greater than the core The thickness of the member 110. This may result in uneven encapsulation thickness. When the thickness t2 of the heat dissipation member 125 is reduced in order to solve this problem, the heat dissipation effect may be adversely affected. Therefore, the thickness t1 of the semiconductor wafer 120 can be reduced to be smaller than the thickness t2 of the heat dissipation member 125. In this regard, the thickness t1 of the semiconductor wafer 120 may be about 0.4 to 0.6 times the thickness t2 of the heat dissipation member 125.

The encapsulant 130 can protect the core member 110, the semiconductor chip 120, the adhesive film 124, the heat dissipation member 125, and the like. The encapsulation form of the encapsulation body 130 is not particularly limited, but the encapsulation body 130 may surround the core member 110, the semiconductor chip 120, and the adhesive film 124. At least part of the heat dissipation member 125 and the like. For example, the encapsulant 130 may cover the upper portion of the core member 110 and the upper portion of the heat dissipation member 125 and fill at least part of the through hole 110H to cover the side of the adhesive film 124 and the side of the semiconductor wafer 120. The encapsulant 130 may fill the through hole 110H, thereby acting as an adhesive, and depending on certain materials, reduce the buckling of the semiconductor wafer 120.

The material of the encapsulation body 130 is not particularly limited. For example, an insulating material can be used as the material of the encapsulation body 130. In this case, the insulating material may be a thermosetting resin, such as epoxy resin; a thermoplastic resin, such as polyimide resin; a resin that mixes a thermosetting resin or thermoplastic resin with an inorganic filler, or a thermosetting resin or thermoplastic resin with inorganic The filler is impregnated together with resins in core materials such as glass fiber (or glass cloth, or glass fiber cloth), such as prepreg, Ajinomoto constituent film, FR-4, bismaleimide triazine, etc. Alternatively, a photoimagable encapsulant (PIE) resin can also be used.

When the encapsulation body 130 is formed of a material including an insulating resin and an inorganic filler, the content of the inorganic filler in the encapsulation body 130 may be higher than the content of the inorganic filler in the general molding material or the encapsulation body to improve thermal conductivity . For example, the content of the inorganic filler in the encapsulant 130 may be 60% to 80% by weight, but it is not limited thereto.

The material of each of the back-side wiring layer 132A and the back-side via 133A may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The material of each of the heat dissipation pattern layer 132B and the heat dissipation via 133B may also be the aforementioned conductive material. The backside wiring layer 132A may perform various functions depending on the design. For example, the backside wiring layer 132A may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and so on. Each of the back-side via 133A and the heat dissipation via 133B may have the same direction as the direction of each of the connection via layer 113a, the connection via layer 113b, and the connection via layer 113c of the core member 110 Tapered shape.

The connection member 140 may rewire the connection pad 122 of the semiconductor wafer 120. The tens to hundreds of connection pads 122 of the semiconductor chip 120 having various functions can be re-wired through the connection member 140, and can be physically or electrically connected to the outside through the electrical connection structure 170 depending on the function. The connection member 140 may include: an insulating layer 141 disposed on the active surface 122A of the core member 110 and the semiconductor wafer 120; a redistribution layer 142 disposed on the insulating layer 141; and a connection via 143 penetrating the insulating layer 141 and connecting The pad 122 and the redistribution layer 142 are connected to each other. The drawing shows a case where the connection member 140 includes a plurality of insulating layers, a plurality of redistribution layers, and a plurality of via layers, but the connection member 140 may include more insulation than the number shown in the drawings depending on the design In terms of layers, redistribution layers, and via layers, a smaller number or a larger number of insulating layers, redistribution layers, and via layers.

The material of each of the insulating layers 141 may be an insulating material. In this case, a photosensitive insulating material such as a photosensitive imaging dielectric resin can also be used as the insulating material. That is, each of the insulating layers 141 may be a photosensitive insulating layer. When the insulating layer 141 has photosensitive characteristics, the insulating layer 141 may be formed to have a smaller thickness, and the precise pitch of the connection via 143 may be more easily achieved. Each of the insulating layers 141 may be a photosensitive insulating layer including insulating resin and inorganic filler. When the insulating layer 141 is multiple layers, the materials of the insulating layer 141 may be the same as each other, or if necessary Are different from each other. When the insulating layers 141 are multiple layers, the insulating layers 141 may be integrated with each other depending on the manufacturing process, so that the boundary between the insulating layers may not be obvious. However, the insulating layer 141 is not limited to this.

The redistribution layer 142 may be substantially used to reroute the connection pad 122. The material of each of the redistribution layers 142 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) ), titanium (Ti), or alloys thereof. The redistribution layer 142 may perform various functions depending on the design of the corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern, a power supply (PWR) pattern, a signal (S) pattern, and so on. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power supply (PWR) pattern, etc., such as a data signal. In addition, the redistribution layer 142 may include various pad patterns and the like.

The connection via 143 may electrically connect the redistribution layer 142, the connection pad 122, and the like formed on different layers, thereby generating an electrical path in the fan-out semiconductor package 100A. The material connecting each of the through holes 143 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) ), titanium (Ti), or alloys thereof. Each of the connection vias 143 may be completely filled with a conductive material, or the conductive material may be formed along the wall of each of the via holes. Meanwhile, each of the connection vias 143 of the connection member 140 may have a direction opposite to the direction of each of the connection via layer 113a, the connection via layer 113b, and the connection via layer 113c of the core member 110 Tapered shape. That is, the upper diameter of each of the connection through holes 143 may be smaller than the lower diameter of each of the connection through holes 143.

The passivation layer 150 can protect the connection member 140 from external physical or chemical damage harm. The passivation layer 150 may have an opening 150h exposing at least part of the lowermost redistribution layer 142 of the connection member 140. The number of openings 150h formed in the passivation layer 150 may be tens to thousands. A surface treatment layer (not shown in the figure) can be formed on the surface of the exposed redistribution layer 142 by plating such as precious metal plating. The material of the passivation layer 150 is not particularly limited. For example, an insulating material may be used as the material of the passivation layer 150. In this case, the insulating material may be a thermosetting resin, such as epoxy resin; a thermoplastic resin, such as polyimide resin; a resin that mixes a thermosetting resin or a thermoplastic resin with an inorganic filler, or a thermosetting resin or a thermoplastic resin Resin impregnated with core material such as glass fiber (or glass cloth or glass fiber cloth) together with inorganic filler, such as prepreg, Ajinomoto film, FR-4, bismaleimide triazine, etc. Alternatively, solder resist can also be used.

The under bump metal 160 can improve the connection reliability of the electrical connection structure 170 to improve the board-level reliability of the fan-out semiconductor package 100A. The under bump metal 160 may be connected to the redistribution layer 142 exposed through the opening 150 h of the passivation layer 150 in the connection member 140. The under bump metal 160 may be formed in the opening 150h of the passivation layer 150 by any known metallization method using any known conductive metal (eg, metal), but it is not limited thereto.

The electrical connection structure 170 can externally or electrically connect the fan-out semiconductor package 100A. For example, the fan-out semiconductor package 100A can be mounted on the motherboard of the electronic device via the electrical connection structure 170. Each of the electrical connection structures 170 may be formed of a low melting point metal (for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu)). However, this is only an example, and the electrical connection structure 170 The material of each of them is not particularly limited to this. Each of the electrical connection structures 170 may be a land, a ball, a pin, or the like. The electrical connection structure 170 may be formed as a multi-layer structure or a single-layer structure. When the electrical connection structure 170 is formed as a multilayer structure, the electrical connection structure 170 may include copper (Cu) pillars and solder. When the electrical connection structure 170 is formed as a single-layer structure, the electrical connection structure 170 may include tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structure 170 is not limited to this.

The number, spacing, and arrangement of the electrical connection structure 170 are not particularly limited, but can be sufficiently modified by those skilled in the art depending on the specific details of the design. For example, the electrical connection structure 170 may be configured into a number of tens to thousands according to the number of connection pads 122. In some embodiments, more or fewer electrical connection structures 170 may be configured. When the electrical connection structure 170 is a solder ball, the electrical connection structure 170 may cover the side surface of the under bump metal 160 extending to one surface of the passivation layer 150, and the connection reliability may be more excellent. At least one of the electrical connection structures 170 may be disposed in the fan-out area. The fan-out area refers to an area other than the area where the semiconductor wafer 120 is provided. Compared to fan-in packages, fan-out packages can have excellent reliability, can implement multiple input/output (I/O) terminals, and can facilitate three-dimensional (3D) interconnects. In addition, compared to ball grid array (BGA) packaging, land grid array (LGA) packaging, etc., the fan-out package can be manufactured to have a small thickness and can have a price Competitiveness.

The cover layer 180 may protect the backside wiring layer 132A and/or the heat dissipation pattern layer 132B from external physical or chemical damage. The cover layer 180 may have exposed back side wiring At least part of the opening 132A of the layer 132A is 180h. The number of openings 180h formed in the cover layer 180 may be tens to thousands. The surface treatment layer P may be formed on the surface of the exposed back-side wiring layer 132A. The material of the cover layer 180 is not particularly limited. For example, an insulating material may be used as the material of the cover layer 180. In this case, the insulating material may be a thermosetting resin, such as epoxy resin; a thermoplastic resin, such as polyimide resin; a resin that mixes a thermosetting resin or a thermoplastic resin with an inorganic filler, or a thermosetting resin or a thermoplastic resin Resin impregnated with core material such as glass fiber (or glass cloth or glass fiber cloth) together with inorganic filler, such as prepreg, Ajinomoto film, FR-4, bismaleimide triazine, etc. Alternatively, solder resist can also be used.

The surface mounting component 190 can be mounted on the lower surface of the passivation layer 150 by surface mounting technology (SMT). The surface mount component 190 may be any known passive component, such as a capacitor, an inductor, etc., but it is not limited thereto. If necessary, the surface mount component 190 may be an active component. The surface mount component 190 can be electrically connected to the connection pad 122 of the semiconductor chip 120 through the redistribution layer 142 of the connection member 140.

Although not shown in the figure, if necessary, a plurality of semiconductor wafers 120 that perform the same or different functions from each other may be provided in the through hole 110H. In addition, if necessary, a separate passive component such as an inductor, a capacitor, etc. may be provided in the through hole 110H.

FIG. 11A is a schematic diagram showing a process of forming an organic coating on a heat dissipation member.

Referring to FIG. 11A, the heat dissipation member 125 may be surface-treated by an organic material coating process such as silane treatment. In this case, as shown in FIG. 11A, an organic coating layer 127 such as a silane coating layer may be formed on the surface of the heat dissipation member 125. As described above, the close adhesion between the heat dissipation member 125 and the encapsulating body 130 can be improved by surface treatment.

11B and 11C are schematic diagrams showing various examples of the process of attaching the heat dissipation member to the inactive surface of the semiconductor wafer.

Referring to FIG. 11B, the semiconductor chip 120 to which the heat dissipation member 125 is attached can be obtained by attaching the adhesive film 124 to the lower portion of the heat dissipation member 125 with the organic coating 127 formed thereon by surface treatment, and then passing The adhesive film 124 attaches the heat dissipation member 125 with the organic coating layer 127 formed thereon to the inactive surface 122P of the semiconductor chip 120. If necessary, a series of processes can be performed by attaching the coated heat dissipation member 125 to the semiconductor chip 120 in a wafer state through the adhesive film 124, and then dicing through the dicing process The semiconductor wafer 120 with the heat dissipation member 125 attached.

Alternatively, referring to FIG. 11C, the semiconductor chip 120 to which the heat dissipation member 125 is attached can be obtained by attaching the adhesive film 124 to the inactive surface of the semiconductor chip 120, and then forming an organic layer above by surface treatment The heat dissipation member 125 of the coating 127 is attached to the adhesive film 124. If necessary, a series of processes can be performed by attaching the adhesive film 124 to the semiconductor chip 120 in a wafer state, attaching the coated heat dissipation member 125 to the adhesive film 124, and then by The singulation process singulates the semiconductor chip 120 to which the heat dissipation member 125 is attached.

12A and 12B are schematic diagrams showing an example of a process of manufacturing a fan-out semiconductor package.

12A, the core member 110 may be prepared first. The core member 110 may be manufactured using a coreless substrate. In detail, the core member 110 can be prepared by repeating the following series of processes: a first wiring layer 112a is formed on a coreless substrate by a plating process, and a first insulating layer is formed by laminating Ajinomoto to form a film, etc. 111a, forming a laser via hole in the first insulating layer 111a using some pad patterns of the first wiring layer 112a as a termination element, and forming the second wiring layer 112b and the first connection via layer by a plating process 113a, and then the coreless substrate is separated and removed. The metal layer remaining on the lower surface of the core member 110 after separating the coreless substrate may be removed by etching. In this case, a stepped portion may be formed between the lower surface of the first insulating layer 111a of the core member 110 and the lower surface of the first wiring layer 112a. Then, laser drilling, mechanical drilling, or the like may be used to form the through hole 110H in the core member 110, and the tape 210 may be attached to the lower portion of the core member 110. Then, the semiconductor wafer 120 to which the heat dissipation member 125 is attached can be attached to the tape 210 in the through hole 110H, and the encapsulant 130 can be formed by forming a film stack or the like with Ajinomoto.

Then, referring to FIG. 12B, the tape 210 may be removed, and the connection member 140 may be formed in the area where the tape 210 is removed. The connection member 140 can be formed by repeating the following series of processes: forming the insulating layer 141 by photosensitive imaging dielectric coating, forming optical via holes in the insulating layer 141 by lithography, and forming by a plating process Re-wiring layer 142 and connection via 143. Then, the back-side wiring layer 132A and the heat dissipation pattern may be formed by forming laser via holes in the encapsulation 130 and then performing plating The layer 132B, the back-side via 133A, the heat dissipation via 133B, etc., or a film stack via Ajinomoto, etc., may be formed on the opposite side of the fan-out semiconductor package 100A to form the passivation layer 150 and the cover layer 180, respectively. Drilling etc. form openings 150h and 180h in the passivation layer 150 and the cover layer 180 respectively, the under bump metal 160 can be formed by plating, the electrical connection structure 170 can be formed using solder material, and reflow can be performed accordingly Process. The fan-out semiconductor package 100A according to the above-described exemplary embodiment may be formed through a series of processes.

The above series of processes can be performed using the core member 110 having a large size, that is, a panel size. In this case, a plurality of fan-out semiconductor packages 100A can be formed by the core member 110 having a panel size, and when the plurality of fan-out semiconductor packages 100A are separated from each other by the singulation process, the A process is performed to obtain the plurality of fan-out semiconductor packages 100A.

13 is a schematic cross-sectional view showing another example of a fan-out type semiconductor package.

Referring to FIG. 13, the fan-out semiconductor package 100B according to another exemplary embodiment of the present disclosure may further include a metal layer 115 formed on the wall of the through hole 110H. The metal layer 115 may extend to the upper surface of the core member 110, and may be electrically connected to the ground pattern of the wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d of the core member 110 and/or the weight of the connection member 140 The ground pattern of the wiring layer 142. The heat generated from the semiconductor wafer 120 can be efficiently transferred to the side of the fan-out semiconductor package 100B through the metal layer 115, and thus can be more easily dissipated outward. The metal layer 115 may be composed of the wiring layer 112a, the wiring layer 112b, and the wiring like the core member 110. The conductive material of the same conductive material of each of the layer 112c and the wiring layer 112d is formed. The other content is the same as the above content, so its detailed description is omitted.

14 is a schematic cross-sectional view showing another example of a fan-out type semiconductor package.

Referring to FIG. 14, the fan-out semiconductor package 100C according to another exemplary embodiment of the present disclosure may further include a reinforcement layer 181. The reinforcement layer 181 may be disposed between the encapsulation 130 and the back-side wiring layer 132A and the heat dissipation pattern layer 132B. By providing the reinforcement layer 181, the warpage of the fan-out semiconductor package 100C can be more effectively suppressed. In this regard, the elastic modulus of the reinforcement layer 181 may be greater than the elastic modulus of the encapsulant 130 and the elastic modulus of the cover layer 180. For example, prepregs, uncoated copper-clad laminates, etc., including insulating resins, inorganic fillers, and glass fibers can be used as the material for the reinforcing layer 181, and Ajinomoto can be used to form films, including insulating layers and The inorganic filler serves as the material of each of the encapsulation body 130 and the cover layer 180. The back side through hole 133A and the heat dissipation through hole 133B may also penetrate the reinforcement layer 181. If necessary, a resin layer (not shown in the figure) may be further provided between the reinforcement layer 181, the back-side wiring layer 132A, and the heat dissipation pattern layer 132B, so that it is easier to form an opening in the reinforcement layer 181. The other content is the same as the above content, so its detailed description is omitted.

15 is a schematic cross-sectional view showing another example of a fan-out type semiconductor package.

15, in the fan-out semiconductor package 100D according to another exemplary embodiment in the present disclosure, the third insulating layer 111c, the third connection via layer 113c, and the fourth wiring layer may be omitted in the core member 110 112d. That is, the core components The number of the insulating layer, the wiring layer, and the connection via layer of 110 may be various. In this case, the thickness of the core member 110 may be changed, and the thickness of the semiconductor chip 120 and the thickness of the heat dissipation member 125 may be changed by a polishing process or the like depending on the changed thickness of the core member 110. However, also in this case, in terms of the heat dissipation effect, it may be advantageous that the thickness of the semiconductor wafer 120 is about 0.4 to 0.6 times the thickness of the heat dissipation member 125. The other content is the same as the above content, so its detailed description is omitted.

16 is a schematic cross-sectional view showing another example of a fan-out type semiconductor package.

Referring to FIG. 16, in a fan-out semiconductor package 100E according to another exemplary embodiment of the present disclosure, the core member 110 may include a first insulating layer 111a; a first wiring layer 112a and a second wiring layer 112b, respectively provided On the lower and upper surfaces of the first insulating layer 111a; the second insulating layer 111b is disposed on the lower surface of the first insulating layer 111a and covers the first wiring layer 112a; the third wiring layer 112c is disposed on the second insulating The lower surface of the layer 111b; the third insulating layer 111c provided on the upper surface of the first insulating layer 111a and covering the second wiring layer 112b; and the fourth wiring layer 112d provided on the upper surface of the third insulating layer 111c . The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may be electrically connected to the connection pad 122. Since the core member 110 may include a large number of wiring layers 112a, wiring layers 112b, wiring layers 112c, and wiring layers 112d, the connection member 140 may be simplified. Therefore, the problem of a decrease in yield due to defects occurring in the process of forming the connection member 140 can be suppressed. At the same time, the first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d can pass through the first connection via layer 113a and the second connection via which respectively penetrate the first insulation layer 111a, the second insulation layer 111b, and the third insulation layer 111c The hole layer 113b and the third connection via layer 113c are electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of wiring layers 112c and wiring layers 112d. The first insulating layer 111a may include an insulating material different from the insulating material of the second insulating layer 111b and the insulating material of the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including glass fiber, inorganic filler, and insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be odorants including inorganic filler and insulating resin The element constitutes a film or a photosensitive imaging dielectric film. However, the material of the first insulating layer 111a, the material of the second insulating layer 111b, and the material of the third insulating layer 111c are not limited thereto. Similarly, the diameter of the first connection via layer 113a penetrating the first insulating layer 111a may be larger than the diameter of the second connection via layer 113b penetrating the second insulating layer 111b and the third insulating layer 111c and the third connection via The diameter of the hole layer 113c.

The lower surface of the third wiring layer 112c of the core member 110 may be disposed at a lower level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the connection member 140 and the third wiring layer 112 c of the core member 110 may be smaller than the distance between the redistribution layer 142 of the connection member 140 and the connection pad 122 of the semiconductor wafer 120. The reason is that the third wiring layer 112c may protrude The form is provided on the second insulating layer 111b, and then contacts the connection member 140. The first wiring layer 112a and the second wiring layer 112b of the core member 110 may be disposed at a level between the active surface and the inactive surface of the semiconductor wafer 120. The thickness of each of the wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d of the core member 110 may be greater than the thickness of each of the redistribution layers 142 of the connection member 140. The first connection via layer 113a may have an hourglass shape, and the second connection via layer 113b and the third connection via layer 113c may have tapered shapes in directions opposite to each other. The detailed description of the other configurations overlaps with the above, and therefore is omitted.

FIG. 17 is a graph schematically showing the heat radiation effect of the fan-out type semiconductor package manufactured according to the example.

In the experiment, copper agglomerates were used as the material of the heat dissipation member, and die attach film (DAF) was used as the adhesive film. In this case, the sum of the thickness of the copper agglomerate and the thickness of the die attach film is set to about 210 microns, and the thickness of the semiconductor wafer is fixed to about 100 microns. The structure of the fan-out type semiconductor package 100A according to the above-described exemplary embodiment is used as the basic structure of the package. The interposer package on package (IPOP) according to the related art has a thermal resistance of about 20°C/watt. However, as can be seen from FIG. 17, the thermal resistance of the fan-out type semiconductor package according to the exemplary embodiment can be reduced to about 17° C./Watt or lower. In this case, it can be seen that the thickness of the die attach film is 10 μm or less is advantageous. The reason is that when the thickness of the die attach film is 10 μm or less, the fan-out semiconductor package has a thermal resistance of 17° C./W or less.

As described above, according to the exemplary embodiment in the present disclosure, heat dissipation can be provided The characteristics can be a fan-out semiconductor package that is excellent and warpage can be effectively controlled.

Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications can be made without departing from the scope of the present invention defined by the scope of the accompanying patent application And variants.

100A‧‧‧Fan-out semiconductor package

110‧‧‧Core components

110H‧‧‧Through hole

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

111c‧‧‧The third insulating layer

112a‧‧‧Wiring layer/first wiring layer

112b‧‧‧Wiring layer/second wiring layer

112c‧‧‧Wiring layer/third wiring layer

112d‧‧‧Wiring layer/uppermost wiring layer/fourth wiring layer

113a‧‧‧Connect via layer/First connect via layer

113b‧‧‧Connect via layer/Second connect via layer

113c‧‧‧Connect via layer/third connect via layer

120‧‧‧Semiconductor chip

121‧‧‧Body

122‧‧‧ connection pad

122A‧‧‧Active surface

122P‧‧‧Nonactive surface

123、150‧‧‧passivation layer

124‧‧‧ Adhesive film

125‧‧‧radiating component

127‧‧‧ organic coating

130‧‧‧Envelope

132A‧‧‧Back wiring layer

132B‧‧‧ heat dissipation pattern layer

133A‧‧‧Back side through hole

133B‧‧‧through hole

140‧‧‧Connecting member

141‧‧‧Insulation

142‧‧‧Rerouting layer/lowest rerouting layer

143‧‧‧Connect through hole

150h, 180h‧‧‧ opening

160‧‧‧Metal under bump

170‧‧‧Electrical connection structure

180‧‧‧overlay

190‧‧‧Surface mounted components

I-I’‧‧‧ line

P‧‧‧Surface treatment layer

t1, t2‧‧‧thickness

Claims (30)

A fan-out semiconductor package includes: a semiconductor chip having an active surface and a non-active surface opposite to the active surface, a connection pad is provided on the active surface; a heat dissipating member attached to the semiconductor chip An inactive surface; an encapsulation body covering at least part of each of the semiconductor chip and the heat dissipation member, wherein the encapsulation body integrally covers at least part of the upper portion of the heat dissipation member, the heat dissipation member Side of the semiconductor wafer; and a connection member provided on the active surface of the semiconductor wafer and including a redistribution layer electrically connected to the connection pad, wherein the heat dissipation member The thickness is greater than the thickness of the semiconductor wafer. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the thickness of the semiconductor wafer is 0.4 to 0.6 times the thickness of the heat dissipation member. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the heat dissipation member is attached to the inactive surface of the semiconductor chip by an adhesive film. The fan-out semiconductor package as described in item 3 of the patent application range, wherein the adhesive film is a die attach film (DAF) having a thickness of 1 μm to 10 μm. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the heat dissipation member is a copper (Cu) agglomerate. The fan-out semiconductor package as described in item 5 of the patent application scope, wherein an organic coating is formed on the surface of the copper agglomerate. The fan-out semiconductor package as described in item 6 of the patent application range, wherein the organic coating layer includes a silane coating layer. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the encapsulation body includes an insulating resin and an inorganic filler, and the content of the inorganic filler in the encapsulation body is 60% by weight to 80% by weight %. The fan-out semiconductor package as described in item 1 of the patent application scope further includes: a heat dissipation pattern layer provided on the encapsulation body; and a heat dissipation through hole penetrating at least part of the encapsulation body and connecting the The heat radiation pattern layer and the heat radiation member are connected to each other. The fan-out semiconductor package as described in item 9 of the patent application scope further includes: a reinforcement layer disposed between the encapsulation body and the heat dissipation pattern layer; and a cover layer disposed on the reinforcement layer and At least part of the heat dissipation pattern layer is covered, wherein the elastic modulus of the reinforcing layer is greater than the elastic modulus of the encapsulation body and the elastic modulus of the cover layer. The fan-out semiconductor package as described in item 1 of the patent application scope further includes a core member having a through hole, wherein the semiconductor chip and the heat dissipation member are disposed in the through hole, and The encapsulant covers at least part of the core member, the semiconductor wafer, and the heat dissipation member, and fills at least part of the through hole. The fan-out type semiconductor package as described in item 11 of the patent application range, wherein the core member includes a plurality of wiring layers, and the plurality of wiring layers of the core member is determined by the weight of the connection member The wiring layer is electrically connected to the connection pad of the semiconductor wafer. The fan-out semiconductor package as described in item 12 of the patent application scope further includes: a backside wiring layer provided on the encapsulation body; and a backside through hole penetrating at least part of the encapsulation body and The back-side wiring layer and the uppermost wiring layer of the plurality of wiring layers of the core member are electrically connected to each other. The fan-out semiconductor package according to item 13 of the patent application scope further includes: a reinforcement layer disposed between the encapsulation body and the back-side wiring layer; and a cover layer disposed on the reinforcement layer And covering at least part of the backside wiring layer, wherein the elastic modulus of the reinforcing layer is greater than the elastic modulus of each of the encapsulant and the cover layer. The fan-out semiconductor package as described in item 12 of the patent application scope, wherein the core member includes a first insulating layer, a first wiring layer, a second wiring layer, a second insulating layer, and a third wiring layer, the A first insulating layer contacts the connection member, the first wiring layer is embedded in the first insulation layer and contacts the connection member, The second wiring layer is provided on the other surface of the first insulating layer opposite to one surface of the first insulating layer in which the first wiring layer is embedded, the second insulating layer is provided on On the first insulating layer and covering the second wiring layer, the third wiring layer is disposed on the second insulating layer, and the first wiring layer to the third wiring layer are electrically connected to The connection pad of the semiconductor wafer. The fan-out semiconductor package according to item 15 of the patent application scope, wherein the core member further includes a third insulating layer disposed on the second insulating layer and covering the third wiring layer, and a third insulating layer disposed on the A fourth wiring layer on the third insulating layer, and the first wiring layer to the fourth wiring layer are electrically connected to the connection pads of the semiconductor wafer. The fan-out semiconductor package as described in item 15 of the patent application range, wherein a step portion is provided between the lower surface of the first wiring layer and the lower surface of the first insulating layer. The fan-out semiconductor package as described in item 12 of the patent application range, wherein the core member includes a first insulating layer, a first wiring layer provided on a lower surface of the first insulating layer, and a A second wiring layer on the upper surface of the first insulating layer, and the first wiring layer and the second wiring layer are electrically connected to the connection pad of the semiconductor wafer. The fan-out semiconductor package as described in item 18 of the patent application scope, which The core member further includes a second insulating layer, a third wiring layer, a third insulating layer, and a fourth wiring layer, the second insulating layer is disposed on and covers the lower surface of the first insulating layer The first wiring layer, the third wiring layer are provided on the lower surface of the second insulating layer, and the third insulating layer is provided on the upper surface of the first insulating layer and covers the A second wiring layer, the fourth wiring layer is provided on an upper surface of the third insulating layer, and the first wiring layer to the fourth wiring layer are electrically connected to the connection of the semiconductor wafer pad. The fan-out semiconductor package as recited in item 19 of the patent application range, wherein the thickness of the first insulating layer is greater than the thickness of each of the second insulating layer and the third insulating layer. A fan-out semiconductor package includes: a semiconductor wafer; a heat dissipating member, the thickness of the heat dissipating member is greater than the thickness of the semiconductor wafer, and the heat dissipating member is disposed on the non-active surface of the semiconductor wafer; the connecting member includes A redistribution layer, the connection member is disposed on the active surface of the semiconductor wafer, so that the connection pad disposed on the active surface is electrically connected to the redistribution layer, wherein the semiconductor wafer and the heat dissipation member At least part of each of them is covered by an encapsulation body, and the encapsulation body integrally covers at least a part of the upper portion of the heat dissipation member, a side portion of the heat dissipation member, and a side portion of the semiconductor wafer. The fan-out semiconductor package as described in item 21 of the patent application scope, which In the heat dissipation member, an organic coating is provided, and the heat dissipation member is attached to the semiconductor chip through an adhesive film. The fan-out semiconductor package as described in item 21 of the patent application scope further includes a core member having a through hole, the semiconductor chip and the heat dissipation member are disposed in the through hole, wherein the encapsulation body covers the At least part of the core member and fill at least part of the through hole. The fan-out semiconductor package as recited in item 23 of the patent application range, wherein the core member includes a metal layer disposed on the sidewall of the through hole. The fan-out semiconductor package as described in item 23 of the patent application scope further includes a reinforcement layer disposed on the encapsulation body and covering the top portion of the heat dissipation member and the top portion of the core member. The fan-out semiconductor package as described in item 23 of the patent application scope further includes a wiring layer electrically connected to the connection pad of the semiconductor wafer through the redistribution layer of the connection member. A fan-out semiconductor package includes: a connection member including at least one redistribution layer; a semiconductor wafer, a connection pad is disposed on an active surface of the semiconductor wafer, and the semiconductor wafer is disposed on the connection member, the connection The pad is electrically connected to the redistribution layer; a heat dissipation member, the thickness of the heat dissipation member is greater than the thickness of the semiconductor wafer, the heat dissipation member is disposed on the non-active surface of the semiconductor wafer, The active surface is opposite to the active surface; and an encapsulation body covering at least part of each of the semiconductor wafer and the heat dissipation member, wherein the encapsulation body integrally covers at least an upper portion of the heat dissipation member Part, the side of the heat dissipation member, and the side of the semiconductor wafer. The fan-out semiconductor package as described in item 27 of the patent application scope further includes a core member provided on the connection member, the core member has a through hole, and the semiconductor wafer and the heat dissipation member are provided on the Through the hole. The fan-out semiconductor package as recited in item 28 of the patent application range, wherein the encapsulation body covers at least a part of the core member and fills at least a part of the through-hole. The fan-out type semiconductor package as described in item 28 of the patent application range, wherein the core member includes a wiring layer electrically connected to the connection pad of the semiconductor chip through the rewiring layer of the connection member .

Images