TWI693873B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

Info

Publication number
TWI693873B
TWI693873B TW107125502A TW107125502A TWI693873B TW I693873 B TWI693873 B TW I693873B TW 107125502 A TW107125502 A TW 107125502A TW 107125502 A TW107125502 A TW 107125502A TW I693873 B TWI693873 B TW I693873B
Authority
TW
Taiwan
Prior art keywords
bonding
layer
substrate
dummy pad
forming
Prior art date
Application number
TW107125502A
Other languages
English (en)
Other versions
TW201916775A (zh
Inventor
魏嘉余
李承遠
林彥良
李國政
黃薰瑩
陳信吉
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201916775A publication Critical patent/TW201916775A/zh
Application granted granted Critical
Publication of TWI693873B publication Critical patent/TWI693873B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03019—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0383—Reworking, e.g. shaping
    • H01L2224/03845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H01L2224/06517—Bonding areas having different functions including bonding areas providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0951—Function
    • H01L2224/09515—Bonding areas having different functions
    • H01L2224/09517—Bonding areas having different functions including bonding areas providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80054—Composition of the atmosphere
    • H01L2224/80075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053—Bonding environment
    • H01L2224/83054—Composition of the atmosphere
    • H01L2224/83075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

提供半導體結構，其包含第一半導體裝置、第二半導體裝置及接合結構。第一半導體裝置包含第一導電層形成於第一基板上，第一蝕刻停止層形成於第一導電層上，且與第一導電層直接接觸，第一接合層形成於第一蝕刻停止層上，以及第一接合導孔穿過第一接合層和第一蝕刻停止層而形成。第二半導體裝置包含第二導電層和第二蝕刻停止層形成於第二基板上，第二接合層形成於第二蝕刻停止層上，以及第二接合導孔穿過第二接合層和第二蝕刻停止層而形成。接合結構位於第一基板與第二基板之間，且包含第一接合導孔接合至第二接合導孔。

Description

半導體結構及其形成方法
本發明實施例係有關於半導體製造，且特別有關於半導體裝置的接合技術及其形成的結構。
半導體裝置用於各種電子產品的應用上，像是個人電腦、手機、數位相機和其他電子設備。半導體裝置通常藉由依序沉積絕緣或介電層、導電層和半導體層的材料於半導體基底上，且使用微影技術將各種材料層圖案化，以形成電路組件和元件在半導體基底上。許多積體電路通常是在單一半導體晶圓上製造，且藉由沿著切割道在積體電路之間進行切割，將晶圓上各自獨立的晶粒分開。舉例而言，在多晶片模組中，或者在其他種類的封裝中，這些各自獨立的晶粒通常分開封裝。
影像感測器係用於將聚焦於影像感測器上的光學影像轉變為電性信號。影像感測器包含光線偵測元件例如光電二極體之陣列，且光線偵測元件配置為對應於照射在光線偵測元件上的光線強度產生電性信號。電性信號用於顯示相對應的影像在螢幕上，或提供關於光學影像的資訊。
雖然目前的影像感測器裝置結構及其形成方法通常已經足夠用於其預期的目的，但是仍無法在全部方面完全地令人滿意。
根據本發明的一些實施例，提供半導體結構。此半導體結構包含第一半導體裝置、第二半導體裝置以及接合結構。第一半導體裝置包含第一導電層形成於第一基板之上；第一蝕刻停止層形成於第一導電層之上，其中第一蝕刻停止層直接接觸第一導電層；第一接合層形成於第一蝕刻停止層之上；以及第一接合導孔穿過第一接合層和第一蝕刻停止層而形成，其中第一接合導孔電性連接至第一導電層。第二半導體裝置包含第二導電層形成於第二基板之上；第二蝕刻停止層形成於第二導電層之上，其中第二蝕刻停止層直接接觸第二導電層；第二接合層形成於第二蝕刻停止層之上；以及第二接合導孔穿過第二接合層和第二蝕刻停止層而形成，其中第二接合導孔電性連接至第二導電層。接合結構位於第一基板與第二基板之間，其中接合結構包含第一接合導孔接合至第二接合導孔。
根據本發明的另一些實施例，提供半導體結構。此半導體結構包含影像感測器裝置、邏輯電路裝置以及混成接合結構。影像感測器裝置包含第一基板，其中第一基板包含第一內連線區和畫素區；光感測區形成於第一基板中的畫素區內；第一氧化物層形成於光感測區下方；第一接合層形成於第一氧化物層下方；以及第一接合導孔穿過第一接合層和第一氧化物層而形成。邏輯電路裝置形成於影像感測器裝置下方，其中邏輯電路裝置包含第二基板，其中第二基板包含第二內連線區和邏輯區；電晶體裝置形成於第二基板之上；第二氧化物層形成於電晶體裝置之上；第二接合層形成於第二氧化物層之 上；以及第二接合導孔穿過第二接合層和第二內連線區內的第二氧化物層而形成。混成接合結構位於影像感測器裝置與邏輯電路裝置之間，且混成接合結構包括第一接合導孔接合至第二接合導孔。
根據本發明的一些實施例，提供形成半導體結構的方法。此方法包含形成第一半導體裝置，其中形成第一半導體裝置的步驟包含形成第一氧化物層於第一基板之上，其中第一基板包含畫素區和第一內連線區；形成第一接合層於第一氧化物層之上；形成第一凹陷於第一接合層中的畫素區內；形成第一溝槽穿過第一內連線區內的第一接合層和第一氧化物層；填充導電材料於第一凹陷和第一溝槽內，以形成第一虛置墊和第一接合導孔。此方法也包含形成第二半導體裝置，其中形成第二半導體裝置的步驟包含形成第二氧化物層於第二基板之上，其中第二基板包含邏輯區和第二內連線區；形成第二接合層於第二氧化物層之上；形成第二凹陷於邏輯區內的第二接合層中；形成第二溝槽穿過第二接合層和第二氧化物層；填充導電材料於第二凹陷和第二溝槽內，以形成第二虛置墊和第二接合導孔。此方法還包含藉由將第一接合導孔接合至第二接合導孔，以及將第一虛置墊接合至第二虛置墊，將第一半導體裝置與第二半導體裝置接合。
11、21‧‧‧第一區
12、22‧‧‧第二區
15a‧‧‧第一蝕刻步驟
15b‧‧‧第二蝕刻步驟
15c‧‧‧第三蝕刻步驟
25‧‧‧光線
100a、100b、500‧‧‧第一半導體裝置
200a、200b、600‧‧‧第二半導體裝置
300a、300b、700‧‧‧半導體結構
102、502‧‧‧第一基板
102a、502a、602a‧‧‧第一表面
102b、502b、602b‧‧‧第二表面
104‧‧‧第一導電層
106‧‧‧第一蝕刻停止層
108‧‧‧第一氧化物層
110‧‧‧第一接合層
111‧‧‧凹陷
T1‧‧‧第一厚度
T2‧‧‧第二厚度
112‧‧‧導電材料
113‧‧‧第一溝槽
114‧‧‧第一虛置墊
116‧‧‧第一接合導孔
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
W4‧‧‧第四寬度
D1‧‧‧第一深度
D2‧‧‧第二深度
D3‧‧‧第三深度
D4‧‧‧第四深度
202、602‧‧‧第二基板
204‧‧‧第二導電層
206‧‧‧第二蝕刻停止層
208‧‧‧第二氧化物層
210‧‧‧第二接合層
214‧‧‧第二虛置墊
216‧‧‧第二接合導孔
310‧‧‧混成接合結構
310a‧‧‧第一金屬接合介面
310b‧‧‧第二金屬接合介面
310c‧‧‧非金屬介面
504‧‧‧光感測區
506、606‧‧‧閘極介電層
508、608‧‧‧閘極電極層
510、610‧‧‧電晶體裝置
512、612‧‧‧閘極間隔物
514、614‧‧‧層間介電層
520‧‧‧第一內連線結構
522、622‧‧‧金屬間介電層
524、624‧‧‧導線
526、626‧‧‧導孔插塞
528‧‧‧金屬阻擋結構
530‧‧‧深隔離結構
532‧‧‧金屬遮蔽結構
534‧‧‧網格結構
534a‧‧‧底部
534b‧‧‧頂部
536‧‧‧介電層
540‧‧‧彩色濾光片
542‧‧‧微透鏡結構
620‧‧‧第二內連線結構
為了讓本發明實施例能更容易理解，以下配合所附圖式作詳細說明。應該注意，根據工業上的標準範例，各個部件(feature)未必按照比例繪製。實際上，為了讓討論清晰易 懂，各個部件的尺寸可以被任意放大或縮小。
第1A-1I圖顯示根據本發明的一些實施例，形成半導體結構的剖面示意圖。
第2圖顯示根據本發明的一些實施例，第1H圖的第一虛置墊、第一接合導孔、第二虛置墊和第二接合導孔的上視圖。
第3A-3C圖顯示根據本發明的一些實施例，形成半導體結構的剖面示意圖。
第4A-4D圖顯示根據本發明的一些實施例，第一虛置墊和第二虛置墊的排列或佈局之立體圖。
第5A-5D圖顯示根據本發明的一些實施例，形成半導體結構的剖面示意圖。
以下內容提供了許多不同實施例或範例，以實現本發明實施例標的之不同部件(feature)。以下描述組件和配置方式的具體範例，以簡化本發明實施例。當然，這些僅僅是範例，而非意圖限制本發明實施例。舉例而言，在以下描述中提及於第二部件上方或其上形成第一部件，其可以包含第一部件和第二部件以直接接觸的方式形成的實施例，並且也可以包含在第一部件和第二部件之間形成額外的部件，使得第一部件和第二部件可以不直接接觸的實施例。此外，本發明實施例可在各個範例中重複參考標號及/或字母。此重複是為了簡化和清楚之目的，其本身並非用於指定所討論的各個實施例及/或配置之間的關係。
以下描述實施例的一些變化，在各種圖式和說明 的實施例中，使用相似的參考標號來標示相似的元件。可以理解的是，在描述的方法之前、期間和之後可以提供額外的操作，並且在此描述的一些操作對於方法的其他實施例而言可以被置換或消除。
提供實施例以形成具有混成接合(hybrid bonding)結構的半導體結構。第1A-1I圖顯示根據本發明的一些實施例，形成半導體結構300a的剖面示意圖，半導體結構300a是通過混成接合製程將第一半導體裝置100a與第二半導體裝置200a接合而形成。
如第1A圖所示，半導體裝置100a包含第一基板102，第一基板102包含第一表面102a，以及與第一表面102a相反的第二表面102b。第一基板102可由矽或其他半導體材料製成。替換地或額外地，第一基板102可包含其他元素半導體材料，像是鍺。在一些實施例中，第一基板102由化合物半導體製成，像是碳化矽、砷化鎵、砷化銦、或磷化銦。在一些實施例中，第一基板102由合金半導體製成，像是矽鍺、矽鍺碳化物、磷化砷鎵(gallium arsenic phosphide)、或磷化銦鎵(gallium indium phosphide)。在一些實施例中，第一基板102包含磊晶層，舉例而言，第一基板102具有磊晶層位於整體半導體上。
第一基板102包含第一區11和第二區12。在一些實施例中，第一基板102為影像感測器裝置的基板，第一區11為第一內連線區(或重分布層(redistribution layer(RDL)區)，且第二區12為畫素區。
在一些實施例中，井區部分(未繪示)可形成在第一 基板102的第二區12中，在第一基板102上進行離子佈植製程以形成井區部分。在一些實施例中，井區部分可用砷(As)或磷(P)離子摻雜，以形成N型井區部分。在一些實施例中，井區部分可用硼(B)離子摻雜，以形成P型井區部分。
第一基板102還可包含隔離部件，像是淺溝槽隔離(shallow trench isolation，STI)部件、或矽局部氧化(local oxidation of silicon，LOCOS)部件。隔離部件可定義並隔離各種裝置元件。
第一導電層104形成在第一基板102的第一區11內，第一導電層104可以是內連線結構的導電層。第一導電層104可由銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金製成。在一些實施例中，第一導電層104藉由電鍍法形成。
第一蝕刻停止層106形成在第一基板102的第一表面102a之上，且第一氧化物層108形成在第一蝕刻停止層106之上。第一蝕刻停止層106由氧化矽(SiOx)、碳化矽(SiC)、氮化矽(SixNy)、碳氮化矽(SiCN)、碳氧化矽(SiOC)、碳氧氮化矽(SiOCN)、或其他合適材料製成。在一些實施例中，第一氧化物層108由氧化矽(SiOx)製成。
第一接合層110形成在第一氧化物層108之上，第一接合層110具有第一抗蝕刻性(etching resistance)，第一氧化物層108具有第二抗蝕刻性，且第二抗蝕刻性大於第一抗蝕刻性。在一些實施例中，第一接合層110由SiOxFyCzNg、介電材料、或其他合適材料製成。舉例而言，第一接合層110由氮氧 化矽(SiON)或氮化矽(SiN)製成。在一些實施例中，第一氧化物層108由二氧化矽(SiO2)製成。應注意的是，由於第一接合層110和第一氧化物層108具有不同的抗蝕刻性，第一接合層110不是由氧化物材料製成。在一些實施例中，第一接合層110不是由二氧化矽(SiO2)製成。
之後，如第1B圖所示，根據本發明的一些實施例，在第二區12內之第一接合層110的一部分被移除，以形成凹陷111。
藉由使用圖案化製程形成凹陷111，圖案化製程包含微影製程和蝕刻製程。微影製程包含光阻塗布(例如旋轉塗布)、軟烤、光罩對準、曝光、曝後烤、將光阻顯影、沖洗和乾燥(例如硬烤)。蝕刻製程可包含乾蝕刻製程或濕蝕刻製程。由於在第一接合層110與第一氧化物層108之間有蝕刻選擇性，直到第一氧化物層108的頂面露出，蝕刻製程才停止。
在一些實施例中，第一接合層110由氮氧化矽(SiON)製成，且第一氧化物層108由二氧化矽(SiO2)製成。應注意的是，相較於第一氧化物層108的材料，第一接合層110的材料具有額外的元素，像是氮(N)。蝕刻製程可識別出SiON與SiO2之間的差異，因此第一接合層110和第一氧化物層108具有不同的抗蝕刻性。當第一氧化物層108的頂面露出時，蝕刻製程才停止。
第一接合層110沿著垂直方向具有第一厚度T1，且第一氧化物層108沿著垂直方向具有第二厚度T2。如果第一接合層110與第一氧化物層108之間的蝕刻選擇比不夠大，很難控 制第一接合層110的蝕刻深度。將需要較高/較厚的第一接合層，以防止第一氧化物層108被移除。由於此實施例之第一接合層110與第一氧化物層108之間有大的蝕刻選擇比，直到第一氧化物層108的頂面露出，化學機械研磨(chemical mechanical polishing，CMP)製程才停止。因此，第一接合層110的第一厚度T1可設計成小於第一氧化物層108的第二厚度T2。在一些實施例中，第一接合層110的第一厚度T1在從約0.1μm到約7μm的範圍內。在一些實施例中，第一氧化物層108的第二厚度T2與第一接合層110的第一厚度T1之比值(T2/T1)在從約2到約10的範圍內。由於第一接合層110的第一厚度T1降低，第一半導體裝置100a的整體厚度降低。此外，由於較薄的第一接合層110，製造時間和成本也降低。
接著，如第1C圖所示，根據本發明的一些實施例，移除在第一區11內之第一接合層110的一部分，以形成第一溝槽113。藉由進行第一蝕刻步驟15a而移除第一接合層110的上述部分，在第一區11內之第一氧化物層108的頂面藉由第一溝槽113而露出。
後續如第1D圖所示，根據本發明的一些實施例，移除第一氧化物層108的一部分以延伸第一溝槽113的深度。藉由進行第二蝕刻步驟15b而移除第一氧化物層108的上述部分，直到第一蝕刻停止層106的頂面露出，停止第二蝕刻步驟15b。
接著，如第1E圖所示，根據本發明的一些實施例，露出第一蝕刻停止層106的一部分，以進一步延伸第一溝槽113 的深度。藉由進行第三蝕刻步驟15c而移除第一蝕刻停止層106的上述部分，第一導電層104由第一溝槽113露出，且因此第一溝槽113穿過第一蝕刻停止層106、第一氧化物層108和第一接合層110。
應注意的是，蝕刻製程包含第一蝕刻步驟15a、第二蝕刻步驟15b和第三蝕刻步驟15c，且第一蝕刻步驟15a、第二蝕刻步驟15b和第三蝕刻步驟15c在原位(in-situ)進行。具體而言，第一蝕刻步驟15a、第二蝕刻步驟15b和第三蝕刻步驟15c在相同的反應腔室進行，而沒有轉移至其他腔室。因此，降低了半導體裝置100a受到污染的風險。
之後，如第1F圖所示，根據本發明的一些實施例，在第一區11的第一溝槽113內和第二區12的凹陷111內形成導電材料112。
導電材料112可由銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金製成。在一些實施例中，導電材料112藉由電鍍法形成。
接著，如第1G圖所示，根據本發明的一些實施例，在導電材料112上進行研磨製程，以平坦化導電材料112的頂面。在一些實施例中，研磨製程為化學機械研磨(CMP)製程。
結果，藉由在凹陷111內填充導電材料112，形成第一虛置墊(dummy pad)114於第二區12中。第一虛置墊114並未電性連接至其他裝置，且不提供任何功能。第一虛置墊114被配置來在進行研磨製程期間，像是化學機械研磨(CMP)製程，降低負載效應(loading effect)。
對於具有不同露出面積(或蝕刻面積)的區域而言，由於負載效應很難控制蝕刻均勻性。取決於蝕刻策略，負載效應為較大面積的蝕刻速率比較小面積的蝕刻速率快或慢。換言之，負載效應為在較大面積的蝕刻速率與較小面積的蝕刻速率不匹配。這表示負載效應可能受到圖案密度影響。由於第一接合導孔116形成在第一基板102的第一區11中，如果在第一基板102的第二區12中沒有形成虛置墊，第二區12的導電材料之圖案密度會小於在第一區11的導電材料之圖案密度。在第一區11中用於接合的導電材料之圖案密度與在第二區12中的導電材料之圖案密度不相等，因此，由於負載效應，第一接合層110的頂面在CMP製程之後可能會不平坦，第一接合層110可能會有凸起或凹陷的頂面。由於不平坦的頂面，第一接合層110與第二接合層210的接合效能可能會下降。為了改善接合效能，在第一基板102的第二區12中形成第一虛置墊114，以增加在第二區12中的圖案密度。
藉由在第一溝槽113內填充導電材料112，在第一區11中形成第一接合導孔116。第一接合導孔116穿過第一接合層110、第一氧化物層108和第一蝕刻停止層106。第一接合導孔116電性連接至第一導電層104，以將信號傳遞至第一基板102中的內連線結構。
應注意的是，第一接合導孔116直接接觸第一導電層104，在第一接合導孔116與第一導電層104之間沒有任何導線或導孔，第一接合導孔116只穿過一層蝕刻停止層(像是第一蝕刻停止層106)。
第一虛置墊114沿著垂直方向具有第一深度D1，且沿著水平方向具有第一寬度W1。在一些實施例中，第一深度D1在從約0.1μm到約7μm的範圍內。在一些實施例中，第一寬度W1在從約0.01μm到約200μm的範圍內。
第一接合導孔116沿著垂直方向具有第二深度D2，且沿著水平方向具有第二寬度W2。第二寬度W2大致上等於第一寬度W1，第二深度D2大於第一深度D1。在一些實施例中，第二深度D2在從約3μm到約20μm的範圍內。在一些實施例中，第二寬度W2在從約0.01μm到約200μm的範圍內。第一接合導孔116從頂面到底面具有大致上固定的第二寬度W2。
後續如第1H圖所示，根據本發明的一些實施例提供第二半導體裝置200a，第二半導體裝置200a與第一半導體裝置100a類似。在一些實施例中，第一半導體裝置100a為影像感測器裝置，且第二半導體裝置200a為邏輯裝置，像是特用積體電路(application specific IC，ASIC)。
第二半導體裝置200a包含第二基板202，且第二基板202包含第一區21和第二區22。在一些實施例中，第一區21為第二內連線區，且第二區22為邏輯區。第二蝕刻停止層206形成於第二基板202之上，且第二氧化物層208形成於第二蝕刻停止層206之上。第二接合層320形成於第二氧化物層208之上。
第二導電層204形成在第二基板202的第一區21中，第二虛置墊214形成在第二基板202的第二區22的第二接合層210中，且形成第二接合導孔216穿過在第二基板202的第一區21中的第二接合層210、第二氧化物層208和第二蝕刻停止層 206。
應注意的是，第二接合導孔216只穿過一層蝕刻停止層206，蝕刻停止層206與第二導電層204直接接觸。第二接合導孔216電性連接至第二導電層204，且與第二導電層204直接接觸，在第二接合導孔216與第二導電層204之間沒有導線或導孔。藉由進行單一蝕刻製程形成第二接合導孔216，單一蝕刻製程包含多個蝕刻步驟，且單一蝕刻製程在一反應腔室內進行，而沒有轉移至其他腔室。
第一接合導孔116面對第二接合導孔216，且第一虛置墊114面對第二虛置墊214。在進行混成接合製程之前，可在第一接合層110及/或第二接合層210的頂面上進行預清潔製程。
第二虛置墊214沿著垂直方向具有第三深度D3，且沿著水平方向具有第三寬度W3。在一些實施例中，第三深度D3在從約0.1μm到約7μm的範圍內。在一些實施例中，第三寬度W3在從約0.01μm到約200μm的範圍內。第二接合導孔216沿著垂直方向具有第四深度D4，且沿著水平方向具有第四寬度W4。在一些實施例中，第四深度D4在從約3μm到約20μm的範圍內。在一些實施例中，第四寬度W4在從約0.01μm到約200μm的範圍內。第二接合導孔216從頂面到底面具有大致上固定的第四寬度W4。
第一虛置墊114的第一寬度W1大抵上與第二虛置墊214的第三寬度W3相同，以幫助接合對準。類似地，第一接合導孔116的第二寬度W2大抵上與第二接合導孔216的第四寬 度W4相同，以幫助接合對準。
接著，如第1I圖所示，根據本發明的一些實施例，藉由將第一接合層110與第二接合層210接合，使第一半導體裝置100a接合至第二半導體裝置200a，以形成半導體結構300a。半導體結構300a為三維積體電路(3DIC)堆疊結構，其使用混成接合製程進行接合。
混成接合製程包含至少兩種接合，其包含金屬對金屬接合，以及非金屬對非金屬接合。混成接合結構310形成於第一半導體裝置100a與第二半導體裝置200a之間。混成接合結構310包含第一接合導孔116和第二接合導孔216，其藉由金屬對金屬接合方式而接合，以及包含第一虛置墊114和第二虛置墊214，其藉由金屬對金屬接合接合方式而接合。另外，第一接合層110和第二接合層210藉由非金屬對非金屬接合方式而接合。應注意的是，由於第一接合層110和第二接合層210兩者皆不是由氧化物製成，在第一接合層110與第二接合層210之間沒有氧化物對氧化物接合層。
在一些實施例中，混成接合製程可在惰性環境中進行，像是充填惰性氣體的環境，惰性氣體包含N2、Ar、He或前述之組合。在混成接合製程之後，在半導體結構300a上進行熱製程。
混成接合結構310具有第一金屬接合介面310a在第一接合導孔116與第二接合導孔216之間，以及第二金屬接合介面310b在第一虛置墊114與第二虛置墊214之間。由於熱製程，混成接合結構310可能沒有清楚的非金屬接合介面310c(以 虛線標示)在第一接合層110與第二接合層210之間。
由於第一接合層110和第二接合層210兩者皆具有平坦的頂面，改善了第一半導體裝置100a與第二半導體裝置200a之間的接合強度。因此，可以避免脫層問題，並且可以改善接合效能。此外，來自CMP製程所造成的碟狀凹陷或突起問題可以獲得解決或大幅地減少。
第2圖顯示根據本發明的一些實施例，第1H圖的第一虛置墊114、第一接合導孔116、第二虛置墊214和第二接合導孔216的上視示意圖。
在第一半導體裝置100a、100b中，第二區12位於第一基板102的中央，且第一區11圍繞第二區12。第一區11用於形成各種重分布層(RDL)，以將在第二區12之裝置的信號傳遞至外界。當從上視角度觀之，在第二區12中的第一虛置墊114被在第一區11中的第一接合導孔116圍繞。
類似地，在第二半導體裝置200a、200b中，第二區22位於第二基板202的中央。當從上視角度觀之，在第二區22中的第二虛置墊214被在第一區21中的第二接合導孔216圍繞。
第3A-3C圖顯示根據本發明的一些實施例，形成半導體結構300b的剖面示意圖。在第3A-3C圖中用於形成半導體結構300b的一些製程和材料，與在第1A-1I圖中用於形成半導體結構300a的那些製程和材料類似或相同，在此不重複敘述。
第3A-3C圖中的半導體結構300b與第1A-1I圖中半導體結構300a相似，且差異處在於第一接合導孔116的形狀與 第二接合導孔216的形狀不同。
如第3A圖所示，第一凹陷111形成於第一接合層110中，且第一凹陷111的寬度從頂部到底面逐漸減少(tapered)。形成第一溝槽113穿過第一接合層110、第一氧化物層108和第一蝕刻停止層106。第一導電層104的頂面由第一溝槽113露出，第一溝槽113的寬度從頂部到底面逐漸減少。
之後，如第3B圖所示，根據本發明的一些實施例，在第一凹陷111和第一溝槽113內形成導電材料，以形成第一虛置墊114在第二區12中，以及形成第一接合導孔116在第一區11中。第一接合導孔116電性連接至第一導電層104。第一接合導孔116的寬度從頂面到底面逐漸減少，且底面比頂面更靠近第一基板102。
接著，如第3C圖所示，根據本發明的一些實施例，藉由將第一接合層110和第二接合層210接合，將第一半導體裝置100b接合至第二半導體裝置200b，以形成半導體結構300b。第二半導體裝置200b包含在第二區12中的第二虛置墊214，以及在第一區11中的第二接合導孔216。半導體結構300b為三維積體電路(3DIC)堆疊結構，其使用混成接合製程進行接合。
混成接合結構310形成於第一半導體裝置100b與第二半導體裝置200b之間，第一接合導孔116的形狀相對於中央界面對稱於第二接合導孔216的形狀，且第一虛置墊114的形狀相對於中央界面對稱於第二虛置墊214的形狀。
混成接合結構310包含第一接合導孔116和第二接合導孔216，其藉由金屬對金屬接合方式而接合，以及包含第 一虛置墊114和第二虛置墊214，其藉由金屬對金屬接合方式而接合。另外，第一接合層110和第二接合層210藉由非金屬對非金屬接合方式而接合。
第4A-4D圖顯示根據本發明的一些實施例，第一虛置墊114和第二虛置墊214的排列或佈局之立體圖。
如第4A圖所示，第一虛置墊114與第二虛置墊214重疊。第一虛置墊114的右側側壁表面對齊第二虛置墊214的右側側壁表面。
如第4B圖所示，第一虛置墊114正交於(orthogonal to)第二虛置墊214。第一虛置墊114的一部分與第二虛置墊214的一部分重疊。由於在第二區12中的導電材料之圖案密度藉由形成第一虛置墊114而增加，以降低負載效應，在進行研磨製程(像是CMP製程)之後，可以得到第一接合層110和第二接合層210的平坦頂面，提供平坦頂面以提高第一接合層110與第二接合層210之間的接合強度。因此，即使第一虛置墊114的整體面積沒有與第二虛置墊214的整體面積重疊，第一半導體裝置100a、100b與第二半導體裝置200a、200b之間的接合強度仍然足夠好到可以防止脫層。在一些實施例中，第一虛置墊114與第二虛置墊214之間重疊的量在從約30%到約100%的範圍內。當重疊的量在上述範圍內時，第一半導體裝置100a、100b與第二半導體裝置200a、200b之間的接合強度佳。
如第4C圖所示，一個第一虛置墊114可能與兩個相鄰的第二虛置墊214重疊。第一虛置墊114可橫跨兩個相鄰的第二虛置墊214。
如第4D圖所示，第一虛置墊114的一部分與第二虛置墊214的一部份重疊。更具體而言，第一虛置墊114的左側側壁表面未對齊第二虛置墊214的左側側壁表面。在第一虛置墊114的左側側壁表面與第二虛置墊214的左側側壁表面之間有間隔。在一些實施例中，第一虛置墊114可與第二虛置墊214的一半重疊。
第5A-5D圖顯示根據本發明的一些實施例，形成半導體結構700的剖面示意圖。半導體結構700由混成接合第一半導體裝置500與第二半導體裝置600而形成。
如第5A圖所示，第一半導體裝置500包含第一基板502。第一基板502包含第一表面502a和第二表面502b，且第一基板502包含第一區11和第二區12。在一些實施例中，第一半導體裝置500為背照式(backside illuminated，BSI)影像感測器裝置。在一些實施例中，第一區11為第一內連線區，且第二區12為畫素區。
數個光感測區504形成在第一基板502中，光感測區504用於分別偵測紅光、綠光和藍光波長的強度(輝度)。在一些實施例中，光感測區504為光電二極體(photodiode，PD)區。光感測區504可用摻質摻雜。在一些實施例中，第一基板502用第一導電類型摻雜，且光感測區504用第二導電類型摻雜。在一些實施例中，第一基板502用p型摻質，像是硼(B)或鎵(Ga)摻雜，且光感測區504用n型摻質，像是磷(P)或砷(As)摻雜。
電晶體裝置510形成在第一基板502的第一表面502a上。電晶體裝置510包含閘極介電層506，以及閘極電極層 508在閘極介電層506上，一對閘極間隔物512形成在電晶體裝置510的側壁表面上。在一些實施例中，電晶體裝置510為傳輸(transfer)電晶體裝置。
閘極介電層506由介電材料製成，像是氧化矽、氮化矽、氮氧化矽、具有高介電常數(high-k)的介電材料、或前述之組合。閘極介電層506可由沉積製程形成，像是化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(atomic layer deposition，ALD)、高密度電漿化學氣相沉積(high density plasma CVD，HDPCVD)、金屬有機化學氣相沉積(metal organic CVD，MOCVD)、或電漿增強化學氣相沉積(plasma enhanced CVD，PECVD)。閘極電極層508可由導電材料製成，像是鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、或其他合適材料。閘極電極層508可由沉積製程形成，像是化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、或其他合適製程。
在一些實施例中，閘極間隔物512由氧化矽、氮化矽、氮氧化矽、或其他合適材料製成。在一些實施例中，閘極間隔物512由化學氣相沉積(CVD)製程、或物理氣相沉積(PVD)製程形成。
在一些實施例中，形成四個n型金屬氧化物半導體(MOS)電晶體，這四個n型金屬氧化物半導體(MOS)電晶體為：用於將光電二極體收集到的光電荷(optical charges)傳輸至浮動擴散(floating diffusion，FD)區之傳輸電晶體(transfer transistor)Tx；將浮動擴散區的電位設定成更合適的位準，並 且在電荷放電後將浮動擴散區重設之重設電晶體(reset transistor)Rx；作為源極隨耦緩衝放大器(source follower buffer amplifier)之用的驅動電晶體(drive transistor)Dx；以及進行切換功能以定址(address)畫素之選擇電晶體(select transistor)Sx。
層間介電層(inter-layer dielectric(ILD)layer)514形成於第一基板502的第一表面102a之上，層間介電層514可包含多層。層間介電層514由氧化矽(SiOx)、氮化矽(SixNy)、氮氧化矽(SiON)、低介電常數介電材料、或其他合適的介電材料製成。
第一內連線結構520形成於層間介電層514之上，第一內連線結構520包含金屬間介電層(inter-metal dielectric(IMD)layer)522、導線524、導孔插塞526、以及金屬阻擋結構(metal block structure)528。金屬阻擋結構528不會電性連接至第一虛置墊114。金屬間介電層522可為單層或多層。金屬阻擋結構528和第一導電層104在相同水平高度。導線524和導孔插塞526形成於金屬間介電層522中，導線524經由導孔插塞526電性連接至另一相鄰的導線524。第一內連線結構520在後段(back-end-of-line)(BEOL)製程中形成。
金屬間介電(IMD)層522由氧化矽(SiOx)、氮化矽(SixNy)、氮氧化矽(SiON)、低介電常數介電材料、或前述之組合製成。在一些實施例中，金屬間介電層522由超低介電常數(extreme low-k，ELK)介電材料製成，其介電常數值(k)小於約2.5。在一些實施例中，超低介電常數(ELK)介電材料包含摻雜 碳的氧化矽、非晶形氟化碳、聚對二甲苯(parylene)、二苯並環丁烯(bis-benzocyclobutenes，BCB)、聚四氟乙烯(polytetrafluoroethylene，PTFE)，又稱鐵氟龍(Teflon)、或碳氧化矽聚合物(silicon oxycarbide polymers，SiOC)。在一些實施例中，超低介電常數(ELK)介電材料包含現有介電材料之多孔型態，像是多孔氫倍半矽氧烷(hydrogen silsesquioxane，HSQ)、多孔甲基倍半矽氧烷(methyl silsesquioxane，MSQ)、多孔聚芳醚(polyarylether，PAE)、多孔高分子(SiLK)、或多孔二氧化矽(SiO2)。在一些實施例中，金屬間介電層522由電漿增強化學氣相沉積(PECVD)製程或旋轉塗布製程沉積而成。
導線524、導孔插塞526和金屬阻擋結構528各自獨立地由銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金製成。在一些實施例中，導線524、導孔插塞526和金屬阻擋結構528由電鍍法形成。
第一蝕刻停止層106形成在第一內連線結構520上，且第一氧化物層108形成在第一蝕刻停止層106上。第一接合層110形成在第一氧化物層108上，第一虛置墊114形成在第一接合層110中，且第一接合導孔116穿過多層形成，這些層包含第一接合層110、第一氧化物層108和第一蝕刻停止層106。第一接合導孔116電性連接至第一內連線結構520的第一導電層104(或頂部金屬層)。
之後，如第5B圖所示，根據本發明的一些實施例，第二半導體裝置600與第一半導體裝置500相對應地設置。在一些實施例中，第二半導體裝置600為邏輯裝置。
第二半導體裝置600包含第二基板602，第二基板602包含第一表面602a和第二表面602b，且第二基板602包含第一區21和第二區22。在一些實施例中，第二半導體裝置600為邏輯裝置。在一些實施例中，第一區21為第二內連線區，且第二區22為邏輯區。
電晶體裝置610形成於第二基板602的第一表面602a之上。電晶體裝置610包含閘極介電層606，以及閘極電極層608在閘極介電層606上，一對閘極間隔物612形成在電晶體裝置610的側壁表面上。
層間介電(ILD)層614形成於第二基板602的第一表面602a之上。第二內連線結構620形成於層間介電層614之上，第二內連線結構620包含金屬間介電(IMD)層622、導線624和導孔插塞626。金屬間介電層622可為單層或多層。導線624和導孔插塞626形成於金屬間介電層622中，導線624經由導孔插塞626電性連接至另一相鄰的導線624。第二內連線結構620在後段(BEOL)製程中形成。
第二蝕刻停止層206形成於第二內連線結構620上，且第二氧化物層208形成於第一蝕刻停止層206上。第二接合層610形成於第二氧化物層608上。第二虛置墊214形成於第二接合層210中，且第二接合導孔216穿過多層形成，其包含第二接合層210、第二氧化物層208和第二蝕刻停止層206。第二接合導孔216電性連接至第二內連線結構620的導電層204(或頂部金屬層)。
接著，如第5C圖所示，根據本發明的一些實施例， 第一半導體裝置500藉由混成接合製程接合至第二半導體裝置600，以形成半導體結構700，半導體結構700為三維積體電路(3DIC)。第一虛置墊114接合至第二虛置墊214，且第一接合導孔116接合至第二接合導孔216。
之後，如第5D圖所示，在混成接合製程之後，在第一基板502內形成深隔離結構530。深隔離結構530由在深溝槽內填充隔離材料而形成，深溝槽從第一基板502的第二表面502b形成。
數個網格(grid)結構534形成於第二區12中的深隔離結構530之上，網格結構534用於引導光線朝向相對應的光感測區504。每個網格結構534包含底部534a和位於底部534a之上的頂部534b。在一些實施例中，底部534a由金屬材料製成，且頂部534b由介電材料製成。金屬遮蔽結構532形成於第一區11中的第一基板502之第二表面502b上。介電層536形成於網格結構534以及金屬遮蔽結構532上，介電層536由氧化矽、氮化矽、氮氧化矽或前述之組合製成。介電層536可具有單層或多層。
數個彩色濾光片540形成在介電層536中，每個網格結構534形成在兩個相鄰的彩色濾光片540之間的界面區下方。彩色濾光片540對準光感測區504，其被配置來過濾可見光，並使得在紅(R)、綠(G)或藍(B)波長的光線可以穿透到達光感測區504。
彩色濾光片540由以染料為主(或顏料為主)的聚合物製成，以過濾出特定頻帶(frequency band)(例如希望得到的光之波長)。在一些其他實施例中，彩色濾光片540由具有彩色 顏料之樹脂或其他以有機為主的材料製成。
數個微透鏡結構542形成在彩色濾光片540之上，微透鏡結構542可具有多種形狀和尺寸，取決於用在微透鏡結構542的材料之折射率。光線25在第一基板502的第二表面502b之上，微透鏡結構542引導光線25至個別的彩色濾光片540。然後，光線25穿過彩色濾光片540到達相對應的光感測區504。
藉由在第一基板102的第二區12形成第一虛置墊114來降低負載效應，可以使得第一接合層110得到平坦的頂面。由於第一接合層110的抗蝕刻性與第一氧化物層108的抗蝕刻性不同，當第一氧化物層108的頂面露出時，化學機械研磨(CMP)製程會停止。第一接合層110的厚度小於第一氧化物層108的厚度，以降低半導體結構300a、300b、700的整體封裝厚度。第一接合導孔116由在第一溝槽113內填充導電材料而形成，第一溝槽113由在反應腔室內進行單一蝕刻製程而形成。第一接合導孔116的第二寬度W2為固定寬度或逐漸減少的(tapered)寬度，取決於第一溝槽113的形狀。
提供實施例以形成具有混成接合結構之半導體結構，半導體結構由第一半導體裝置與第二半導體裝置混成接合而形成。第一半導體裝置包含第一基板、第一蝕刻停止層、第一氧化物層和第一接合層。第一虛置墊形成在第一接合層中，且第一接合導孔穿過第一接合層、第一氧化物層和第一蝕刻停止層而形成。第二半導體裝置包含第二虛置墊和第二接合導孔，其類似於第一虛置墊和第一接合導孔。
藉由在一個反應腔室中進行單一蝕刻製程，形成 第一接合導孔和第二接合導孔各自穿過多層。第一接合導孔接合至第二接合導孔，且第一虛置墊接合至第二虛置墊。第一虛置墊和第二虛置墊用於增加在第二區中的圖案密度，以降低負載效應。結果，得到第一接合層和第二接合層之平坦頂面。由於第一接合層和第二接合層兩者皆具有平坦頂面，可以改善第一半導體裝置與第二半導體裝置之間的接合強度。因此，改善了半導體結構的效能。
在一些實施例中，提供半導體結構。此半導體結構包含第一半導體裝置。第一半導體裝置包含第一導電層形成於第一基板之上；第一蝕刻停止層形成於第一導電層之上，且第一蝕刻停止層直接接觸第一導電層；第一接合層形成於第一蝕刻停止層之上；以及第一接合導孔穿過第一接合層和第一蝕刻停止層而形成，且第一接合導孔電性連接至第一導電層。此半導體結構也包含第二半導體裝置。第二半導體裝置包含第二導電層形成於第二基板之上；第二蝕刻停止層形成於第二導電層之上，且第二蝕刻停止層直接接觸第二導電層；第二接合層形成於第二蝕刻停止層之上；以及第二接合導孔穿過第二接合層和第二蝕刻停止層而形成，第二接合導孔電性連接至第二導電層。此半導體結構還包含接合結構位於第一基板與第二基板之間，且接合結構包含第一接合導孔接合至第二接合導孔。
在一些實施例中，第一半導體裝置更包含第一氧化物層位於第一蝕刻停止層與第一接合層之間，其中第一接合導孔穿過第一氧化物層。
在一些實施例中，第一接合層具有第一耐蝕刻 性，第一氧化物層具有第二耐蝕刻性，且第二耐蝕刻性大於第一耐蝕刻性。
在一些實施例中，半導體結構更包含金屬阻擋結構形成於第一基板之上，其中金屬阻擋結構和第一導電層位於相同水平高度。
在一些實施例中，第一接合層和第二接合層不是由氧化物製成。
在一些實施例中，第一接合導孔直接接觸第一導電層。
在一些實施例中，第一接合導孔具有頂面和底面，底面比頂面更靠近第一基板，且第一接合導孔的寬度從頂面到底面逐漸減少。
在一些實施例中，半導體結構更包含第一虛置墊形成於第一接合層中；以及第二虛置墊形成於第二接合層中，其中接合結構更包含第一虛置墊接合至第二虛置墊。
在一些實施例中，當從上視角度觀之，第一虛置墊被第一接合導孔圍繞。
在一些實施例中，第一虛置墊的第一側壁表面與第二虛置墊的第二側壁表面不對齊，且在第一側壁表面與第二側壁表面之間有間隔。
在一些實施例中，半導體結構更包含電晶體裝置形成於第一基板之上，其中第一基板具有第一表面和與第一表面相反的第二表面，且電晶體裝置形成於第一表面之上；複數個網格結構形成於第一基板的第二表面之上；複數個彩色濾光 片形成於複數個網格結構之上；以及複數個微透鏡結構形成於複數個彩色濾光片之上。
在一些實施例中，提供半導體結構。此半導體結構包含影像感測器裝置。影像感測器裝置包含第一基板，第一基板包含第一內連線區和畫素區。光感測區形成於第一基板的畫素區中，且第一氧化物層形成於光感測區下方。第一接合層形成於第一氧化物層下方，且第一接合導孔穿過第一接合層和第一氧化物層而形成。半導體結構也包含邏輯電路裝置形成於影像感測器裝置下方，邏輯電路裝置包含第二基板，且第二基板包含第二內連線區和邏輯區。電晶體裝置形成於第二基板之上，且第二氧化物層形成於電晶體裝置之上。第二接合層形成於第二氧化物層之上，且第二接合導孔穿過在第二內連線區中的第二接合層和第二氧化物層而形成。半導體結構還包含混成接合結構位於影像感測器裝置與邏輯電路裝置之間，且混成接合結構包含第一接合導孔接合至第二接合導孔。
在一些實施例中，半導體結構更包含第一內連線結構，其形成於第一基板下方且位於第一內連線區中，其中第一接合導孔電性連接至第一內連線結構的一導電層；以及第二內連線結構，其形成於電晶體裝置之上且位於第二內連線區中，其中第二接合導孔電性連接至第二內連線結構的一導電層。
在一些實施例中，半導體結構更包含第一虛置墊，其形成於第一接合層中且位於畫素區內；以及第二虛置墊，其形成於第二接合層中且位於邏輯區內，其中第一虛置墊 接合至第二虛置墊。
在一些實施例中，第一虛置墊的第一側壁表面與第二虛置墊的第二側壁表面不對齊，且在第一側壁表面與第二側壁表面之間有間隔。
在一些實施例中，第一接合導孔具有頂面和底面，底面比頂面更靠近第一基板，且第一接合導孔的寬度從頂面到底面逐漸減少。
在一些實施例中，影像感測器裝置更包含第一蝕刻停止層位於光感測區與第一氧化物層之間，且第一接合導孔穿過第一蝕刻停止層。
在一些實施例中，提供形成半導體結構的方法。此方法包含形成第一半導體裝置。形成第一半導體裝置的步驟包含形成第一氧化物層於第一基板之上，且第一基板包含畫素區和第一內連線區。形成第一接合層於第一氧化物層之上，以及形成第一凹陷於畫素區內的第一接合層中。形成第一溝槽穿過在第一內連線區中的第一接合層和第一氧化物層，以及在第一凹陷和第一溝槽內填充導電材料，以形成第一虛置墊和第一接合導孔。此方法也包含形成第二半導體裝置。形成第二半導體裝置的步驟包含形成第二氧化物層於第二基板之上，且第二基板包含邏輯區和第二內連線區。形成第二接合層於第二氧化物層之上，以及形成第二凹陷於邏輯區內的第二接合層中。形成第二溝槽穿過第二接合層和第二氧化物層，且在第二凹陷和第二溝槽內填充導電材料，以形成第二虛置墊和第二接合導孔。此方法還包含藉由將第一接合導孔接合至第二接合導孔， 以及將第一虛置墊接合至第二虛置墊，將第一半導體裝置與第二半導體裝置接合。
在一些實施例中，此方法更包含在將第一半導體裝置與第二半導體裝置接合之後，形成複數個網格結構於第一基板之上；形成複數個彩色濾光片於複數個網格結構之上；以及形成複數個微透鏡結構於複數個彩色濾光片之上。
在一些實施例中，藉由混成接合製程將第一半導體裝置與第二半導體裝置接合。
以上概述了數個實施例的部件，使得在本發明所屬技術領域中具有通常知識者可以更理解本發明實施例的概念。在本發明所屬技術領域中具有通常知識者應該理解，可以使用本發明實施例作為基礎，來設計或修改其他製程和結構，以實現與在此所介紹的實施例相同的目的及/或達到相同的好處。在本發明所屬技術領域中具有通常知識者也應該理解，這些等效的結構並不背離本發明的精神和範圍，並且在不背離本發明的精神和範圍的情況下，在此可以做出各種改變、取代和其他選擇。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
11、21‧‧‧第一區
12、22‧‧‧第二區
100a‧‧‧第一半導體裝置
200a‧‧‧第二半導體裝置
300a‧‧‧半導體結構
102‧‧‧第一基板
104‧‧‧第一導電層
106‧‧‧第一蝕刻停止層
108‧‧‧第一氧化物層
110‧‧‧第一接合層
114‧‧‧第一虛置墊
116‧‧‧第一接合導孔
202‧‧‧第二基板
204‧‧‧第二導電層
206‧‧‧第二蝕刻停止層
208‧‧‧第二氧化物層
210‧‧‧第二接合層
214‧‧‧第二虛置墊
216‧‧‧第二接合導孔
310‧‧‧混成接合結構
310a‧‧‧第一金屬接合介面
310b‧‧‧第二金屬接合介面
310c‧‧‧非金屬介面

Claims (10)

  1. 一種半導體結構，包括：一第一半導體裝置，其中該第一半導體裝置包括：一第一導電層，形成於一第一基板之上，其中該第一基板包括一畫素區和一第一內連線區；一第一蝕刻停止層，形成於該第一導電層之上，其中該第一蝕刻停止層直接接觸該第一導電層；一第一接合層，形成於該第一蝕刻停止層之上；一第一虛置墊，形成於該第一接合層中且位於該畫素區內；一第一接合導孔，穿過該第一內連線區中的該第一接合層和該第一蝕刻停止層而形成，其中該第一接合導孔電性連接至該第一導電層；以及一第二半導體裝置，其中該第二半導體裝置包括：一第二導電層，形成於一第二基板之上；一第二蝕刻停止層，形成於該第二導電層之上，其中該第二蝕刻停止層直接接觸該第二導電層；一第二接合層，形成於該第二蝕刻停止層之上；一第二接合導孔，穿過該第二接合層和該第二蝕刻停止層而形成，其中該第二接合導孔電性連接至該第二導電層；以及一接合結構，位於該第一基板與該第二基板之間，其中該接合結構包括該第一接合導孔接合至該第二接合導孔。
  2. 如申請專利範圍第1項所述之半導體結構，其中該第一半導體裝置更包括一第一氧化物層位於該第一蝕刻停止層與該 第一接合層之間，其中該第一接合導孔穿過該第一氧化物層，該第一接合層具有一第一耐蝕刻性，該第一氧化物層具有一第二耐蝕刻性，且該第二耐蝕刻性大於該第一耐蝕刻性。
  3. 如申請專利範圍第1或2項所述之半導體結構，更包括：一第二虛置墊，形成於該第二接合層中，其中該接合結構更包括該第一虛置墊接合至該第二虛置墊。
  4. 如申請專利範圍第3項所述之半導體結構，其中當從上視角度觀之，該第一虛置墊被該第一接合導孔圍繞。
  5. 如申請專利範圍第3項所述之半導體結構，其中該第一虛置墊的一第一側壁表面與該第二虛置墊的一第二側壁表面不對齊，且在該第一側壁表面與該第二側壁表面之間有一間隔。
  6. 一種半導體結構，包括：一影像感測器裝置，其中該影像感測器裝置包括：一第一基板，其中該第一基板包括一第一內連線區和一畫素區；一光感測區，形成於該第一基板中且位於該畫素區內；一第一氧化物層，形成於該光感測區下方；一第一接合層，形成於該第一氧化物層下方；一第一接合導孔，穿過該第一接合層和該第一氧化物層而形成；以及一邏輯電路裝置，形成於該影像感測器裝置下方，其中該邏輯電路裝置包括： 一第二基板，其中該第二基板包括一第二內連線區和一邏輯區；一電晶體裝置，形成於該第二基板之上；一第二氧化物層，形成於該電晶體裝置之上；一第二接合層，形成於該第二氧化物層之上；一第二接合導孔，穿過該第二內連線區中的該第二接合層和該第二氧化物層而形成；以及一混成接合結構，位於該影像感測器裝置與該邏輯電路裝置之間，且該混成接合結構包括該第一接合導孔接合至該第二接合導孔。
  7. 如申請專利範圍第6項所述之半導體結構，更包括：一第一虛置墊，形成於該第一接合層中且位於該畫素區內；以及一第二虛置墊，形成於該第二接合層中且位於該邏輯區內，其中該第一虛置墊接合至該第二虛置墊。
  8. 如申請專利範圍第6或7項所述之半導體結構，其中該第一接合導孔具有一頂面和一底面，該底面比該頂面更靠近該第一基板，且該第一接合導孔的寬度從該頂面到該底面逐漸減少。
  9. 一種半導體結構的形成方法，包括：形成一第一半導體裝置，其中形成該第一半導體裝置的步驟包括：形成一第一氧化物層於一第一基板之上，其中該第一基板包括一畫素區和一第一內連線區； 形成一第一接合層於該第一氧化物層之上；形成一第一凹陷於該第一接合層中且位於該畫素區內；形成一第一溝槽穿過該第一內連線區中的該第一接合層和該第一氧化物層；填充一導電材料於該第一凹陷和該第一溝槽內，以形成一第一虛置墊和一第一接合導孔；以及形成一第二半導體裝置，其中形成該第二半導體裝置的步驟包括：形成一第二氧化物層於一第二基板之上，其中該第二基板包括一邏輯區和一第二內連線區；形成一第二接合層於該第二氧化物層之上；形成一第二凹陷於該第二接合層中且位於該邏輯區內；形成一第二溝槽穿過該第二接合層和該第二氧化物層；填充該導電材料於第二凹陷和該第二溝槽內，以形成一第二虛置墊和一第二接合導孔；以及藉由將該第一接合導孔接合至該第二接合導孔，以及將該第一虛置墊接合至該第二虛置墊，將該第一半導體裝置與該第二半導體裝置接合。
  10. 如申請專利範圍第9項所述之半導體結構的形成方法，更包括：在將該第一半導體裝置與該第二半導體裝置接合之後，形成複數個網格結構於該第一基板之上；形成複數個彩色濾光片於該複數個網格結構之上；以及形成複數個微透鏡結構於該複數個彩色濾光片之上。
TW107125502A 2017-09-27 2018-07-24 半導體結構及其形成方法 TWI693873B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762563871P 2017-09-27 2017-09-27
US62/563,871 2017-09-27
US15/906,214 US10692826B2 (en) 2017-09-27 2018-02-27 Semiconductor structure and method for forming the same
US15/906,214 2018-02-27

Publications (2)

Publication Number Publication Date
TW201916775A TW201916775A (zh) 2019-04-16
TWI693873B true TWI693873B (zh) 2020-05-11

Family

ID=65808370

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107125502A TWI693873B (zh) 2017-09-27 2018-07-24 半導體結構及其形成方法

Country Status (4)

Country Link
US (2) US10692826B2 (zh)
KR (1) KR102205746B1 (zh)
CN (1) CN109560094B (zh)
TW (1) TWI693873B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117012754A (zh) * 2018-06-29 2023-11-07 长江存储科技有限责任公司 半导体结构及其形成方法
CN116995059A (zh) * 2018-06-29 2023-11-03 长江存储科技有限责任公司 半导体结构及其形成方法
CN109643700B (zh) 2018-11-21 2019-09-10 长江存储科技有限责任公司 用于接合界面处的接合对准标记的方法、器件和结构
US20210020455A1 (en) * 2019-07-17 2021-01-21 Nanya Technology Corporation Conductive via structure
KR20210021626A (ko) * 2019-08-19 2021-03-02 삼성전자주식회사 반도체 장치
US11309243B2 (en) * 2019-08-28 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package having different metal densities in different regions and manufacturing method thereof
JP2021044347A (ja) * 2019-09-10 2021-03-18 キオクシア株式会社 半導体装置
TWI726432B (zh) * 2019-10-01 2021-05-01 健鼎科技股份有限公司 多截式金手指結構及其製造方法
US20210125910A1 (en) * 2019-10-25 2021-04-29 Nanya Technology Corporation Semiconductor structure
US11270962B2 (en) * 2019-10-28 2022-03-08 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
US20210257290A1 (en) * 2020-02-19 2021-08-19 Nanya Technology Corporation Semiconductor device with connecting structure and method for fabricating the same
JP2021141252A (ja) * 2020-03-06 2021-09-16 キオクシア株式会社 半導体装置およびその製造方法
KR20220126539A (ko) 2021-03-09 2022-09-16 삼성전자주식회사 반도체 패키지
US11423204B1 (en) * 2021-04-14 2022-08-23 Taiwan Semiconductor Manufacturing Company Limited System and method for back side signal routing
CN113488392B (zh) * 2021-07-13 2022-08-02 武汉新芯集成电路制造有限公司 集成电路器件制造方法
CN115911073B (zh) * 2023-01-09 2023-08-11 湖北江城芯片中试服务有限公司 一种半导体结构及其制作方法、图像传感器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201417227A (zh) * 2012-10-31 2014-05-01 Taiwan Semiconductor Mfg 半導體基板、混成接合結構及混成接合基板的形成方法
TW201729371A (zh) * 2015-12-29 2017-08-16 台灣積體電路製造股份有限公司 三維積體電路晶粒與其形成方法
TW201733069A (zh) * 2016-03-11 2017-09-16 台灣積體電路製造股份有限公司 半導體元件結構

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8878325B2 (en) 2012-07-31 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Elevated photodiode with a stacked scheme
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
KR102274775B1 (ko) * 2014-11-13 2021-07-08 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201417227A (zh) * 2012-10-31 2014-05-01 Taiwan Semiconductor Mfg 半導體基板、混成接合結構及混成接合基板的形成方法
TW201729371A (zh) * 2015-12-29 2017-08-16 台灣積體電路製造股份有限公司 三維積體電路晶粒與其形成方法
TW201733069A (zh) * 2016-03-11 2017-09-16 台灣積體電路製造股份有限公司 半導體元件結構

Also Published As

Publication number Publication date
US20200321294A1 (en) 2020-10-08
US11456263B2 (en) 2022-09-27
US20190096830A1 (en) 2019-03-28
CN109560094A (zh) 2019-04-02
TW201916775A (zh) 2019-04-16
US10692826B2 (en) 2020-06-23
KR20190036493A (ko) 2019-04-04
KR102205746B1 (ko) 2021-01-22
CN109560094B (zh) 2021-01-12

Similar Documents

Publication Publication Date Title
TWI693873B (zh) 半導體結構及其形成方法
US10163952B2 (en) Backside illuminated image sensor device structure
JP6259418B2 (ja) 縦方向に集積化される背面照射型イメージセンサ装置
US11189654B2 (en) Manufacturing methods of semiconductor image sensor devices
US8710612B2 (en) Semiconductor device having a bonding pad and shield structure of different thickness
KR102352520B1 (ko) 내산 층을 가지는 반도체 장치 구조물 및 그 형성 방법
TWI674669B (zh) 影像感測器裝置結構及其形成方法
US20160064433A1 (en) Backside illuminated image sensor structure
TWI604599B (zh) 影像感測結構及其形成方法
US9153620B2 (en) Method of fabricating a metal grid for semiconductor device
TWI717795B (zh) 影像感測器及其形成方法
US20220367391A1 (en) Semiconductor structure
US12009323B2 (en) Semiconductor structure
US20240021636A1 (en) Optical structure and method for manufacturing the same